Detection method and device for storage unit of chip
By generating scan mode entry instructions in the chip and calling joint test behavior organization interfaces, generating scan chains and using reset counters for detection, the problem of low detection efficiency of chip storage units is solved, and efficient and accurate detection is achieved.
Patent Information
- Application Number
- CN202310954449.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-14
AI Technical Summary
The prior art is difficult to effectively improve the detection efficiency of chip storage units, resulting in a decrease in chip yield.
By generating scan mode entry instructions, calling the joint test behavior organization interface control chip to enter scan mode, generating a scan chain for storage units, using reset counters and built-in self-test scan chains to obtain scan data, and detecting storage units.
A variety of diagnostic modes have been realized, which improves the detection efficiency of chip storage units and improves the detection accuracy and efficiency of on-chip registers.
Smart Images
Figure CN119446245A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of detection of memory cells of chips, and in particular to a detection method for memory cells of chips, a detection device for memory cells of chips, a chip, an electronic device and a computer-readable storage medium. Background Art
[0002] With the development of information technology, IC design is becoming more and more complex, and embedded memory is taking up more and more area in the chip. Due to its high unit density, embedded storage unit RAM is prone to silicon defects and reduce the chip yield. Therefore, it is becoming more and more important to achieve fast and effective memory testing. Summary of the invention
[0003] The embodiments of the present invention provide a method, an apparatus, an electronic device and a computer-readable storage medium for detecting a memory unit of a chip, so as to solve the problem of how to improve the detection efficiency of the memory unit on the chip.
[0004] An embodiment of the present invention discloses a detection method for a memory unit of a chip, wherein the memory unit is configured with a corresponding register and a reset counter, the chip is configured with a scan mode, and a corresponding joint test behavior organization interface, and the method may include:
[0005] Generate a scan mode entry instruction, and call the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction;
[0006] In the scan mode, a scan chain for the storage unit is generated through the register; the scan chain includes a first storage built-in self-test scan chain for the native storage unit generated according to the register, and a second storage built-in self-test scan chain for the custom storage unit;
[0007] When it is determined that the storage unit has a fault, obtaining scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and obtaining a first count value through the reset counter;
[0008] The storage cell is detected based on the scan data and the first count value.
[0009] Optionally, the chip is configured with a storage built-in self-test mode, and when it is determined that the storage unit has a fault, the step of acquiring scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquiring a first count value through the reset counter comprises:
[0010] Generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0011] Controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation;
[0012] When it is determined that the storage unit has a fault, stopping the reset counter;
[0013] Scan data for the storage unit is acquired through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is acquired through the reset counter.
[0014] Optionally, the storage unit is configured with a corresponding error count counter.
[0015] Optionally, the chip is configured with a storage built-in self-test mode, and when it is determined that the storage unit has a fault, the step of acquiring scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquiring a first count value through the reset counter comprises:
[0016] Generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0017] Controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation;
[0018] When it is determined that the storage unit has a fault, stopping the reset counter and the error count counter;
[0019] Acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter;
[0020] The second count value is read through the error number counter.
[0021] Optionally, it also includes:
[0022] When the second count value does not reach the preset threshold, the reset counter is started and the storage built-in self-test logic operation is continued.
[0023] Optionally, it also includes:
[0024] When the second count value reaches a preset threshold, the storage built-in self-test logic operation is stopped.
[0025] The embodiment of the present invention further discloses a detection device for a memory unit of a chip, wherein the memory unit is configured with a corresponding register and a reset counter, the chip is configured with a scan mode, and a corresponding joint test behavior organization interface, and the device comprises:
[0026] A scan mode entry instruction generation module is used to generate a scan mode entry instruction and call the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction;
[0027] A scan chain generation module, configured to generate a scan chain for the storage unit through the register in the scan mode; the scan chain includes a first storage built-in self-test scan chain for the native storage unit generated according to the register, and a second storage built-in self-test scan chain for the custom storage unit;
[0028] a scan data acquisition module, configured to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter when it is determined that the storage unit has a fault;
[0029] The storage unit detection module is used to detect the storage unit based on the scan data and the first count value.
[0030] Optionally, the chip is configured with a storage built-in self-test mode, and the scan data acquisition module includes:
[0031] A first storage built-in self-test mode entry instruction generation submodule, used to generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0032] A first storage built-in self-test logic operation execution submodule, used for controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation;
[0033] A reset counter stop submodule, used to stop the reset counter when it is determined that the storage unit has a fault;
[0034] The first count value acquisition submodule is used to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter.
[0035] Optionally, the storage unit is configured with a corresponding error count counter.
[0036] Optionally, the chip is configured with a storage built-in self-test mode, and the scan data acquisition module includes:
[0037] a second storage built-in self-test mode entry instruction generating submodule, used for generating a storage built-in self-test mode entry instruction, and using the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0038] a second storage built-in self-test logic operation execution submodule, used for controlling the storage unit to execute the storage built-in self-test logic operation in the storage built-in self-test mode, and judging whether the storage unit has a fault through the storage built-in self-test logic operation;
[0039] A reset counter and error number counter stop submodule, used to stop the reset counter and the error number counter when it is determined that the storage unit has a fault;
[0040] A first count value acquisition unit, configured to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter;
[0041] The second count value acquisition submodule is used to read the second count value through the error number counter.
[0042] Optionally, it also includes:
[0043] The storage built-in self-test logic operation restart submodule is used to start the reset counter and continue to execute the storage built-in self-test logic operation when the second count value does not reach a preset threshold.
[0044] Optionally, it also includes:
[0045] The storage built-in self-test logic operation stopping submodule is used to stop executing the storage built-in self-test logic operation when the second count value reaches a preset threshold.
[0046] An embodiment of the present invention also discloses a chip, including a storage unit; the storage unit is configured with corresponding registers and a reset counter, the chip is configured with a scanning mode, and a corresponding joint test behavior organization interface, and the chip is used to implement the method described in the embodiment of the present invention when detecting the storage unit.
[0047] The embodiment of the present invention further discloses an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;
[0048] The memory is used to store computer programs;
[0049] The processor is used to implement the method described in the embodiment of the present invention when executing the program stored in the memory.
[0050] The embodiment of the present invention further discloses a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the method described in the embodiment of the present invention.
[0051] The embodiments of the present invention include the following advantages:
[0052] In an embodiment of the present invention, a scan mode entry instruction is generated, and the joint test behavior organization interface is called to control the chip to enter the scan mode based on the scan mode entry instruction; in the scan mode, a scan chain for the storage unit is generated through the register; the scan chain includes a first storage built-in self-test scan chain for the native storage unit generated according to the register, and a second storage built-in self-test scan chain for the customized storage unit; when it is determined that the storage unit has a fault, scan data for the storage unit is obtained through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is obtained through the reset counter; the storage unit is detected based on the scan data and the first count value, so that a plurality of diagnostic modes can be provided for detecting the storage unit, thereby improving the detection efficiency of the on-chip storage unit.
[0053] Furthermore, the chip can be freely switched between multiple modes under MBIST, thereby further improving the detection efficiency of on-chip registers.
[0054] Furthermore, when the chip is in scan mode, the diagnosis mechanism can be implemented based on the MBIST scan chain of the standard RAM and the MBIST scan chain of the customized RAM respectively, thereby improving the detection accuracy of the register. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] Figure 1 is a flowchart of a method for detecting a memory unit of a chip provided in an embodiment of the present invention;
[0056] Figure 2 It is a schematic flow chart of a detection method for a memory unit of a chip provided in an embodiment of the present invention;
[0057] Figure 3 is a structural block diagram of a detection device for a memory unit of a chip provided in an embodiment of the present invention;
[0058] Figure 4 It is a hardware structure block diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0059] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0060] Mbist is the abbreviation of memory build-in-self test, which means memory built-in self test.
[0061] The main reasons for doing built-in self-test are:
[0062] Reduce test costs - Modern chips integrate more memory cells in a smaller area. The test cost of external test equipment ATE is too high and it is not suitable for externally injecting test vectors for memory.
[0063] The particularity of memory testing: there are many units that need to be tested, but they are distributed regularly, and algorithms can be used to generate test vectors in batches.
[0064] The need for online testing - the safety requirements for chips are gradually increasing. For example, automotive electronic chips need to be tested online while the chip is running (that is, they do not rely on test machines, but can be integrated at the board level, in the chip, or called by software to achieve testing anytime and anywhere) to eliminate possible faults at any time.
[0065] As can be seen from the above, storage built-in self-test is one of the most effective methods for testing on-chip memory. This method uses built-in self-test state machines, logic and algorithms to issue read, write and other access requests to storage units. The on-chip memory integrates many storage units and is distributed regularly. Many accesses to the on-chip memory are high-frequency access requests. Relying only on the external test machine ATE to use a low-speed clock to move in external test vectors beat by beat, the test time is long, the test efficiency is low, and the test cost is high. For MBIST operation, you only need to configure the BIST test instructions from the ATE machine through the standard JTAG test interface, and then obtain the BIST test results through the TDO port and collect observations. MBIST test technology has been widely used in high-performance and high-frequency processors.
[0066] The memory built-in self-test technology can effectively identify on-chip memory failures. If there is a faulty RAM and the RAM cannot be repaired, the chip is unusable. If there is a faulty RAM and the RAM can be repaired, the chip is usable. Repair means that the RAM has redundant storage units. When a row or column of the RAM fails, the redundant row or column can be read and written to replace the faulty row or column without affecting the correct access to the RAM. However, due to the area of the RAM, each RAM has relatively few redundant units, and only a few RAM failures can be repaired. When the RAM failure cannot be repaired, if it is necessary to further analyze the specific information of the faulty RAM during the chip production process, such as the faulty address, faulty data bits, and operations at the time of the error, the MBIST diagnostic mechanism needs to be implemented.
[0067] In view of the above problems, the related art implements different diagnostic mechanisms for different MBIST codes. One type of MBIST diagnostic mechanism can only diagnose a certain RAM of the entire chip at a time. During diagnosis, through the standard JTAG interface, first use user-defined instructions to make the MBIST state machine enter the RAM group selection mode. In the RAM group selection mode, the group to be diagnosed in multiple RAM groups is selected by shifting the JTAG BIST chain. Then use user-defined instructions to make the MBIST state machine enter the RAM block selection mode. In the RAM block selection mode, a certain RAM block to be diagnosed in the RAM group to be diagnosed is selected by shifting the JTAG BIST chain. Then use user-defined instructions to perform MBIST operations in diagnostic mode. After the MBIST operation in diagnostic mode is completed, the user-defined instructions are configured through the standard JTAG interface, and the TDO port is used to shift out the RAM diagnosis related information bit by bit for observation. This diagnostic method can only diagnose a certain RAM on the chip at a time, and can only observe the information of a certain RAM failure.
[0068] Another type of MBIST diagnostic mechanism has a low implementation cost and is more flexible. This type of diagnostic mechanism chains the MBIST internal registers of each RAM in sequence. The MBIST internal registers between different RAMs can be chained in sequence or bypassed. For bypassed RAMs, the MBIST internal registers are not on the diagnostic chain. The diagnostic-related registers mainly include the diagnostic enable register, the ERROR counter, and the BIST_SETUP register. When the diagnostic enable register is shifted to 1, the MBIST diagnostic function is enabled. Configuring the BIST_SETUP register can enable MBIST to enter the diagnostic mode, and configuring the ERROR register is used to terminate the MBIST operation. First, use the user-defined diagnostic instruction to make the MBIST state machine enter the diagnostic mode. Then, through the JTAG TDI port, shift the MBIST internal register to the given value to enable the diagnostic function, and then use the user-defined instruction to start the BIST operation in the diagnostic mode. When the number of faults encountered during MBIST execution reaches the ERROR value, MBIST pauses and the value of the diagnostic register is shifted out bit by bit through the standard JTAG TDO port. The values of the diagnostic register can be collected to analyze the address, data, and read / write status of the RAM fault.
[0069] As can be seen from the above, the MBIST diagnostic function adopted by the related art needs to add additional diagnostic-related registers and move the internal registers in and out of the chain, which has certain hardware overhead, thereby increasing the hardware cost pressure. Some MBIST diagnostic mechanisms can only diagnose the fault of a RAM at a time, with large diagnostic overhead and weak diagnostic ability; some MBIST diagnostic mechanisms, in order to realize the diagnostic function, need to string all the internal registers of MBIST into a chain, and each register adds an additional set of selection signals, and the MBIST control state is also much more complicated.
[0070] The embodiment of the present invention provides a method for diagnosing storage unit faults based on storage built-in self-test. In order to improve processor performance, the register stack, memory access queue and other units inside the processor are implemented by a customized storage method. With the large scale, high frequency and advanced technology of chips, the failure rate of storage units is getting higher and higher. In order to better test chips, the embodiment of the present invention can implement the MBIST mechanism for storage units. After the MBIST mechanism is enabled, the storage unit will be read and written according to the implemented BIST algorithm, and the read and write addresses will traverse the entire storage unit. When the storage unit fails, it is necessary to further analyze the state, address, data, operation and other contents at the time of the error to locate the fault. Therefore, the embodiment of the present invention proposes a mechanism for customized unit storage built-in self-test diagnosis. The mechanism multiplexes the DFT scan chain of the storage unit, and the method implements a diagnostic trigger mechanism, realizes the collection and observation of diagnostic information, and realizes that BIST continues to be executed after diagnosis, without adding additional diagnostic registers, thereby avoiding additional hardware costs. At the same time, it also avoids stringing all registers inside MBIST into a chain, thereby improving MBIST control efficiency.
[0071] In order to enable those skilled in the art to better understand the embodiments of the present invention, some technical terms involved in the embodiments of the present invention are explained below.
[0072] Random Access Memory (RAM), also known as main memory, is an internal memory that directly exchanges data with the CPU. It can be read and written at any time (except when refreshed) and is very fast. It is usually used as a temporary data storage medium for the operating system or other running programs.
[0073] ATE is the abbreviation of Automatic Test Equipment. In the semiconductor industry, it refers to an integrated circuit (IC) automatic test machine, which is used to detect the integrity of the integrated circuit function. It is the final process of integrated circuit manufacturing to ensure the quality of integrated circuit manufacturing.
[0074] JTAG is the abbreviation of Joint Test Action Group, which is the common name of the IEEE standard 1149.1 called Standard Test Access Port and Boundary Scan Architecture. This standard is used to verify the functionality of the designed and tested printed circuit boards.
[0075] BIST (Built-in Self Test) is a technology that implants relevant functional circuits into the circuit during design to provide self-test functions, thereby reducing the dependence of device testing on automatic test equipment (ATE).
[0076] Test Data Output (TDO), TDO is mandatory in the IEEE1149.1 standard. TDO is the interface for data output. All data to be output from a specific register is output serially one bit at a time through the TDO interface (driven by TCK).
[0077] Reference Figure 1 , shows a flowchart of a method for detecting a memory unit of a chip provided in an embodiment of the present invention, which may specifically include the following steps:
[0078] Step 101, generating a scan mode entry instruction, and calling the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction;
[0079] Step 102, in the scan mode, generating a scan chain for the storage unit through the register; the scan chain includes generating a first storage built-in self-test scan chain for the native storage unit according to the register, and a second storage built-in self-test scan chain for the custom storage unit;
[0080] Step 103, when it is determined that the storage unit has a fault, obtaining scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and obtaining a first count value through the reset counter;
[0081] Step 104: Detect the storage unit based on the scan data and the first count value.
[0082] In a specific implementation, the embodiment of the present invention can be applied to a storage built-in self test MBIST.
[0083] Scan chain is a testability design implementation technology. It allows testers to control and observe the signal value of the internal trigger of the circuit from the outside by implanting a shift register.
[0084] In a specific implementation, an embodiment of the present invention can configure registers for a storage unit RAM. Exemplarily, the registers can be built-in self-test related registers, and the built-in self-test related registers are strung together into a scan chain to achieve subsequent generation of ATPG (Automatic test pattern generation) vectors to test the chip.
[0085] The chip of the embodiment of the present invention can have multiple modes, including a scan mode scanmode. The embodiment of the present invention can generate a scan mode entry instruction, which can be used to control the chip to enter the scan mode. The embodiment of the present invention can determine the scan chain for the register in the scan mode.
[0086] Exemplarily, a corresponding joint test behavior organization interface, ie, a JTAG interface, may be configured for the chip. After a scan mode entry instruction is generated, the chip may be controlled to enter the scan mode based on the scan mode entry instruction through the joint test behavior organization interface.
[0087] By generating a scan mode entry instruction and calling the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction, the chip can be freely switched in multiple modes under MBIST, thereby further improving the detection efficiency of on-chip registers.
[0088] In the scanning mode, the embodiment of the present invention can generate a first storage built-in self-test scan chain for native storage units and a second storage built-in self-test scan chain for the customized storage units by generating a first storage built-in self-test scan chain for native storage units and a second storage built-in self-test scan chain for the customized storage units for registers. In practical applications, the storage units may include native storage units and customized storage units, the native storage units may be standard RAMs provided by process manufacturers, and the customized storage units may be RAMs customized according to user requirements. The functions of native storage units and customized storage units are quite different, and customized storage units are also more prone to failure. Therefore, the embodiment of the present invention can adopt different processing methods for memory RAMs with different functions during the scan chain operation, by generating a first storage built-in self-test scan chain for native storage units and a second storage built-in self-test scan chain for customized storage units for registers, that is, the MBIST-related registers of the standard RAM can be separately strung into a scan chain, and the MBIST-related registers of the customized storage units can be separately strung into a scan chain, thereby creating a prerequisite for the subsequent generation of independent scan data, a first count value, and a second count value for different scan chains, and also realizing that when the chip is in the scanning mode, the diagnosis mechanism can be implemented based on the MBIST scan chain of the standard RAM and the MBIST scan chain of the customized RAM, respectively, thereby improving the detection accuracy of the registers.
[0089] The embodiment of the present invention can also configure a corresponding reset counter bist_counter for the built-in self-test logic of the storage unit. When it is determined that the storage unit has a fault, scan data for the storage unit can be obtained through the scan chain, and a first count value can be obtained by resetting the counter bist_counter, wherein the scan data can be used to express the fault information of the storage unit, the first count value can express the moment when the built-in self-test logic of the storage unit fails, and the first count value can be used for on-chip diagnosis of the storage unit fault.
[0090] After obtaining the scan data and the first count value, the embodiment of the present invention can detect the storage unit based on the scan data and the first count value. For example, since the first count value can directly locate the moment when the fault occurs when executing MBIST, when the user has the chip source code, the first count value can be used to perform fault analysis based on the source code to diagnose the storage unit. However, in actual applications, since not all users have the chip source code, and not all users are familiar with debugging the storage unit based on the source code, considering that the diagnosis method of the storage unit using the first count value is not universal, the scan data can also be directly used to diagnose the storage unit.
[0091] In an embodiment of the present invention, a scan mode entry instruction is generated, and the joint test behavior organization interface is called to control the chip to enter the scan mode based on the scan mode entry instruction; in the scan mode, a scan chain for the storage unit is generated through the register; the scan chain includes a first storage built-in self-test scan chain for the native storage unit generated according to the register, and a second storage built-in self-test scan chain for the customized storage unit; when it is determined that the storage unit has a fault, scan data for the storage unit is obtained through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is obtained through the reset counter; the storage unit is detected based on the scan data and the first count value, so that a plurality of diagnostic modes can be provided for detecting the storage unit, thereby improving the detection efficiency of the on-chip storage unit.
[0092] Furthermore, the chip can be freely switched between multiple modes under MBIST, thereby further improving the detection efficiency of on-chip registers.
[0093] Furthermore, when the chip is in scan mode, the diagnosis mechanism can be implemented based on the MBIST scan chain of the standard RAM and the MBIST scan chain of the customized RAM respectively, thereby improving the detection accuracy of the register.
[0094] Based on the above embodiment, a variant embodiment of the above embodiment is proposed. It should be noted that in order to make the description concise, only the differences from the above embodiment are described in the variant embodiment.
[0095] In an optional embodiment of the present invention, the chip is configured with a storage built-in self-test mode, and when it is determined that the storage unit has a fault, the step of acquiring scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquiring a first count value through the reset counter comprises:
[0096] Generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0097] Controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation;
[0098] When it is determined that the storage unit has a fault, stopping the reset counter;
[0099] Scan data for the storage unit is acquired through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is acquired through the reset counter.
[0100] In a specific implementation, the chip according to the embodiment of the present invention may also be configured to store a built-in self-test mode bistmode.
[0101] Exemplarily, a corresponding joint test behavior organization interface, i.e., a JTAG interface, can be configured for the chip. After generating a storage built-in self-test mode entry instruction, the chip can be controlled to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction through the joint test behavior organization interface, and the storage unit can be controlled to perform the storage built-in self-test logic operation in the storage built-in self-test mode. During the execution of the MBIST operation, if a faulty RAM is found and the relevant information of the faulty RAM needs to be moved out for observation, specifically, the reset counter can be stopped, and a scan mode entry instruction can be regenerated through the standard JTAG interface. In the scan mode, the MBIST scan chain data of the native storage unit and the MBIST scan chain data of the customized storage unit are moved out for observation. The main observation information can include MBIST state machine related registers, RAM access operations, RAM access addresses, RAM error bits, the first count value of the reset counter bist_counter, etc. At this point, the fault information for the RAM has been determined, as well as the first count value used to locate the moment of failure when executing MBIST, so that the storage unit RAM of the chip can be detected based on multiple diagnostic modes.
[0102] According to an embodiment of the present invention, a storage built-in self-test mode entry instruction is generated, and the joint test behavior organization interface is used to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction; the storage unit is controlled to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and whether the storage unit has a fault is determined by the storage built-in self-test logic operation; when it is determined that the storage unit has a fault, the reset counter is stopped; scan data for the storage unit is obtained by the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is obtained by the reset counter, thereby realizing the execution of a logic self-test on the storage unit in the storage built-in self-test mode, thereby further improving the detection efficiency of the storage unit.
[0103] In an optional embodiment of the present invention, the storage unit is configured with a corresponding error count counter.
[0104] In a specific implementation, in addition to configuring a reset counter bist_counter to the storage unit RAM, the embodiment of the present invention can also configure an error counter error_counter to the storage unit RAM, which can also be referred to as error_cnt in practical applications. Specifically, the error counter error_counter can be configured before bist is executed, and the error counter error_counter can be used as a clock gating unit to stop the MBIST operation according to preset requirements through its enable terminal, thereby further improving the detection efficiency of the on-chip register.
[0105] In an optional embodiment of the present invention, the chip is configured with a storage built-in self-test mode, and when it is determined that the storage unit has a fault, the step of acquiring scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquiring a first count value through the reset counter comprises:
[0106] Generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0107] Controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation;
[0108] When it is determined that the storage unit has a fault, stopping the reset counter and the error count counter;
[0109] Acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter;
[0110] The second count value is read through the error number counter.
[0111] Exemplarily, a corresponding joint test behavior organization interface, i.e., a JTAG interface, can be configured for the chip. After generating a storage built-in self-test mode entry instruction, the chip can be controlled to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction through the joint test behavior organization interface, and the storage unit can be controlled to perform storage built-in self-test logic operations in the storage built-in self-test mode. During the execution of the MBIST operation, if a faulty RAM is found and the relevant information of the faulty RAM needs to be removed for observation, the reset counter and the error count counter can be stopped, and the scan mode entry instruction can be generated again through the standard JTAG interface. In the scan mode, the MBIST scan chain data of the native storage unit and the MBIST scan chain data of the customized storage unit are scanned. Chain data is shifted out for observation, and the main observation information may include MBIST state machine related registers, RAM access operations, RAM access addresses, RAM error bits, the first count value of the reset counter bist_counter, the second count value of the error number counter error_counter, etc. At this point, the fault information for the RAM has been determined, as well as the first count value for locating the moment of failure when executing MBIST, so that the storage unit RAM of the chip can be detected based on multiple diagnostic modes. At the same time, after completing the detection of the on-chip registers, the second count value of the error for the error number counter can be read, and the second count value can be used to control the subsequent execution of the storage built-in self-test logic operation.
[0112] According to an embodiment of the present invention, a storage built-in self-test mode entry instruction is generated, and the joint test behavior organization interface is used to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction; the storage unit is controlled to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and whether the storage unit has a fault is determined by the storage built-in self-test logic operation; when it is determined that the storage unit has a fault, the reset counter and the error count counter are stopped; scan data for the storage unit is obtained by the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is obtained by the reset counter; the second count value is read by the error count counter, so that on the basis of realizing the execution of logic self-test on the storage unit in the storage built-in self-test mode, a prerequisite is provided for the subsequent control of the execution of the storage built-in self-test logic operation by reading the second count value, thereby further improving the detection efficiency of the storage unit.
[0113] In an optional embodiment of the present invention, when the second count value does not reach a preset threshold, the reset counter is started and the storage built-in self-test logic operation continues to be executed.
[0114] Exemplarily, a corresponding joint test behavior organization interface, i.e., a JTAG interface, can be configured for the chip. After generating a storage built-in self-test mode entry instruction, the chip can be controlled to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction through the joint test behavior organization interface, and the storage unit can be controlled to perform the storage built-in self-test logic operation in the storage built-in self-test mode. During the execution of the MBIST operation, if a faulty RAM is found and the related information of the faulty RAM needs to be moved out of observation, the reset counter and the error count counter can be stopped, and a scan mode entry instruction can be generated again through the standard JTAG interface. In the scan mode, the MBIST scan chain data of the native storage unit and the MBIST scan chain data of the customized storage unit are moved out of observation. The main observation information can include MBIST. BIST state machine related registers, RAM access operations, RAM access addresses, RAM error bits, the first count value of the reset counter bist_counter, the second count value of the error number counter error_counter, etc., have now determined the fault information for the RAM, as well as the first count value for locating the moment of failure when executing MBIST, so that the memory unit RAM of the chip can be detected based on a variety of diagnostic modes. At the same time, after completing the detection of the on-chip registers, the second count value of the error for the error number counter can be read, and when the second count value reaches a preset threshold, it is determined that the storage built-in self-test logic operation needs to be continued, and the reset counter can be started, and the storage built-in self-test logic operation can be continued.
[0115] In the embodiment of the present invention, when the second count value does not reach the preset threshold value, it is determined that the storage built-in self-test logic operation needs to be continued, and the reset counter can be started, and the storage built-in self-test logic operation can be continued. Thus, under the premise of being able to provide multiple diagnostic modes for detecting the storage unit, the storage built-in self-test logic operation can be automatically continued, thereby further improving the detection efficiency of the on-chip register.
[0116] In an optional embodiment of the present invention, when the second count value reaches a preset threshold, the storage built-in self-test logic operation is stopped.
[0117] Exemplarily, a corresponding joint test behavior organization interface, i.e., a JTAG interface, can be configured for the chip. After generating a storage built-in self-test mode entry instruction, the chip can be controlled to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction through the joint test behavior organization interface, and the storage unit can be controlled to perform storage built-in self-test logic operations in the storage built-in self-test mode. During the execution of the MBIST operation, if a faulty RAM is found and the related information of the faulty RAM needs to be moved out for observation, the reset counter and the error count counter can be stopped, and the scan mode entry instruction can be generated again through the standard JTAG interface. In the scan mode, the MBIST scan chain data of the native storage unit and the MBIST scan chain data of the customized storage unit are moved out for observation. The main observation information It can include MBIST state machine related registers, RAM access operations, RAM access addresses, RAM error bits, a first count value of a reset counter bist_counter, a second count value of an error number counter error_counter, etc. So far, fault information for the RAM has been determined, as well as a first count value for locating the moment of failure when executing MBIST, so that the storage unit RAM of the chip can be detected based on a variety of diagnostic modes. At the same time, after completing the detection of the on-chip register, the second count value of the error for the error number counter can be read, and when the second count value reaches a preset threshold, it is determined that there is no need to continue to execute the storage built-in self-test logic operation, and the execution of the storage built-in self-test logic operation can be stopped.
[0118] The embodiment of the present invention stops executing the storage built-in self-test logic operation when the second count value reaches a preset threshold value, thereby achieving the ability to automatically stop executing the storage built-in self-test logic operation while providing multiple diagnostic modes for detecting the storage unit, thereby further improving the detection efficiency of the on-chip register.
[0119] In order to enable those skilled in the art to better understand the embodiments of the present invention, a complete example is used below to illustrate the embodiments of the present invention.
[0120] refer to Figure 2 , Figure 2 It is a flow chart of a detection method for a memory unit of a chip provided in an embodiment of the present invention.
[0121] The chip registers can be strung together into a scan chain, and ATPG (Automatic test pattern generation) vectors can be generated later to test the chip, thereby realizing the scan chain operation. When the scan chain operation is implemented, registers with different functions are processed differently, and the MBIST-related registers are strung together into a scan chain separately, and the MBIST registers of the storage unit in the MBIST register are strung together into a scan chain separately. The implemented diagnostic mechanism can be implemented separately based on the MBIST scan chain of the standard native RAM and the MBIST scan chain of the customized storage unit.
[0122] Through the standard JTAG interface, using custom instructions, the chip can switch freely between scan mode (scanmode) and storage built-in self-test mode (bistmode). Through the standard JTAG interface, first configure the scanmode instruction to enter the scan mode.
[0123] In the scanning mode, the MBIST scan chain of the native RAM and the MBIST scan chain of the customized storage unit are shifted by bits, and the corresponding values are assigned to the registers related to diagnosis, mainly two groups of registers, bist_counter counter and error_counter counter.
[0124] After the shift assignment is completed, the bistmode instruction is configured through the standard JTAG interface to perform MBIST logic operations in the built-in self-test mode and issue read and write requests to the RAM.
[0125] During the execution of the MBIST operation, if a faulty RAM is found and the relevant information of the faulty RAM needs to be moved out for observation, it is necessary to configure the scanmode instruction through the standard JTAG interface, and move the MBIST scan chain data of the native storage unit and the MBIST scan chain data of the customized storage unit out for observation in the scan mode. The main observation information includes the MBIST state machine related registers, the operation of accessing RAM, the RAM access address, the RAM error bit, the value of the bist_counter counter, etc.
[0126] For realizing the diagnostic function, can realize counting mechanism inside MBIST code, this mechanism can accurately count the number of clock cycles that MBIST has performed when MBIST makes mistakes.For example, this counting mechanism starts counting from MBIST reset end, and every clock cycle, this counting mechanism adds one.This counting mechanism uses the width of register relevant with MBIST execution time length, and MBIST execution time is relevant with the size of RAM again.When MBIST resets, counting mechanism resets to 0, and when diagnosing by scan chain shift at first, the shift-in zero value of this counting mechanism is also zero.
[0127] To realize the diagnostic function, an error_cnt counter can be added inside the MBIST code to indicate that the MBIST operation needs to be stopped when the RAM fault is detected. The value of error_cnt is 0 during reset, indicating that the MBIST operation is stopped when a fault of RAM access is encountered. The error_cnt register is placed on the MBIST scan chain, and the register is shifted into the value to be configured when the diagnosis is initially shifted by the scan chain. For example, after the MBIST performs the operation, each RAM fault occurs, the error_cnt counter is reduced by 1, and when the error_cnt counter value is 0 and the RAM accesses an error again, the MBIST operation stops, and the value of the MBIST internal register remains unchanged. The MBIST operation stops in the diagnostic mode and is realized by turning off the MBIST clock. After the clock stops, the state of the entire MBIST remains unchanged, and the value of the register remains unchanged. To turn off the clock, the present invention adds a clock gating unit, which controls the clock by controlling the gating unit enable end. When MBIST makes a mistake and error_cnt is 0, the clock is turned off.
[0128] In the above manner, there is no need to add additional diagnostic-related registers, reuse the MBIST internal registers on the DFT scan chain, and there is no need to connect the MBIST internal registers to the additional diagnostic chain. This method can diagnose multiple RAM faults at the same time, and different diagnostic configurations can be made for different RAMs, thereby achieving the effect of efficiently detecting on-chip registers.
[0129] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.
[0130] An embodiment of the present invention also discloses a chip, including a storage unit; the storage unit is configured with corresponding registers and a reset counter, the chip is configured with a scanning mode, and a corresponding joint test behavior organization interface, and the chip is used to implement the method described in the embodiment of the present invention when detecting the storage unit.
[0131] As for the chip embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0132] Reference Figure 3 , shows a structural block diagram of a detection device for a memory unit of a chip provided in an embodiment of the present invention, which may specifically include the following modules:
[0133] A scan mode entry instruction generation module 301 is used for generating a scan mode entry instruction and calling the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction;
[0134] A scan chain generation module 302, configured to generate a scan chain for the storage unit through the register in the scan mode; the scan chain includes generating a first storage built-in self-test scan chain for the native storage unit according to the register, and a second storage built-in self-test scan chain for the custom storage unit;
[0135] a scan data acquisition module 303, configured to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain when it is determined that the storage unit has a fault, and acquire a first count value through the reset counter;
[0136] The storage unit detection module 304 is used to detect the storage unit based on the scan data and the first count value.
[0137] Optionally, the chip is configured with a storage built-in self-test mode, and the scan data acquisition module includes:
[0138] A first storage built-in self-test mode entry instruction generation submodule, used to generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0139] A first storage built-in self-test logic operation execution submodule, used for controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation;
[0140] A reset counter stop submodule, used to stop the reset counter when it is determined that the storage unit has a fault;
[0141] The first count value acquisition submodule is used to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter.
[0142] Optionally, the storage unit is configured with a corresponding error count counter.
[0143] Optionally, the chip is configured with a storage built-in self-test mode, and the scan data acquisition module includes:
[0144] a second storage built-in self-test mode entry instruction generating submodule, used for generating a storage built-in self-test mode entry instruction, and using the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction;
[0145] a second storage built-in self-test logic operation execution submodule, used for controlling the storage unit to execute the storage built-in self-test logic operation in the storage built-in self-test mode, and judging whether the storage unit has a fault through the storage built-in self-test logic operation;
[0146] A reset counter and error number counter stop submodule, used to stop the reset counter and the error number counter when it is determined that the storage unit has a fault;
[0147] A first count value acquisition unit, configured to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter;
[0148] The second count value acquisition submodule is used to read the second count value through the error number counter.
[0149] Optionally, it also includes:
[0150] The storage built-in self-test logic operation restart submodule is used to start the reset counter and continue to execute the storage built-in self-test logic operation when the second count value does not reach a preset threshold.
[0151] Optionally, it also includes:
[0152] The storage built-in self-test logic operation stopping submodule is used to stop executing the storage built-in self-test logic operation when the second count value reaches a preset threshold.
[0153] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0154] In addition, an embodiment of the present invention further provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned detection method embodiment for the memory unit of the chip are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.
[0155] The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned detection method embodiment for the storage unit of the chip is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0156] Figure 4 A schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention.
[0157] The electronic device 400 includes but is not limited to: a radio frequency unit 401, a network module 402, an audio output unit 403, an input unit 404, a sensor 405, a display unit 406, a user input unit 407, an interface unit 408, a memory 409, a processor 410, and a power supply 411. Those skilled in the art will appreciate that Figure 4 The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. In the embodiments of the present invention, the electronic device includes but is not limited to a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted terminal, a wearable device, and a pedometer.
[0158] It should be understood that in the embodiment of the present invention, the radio frequency unit 401 can be used for receiving and sending signals during information transmission or communication. Specifically, after receiving downlink data from the base station, it is sent to the processor 410 for processing; in addition, uplink data is sent to the base station. Generally, the radio frequency unit 401 includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, etc. In addition, the radio frequency unit 401 can also communicate with the network and other devices through a wireless communication system.
[0159] The electronic device provides users with wireless broadband Internet access through the network module 402, such as helping users to send and receive emails, browse web pages, and access streaming media.
[0160] The audio output unit 403 can convert the audio data received by the RF unit 401 or the network module 402 or stored in the memory 409 into an audio signal and output it as sound. Moreover, the audio output unit 403 can also provide audio output related to a specific function performed by the electronic device 400 (for example, a call signal reception sound, a message reception sound, etc.). The audio output unit 403 includes a speaker, a buzzer, a receiver, etc.
[0161] The input unit 404 is used to receive audio or video signals. The input unit 404 may include a graphics processor (GPU) 4041 and a microphone 4042, and the graphics processor 4041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The processed image frame can be displayed on the display unit 406. The image frame processed by the graphics processor 4041 can be stored in the memory 409 (or other storage medium) or sent via the radio frequency unit 401 or the network module 402. The microphone 4042 can receive sound and can process such sound into audio data. The processed audio data can be converted into a format output that can be sent to a mobile communication base station via the radio frequency unit 401 in the case of a telephone call mode.
[0162] The electronic device 400 also includes at least one sensor 405, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 4061 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 4061 and / or the backlight when the electronic device 400 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally three axes), and can detect the magnitude and direction of gravity when stationary, which can be used to identify the posture of the electronic device (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc.; the sensor 405 can also include a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, etc., which will not be repeated here.
[0163] The display unit 406 is used to display information input by the user or information provided to the user. The display unit 406 may include a display panel 4061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.
[0164] The user input unit 407 can be used to receive input digital or character information, and to generate key signal input related to user settings and function control of the electronic device. Specifically, the user input unit 407 includes a touch panel 4071 and other input devices 4072. The touch panel 4071, also known as a touch screen, can collect the user's touch operation on or near it (such as the user's operation on the touch panel 4071 or near the touch panel 4071 using any suitable object or accessory such as a finger, stylus, etc.). The touch panel 4071 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the contact point coordinates, and then sends it to the processor 410, receives the command sent by the processor 410 and executes it. In addition, the touch panel 4071 can be implemented using various types such as resistive, capacitive, infrared and surface acoustic waves. In addition to the touch panel 4071, the user input unit 407 may also include other input devices 4072. Specifically, other input devices 4072 may include but are not limited to a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail here.
[0165] Furthermore, the touch panel 4071 may be overlaid on the display panel 4061. When the touch panel 4071 detects a touch operation on or near it, it is transmitted to the processor 410 to determine the type of the touch event. Then, the processor 410 provides a corresponding visual output on the display panel 4061 according to the type of the touch event. Figure 4 In the figure, the touch panel 4071 and the display panel 4061 are two independent components to realize the input and output functions of the electronic device. However, in some embodiments, the touch panel 4071 and the display panel 4061 can be integrated to realize the input and output functions of the electronic device, which is not limited here.
[0166] The interface unit 408 is an interface for connecting an external device to the electronic device 400. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, etc. The interface unit 408 may be used to receive input (e.g., data information, power, etc.) from an external device and transmit the received input to one or more elements within the electronic device 400 or may be used to transmit data between the electronic device 400 and an external device.
[0167] The memory 409 can be used to store software programs and various data. The memory 409 can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the memory 409 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.
[0168] The processor 410 is the control center of the electronic device. It uses various interfaces and lines to connect various parts of the entire electronic device. It executes various functions of the electronic device and processes data by running or executing software programs and / or modules stored in the memory 409, and calling data stored in the memory 409, so as to monitor the electronic device as a whole. The processor 410 may include one or more processing units; preferably, the processor 410 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 410.
[0169] The electronic device 400 may also include a power supply 411 (such as a battery) for supplying power to each component. Preferably, the power supply 411 may be logically connected to the processor 410 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system.
[0170] In addition, the electronic device 400 includes some functional modules not shown, which will not be described in detail here.
[0171] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0172] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.
[0173] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.
[0174] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.
[0175] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0176] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0177] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0178] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0179] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical disks.
[0180] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A method for detecting a memory cell of a chip, characterized in that: The storage unit is configured with a corresponding register and a reset counter, the chip is configured with a scan mode, and a corresponding joint test behavior organization interface, and the method includes: Generate a scan mode entry instruction, and call the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction; In the scan mode, a scan chain for the storage unit is generated through the register; the scan chain includes a first storage built-in self-test scan chain for the native storage unit generated according to the register, and a second storage built-in self-test scan chain for the custom storage unit; When it is determined that the storage unit has a fault, obtaining scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and obtaining a first count value through the reset counter; The storage cell is detected based on the scan data and the first count value.
2. The method according to claim 1, characterized in that The chip is configured with a storage built-in self-test mode. When it is determined that the storage unit has a fault, the steps of obtaining scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and obtaining a first count value through the reset counter include: Generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction; Controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation; When it is determined that the storage unit has a fault, stopping the reset counter; Scan data for the storage unit is acquired through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and a first count value is acquired through the reset counter.
3. The method according to claim 1, characterized in that The storage unit is configured with a corresponding error count counter.
4. The method according to claim 3, characterized in that The chip is configured with a storage built-in self-test mode. When it is determined that the storage unit has a fault, the steps of obtaining scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and obtaining a first count value through the reset counter include: Generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction; Controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation; When it is determined that the storage unit has a fault, stopping the reset counter and the error count counter; Acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter; The second count value is read through the error number counter.
5. The method according to claim 4, characterized in that Also includes: When the second count value does not reach a preset threshold, the reset counter is started and the storage built-in self-test logic operation is continued.
6. The method according to claim 5, characterized in that Also includes: When the second count value reaches a preset threshold, the storage built-in self-test logic operation is stopped.
7. A detection device for a memory unit of a chip, characterized in that: The storage unit is configured with a corresponding register and a reset counter, the chip is configured with a scan mode, and a corresponding joint test behavior organization interface, and the device includes: A scan mode entry instruction generation module is used to generate a scan mode entry instruction and call the joint test behavior organization interface to control the chip to enter the scan mode based on the scan mode entry instruction; A scan chain generation module, configured to generate a scan chain for the storage unit through the register in the scan mode; the scan chain includes a first storage built-in self-test scan chain for the native storage unit generated according to the register, and a second storage built-in self-test scan chain for the custom storage unit; a scan data acquisition module, configured to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter when it is determined that the storage unit has a fault; The storage unit detection module is used to detect the storage unit based on the scan data and the first count value.
8. The device according to claim 7, characterized in that The chip is configured with a storage built-in self-test mode, and the scan data acquisition module includes: A first storage built-in self-test mode entry instruction generation submodule, used to generate a storage built-in self-test mode entry instruction, and use the joint test behavior organization interface to control the chip to enter the storage built-in self-test mode based on the storage built-in self-test mode entry instruction; A first storage built-in self-test logic operation execution submodule, used for controlling the storage unit to perform a storage built-in self-test logic operation in the storage built-in self-test mode, and determining whether the storage unit has a fault through the storage built-in self-test logic operation; A reset counter stop submodule, used to stop the reset counter when it is determined that the storage unit has a fault; The first count value acquisition submodule is used to acquire scan data for the storage unit through the first storage built-in self-test scan chain and the second storage built-in self-test scan chain, and acquire a first count value through the reset counter.
9. The device according to claim 7, characterized in that The storage unit is configured with a corresponding error count counter.
10. A chip comprising a storage unit, characterized in that: The storage unit is configured with corresponding registers and reset counters, the chip is configured with a scan mode and a corresponding joint test behavior organization interface, and the chip is configured to implement the method described in any one of claims 1-6 when detecting the storage unit.
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Chip problem positioning method and device, equipment, storage medium and product
CN122085094A