Wafer before semiconductor process and semiconductor chip manufacturing method using same

Abstract

A wafer includes a scribe lane surrounding a semiconductor chip region on one surface of a wafer body; and a stress adjusting portion in the scribe lane and including a first film and a second film having at least a material different from a material of the wafer body. A wafer may be provided prior to a semiconductor process.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0101181 filed on August 2, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to a wafer prior to a semiconductor process and / or a semiconductor chip manufacturing method using the wafer. Background Art

[0004] Recently, wafer warpage has increased due to an increase in the size (eg, diameter) of semiconductor wafers and / or process advancements. Increased wafer warpage in semiconductor processes may result in process risks (eg, defective chips) in final semiconductor chips.

[0005] Since the semiconductor wafer is a single crystal of Si, the wafer itself has no stress, but tensile stress and / or compressive stress occurring in stacked thin films during the process may accumulate, which may cause the wafer to warp.

[0006] In order to solve or at least partially address this problem, thin films of different materials are stacked on the back surface of the wafer to release tensile stress and / or compressive stress occurring in a semiconductor process such as deposition or etching.

[0007] This warpage mitigation method can handle warpage up to 150 μm, but the method is insufficient to handle warpage of 300 μm to 400 μm with high stress. When the thickness of the thin film stacked on the rear surface of the wafer exceeds a certain level, a wafer cracking phenomenon also occurs.

[0008] A method of reducing warpage by forming scribe lines on a wafer has also been proposed, but this method also has a problem in that it is difficult to actively respond to the warpage. Summary of the invention

[0009] Various example embodiments may provide a wafer before a semiconductor process having scribe streets in which different materials are buried to help reduce warpage occurring in the semiconductor process.

[0010] Alternatively or additionally, various example embodiments may provide a method of manufacturing a semiconductor chip capable of reducing warpage of a wafer prior to a semiconductor process by increasing tensile stress in response to positive warpage of the wafer occurring during the semiconductor process.

[0011] Alternatively or additionally, various example embodiments may provide a method of manufacturing a semiconductor chip capable of reducing warpage of a wafer before a semiconductor process by increasing compressive stress in response to negative warpage of the wafer occurring during the semiconductor process.

[0012] According to various example embodiments, a wafer includes: a wafer body; a scribe line surrounding a semiconductor chip region on one surface of the wafer body; and a stress adjustment portion in the scribe line and including a first film and a second film having a material different from at least a material of the wafer body.

[0013] Alternatively or additionally according to various example embodiments, a semiconductor chip manufacturing process includes: preparing a wafer before a semiconductor process, the wafer including at least a first film and a second film of at least different materials in a scribe line surrounding a semiconductor chip area; inserting the wafer into a semiconductor process chamber before the semiconductor process, and starting the semiconductor process in the process chamber; in response to positive warpage occurring in the wafer during the semiconductor process, etching the first film to generate tensile stress, the generated tensile stress at least partially alleviating the positive warpage; and completing the semiconductor process.

[0014] Alternatively or additionally according to various example embodiments, a semiconductor chip manufacturing process includes: preparing a wafer before a semiconductor process, the wafer including at least a first film and a second film of at least different materials in a scribe line surrounding a semiconductor chip area; inserting the wafer into a semiconductor process chamber before the semiconductor process, and starting the semiconductor process in the process chamber; in response to negative warpage occurring in the wafer during the semiconductor process, etching the second film to generate compressive stress, the generated compressive stress at least partially alleviating the negative warpage; and completing the semiconductor process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and advantages of various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a schematic plan view of a wafer before a semiconductor process according to some example embodiments.

[0017] Figure 2 yes Figure 1 An enlarged view of part A of FIG.

[0018] Figure 3 is along Figure 2 A cross-sectional view taken along line II' in FIG.

[0019] Figure 4 yes Figure 3 0 is an enlarged view of portion B in FIG. 1 and is a schematic diagram illustrating scribe lines in some example embodiments.

[0020] Figure 5 yes Figure 3 0 is an enlarged view of portion B in FIG. 1 and is a schematic diagram illustrating the scribe lines in some example embodiments.

[0021] Figure 6 yes Figure 3 0 is an enlarged view of portion B in FIG. 1 and is a schematic diagram illustrating scribe lines in some example embodiments.

[0022] Figure 7 yes Figure 3 0 is an enlarged view of portion B in FIG. 1 and is a schematic diagram illustrating scribe lines in some example embodiments.

[0023] Figure 8 is a flow chart of a semiconductor chip manufacturing process according to various example embodiments.

[0024] Fig. 9 It is shown Figure 8 Schematic diagram of the first film etching process (S40A).

[0025] Fig.10 is a flow chart of a semiconductor chip manufacturing process according to various example embodiments.

[0026] Fig.11 It is shown Fig.10 Schematic diagram of the second film etching process (S40B). DETAILED DESCRIPTION

[0027] Hereinafter, various example embodiments will be described with reference to the accompanying drawings.

[0028] Example embodiments may be modified to other forms and are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the shapes and / or sizes of elements may be exaggerated for clarity, and the same reference numerals represent the same elements.

[0029] In various exemplary embodiments, the meaning of a component being "connected" to another component includes an indirect connection through another element as well as a direct connection between two components. In addition, in some cases, the meaning of "connected" includes all "electrical connections".

[0030] It is understood that when an element is mentioned together with "first" and "second", the elements are not limited thereto. They may be used only for the purpose of distinguishing the element from other elements, and may not limit the order or importance of the elements. In some cases, the first element may be referred to as the second element without departing from the scope of the claims set forth herein. Similarly, the second element may also be referred to as the first element.

[0031] The terms used in the various exemplary embodiments are used to simply describe the examples and are not intended to limit the inventive concept. Unless otherwise indicated or clear from the context, a singular term includes a plural form.

[0032] Wafers before semiconductor processing

[0033] Figure 1 is a schematic plan view of a wafer before semiconductor processing according to various example embodiments, Figure 2 yes Figure 1 In addition, Figure 3 is along Figure 2 A cross-sectional view taken along line II' in FIG.

[0034] Reference Figures 1 to 3 , a wafer 100 before a semiconductor process according to various example embodiments includes a wafer body 110 , scribe lanes 120 , and a stress adjustment portion 150 .

[0035] The wafer 100 before the semiconductor process is the main body of the wafer before the semiconductor process is started, and the wafer 100 before the semiconductor process of the present invention is a thin crystalline silicon sheet grown from polycrystalline molten silicon in a specific direction. The wafer 100 before the semiconductor process may refer to a wafer before the semiconductor process is performed and after being transferred to a semiconductor process chamber. The size (e.g., diameter) of the wafer 100 is 50 mm to 300 mm or 450 mm, and its thickness is generally 0.5 mm to 1 mm, and in some example embodiments, the wafer 100 may be made thinner. The wafer 100 may include a flat portion (not shown) on its edge; example embodiments are not limited thereto.

[0036] When a semiconductor process is performed, thermal deformation of the wafer may occur, resulting in a bow phenomenon in which the middle of the wafer is convexly or concavely bent, resulting in poor flatness of the wafer. The flatness of the wafer is managed by reducing the occurrence of warpage. The warpage can be expressed as Warp = |RPDmax| - |RPDmin|, that is, the difference between the absolute value of the maximum value and the absolute value of the minimum value between the reference plane and the median plane of the wafer.

[0037] Here, RPDmax is the distance of the maximum convex deformation point from the center plane of the wafer, and RPDmin is the distance of the maximum concave deformation point from the center plane of the wafer.

[0038] For example, a positive (+) value of Warp is called +Warp, and a negative (-) value of Warp is called -Warp.

[0039] Because the flatness of the wafer is related to (e.g., directly related to) the quality of semiconductor chips after the semiconductor process and / or process yield, it may be important or desirable or necessary to manage the flatness of the wafer to prevent or reduce the possibility and / or impact of warping that occurs as the wafer becomes larger and / or thinner.

[0040] In order to prevent or reduce warpage during the semiconductor process, a scribing lane 120 is formed on the upper surface of the wafer body 110 before the semiconductor process. The upper surface may be a front side surface on which various semiconductor chips are to be manufactured. The scribing lane 120 is arranged to surround semiconductor chip forming areas SA1, SA2, SA3, ..., in which semiconductor chips are formed during the semiconductor process. The number of semiconductor chip forming areas SA1, SA2, SA3, ... is not limited to the number disclosed in the figure, and may be greater than or less than Figure 1 The semiconductor chip formation areas SA1, SA2, SA3, ... are subjected to processes such as exposure, deposition, and etching in a semiconductor process and then cut along scribe streets 120 to become semiconductor chips (devices).

[0041] The wafer body 110 may have a notch formed at one end to distinguish an upper position and a lower position in a semiconductor process, and directions may be defined in a horizontal direction (X direction) and a vertical direction (Y direction) based on the notch.

[0042] The scribe lanes 120 are recessed to surround the semiconductor chip in the horizontal direction (X direction) and the vertical direction (Y direction) to form regions SA1, SA2, SA3, ... The scribe lanes 120 include scribe lanes 122 in the vertical direction and scribe lanes 124 in the horizontal direction.

[0043] The stress regulating portion 150 is disposed in the scribe lane 120 to suppress or at least partially suppress or mitigate warpage that occurs due to thermal deformation during a semiconductor process. The stress regulating portion 150 is or includes a laminated thin film formed of a material different from that of the wafer body. When +warpage occurs in the wafer body 110 during a semiconductor process, the stress regulating portion 150 may generate a tensile stress to make the wafer body 110 flat or at least partially flat, and when -warpage occurs in the wafer body 110 during a semiconductor process, the stress regulating portion 150 may generate a compressive stress to make the wafer body 110 flat or at least partially flat.

[0044] Reference Figure 3, two vertical scribe lanes 122-1 and 122-2 are shown on the upper surface of the wafer body 110, and the semiconductor chip forming areas SA1, SA2, SA3, ... are arranged based on the scribe lanes 122-1 and 122-2. The stress adjustment portion 150 is stacked on the scribe lanes 122-1 and 122-2 and exposed to the upper surface of the wafer body 110. The stress adjustment portion 150 includes at least a first film 152 and a second film 154 formed of a material different from that of the wafer body 110, and the first film 152 and the second film 154 can be formed of different materials from each other. For example, the wafer body 110 can be formed of single crystal silicon such as doped single crystal silicon or undoped single crystal silicon, one of the first film 152 and the second film 154 can be formed of polycrystalline silicon such as doped polycrystalline silicon or undoped polycrystalline silicon, and the other of the first film 152 and the second film 154 can be formed of silicon dioxide (SiO2) in an amorphous phase. 2 )form.

[0045] The first film 152 may generate compressive stress due to its higher thermal expansion coefficient than the wafer body 110. In some example embodiments, the first film 152 may include polysilicon such as doped silicon or undoped silicon, and may not include silicon dioxide and / or single crystal silicon.

[0046] The second film 154 may generate tensile stress due to a lower thermal expansion coefficient than the wafer body 110. In some example embodiments, the second film 154 may include silicon dioxide (SiO 2 In some example embodiments, the second film 154 may not include single crystalline silicon or polycrystalline silicon.

[0047] In the deposition and / or growth of silicon dioxide (SiO 2 ), the thermal expansion coefficient at room temperature is 0.5 ppm, the thermal expansion coefficient of the wafer body 110 formed of Si is 2.6 ppm, and the thermal expansion coefficient at room temperature after the deposition of polysilicon is 3.0 ppm. Therefore, silicon dioxide may cause tensile stress when being deposited in the scribe lane 122 and / or growing in the scribe lane 122, and polysilicon causes compressive stress when being deposited in the scribe lane 122.

[0048] The tensile stress and the compressive stress of the first film 152 and the second film 154 may be balanced or at least partially balanced in the wafer 100 before the process, but the tensile stress or the compressive stress may occur when the volume is reduced by etching in the semiconductor process.

[0049] Although the example embodiment describes the inclusion of two materials, other materials may be added or repeatedly arranged in scribe lanes 122 .

[0050] Figure 4 yes Figure 3is an enlarged view of a portion B in FIG. 1 and is a schematic diagram showing the scribe lines of some embodiments, Figure 5 yes Figure 3 is an enlarged view of a portion B in FIG. 1 and is a schematic diagram showing the scribe lines of some embodiments, Figure 6 yes Figure 3 0 is an enlarged view of portion B in FIG. 1 and is a schematic diagram showing the scribe lines of some embodiments.

[0051] Figure 7 yes Figure 3 0 is an enlarged view of portion B in FIG. 1 and is a schematic diagram showing the scratch lanes in some embodiments.

[0052] Reference Figures 4 to 6 , various shapes of the scribe lane 120 and the stacked appearance of the first film 152 and the second film 154 stacked on the scribe lane 120 are disclosed.

[0053] Figure 4 The scribe lane 122-1 of the embodiment has a triangular groove shape or a quadrilateral groove shape, and the boundary surfaces of the first film 152 and the second film 154 stacked thereon form an oblique line. The first film 152 and the second film 154 are exposed upward side by side in the scribe lane 122-1. The first film 152 and the second film 154 may have different volumes in the scribe lane 122-1.

[0054] Figure 5 The scribe lane 122 - 1 of the embodiment has an elliptical groove shape, and the first film 152 stacked thereon is stacked to surround the second film 154 therein. Figure 6 The scribe lane 122 - 1 of the embodiment has a trapezoidal groove shape, and the first film 152 stacked thereon is stacked to surround the second film 154 therein.

[0055] In some example embodiments, for example, Figure 5 and Figure 6 As shown, the first film 152 and the second film 154 may be exposed upward from the scribe line 122-1. In addition, in the scribe line 122-1, the first film 152 and the second film 154 may have different volumes. In some example embodiments, for example, Figure 5 and Figure 6 As shown, the second film 154 is embedded in the first film 152 , but example embodiments are not particularly limited thereto, and at least one of the first film 152 and the second film 154 may be embedded in the other.

[0056] In e.g. Figure 7In some example embodiments shown, the scribe line 122-1 is formed by a rectangular groove, and in the scribe line 122-1 located between the semiconductor chip forming region SA1 and the adjacent semiconductor chip forming region SA2, the first film 152, the second film 154 and the first film 152 are sequentially arranged adjacent to the semiconductor chip forming regions SA1 and SA2.

[0057] Semiconductor chip manufacturing method

[0058] A semiconductor chip manufacturing method such as a semiconductor process is performed, for example, in a semiconductor processing device having a vacuum chamber. The wafer 100 before the process according to the inventive concept is transferred into the vacuum chamber, and various treatment processes are performed thereon.

[0059] The wafer 100 before the process in the vacuum chamber undergoes various processes, such as chemical vapor deposition (CVD) in a vacuum state, plasma enhanced chemical vapor deposition (PECVD), reactive ion etching (RIE), plasma assisted ion implantation (PLAID), annealing, oxidation and nitridation. In the semiconductor process, the chip is manufactured by repeatedly depositing, patterning and etching in the semiconductor chip forming areas SA1, SA2, SA3, ... and cutting or singulating along the scribe line 120, thereby completing the semiconductor chip manufacturing process.

[0060] Figure 8 is a flow chart of a semiconductor chip manufacturing process according to various example embodiments, and Fig. 9 It is shown Figure 8 FIG. 5 is a schematic diagram of a first film etching process S40A.

[0061] The semiconductor chip manufacturing process according to various example embodiments includes a process of alleviating or at least partially alleviating +warpage when +warpage occurs on the wafer 100 due to thermal deformation during a process, and the process of alleviating +warpage includes the following operations.

[0062] S10A: Prepare the wafer 100 before the process. The wafer 100 before the process includes at least a first film 152 and a second film 154 of different materials in the scribe streets 120 surrounding the semiconductor chip formation regions SA1, SA2, SA3, ... The stress of the first film 152 and the second film 154 may be adjusted or at least partially adjusted during the process.

[0063] S20A: The wafer 100 before the semiconductor process is put into the semiconductor process chamber, and the semiconductor process starts in the process chamber. A plurality of process chambers may be provided as needed or desired, and the wafer 100 may be transferred during the process.

[0064] S40A, S60A: When +warpage occurs on the wafer 100 above the susceptor 200 in the process chamber during a semiconductor process, the first film 152 may be etched or partially etched to generate tensile stress, which may thereby reduce the +warpage.

[0065] The first film 152 has a thermal expansion coefficient higher or greater than that of the wafer body 110 to generate compressive stress, and the second film 154 has a thermal expansion coefficient lower than that of the wafer body 110 to generate tensile stress.

[0066] When the first film 152 is etched due to the occurrence of +warpage in the process chamber, the volume of the second film 154 generating the tensile stress remains large, and the tensile stress increases. As a result, the occurrence of +warpage is alleviated or at least partially alleviated.

[0067] S80A: When the semiconductor process is completed, dicing may be performed to manufacture semiconductor chips. The process of reducing warpage may improve the quality and / or yield of the semiconductor chips.

[0068] Fig.10 is a flow chart of a semiconductor chip manufacturing process according to various example embodiments, and Fig.11 It is shown Fig.10 FIG. 5 is a schematic diagram of a second film etching process S40B.

[0069] The semiconductor chip manufacturing process according to various example embodiments includes a process of alleviating or at least partially alleviating warpage when warpage occurs in the wafer 100 due to thermal deformation during a process, and the process of alleviating warpage includes the following operations.

[0070] S10B: Prepare the wafer 100 before the process of the present invention. The wafer 100 before the process of the present invention includes at least a first film 152 and a second film 154 of different materials in the scribe streets 120 surrounding the semiconductor chip formation regions SA1, SA2, SA3, ... The stress of the first film 152 and the second film 154 can be adjusted during the process.

[0071] S20B: The wafer 100 before the semiconductor process is put into the semiconductor process chamber, and the semiconductor process starts in the process chamber. A plurality of process chambers may be prepared as needed or desired, and the wafer 100 may be transferred during the process.

[0072] S40B, S60B: When warpage occurs on the wafer 100 above the susceptor 200 in the process chamber during a semiconductor process, the second film 154 may be etched to generate compressive stress, thereby reducing the warpage.

[0073] The first film 152 has a higher thermal expansion coefficient than that of the wafer body 110 to generate compressive stress, and the second film 154 has a lower thermal expansion coefficient than that of the wafer body 110 to generate tensile stress.

[0074] When the second film 154 is etched due to the occurrence of warpage in the process chamber, the volume of the first film 152 generating the compressive stress remains large, and the compressive stress increases. As a result, the occurrence of warpage is alleviated or at least partially alleviated.

[0075] S80B: When the semiconductor process is completed, cutting is performed to manufacture semiconductor chips. The process of reducing warpage improves the quality and / or yield of the semiconductor chips.

[0076] exist Figure 8 and Fig. 9 as well as Fig.10 and Fig.11 Various example embodiments shown in the drawings may be integrated. In complex and precise semiconductor chip manufacturing, when +warpage occurs on the wafer 100 in a process chamber, the first film 152 is etched to alleviate or partially alleviate the +warpage and increase the flatness of the wafer 100. When -warpage occurs in another process, the second film 154 may be etched to alleviate or partially alleviate the -warpage and increase the flatness of the wafer 100.

[0077] During a semiconductor process, warpage can be maintained at 50 μm or less by adjusting the volume of the stress adjustment portion (eg, first film and second film) during the process, and flatness of the wafer can be improved to improve quality and / or yield of semiconductor devices.

[0078] According to various example embodiments, a wafer before a semiconductor process and a semiconductor chip manufacturing method using the wafer can maintain warpage at 50 μm or less during the process by adjusting the volume of the stress adjustment portion (e.g., the first film and the second film), and can improve the flatness of the wafer, thereby improving the quality and / or yield of the semiconductor device.

[0079] Although various example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the inventive concept as defined by the appended claims. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more features described with reference to one or more other figures.

Claims

1. A wafer comprising: Wafer body; a scribe line surrounding a semiconductor chip area on one surface of the wafer body; as well as A stress adjustment portion is in the scribe line and includes a first film and a second film having a material different from that of at least the wafer main body.

2. The wafer according to claim 1, wherein: The first film has a coefficient of thermal expansion greater than a coefficient of thermal expansion of the wafer body.

3. The wafer according to claim 2, wherein: The first film includes polysilicon.

4. The wafer according to claim 1, wherein: The second film has a thermal expansion coefficient that is smaller than a thermal expansion coefficient of the wafer body.

5. The wafer according to claim 4, wherein: The second film includes silicon dioxide.

6. The wafer according to claim 1, wherein: The cross section of the scratching track is at least one of a quadrilateral groove, a triangular groove, an elliptical groove and a trapezoidal groove.

7. The wafer according to claim 1, wherein: The first film and the second film are exposed side by side upward in the scribe line.

8. The wafer according to claim 1, wherein: The first film and the second film have different volumes in the scribe lane.

9. The wafer according to claim 1, wherein: At least one of the first film and the second film is embedded in the other.

10. The wafer according to claim 1, wherein: In a scribe street between the semiconductor chip region and an adjacent semiconductor chip region, a first one of the first films, the second film, and a second one of the first films are arranged adjacent to the semiconductor chip region.

11. A semiconductor chip manufacturing process, comprising: preparing a wafer before semiconductor processing, the wafer including at least a first film and a second film of different materials in a scribe line surrounding a semiconductor chip region; inserting the wafer into a semiconductor process chamber before the semiconductor process, and starting the semiconductor process in the semiconductor process chamber; in response to positive warpage occurring in the wafer during the semiconductor process, etching the first film to generate tensile stress; as well as The semiconductor process is completed.

12. The semiconductor chip manufacturing process according to claim 11, wherein: The wafer includes a wafer body, and the first film has a thermal expansion coefficient greater than a thermal expansion coefficient of the wafer body.

13. The semiconductor chip manufacturing process according to claim 12, wherein: The first film includes polysilicon.

14. The semiconductor chip manufacturing process according to claim 11, wherein: The wafer includes a wafer body, and the second film has a thermal expansion coefficient that is smaller than a thermal expansion coefficient of the wafer body.

15. The semiconductor chip manufacturing process according to claim 14, wherein: The second film includes silicon dioxide.

16. A semiconductor chip manufacturing process, comprising: preparing a wafer before semiconductor processing, the wafer including at least a first film and a second film of different materials in a scribe line surrounding a semiconductor chip region; inserting the wafer into a semiconductor process chamber before the semiconductor process, and starting the semiconductor process in the semiconductor process chamber; in response to negative warpage occurring in the wafer during the semiconductor process, etching the second film to generate compressive stress; as well as The semiconductor process is completed.

17. The semiconductor chip manufacturing process according to claim 16, wherein: The wafer includes a wafer body, and the first film has a thermal expansion coefficient greater than a thermal expansion coefficient of the wafer body.

18. The semiconductor chip manufacturing process according to claim 17, wherein: The first film includes polysilicon.

19. The semiconductor chip manufacturing process according to claim 16, wherein: The wafer includes a wafer body, and the second film has a thermal expansion coefficient that is smaller than a thermal expansion coefficient of the wafer body.

20. The semiconductor chip manufacturing process according to claim 19, wherein: The second film includes silicon dioxide.

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