Manufacturing method of floating gate of flash memory

Abstract

The invention discloses a method for manufacturing a floating gate of a flash memory, which comprises the following steps of: S1, providing a substrate with a storage region and a peripheral region, forming an isolation oxide layer on the surface of the substrate, forming a shallow trench isolation structure in the substrate, forming a floating gate polycrystalline silicon layer on the isolation oxide layer in the storage region, the floating gate polycrystalline silicon layer covers the shallow trench isolation structure; s2, carrying out planarization processing on the floating gate polycrystalline silicon layer; s3, etching the floating gate polycrystalline silicon layer by adopting an anisotropic etching process so as to expose the top of the shallow trench isolation structure in the storage region; s4, etching the top of the shallow trench isolation structure to enable the top of the shallow trench isolation structure in the storage region to be lower than the top of the floating gate polycrystalline silicon layer; and S5, etching the floating gate polycrystalline silicon layer by adopting an isotropic etching process, wherein the remaining floating gate polycrystalline silicon layer forms a floating gate. According to the scheme, the problem that the data retention function of the flash memory device is affected in the prior art can be solved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a floating gate of a flash memory. Background Art

[0002] With the development of semiconductor technology, flash memory has been widely used as a non-volatile memory. Flash memory adds a floating gate and a tunneling oxide layer to the traditional MOS transistor structure, and uses the floating gate to store charges, thereby achieving non-volatility of storage content. The manufacturing of the floating gate in flash memory is crucial.

[0003] In the manufacturing process of some flash memory devices, after the top floating gate polysilicon is subjected to chemical mechanical polishing, the floating gate polysilicon will continue to be etched to form the final floating gate. However, due to the shadow effect of the shallow trench isolation structure, sharp corners will be formed on both sides of the formed floating gate, such as Figure 1 As shown in the dotted box in FIG, the data retention function of the flash memory device is affected. Summary of the invention

[0004] In order to solve the above problems, the present application provides a method for manufacturing a flash memory floating gate.

[0005] The present application provides a method for manufacturing a flash memory floating gate, comprising: S1: providing a substrate having a storage area and a peripheral area, wherein an isolation oxide layer is formed on the surface of the substrate, a shallow trench isolation structure is formed in the substrate, a top of the shallow trench isolation structure is higher than the surface of the substrate, a floating gate polysilicon layer is formed on the isolation oxide layer in the storage area, and the floating gate polysilicon layer covers the shallow trench isolation structure; S2: performing a planarization process on the floating gate polysilicon layer; S3: etching the floating gate polysilicon layer using an anisotropic etching process to expose the top of the shallow trench isolation structure in the storage area; S4: etching the top of the shallow trench isolation structure so that the top of the shallow trench isolation structure in the storage area is lower than the top of the floating gate polysilicon layer; S5: etching the floating gate polysilicon layer using an isotropic etching process, and the remaining floating gate polysilicon layer constitutes a floating gate.

[0006] In some embodiments, a silicon nitride layer is formed on the isolation oxide layer in the peripheral region, and the planarization process of the floating gate polysilicon layer includes: The floating gate polysilicon layer is subjected to chemical mechanical polishing so that the top of the floating gate polysilicon layer is flush with the top of the silicon nitride layer.

[0007] In some embodiments, in step S3, the anisotropic etching process used is dry etching.

[0008] In some embodiments, in step S4, a wet etching process is used to etch the top of the shallow trench isolation structure.

[0009] In some embodiments, in step S5, the isotropic etching process used is CDE etching.

[0010] In some embodiments, in step S2, a height difference between a top of the remaining floating gate polysilicon layer and a top of the shallow trench isolation structure is 400-500 angstroms.

[0011] In some embodiments, in step S3, the etching depth of the anisotropic etching process is 500-600 angstroms.

[0012] In some embodiments, in step S4, the top of the shallow trench isolation structure remaining in the storage area is 250-300 angstroms higher than the substrate surface.

[0013] The technical solution of this application has at least the following advantages: 1. By adjusting the process sequence, after the floating gate polysilicon layer is subjected to an anisotropic etching process, the top of the exposed shallow trench isolation structure is etched first, so that the top of the shallow trench isolation structure in the storage area is lower than the top of the floating gate polysilicon layer, and the sharp corner of the top of the shallow trench isolation structure is exposed, and then the remaining floating gate polysilicon layer is subjected to an isotropic etching process, so that the above-mentioned sharp corner can be removed, and at the same time, the shadow effect of the shallow trench isolation structure is avoided to affect the data retention function of the flash memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 It is a schematic diagram of the sharp corners formed on both sides of the floating gate in the existing flash memory device; Figure 2 is a flow chart of a method for manufacturing a flash memory floating gate provided by an exemplary embodiment of the present application; Figure 3-6 It is a schematic diagram of the device structure during the implementation of a method for manufacturing a flash memory floating gate provided by an exemplary embodiment of the present application.

[0016] Explanation of the reference numerals: 1, substrate; 101, storage area; 102, peripheral area; 2, isolation oxide layer; 3, shallow trench isolation structure; 4, floating gate polysilicon layer; 5, silicon nitride layer. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] The present application provides a method for manufacturing a flash memory floating gate, referring to Figure 2 , the method comprises the following steps: S1: A substrate having a storage area and a peripheral area is provided, an isolation oxide layer is formed on the surface of the substrate, a shallow trench isolation structure is formed in the substrate, the top of the shallow trench isolation structure is higher than the surface of the substrate, a floating gate polysilicon layer is formed on the isolation oxide layer in the storage area, and the floating gate polysilicon layer covers the shallow trench isolation structure.

[0022] For example, refer to Figure 3A substrate 1 having a storage area 101 and a peripheral area 102 is provided, and an isolation oxide layer 2 is formed on the surface of the substrate 1. A plurality of shallow trench isolation structures 3 are formed in the substrate 1, and the top of the shallow trench isolation structure 3 passes through the isolation oxide layer 2 and is higher than the surface of the substrate 1. A floating gate polysilicon layer 4 is formed on the isolation oxide layer 2 located in the storage area 101, and the floating gate polysilicon layer 4 covers the portion of the shallow trench isolation structure 3 below that is higher than the substrate 1, and a silicon nitride layer 5 is formed on the isolation oxide layer 2 located in the peripheral area 102, and the silicon nitride layer 5 covers the portion of the shallow trench isolation structure 3 below that is higher than the substrate 1.

[0023] The substrate 1 may be at least one of the following materials: Si, SiC, SiGe, SiGeC, GeAs, InAs, InP, and other III-V or II-VI compound semiconductors. Here, only a few examples of substrate 1 are described. Those skilled in the art may select the type of substrate 1 according to the semiconductor device formed on the substrate 1. The type of substrate 1 does not limit the scope of protection of the present invention.

[0024] S2: performing planarization processing on the floating gate polysilicon layer.

[0025] For example, refer to Figure 3 The top of the floating gate polysilicon layer 4 may be planarized by using a chemical vapor polishing process until the top of the floating gate polysilicon layer 4 is flush with the top of the silicon nitride layer 5 .

[0026] S3: Etching the floating gate polysilicon layer using an anisotropic etching process to expose the top of the shallow trench isolation structure in the storage area.

[0027] For example, refer to Figure 4 , the floating gate polysilicon layer 4 may be etched using an anisotropic etching process to expose the top of the shallow trench isolation structure 3 covered by the floating gate polysilicon layer 4 .

[0028] Furthermore, in this step, the anisotropic etching process adopted is dry etching.

[0029] In order to facilitate the etching of the shallow trench isolation structure 3 in the subsequent steps, in this step, the top portion of the shallow trench isolation structure 3 can be exposed. For example, after the chemical mechanical polishing process in step S2, the top of the remaining floating gate polysilicon layer 4 is 400-500 angstroms higher than the top of the shallow trench isolation structure 3. In step S3, the etching depth of the anisotropic etching process is 500-600 angstroms, thereby exposing the shallow trench isolation structure 3 of about 100 angstroms.

[0030] S4: etching the top of the shallow trench isolation structure so that the top of the shallow trench isolation structure in the storage area is lower than the top of the floating gate polysilicon layer.

[0031] For example, refer to Figure 5 After the floating gate polysilicon layer 4 is subjected to the anisotropic etching process, the remaining floating gate polysilicon layer 4 is not directly subjected to the isotropic etching process. Instead, the top of the shallow trench isolation structure 3 in the storage area 101 is etched first, so that the top of the shallow trench isolation structure 3 in the storage area 101 is lower than the top of the floating gate polysilicon layer 4, thereby exposing the sharp corners on both sides of the top of the floating gate polysilicon layer 4.

[0032] Furthermore, in this step, a wet etching process is used to etch the top of the shallow trench isolation structure 3 .

[0033] S5: etching the floating gate polysilicon layer using an isotropic etching process, and the remaining floating gate polysilicon layer constitutes a floating gate.

[0034] For example, refer to Figure 6 , the floating gate polysilicon layer 4 can be etched by an isotropic etching process, and the remaining floating gate polysilicon layer 4 constitutes a floating gate. Since the sharp corners on both sides of the top of the floating gate polysilicon layer 4 have been exposed in step S4 and are no longer blocked by the shallow trench isolation structure 3, they will be removed during the isotropic etching process, thereby avoiding the data storage function of the flash memory device from being affected.

[0035] Furthermore, in this step, the isotropic etching process adopted is CDE etching.

[0036] Furthermore, after steps S4 and S5 are completed, the top of the remaining shallow trench isolation structure 3 in the storage area 101 is 250 to 300 angstroms higher than the surface of the substrate 1, the thickness of the remaining floating gate polysilicon layer 4 is 250 to 350 angstroms, and the top of the remaining floating gate polysilicon layer 4 is higher than the top of the shallow trench isolation structure 3 in the storage area 101.

[0037] A method for manufacturing a floating gate of a flash memory provided in an embodiment of the present application adjusts the process sequence. After an anisotropic etching process is performed on the floating gate polysilicon layer 4, the top of the exposed shallow trench isolation structure 3 is first etched, so that the top of the shallow trench isolation structure 3 in the storage area 101 is lower than the top of the floating gate polysilicon layer 4, and the sharp corner of the top of the shallow trench isolation structure 3 is exposed. Then, an isotropic etching process is performed on the remaining floating gate polysilicon layer 4, thereby removing the sharp corner mentioned above and avoiding the shadow effect of the shallow trench isolation structure 3 from affecting the data retention function of the flash memory device.

[0038] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a flash memory floating gate, characterized in that: include: S1: providing a substrate having a storage area and a peripheral area, wherein an isolation oxide layer is formed on the surface of the substrate, a shallow trench isolation structure is formed in the substrate, a top of the shallow trench isolation structure is higher than the surface of the substrate, a floating gate polysilicon layer is formed on the isolation oxide layer in the storage area, and the floating gate polysilicon layer covers the shallow trench isolation structure; S2: performing a planarization process on the floating gate polysilicon layer; S3: etching the floating gate polysilicon layer using an anisotropic etching process to expose the top of the shallow trench isolation structure in the storage area; S4: etching the top of the shallow trench isolation structure so that the top of the shallow trench isolation structure in the storage area is lower than the top of the floating gate polysilicon layer; S5: etching the floating gate polysilicon layer using an isotropic etching process, and the remaining floating gate polysilicon layer constitutes a floating gate.

2. The method for manufacturing a flash memory floating gate according to claim 1, characterized in that: A silicon nitride layer is formed on the isolation oxide layer in the peripheral region, and the planarization process of the floating gate polysilicon layer includes: The floating gate polysilicon layer is subjected to chemical mechanical polishing so that the top of the floating gate polysilicon layer is flush with the top of the silicon nitride layer.

3. The method for manufacturing a flash memory floating gate according to claim 1, characterized in that: In the step S3, the anisotropic etching process adopted is dry etching.

4. The method for manufacturing a flash memory floating gate according to claim 1, characterized in that: In the step S4, a wet etching process is used to etch the top of the shallow trench isolation structure.

5. The method for manufacturing a flash memory floating gate according to claim 1, characterized in that: In the step S5, the isotropic etching process adopted is CDE etching.

6. The method for manufacturing a flash memory floating gate according to claim 1, characterized in that: In the step S2, the height difference between the top of the remaining floating gate polysilicon layer and the top of the shallow trench isolation structure is 400-500 angstroms.

7. The method for manufacturing a flash memory floating gate according to claim 6, characterized in that: In the step S3, the etching depth of the anisotropic etching process is 500-600 angstroms.

8. The method for manufacturing a flash memory floating gate according to claim 7, characterized in that: In the step S4, the top of the remaining shallow trench isolation structure in the storage area is 250-300 angstroms higher than the substrate surface.

9. The method according to claim 8, characterized in that In the step S5, the thickness of the remaining floating gate polysilicon layer is 250-350 angstroms.

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