Modular interconnect unit, semiconductor package and method of manufacturing same

Abstract

The application provides a modular interconnect unit, a semiconductor package, and a method of manufacturing the same. The method includes: providing a first sub-package including a first substrate, at least one first interconnect pattern, and at least one first electronic component; mounting at least one modular interconnect unit on the first substrate, where the modular interconnect unit includes a dielectric layer, at least one conductive via through the dielectric layer, at least one conductive bump protruding from an upper surface of the dielectric layer, and a protective layer covering the conductive bump and having a planar upper surface, the conductive through hole is electrically coupled with the first interconnection pattern; forming a first sealant on an upper surface of the first substrate; removing a portion of the protective layer to expose an upper surface of the conductive bump; and mounting a second sub-package over the first encapsulant.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology, and more particularly to modular interconnect units, semiconductor packages, and methods of manufacturing the same. Background Art

[0002] The semiconductor industry continues to face the challenge of complex integration as consumers want their electronic devices to be smaller, faster, and higher performing, and to pack more and more functionality into a single device. One solution is package-on-package (PoP). PoP is a packaging method that combines two or more integrated circuit (IC) packages together. In a typical PoP, two or more packages are vertically connected (i.e., stacked) via vertical interconnect units that can guide signals between them. PoP assemblies can use space more efficiently and reduce the length of signal paths between packages. As a result, better electrical performance can be achieved because shorter signal path lengths can reduce noise and crosstalk in integrated circuits and facilitate faster signal response. However, the process for forming PoP assemblies is more complex and the yield is still low.

[0003] Therefore, there is a need for improved methods of manufacturing semiconductor packages. Summary of the invention

[0004] An object of the present application is to provide a method for manufacturing a semiconductor package with higher reliability.

[0005] According to aspects of the present application, a method for forming a semiconductor package is provided. The method may include: providing a first sub-package, the first sub-package including a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on the upper surface of the first substrate; mounting at least one modular interconnection unit on the upper surface of the first substrate, wherein the modular interconnection unit includes a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump disposed on the dielectric layer and protruding from the upper surface of the dielectric layer, and a protective layer covering the conductive bump and having a flat upper surface, wherein the conductive via is electrically coupled to the first interconnection pattern; forming a first sealant on the upper surface of the first substrate to seal the first electronic component and the modular interconnection unit; removing a portion of the protective layer to expose the upper surface of the conductive bump; and mounting a second sub-package above the first sealant, wherein the second sub-package includes a second substrate, at least one second interconnection pattern formed in the second substrate, and at least one second electronic component mounted on the upper surface of the second substrate, and the second interconnection pattern is electrically coupled to the conductive bump.

[0006] According to another aspect of the present application, a semiconductor package is provided. The semiconductor package may include: a first sub-package, the first sub-package includes a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on the upper surface of the first substrate; at least one modular interconnection unit mounted on the upper surface of the first substrate, wherein the modular interconnection unit includes a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump disposed on the dielectric layer and protruding from the upper surface of the dielectric layer, and a protective layer disposed on the dielectric layer and partially covering the conductive bump, wherein the conductive via is electrically coupled to the first interconnection pattern, and wherein the upper surface of the conductive bump is exposed from the protective layer; a first sealant, which is disposed on the upper surface of the first substrate, wherein the first sealant surrounds the first electronic component and the modular interconnection unit and exposes the upper surface of the conductive bump; and a second sub-package, which is mounted above the first sealant, wherein the second sub-package includes a second substrate, at least one second interconnection pattern formed in the second substrate, and at least one second electronic component mounted on the upper surface of the second substrate, and the second interconnection pattern is electrically coupled to the conductive bump.

[0007] According to another aspect of an embodiment of the present application, a modular interconnection unit is provided. The modular interconnection unit may include: a dielectric layer; at least one conductive via, which passes through the dielectric layer; at least one conductive bump, which is disposed on the dielectric layer and protrudes from the upper surface of the dielectric layer; and a protective layer, which is disposed on the dielectric layer, wherein the protective layer covers the conductive bump and has a flat upper surface.

[0008] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in this specification and constitute a part of this specification, illustrate embodiments of the present invention and together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings cited herein form part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, rather than all embodiments of the present application, unless the specific implementation mode clearly indicates otherwise, and the reader of this specification should not make an inference to the contrary.

[0010] Figure 1 It is a cross-sectional view of an interconnected unit.

[0011] Figure 2 is a cross-sectional view of a modular interconnect unit according to an embodiment of the present application.

[0012] Figures 3A to 3D is a cross-sectional view showing various steps of a method for manufacturing a modular interconnection unit according to an embodiment of the present application.

[0013] FIG. 4A to FIG. 4I are cross-sectional views showing respective steps of a method for manufacturing a semiconductor package according to an embodiment of the present application.

[0014] FIG. 5A to FIG. 5D is a cross-sectional view showing respective steps of a method for manufacturing a semiconductor package according to another embodiment of the present application.

[0015] Figure 6 is a cross-sectional view showing a semiconductor package according to an embodiment of the present application.

[0016] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0017] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. BRIEF DESCRIPTION OF THE DRAWINGS Specific exemplary embodiments of the present application can be practiced. The detailed description including the accompanying drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret this specification in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0018] In this application, unless otherwise expressly stated, the use of the singular includes the plural. In this application, unless otherwise stated, the use of "or" means "and / or". In addition, the use of the term "includes" and other forms such as "comprises" and "contains" is not restrictive. In addition, unless otherwise specifically stated, terms such as "element" or "component" cover elements and components that contain one unit, and elements and components that contain more than one subunit. The section headings used herein are for organizational purposes only and should not be interpreted as limiting the desired subject matter in any way.

[0019] As used herein, for ease of description, spatially relative terms such as "under", "below", "above", "on", "upper", "lower", "left", "right", "vertical", "horizontal", "side", etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as illustrated in the figure. In addition to the orientation depicted in the figure, spatially relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element can be directly connected or coupled to the other element, or there can be intervening elements.

[0020] Figure 1 1 shows a cross-sectional view of a modular interconnect unit 100. The modular interconnect unit 100 can be used in a package-on-package (PoP) assembly to guide signals between two integrated circuit (IC) packages. The modular interconnect unit 100 includes a dielectric body 110, at least one conductive via 120 passing through the dielectric body 110, and at least one conductive bump 130 formed on the dielectric body 110. In a process for forming a PoP assembly, as shown in FIG. Figure 1 As shown in FIG, the modular interconnect unit 100 is first picked up using a vacuum pick-and-place tool 20 and then mounted on a lower package. Then, an upper package is mounted over the modular interconnect unit 100 to form a PoP assembly. However, when the conductive bump 130 protrudes from the upper surface of the dielectric layer 120, a vacuum leak may occur between the vacuum nozzle of the vacuum pick-and-place tool 20 and the conductive bump 130, and the modular interconnect unit 100 may fall from the tool 20 during the pick-and-place process, resulting in low yield and low units-per-hour (UPH) production value.

[0021] In order to solve at least one of the above problems, a new modular interconnection unit is provided in an embodiment of the present application. In the modular interconnection unit, a protective layer is formed on the upper surface of the modular interconnection unit to cover the protruding conductive bumps. Since the protective layer is formed to have a flat upper surface, there will be no vacuum leakage between the vacuum pick-and-place tool and the modular interconnection unit.

[0022] refer to Figure 2 , a modular interconnect unit 200 is shown according to an embodiment of the present application.

[0023] The modular interconnect unit 200 includes a dielectric layer 210 and at least one conductive via 220 passing through the dielectric layer 210. In some embodiments, the dielectric layer 210 may be a laminate core of a printed wiring board (PWB), and the conductive via 220 may include one or more of Cu, Al, Sn, Ni, Au, Ag, Ti, W, or other suitable conductive materials. In some embodiments, the modular interconnect unit 200 may be a semiconductor interposer and may be manufactured using any suitable IC manufacturing process. For example, the dielectric layer 210 may include silicon and any other semiconductor-like material, and the conductive via 220 may be formed by filling a through-silicon via (TSV) with a conductive material.

[0024] The modular interconnect unit 200 further includes at least one conductive bump 230 disposed on the dielectric layer 210. The conductive bump 230 may protrude from the upper surface of the dielectric layer 210 and be electrically connected to the conductive via 220. Figure 2 In the example shown in FIG. 2 , the conductive bump 230 is shown as a solder bump, but the present application is not limited thereto. In some other embodiments, the conductive bump 230 may include a conductive pillar such as a copper pillar. The conductive bump 230 together with the conductive via 220 can be used to electrically connect the lower package to the upper package in the PoP assembly.

[0025] The protective layer 240 is formed on the dielectric layer 210. The protective layer 240 covers the conductive bumps 230 and has a flat upper surface 240a. In some embodiments, the protective layer 240 may include a molding compound or a resin, such as an epoxy-based resin, but the scope of the present application is not limited thereto. In some embodiments, the thickness of the protective layer 240 is in the range of 105% to 200% (e.g., 110%, 130%, 150%, 170%, or 190%) of the height of the conductive bump. In some embodiments, a grinding process may be used to flatten the upper surface 240a of the protective layer 240. Since the upper surface 240a of the protective layer 240 is flat, when the vacuum pick-and-place tool 20 applies a suction vacuum pressure on the upper surface 240a of the protective layer 240, the modular interconnect unit 200 can be easily picked up and placed at a desired location, such as Figure 2 As shown in .

[0026] Figures 3A to 3D The process for making a modular interconnection unit according to an embodiment of the present application is shown. The modular interconnection unit can be used with Figure 2 The modular interconnection unit 200 is the same or similar.

[0027] like Figure 3AAs shown in , a dielectric layer or body 310 is provided. The dielectric layer 310 may be a laminate core of a printed wiring board, or include a semiconductor material. A plurality of through-holes are formed in the dielectric layer 310 using laser drilling, mechanical drilling, deep reactive ion etching (DRIE), or other suitable processes. Then, a conductive material is deposited within the through-holes to form a plurality of conductive vias 320. For example, the conductive vias 320 may be formed using electrolytic plating, electroless plating, evaporation, or screen printing processes, and may include one or more of Cu, Al, Sn, Ni, Au, Ag, Ti, W, or other suitable conductive materials. The upper surface of each conductive via 320 is substantially flush or coplanar with the upper surface of the dielectric layer 310.

[0028] refer to Figure 3B , a plurality of conductive bumps 330 are formed on the dielectric layer 310 and are respectively in contact with the plurality of conductive vias 320. In some embodiments, a solder material may be deposited on the upper surface of each conductive via 320, and then the solder material may be reflowed to form the conductive bump 330. In some other embodiments, a conductive pillar (e.g., a copper pillar) may be mounted on the upper surface of each conductive via 320.

[0029] refer to Figure 3C , a protective layer 340 is formed on the dielectric layer 310 to cover the conductive bumps 330. In some embodiments, the protective layer 340 can be formed using a molding process such as a compression molding process or an injection molding process. In some other embodiments, the protective layer 340 can be formed using paste printing, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable processes. After the protective layer 340 is formed on the dielectric layer 310, the upper surface of the protective layer 340 can be planarized using a grinding process. The protective layer 340 can be made of a polymer composite material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler, but the scope of the present application is not limited thereto.

[0030] When performed on a strip-type substrate Figures 3A to 3C When the process Figure 3D In some embodiments, a singulation step is performed on a substrate strip to form a plurality of modular interconnect units. In some embodiments, a laser cutting process, a sawing process, an etching process, or any other suitable process known in the art may be used to singulate the strip into individual units. The plurality of modular interconnect units may have a footprint of a square, a rectangle, a hexagon, or any other geometric shape as desired. In addition, the footprints of the plurality of modular interconnect units may have the same size and / or shape, or may differ in size and / or shape.

[0031] According to another aspect of the present application, a method for forming a PoP type package is provided. Figure 2 The modular interconnect unit shown in can be used in this PoP type package to provide connectivity between two sub-packages.

[0032] FIG. 4A to FIG. 4I is a cross-sectional view showing a method for manufacturing the illustrated PoP type package according to an embodiment of the present application.

[0033] like Figure 4A , a first sub-package 410 is provided. The first sub-package 410 may include a first substrate 412 having an upper surface 412a and a lower surface 412b, at least one first interconnection pattern 414 formed in the first substrate 412, and at least one first electronic element 415 mounted on the upper surface 412a of the first substrate 412.

[0034] Specifically, the first substrate 412 may provide support and connectivity for the electronic components and devices mounted thereon. For example, the first substrate 412 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnections, or a ceramic substrate. However, the first substrate 412 is not limited to these examples. In some other examples, the first substrate 412 may include a laminate insert, a strip insert, a lead frame, or other suitable substrates. In order to increase manufacturing output, the first substrate 412 may include a plurality of predefined substrate units arranged in a strip manner, thereby allowing certain manufacturing processes to be performed on all of these substrate units in parallel. The first substrate 412 also includes a plurality of singulation regions, which may provide corresponding cutting regions to singulate the substrate unit into separate substrate units.

[0035] like Figure 4A , the first substrate 412 may include a plurality of first interconnect patterns 414. The first interconnect patterns 414 may provide connectivity for electronic components mounted on the first substrate 412. The first interconnect patterns 414 may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across the first substrate 412. For example, Figure 4A As shown in FIG. 4 , some of the first interconnect patterns 414 may provide a plurality of contact pads on the upper surface 412 a and the lower surface 412 b of the first substrate 412 .

[0036] In addition, a plurality of first electronic components 415 are mounted on the upper surface 412a of the first substrate 412. The first electronic components 415 can be mounted on the front surface 412a of the first substrate 412 by flip chip bonding or other suitable surface mounting techniques. For example, solder paste can be deposited or printed on the contact pads to which the first electronic components 415 are to be surface mounted. Subsequently, the first electronic components 415 can be placed on the upper surface 412a of the first substrate 412, wherein the terminals or contacts of the first electronic components 415 are in contact with and above the solder paste. The solder paste can then be reflowed to mechanically and electrically couple the first electronic components 415 to the contact pads on the upper surface 412a of the first substrate 412.

[0037] The first electronic component 415 may include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the first electronic component 415 may include an ultra-wideband (UWB) device, a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, an RF circuit, a wireless baseband system on chip (SoC) processor, a sensor, a memory controller, a memory device, an application specific integrated circuit (ASIC), etc.

[0038] refer to Figure 4B , at least one modular interconnect unit 420 is mounted on the upper surface 412 a of the first substrate 412 .

[0039] The modular interconnect unit 420 may include a dielectric layer 422, at least one conductive via 424 passing through the dielectric layer 422, and at least one conductive bump 426 disposed on the dielectric layer 422 and protruding from the upper surface of the dielectric layer 422. The modular interconnect unit 420 further includes a protective layer 428 covering the conductive bump 426 and having a flat upper surface. The conductive via 424 is electrically coupled to the first interconnect pattern 414 in the first substrate 412. The modular interconnect unit 420 may have Figure 2 The modular interconnect unit 200 has a similar structure and configuration to that shown in FIG. 1 and will not be described in detail here.

[0040] In some embodiments, solder paste may be deposited or printed onto the first interconnect pattern 414 where the modular interconnect unit 420 is to be surface mounted.

[0041] Next, a vacuum pick-and-place tool may be used to place the modular interconnect unit 420 into position over the first interconnect pattern 414, with the terminals of the modular interconnect unit 420 in contact with and over the solder paste. The solder paste may be reflowed to mechanically and electrically couple the modular interconnect unit 420 to the contact pads on the first interconnect pattern 414.

[0042] refer to Figure 4C , a first sealant 430 is formed on the upper surface of the first substrate 412 to seal the first electronic element 415 and the modular interconnection unit 420 .

[0043] In some embodiments, the first sealant 430 can be formed using a molding process such as a compression molding process or an injection molding process. In some other embodiments, the first sealant 430 can be formed using paste printing, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable processes. The first sealant 430 can be made of a polymer composite material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler, but the scope of the present application is not limited thereto.

[0044] In some embodiments, a grinding process may be performed on the first encapsulant 430 to planarize the first encapsulant 430 and expose the modular interconnection unit 420 .

[0045] refer to Figure 4D , a portion of the protection layer 428 of the modular interconnect unit 420 is removed to expose the upper surface of the conductive bump 426 .

[0046] In some embodiments, a laser ablation process may be used to remove a portion of the protective layer 428 and form a groove 429 in the protective layer 428. The groove 429 exposes at least the upper surface of the conductive bump 426. The laser ablation technique can accurately control the shape and / or depth of the groove 429. However, the present application is not limited thereto. In other embodiments, the groove 429 may be formed by a dry or wet etching process or any other process known in the art, as long as the material of the protective layer can be removed as needed. In some other embodiments, after the groove 429 is formed, a cleaning process for removing residues at the groove may be further performed. It is understood that when a plurality of conductive bumps 426 are formed on the modular interconnect unit 420, the laser ablation process may not remove a portion of the protective layer 428 that separates adjacent conductive bumps 426 from each other to maintain electrical isolation of these conductive bumps 426. In this case, the laser ablation process may be more similar to a drilling process for removing material above the conductive bump 426.

[0047] refer to Figure 4E , at least one second sub-package 440 is mounted on the modular interconnect unit 420 and over the first encapsulant 430 .

[0048] The second sub-package 440 may include a second substrate 442, a second interconnect pattern 444 formed in the second substrate 442, and at least one second electronic component 445 mounted on the upper surface of the second substrate 442. In addition, the second sub-package 440 may include a second sealant 448 that seals the second electronic component 445. The second electronic component 445 may include any of a variety of types of semiconductor dies, semiconductor packages, or discrete devices. For example, the first electronic component 415 may include a WiFi module, a digital signal processor (DSP), a memory device, a microcontroller, an RF circuit, etc. The second substrate 442 may provide support for the second electronic component 445, and the second interconnect pattern 444 may provide connectivity for the second electronic component 445.

[0049] After the second sub-package 440 is mounted on the modular interconnect unit 420 , the second interconnect pattern 444 in the second sub-package 440 is electrically connected to the conductive bump 426 of the modular interconnect unit 420 , so that the modular interconnect unit 420 can provide connectivity between the first sub-package 410 and the second sub-package 440 .

[0050] In some embodiments, before mounting the second sub-package 440 on the modular interconnect unit 420, a solder ball mounting (SBM) process may be performed to form additional solder balls on the conductive bumps 426 so that the solder balls may be raised higher than the upper surface of the first sealant 430 to ensure contact with the second interconnect pattern 444 of the second sub-package 440.

[0051] Then, refer to Figure 4F , an underfill sealant 450 is formed between the first sealant 430 and the second substrate 442 .

[0052] The bottom fill sealant 450 can fill any gap between the first sealant 430 and the second substrate 442 and optionally cover the side surfaces of the second sub-package 440. The bottom fill sealant 450 can include a polymer composite material, such as an epoxy resin, an epoxy acrylate, or a polymer with or without a filler. In some examples, the bottom fill sealant 450 is formed by depositing a fluid material at a position adjacent to the second substrate 442 on the first sealant 430 and allowing capillary action to draw the fluid material into the space between the first sealant 430 and the second substrate 442.

[0053] exist Figure 4FIn the example shown in FIG. 4 , the bottom fill encapsulant 450 also covers a portion of the side surfaces of the second substrate 442 and the second encapsulant 448. The bottom fill encapsulant 450 can provide mechanical support for the interconnection between the first sub-package 410 and the second sub-package 440, thereby helping to mitigate the risk of cracks or delamination due to different thermal expansion between the first sub-package 410 and the second sub-package 440.

[0054] Then, refer to Figure 4G , flip Figure 4F , and a plurality of external interconnection bumps 460 are formed on the lower surface 412 b of the first substrate 412. The plurality of external interconnection bumps 460 are electrically coupled to the first interconnection pattern 414.

[0055] In some embodiments, the conductive bump material is deposited on the first interconnect pattern 414 exposed from the lower surface 412b of the first substrate 412 using one or any combination of the following processes: evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The conductive bump material can be solder, Al, Sn, Ni, Au, Ag, Pb, Bi, Cu or a combination thereof, and an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder.

[0056] In some embodiments, the bump material may be reflowed by heating the material above its melting point to form external interconnect balls or bumps 460. In some embodiments, the external interconnect balls or bumps 460 may be compression bonded or thermocompression bonded to the first interconnect pattern 414 exposed from the lower surface 412b. Figure 4G The ball bump 460 shown in FIG. 4 may represent one type of external interconnect bump that may be formed on the lower surface 412b of the first substrate 412. In other examples, the external interconnect bump 460 may be a stud bump, a micro bump, or other electrical interconnect.

[0057] Then, if Figure 4H , a singulation process is performed to singulate each individual package from the package strip along a singulation channel. For example, a saw blade may be used to singulate the package strip into individual packages via the singulation channel. In some other examples, a laser cutting tool may also be used to singulate the package strip.

[0058] Finally, reference Fig. 4I An electromagnetic interference (EMI) shield 470 is formed to cover the second sub-package 440 and the side surfaces of the first sub-package 410 .

[0059] EMI shield 470 can be formed of copper, aluminum, iron or any other suitable material for EMI shielding. In some embodiments, EMI shield 470 can be formed by spraying, electroplating, sputtering or any other suitable metal deposition process. EMI shield 470 can follow the shape and / or contour of second sub-package 440 and the side surface of first sub-package 410.

[0060] refer to FIG. 5A to FIG. 5D , a cross-sectional view showing a method for manufacturing a PoP type package according to another embodiment of the present application.

[0061] like Figure 5A As shown in , a first sub-package 510 is provided. The first sub-package 510 may include a first substrate 512 having an upper surface 512a and a lower surface 512b, at least one first interconnect pattern 514 formed in the first substrate 512, and at least one first electronic component 515 mounted on the upper surface 512a of the first substrate 512. At least one modular interconnect unit 520 is mounted on the upper surface 512a of the first substrate 512. The modular interconnect unit 520 may include a dielectric layer 522, at least one conductive via 524 passing through the dielectric layer 522, and at least one conductive bump 526 disposed on the dielectric layer 522 and protruding from the upper surface of the dielectric layer 522. The modular interconnect unit 520 further includes a protective layer 528 covering the conductive bump 526 and having a flat upper surface. A first sealant 530 is formed on the upper surface of the first substrate 512 to seal the first electronic component 515 and the modular interconnect unit 520. Figure 5A The package structure shown in Figure 4C The structure shown in and will not be described in detail here.

[0062] Then, refer to Figure 5B , the protection layer 528 of the modular interconnect unit 520 is ground to expose the conductive bumps 526 .

[0063] In some embodiments, the upper portion of the first encapsulant 530 and the upper portion of the protective layer 528 are removed simultaneously by a grinder. The grinding process can also planarize the upper surfaces of the first encapsulant 530 and the protective layer 528. In some cases, the upper portion of the conductive bump 526 is also removed in the grinding process to expose more areas of the conductive bump 526.

[0064] refer to Figure 5B and Figure 5C Both, at least one second sub-package 540 is mounted on the modular interconnect unit 520 and over the first encapsulant 530 .

[0065] The second sub-package 540 may include a second substrate 542, at least one second interconnect pattern 544 formed in the second substrate 542, and at least one second electronic component 545 mounted on the upper surface of the second substrate 542. In addition, the second sub-package 540 may include a second sealant 548 that seals the second electronic component 545. In some embodiments, solder paste may be deposited or printed onto the conductive bumps 526 exposed from the first sealant 530 and the protective layer 528. Subsequently, the second sub-package 540 may be placed on the first sealant 530, wherein the terminals or contacts of the second sub-package 540 are in contact with and over the solder paste. The solder paste may then be reflowed to mechanically and electrically couple the second sub-package 540 to the conductive bumps 526.

[0066] Then, see Figure 5D , an underfill sealant 550 is formed between the second sub-package 540 and the first sub-package 510, a plurality of external interconnect bumps 560 are formed on the lower surface of the first substrate 510, and then a singulation process is performed to singulate each individual package from the package strip. Finally, an EMI shield 570 is formed to cover the side surfaces of the second sub-package 540 and the first sub-package 510.

[0067] According to another aspect of the present application, a semiconductor package is provided.

[0068] refer to Figure 6 , a cross-sectional view of a semiconductor package 600 according to an embodiment of the present disclosure is shown. The semiconductor package 600 may include a first sub-package 610, at least one modular interconnect unit 620, a first encapsulant 630, and a second sub-package 640.

[0069] The first sub-package 610 may include a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on the upper surface of the first substrate. The modular interconnection unit 620 may be mounted on the upper surface of the first substrate. The modular interconnection unit 620 may include a dielectric layer, at least one conductive via passing through the dielectric layer, at least one conductive bump disposed on the dielectric layer and protruding from the upper surface of the dielectric layer, and a protective layer disposed on the dielectric layer and partially covering the conductive bump. The conductive via is electrically coupled to the first interconnection pattern, and the upper surface of the conductive bump is exposed from the protective layer. The first sealant 630 is disposed on the upper surface of the first substrate, and the first sealant 630 surrounds the first electronic component and the modular interconnection unit 620 but exposes the upper surface of the conductive bump. The second sub-package 640 is mounted above the first sealant 630. The second sub-package 640 may include a second substrate, at least one second interconnection pattern formed in the second substrate, and at least one second electronic component mounted on the upper surface of the second substrate, and the second interconnection pattern is electrically coupled to the conductive via. The second sub-package 640 may further include a second encapsulant disposed on the upper surface of the second substrate and encapsulating the second electronic element.

[0070] In some embodiments, the semiconductor package 600 may further include an underfill encapsulant 650 between the first encapsulant and the second substrate.

[0071] In some embodiments, the semiconductor package 600 may further include a plurality of external interconnection bumps 660 formed on the lower surface of the first substrate. The plurality of external interconnection bumps 660 are electrically coupled to the first interconnection pattern.

[0072] In some embodiments, the semiconductor package 600 may further include an EMI shield 670 covering the second sub-package 640 and side surfaces of the first sub-package 610 .

[0073] The semiconductor package 600 may be FIG. 4A to FIG. 4I The steps shown in or FIG. 5A to FIG. 5D Therefore, more details about the semiconductor package 600 may refer to the above method embodiments, and will not be described in detail here.

[0074] Although the semiconductor package of the present application has been described in conjunction with the corresponding drawings, it will be appreciated by those skilled in the art that modifications and adaptations may be made to the semiconductor package without departing from the scope of the present invention.

[0075] The discussion herein includes numerous illustrative drawings showing various parts of semiconductor packages and methods of making them. For clarity, such drawings do not show all aspects of each example semiconductor package. Any example package and / or method provided herein may share any or all features with any or all other devices and / or methods provided herein.

[0076] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be appreciated that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by consideration of the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A method for forming a semiconductor package, characterized in that: The method comprises: providing a first sub-package, the first sub-package comprising a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on an upper surface of the first substrate; Mounting at least one modular interconnect unit on the upper surface of the first substrate, wherein the modular interconnect unit comprises a dielectric layer, at least one conductive via penetrating the dielectric layer, at least one conductive bump disposed on the dielectric layer and protruding from the upper surface of the dielectric layer, and a protection layer covering the conductive bump and having a flat upper surface, wherein the conductive via is electrically coupled to the first interconnect pattern; forming a first sealant on an upper surface of the first substrate to seal the first electronic component and the modular interconnection unit; removing a portion of the protective layer to expose an upper surface of the conductive bump; and A second sub-package is mounted over the first encapsulant, wherein the second sub-package includes a second substrate, at least one second interconnect pattern formed in the second substrate, and at least one second electronic component mounted on an upper surface of the second substrate, and the second interconnect pattern is electrically coupled to the conductive bump.

2. The method according to claim 1, characterized in that Mounting the modular interconnect unit on the upper surface of the first substrate further comprises: A pick-and-place operation is performed using a vacuum pick-and-place tool to move the modular interconnect unit to a position over the first interconnect pattern.

3. The method according to claim 1, characterized in that Removing a portion of the protective layer to expose the conductive bump comprises: A laser ablation process is performed on the protection layer to expose the conductive bumps.

4. The method according to claim 1, characterized in that: Removing a portion of the protective layer to expose the conductive bump comprises: The protection layer is ground to expose the conductive bumps.

5. The method according to claim 1, characterized in that The method further comprises: An underfill encapsulant is formed between the first encapsulant and the second substrate.

6. The method according to claim 1, characterized in that The method further comprises: A plurality of external interconnection bumps are formed on a lower surface of the first substrate, wherein the plurality of external interconnection bumps are electrically coupled to the first interconnection pattern.

7. The method according to claim 1, characterized in that The method further comprises: An electromagnetic interference (EMI) shield is formed to cover the second sub-package and side surfaces of the first sub-package.

8. A semiconductor package, characterized in that: The semiconductor package comprises: a first sub-package including a first substrate, at least one first interconnection pattern formed in the first substrate, and at least one first electronic component mounted on an upper surface of the first substrate; at least one modular interconnect unit mounted on the upper surface of the first substrate, wherein the modular interconnect unit comprises a dielectric layer, at least one conductive via penetrating the dielectric layer, at least one conductive bump disposed on the dielectric layer and protruding from the upper surface of the dielectric layer, and a protective layer disposed on the dielectric layer and partially covering the conductive bump, wherein the conductive via is electrically coupled to the first interconnect pattern, and the upper surface of the conductive bump is exposed from the protective layer; a first encapsulant disposed on an upper surface of the first substrate, wherein the first encapsulant surrounds the first electronic component and the modular interconnection unit and exposes an upper surface of the conductive bump; and A second sub-package is mounted above the first encapsulant, wherein the second sub-package includes a second substrate, at least one second interconnect pattern formed in the second substrate, and at least one second electronic component mounted on an upper surface of the second substrate, and the second interconnect pattern is electrically coupled to the conductive bump.

9. The semiconductor package according to claim 8, wherein: The semiconductor package further comprises: An underfill sealant is formed between the first sealant and the second substrate.

10. The semiconductor package according to claim 8, wherein The semiconductor package further comprises: A plurality of external interconnection bumps are formed on a lower surface of the first substrate, wherein the plurality of external interconnection bumps are electrically coupled to the first interconnection pattern.

11. The semiconductor package according to claim 8, wherein: The semiconductor package further comprises: An electromagnetic interference (EMI) shield covers the second sub-package and side surfaces of the first sub-package.

12. The semiconductor package according to claim 8, wherein: The semiconductor package further comprises: A second sealant is disposed on the upper surface of the second substrate and seals the second electronic element.

13. A modular interconnection unit, characterized in that: The modular interconnection unit comprises: Dielectric layer; at least one conductive via extending through the dielectric layer; at least one conductive bump disposed on the dielectric layer and protruding from an upper surface of the dielectric layer; and The protection layer is disposed on the dielectric layer, wherein the protection layer covers the conductive bump and has a flat upper surface.

14. The modular interconnection unit according to claim 13, characterized in that The thickness of the protection layer is in a range from 105% to 200% of the height of the conductive bump.

15. The modular interconnection unit according to claim 13, characterized in that The protective layer includes a molding compound.

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