Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; forming a sacrificial layer on the substrate; forming a functional layer comprising a semiconductor device on one side, far away from the substrate, of the sacrificial layer, wherein the functional layer exposes the first part of the sacrificial layer; etching the sacrificial layer by adopting electrochemical corrosion; and separating the functional layer from the substrate by using the transfer substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The third generation of semiconductor materials (such as gallium nitride) have the characteristics of large bandgap, strong pressure resistance, stable physical properties, etc., and are widely used in power devices, radio frequency devices and optoelectronics. Usually, the third generation of semiconductor materials need to be prepared epitaxially on a substrate (such as a sapphire substrate). Since the sapphire substrate is not conductive, has poor thermal conductivity, and the thickness of the device is large after miniaturization, it is usually necessary to peel off the sapphire substrate. Due to the high hardness and strong chemical resistance of sapphire, the currently widely used substrate peeling scheme is to use ultraviolet lasers to ablate semiconductor materials through sapphire. The semiconductor material absorbs the ultraviolet laser energy and decomposes, thereby achieving sapphire substrate peeling. However, due to the influence of laser stability and local thermal stress, the laser peeling substrate solution has the problems of low yield, low processing efficiency and high cost.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0004] In one aspect, a method for preparing a semiconductor device is provided, comprising:

[0005] providing a substrate base plate;

[0006] forming a sacrificial layer on the substrate;

[0007] forming a functional layer including a semiconductor device on a side of the sacrificial layer away from the substrate, wherein the functional layer exposes a first portion of the sacrificial layer;

[0008] Etching the sacrificial layer by electrochemical etching; and

[0009] The functional layer is separated from the base substrate using a transfer substrate.

[0010] According to some exemplary embodiments, etching the sacrificial layer by electrochemical etching includes:

[0011] connecting a first portion of the sacrificial layer to a first electrode;

[0012] Immersing the entire device including the substrate, the sacrificial layer and the functional layer in an electrolyte;

[0013] providing a second electrode, and immersing at least a portion of the second electrode in the electrolyte;

[0014] Respectively electrically connecting the first electrode and the second electrode to the positive and negative electrodes of a power source; and

[0015] The sacrificial layer is corroded by adjusting the voltage value and power-on time provided by the power supply.

[0016] According to some exemplary embodiments, forming a sacrificial layer on the substrate includes:

[0017] forming a sacrificial body layer on one side of the base substrate;

[0018] doping the sacrificial main layer with a first doping material to form a sacrificial layer,

[0019] The functional layer includes at least one semiconductor layer, and the doping concentration of the first doping material in the sacrificial layer is higher than the doping concentration of the semiconductor layer in the functional layer.

[0020] According to some exemplary embodiments, the doping concentration of the first doping material is between 10 18 -10 20 cm -3 within the scope; and / or,

[0021] The first doping material includes silicon.

[0022] According to some exemplary embodiments, a thickness of the sacrificial layer in a first direction is in a range of 5 nanometers to 10 micrometers, wherein the first direction is parallel to a direction from the base substrate toward the sacrificial layer.

[0023] According to some exemplary embodiments, the electrolyte includes one of an acidic electrolyte and an alkaline electrolyte; and / or,

[0024] The material of the second electrode includes a metal conductive material or a non-metal conductive material; and / or,

[0025] The voltage value provided by the power supply is in the range of 5 to 50V.

[0026] According to some exemplary embodiments, forming a functional layer including a semiconductor device on a side of the sacrificial layer away from the substrate includes:

[0027] Forming a first semiconductor layer, a quantum well layer, a second semiconductor layer and a first conductive layer in sequence on a side of the sacrificial layer away from the substrate;

[0028] Performing a patterning process on the first semiconductor layer, the quantum well layer, the second semiconductor layer and the first conductive layer to form a first mesa on the first semiconductor layer;

[0029] Forming a second conductive layer on a side of the first table away from the substrate by thin film deposition technology and patterning process;

[0030] Forming a passivation layer on a side of both the first conductive layer and the second conductive layer away from the substrate by thin film deposition technology and patterning process, wherein the passivation layer comprises a first opening exposing at least a portion of the first conductive layer, and a second opening exposing at least a portion of the second conductive layer; and

[0031] A third conductive layer is formed on a side of the passivation layer away from the substrate, and a patterning process is performed to form a third electrode and a fourth electrode, wherein the third electrode is electrically connected to the first conductive layer, and the fourth electrode is electrically connected to the second conductive layer, so as to form a functional layer including a semiconductor device.

[0032] According to some exemplary embodiments, the semiconductor device includes at least one of gallium nitride, silicon carbide, zinc oxide, gallium indium nitride, aluminum gallium indium nitride, aluminum gallium indium phosphide, and diamond.

[0033] According to some exemplary embodiments, the method further comprises:

[0034] Before forming the sacrificial layer, a seed layer is formed on the base substrate, and the material of the seed layer includes aluminum nitride.

[0035] According to some exemplary embodiments, the method further comprises:

[0036] Before forming the sacrificial layer, a buffer layer and a transition layer are formed on the base substrate, wherein the buffer layer comprises gallium nitride and the transition layer comprises undoped gallium nitride.

[0037] According to some exemplary embodiments, causing the functional layer to expose a first portion of the sacrificial layer includes:

[0038] An edge region of the first semiconductor layer in the functional layer is etched to expose a first portion of the sacrificial layer.

[0039] According to some exemplary embodiments, forming a first mesa on the first semiconductor layer includes:

[0040] The first conductive layer, the second semiconductor layer, the quantum well layer and the first semiconductor layer in a designated area are etched, wherein the first conductive layer, the second semiconductor layer and the quantum well layer in the designated area are completely etched.

[0041] According to some exemplary embodiments, separating the functional layer from the base substrate using a transfer substrate comprises:

[0042] The surface of the functional layer away from the base substrate is bonded by using the first surface of the transfer substrate, so that the functional layer is separated from the base substrate.

[0043] According to some exemplary embodiments, the substrate includes one of a sapphire substrate and a silicon substrate.

[0044] According to some exemplary embodiments, forming the third electrode and the fourth electrode includes:

[0045] The third conductive layer is patterned using electron beam lithography and lift-off techniques to form the third electrode and the fourth electrode, wherein the material of the third conductive layer includes metals such as titanium, aluminum, gold, tin, nickel, platinum, chromium, or metal alloys or laminated metals.

[0046] According to some exemplary embodiments, forming a passivation layer on a side of both the first conductive layer and the second conductive layer away from the substrate includes:

[0047] A single-layer passivation layer is formed on the side of both the first conductive layer and the second conductive layer away from the substrate, wherein the material of the passivation layer includes a stack of one or more of silicon oxide, silicon nitride and aluminum oxide; and / or,

[0048] Alternatingly stacked first and second sub-passivation layers are formed on the sides of the first and second conductive layers away from the substrate.

[0049] In another aspect of the present disclosure, a semiconductor device is provided, wherein the semiconductor device is manufactured using any of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0051] Figure 1 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0052] Figure 2 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure;

[0053] Figure 3 is a schematic diagram of electrochemical corrosion according to an exemplary embodiment of the present disclosure;

[0054] Figure 4 is a flow chart of electrochemical corrosion according to an exemplary embodiment of the present disclosure;

[0055] Figure 5is a flow chart of preparing a sacrificial layer according to an exemplary embodiment of the present disclosure;

[0056] Figure 6 is a schematic structural diagram of a portion of a film layer during a preparation process according to an exemplary embodiment of the present disclosure;

[0057] Figure 7 is a flow chart of preparing a functional layer according to an exemplary embodiment of the present disclosure;

[0058] Figures 8A-8E They are schematic diagrams of the structures of some film layers during the preparation process according to the embodiments of the present disclosure;

[0059] Fig. 9 is a schematic structural diagram of a passivation layer according to an exemplary embodiment of the present disclosure;

[0060] Fig.10 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure;

[0061] Fig.11 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure;

[0062] Fig.12 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure; and

[0063] Fig.13A and Fig. 13B is a schematic diagram of substrate peeling according to an exemplary embodiment of the present disclosure.

[0064] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0066] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0067] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by ordinary technicians in the field. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0068] In this document, unless otherwise specified, directional terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the device, element or component referred to must have a specific orientation, be constructed or operate in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms should not be understood as limiting the present disclosure.

[0069] In this document, directional expressions "first direction" and "second direction" are used to describe different directions of the semiconductor device. It should be understood that such expressions are only exemplary descriptions and are not limitations of the present disclosure.

[0070] As used herein, the terms "substantially," "approximately," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0071] The following is a brief explanation of technical terms used in the present disclosure.

[0072] Liftoff process: It is a process used for pattern definition and metal stripping in microelectronics manufacturing. Its principle is to form a photoresist layer after photolithography on the substrate, and then deposit metal on this pattern layer using processes such as electron beam evaporation or sputtering. Subsequently, while removing the photoresist (photoresist), the metal on the film is stripped off together, so that only the metal of the original pattern is retained on the substrate.

[0073] DBR structure: It is composed of multiple layers of high refractive index materials and low refractive index materials stacked alternately. Through periodic changes in the refractive index, it achieves high reflection of light of a specific wavelength and low reflection of light of other wavelengths.

[0074] In order to improve the crystal growth quality of third-generation semiconductor materials, it is usually necessary to epitaxially grow third-generation semiconductor material crystals on a substrate substrate (such as a sapphire substrate or a silicon substrate) and then process them into the desired semiconductor devices. In some application scenarios, in order to improve the performance of semiconductor devices, such as improving electrical conductivity, thermal conductivity or reducing volume, it is usually necessary to peel off the substrate substrate. The currently commonly used laser peeling technology has problems such as low yield, low processing efficiency and high cost. Therefore, it is necessary to further optimize the substrate peeling technology to improve the yield and processing efficiency and reduce costs.

[0075] Illustratively, in an embodiment of the present disclosure, a method for preparing a semiconductor device is provided. Specifically, the method for preparing a semiconductor device includes: providing a substrate; forming a sacrificial layer on the substrate; forming a functional layer including a semiconductor device on a side of the sacrificial layer away from the substrate, wherein the functional layer exposes a first portion of the sacrificial layer; etching the sacrificial layer by electrochemical etching; and separating the functional layer from the substrate by using a transfer substrate.

[0076] By adding a sacrificial layer between the substrate and the semiconductor device, and using an electrochemical etching method to etch the sacrificial layer, the semiconductor device and the substrate can be separated. By stripping the substrate in this way, the requirements for equipment can be reduced, and the yield rate and processing efficiency are high, which can effectively reduce costs.

[0077] Figure 1 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present disclosure, Figure 2 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure.

[0078] Illustratively, in an embodiment of the present disclosure, a method for preparing a semiconductor device is provided. Figure 1-Figure 2 , the method for preparing a semiconductor device may include the following steps S1-S5.

[0079] In step S1 , a base substrate 1 is provided.

[0080] In step S2 , a sacrificial layer 2 is formed on the base substrate 1 .

[0081] In step S3 , a functional layer 3 including a semiconductor device 30 is formed on a side of the sacrificial layer 2 away from the substrate 1 , and the functional layer 3 exposes the first portion 21 of the sacrificial layer 2 .

[0082] In step S4, the sacrificial layer 2 is etched by electrochemical etching.

[0083] In step S5 , the functional layer 3 is separated from the base substrate 1 by using a transfer substrate.

[0084] Exemplarily, the substrate 1 may include one of a sapphire substrate and a silicon substrate.

[0085] Exemplarily, the semiconductor device 30 may include at least one of gallium nitride, silicon carbide, zinc oxide, gallium indium nitride, aluminum gallium indium nitride, aluminum gallium indium phosphide, and diamond.

[0086] By epitaxially growing semiconductor material crystals on a sapphire substrate or a silicon substrate, the number of defects in the crystal can be reduced, thereby improving the performance of semiconductor devices.

[0087] Exemplarily, the functional layer 3 may include at least one semiconductor layer. The material of at least one semiconductor layer in the functional layer 3 may be the same as the material type in the sacrificial layer 2. Taking the semiconductor device as a gallium nitride device as an example, the functional layer 3 may include N-type gallium nitride and P-type gallium nitride. The sacrificial layer 2 may include N-type gallium nitride. The material of the film layer in the functional layer 3 that is in direct contact with the sacrificial layer 2 may be the same type of material as the material of the sacrificial layer 2, for example, both are gallium nitride materials.

[0088] This design ensures that the semiconductor layer in the functional layer 3 epitaxially grown on the sacrificial layer 2 has good crystal quality, and avoids affecting the film quality in the functional layer 3 due to lattice mismatch between the sacrificial layer 2 and the semiconductor layer in the functional layer 3 .

[0089] Figure 3 is a schematic diagram of electrochemical corrosion according to an exemplary embodiment of the present disclosure, Figure 4 is a flow chart of electrochemical corrosion according to an exemplary embodiment of the present disclosure.

[0090] For example, in the embodiments of the present disclosure, in combination with reference Figure 2-Figure 4 In step S4, the electrochemical etching to etch the sacrificial layer 2 may specifically include the following steps S41-S45.

[0091] In step S41 , the first portion 21 of the sacrificial layer 2 is connected to the first electrode T1 .

[0092] Exemplarily, the first electrode T1 may be a fixture electrode. For example, the shape of the first portion 21 in the sacrificial layer may be a ring-shaped pattern, and the first electrode T1 may be a ring-shaped fixture, which is beneficial to improving the efficiency of electrochemical corrosion.

[0093] In step S42 , the overall device 10 including the base substrate 1 , the sacrificial layer 2 and the functional layer 3 is immersed in the electrolyte ES.

[0094] In step S43 , a second electrode T2 is provided, and at least a portion of the second electrode T2 is immersed in the electrolyte ES.

[0095] Exemplarily, the second electrode T2 may be completely immersed in the electrolyte ES.

[0096] In step S44 , the first electrode T1 and the second electrode T2 are electrically connected to the positive and negative electrodes of the power source DC, respectively.

[0097] In step S45, the sacrificial layer 2 is etched by adjusting the voltage value and the power-on time provided by the power source DC.

[0098] Exemplarily, the resistance of the sacrificial layer 2 may be less than the resistance of any layer in the functional layer 3. For example, the resistance of the sacrificial layer 2 may be less than 1 / 5 or 1 / 8 of the resistance of any layer in the functional layer 3. Since the resistance of the sacrificial layer 2 is small and the first electrode T1 is directly connected to the sacrificial layer 2, the sacrificial layer 2 will be corroded preferentially during the electrochemical corrosion process.

[0099] In some embodiments, the thickness and resistance of the sacrificial layer 2 are controllable, for example, the thickness of the sacrificial layer is controlled by controlling the growth time of the sacrificial layer, and the resistance of the sacrificial layer is controlled by controlling the doping concentration in the sacrificial layer.

[0100] For example, the voltage value and the power-on time provided by the power supply DC can be adjusted to ensure that the electrochemical corrosion etches and disconnects the sacrificial layer 2, while the functional layer 3 is not etched as much as possible. For example, if the thickness of the sacrificial layer 2 increases, the power-on time can be extended or the voltage value can be increased accordingly. If the thickness of the sacrificial layer 2 decreases, the power-on time can be shortened or the voltage value can be reduced accordingly. By controlling the voltage value and the power-on time during the electrochemical reaction, the electrochemical reaction can be mainly caused to occur in the sacrificial layer, which is beneficial to improving the corrosion efficiency and avoiding the influence on the functional layer.

[0101] Exemplarily, the electrolyte ES may include one of an acidic electrolyte and an alkaline electrolyte. For example, the electrolyte ES may include oxalic acid solution, dilute hydrochloric acid, sulfuric acid, potassium hydroxide, sodium hydroxide, and the like.

[0102] Exemplarily, the material of the second electrode T2 may include a metal conductive material, such as gold, platinum, silver, copper, etc. The material of the second electrode T2 may also include a non-metal conductive material, such as a graphite conductive material, a carbon nanotube, etc.

[0103] Exemplarily, the voltage value provided by the power supply DC is in the range of 5 to 50V.

[0104] Through such a design, the electrochemical corrosion efficiency can be improved and the cost can be reduced.

[0105] Exemplarily, the semiconductor device includes a gallium nitride device, the sacrificial layer includes highly doped N-type gallium nitride, and the electrolyte ES is selected as an oxalic acid solution, and the oxalic acid concentration can be about 0.3 mol / L. The first electrode T1 is electrically connected to the sacrificial layer 2 in a point connection manner, and the power-on time can be adjusted and optimized according to the thickness of the sacrificial layer 2 to ensure that the electrochemical corrosion can etch away the sacrificial layer 2, so as to facilitate the subsequent separation of the substrate 1 and the functional layer 3.

[0106] Figure 5 is a flow chart of preparing a sacrificial layer according to an exemplary embodiment of the present disclosure, Figure 6 Schematic diagram of the structure of a portion of a film layer during the preparation process according to an exemplary embodiment of the present disclosure.

[0107] For example, in the embodiments of the present disclosure, in combination with reference Figure 5 and Figure 6 The step S2 of forming the sacrificial layer 2 on the base substrate 1 may include the following steps S21-S22.

[0108] In step S21 , a sacrificial body layer 20 is formed on one side of the base substrate 1 .

[0109] In step S22 , the first doping material 201 is doped into the sacrificial body layer 20 to form a sacrificial layer 2 .

[0110] For example, the doping concentration of the first doping material 201 is 10 18 -10 20 cm -3 For example, the doping concentration of the first doping material 201 is about 10 19 cm -3 .

[0111] For example, the first doping material 201 may include silicon, and the sacrificial body layer 20 may include gallium nitride. Doping gallium nitride with high concentration of silicon can form N-type gallium nitride with low resistance, thereby improving the efficiency of etching the sacrificial layer during electrochemical corrosion, which is beneficial to improving processing efficiency and reducing costs.

[0112] Exemplarily, in the embodiments of the present disclosure, return to reference Figure 2 , a thickness H1 of the sacrificial layer 2 in a first direction Z is in a range of 5 nanometers to 10 micrometers. The first direction Z is parallel to a direction from the base substrate 1 to the sacrificial layer 2 .

[0113] By adjusting the thickness of the sacrificial layer 2 , the base substrate 1 and the functional layer 3 can be effectively separated, so that the base substrate 1 and the functional layer 3 can be separated after the sacrificial layer 2 is etched away.

[0114] Exemplarily, the thickness H1 of the sacrificial layer 2 in the first direction Z is in the range of 100 nanometers to 500 nanometers. For example, the thickness H1 of the sacrificial layer 2 in the first direction Z is about 200 nanometers. Through such a design, while ensuring that the sacrificial layer 2 can effectively separate the base substrate 1 and the functional layer 3, the thickness of the sacrificial layer 2 is relatively thin, and the growth time and etching time of the sacrificial layer 2 are both relatively short, which is conducive to improving production efficiency.

[0115] Exemplarily, the functional layer 3 may include at least one semiconductor layer. For example, the functional layer may include an N-type semiconductor layer and a P-type semiconductor layer. The doping concentration of the first doping material 201 in the sacrificial layer 2 is higher than the doping concentration of the semiconductor layer in the functional layer 3. Through such a design, the resistance value of each film layer in the functional layer can be greater than the resistance value of the sacrificial layer 2, so that the influence on the functional layer 3 can be minimized when the sacrificial layer 2 is electrochemically corroded.

[0116] Figure 7 is a flow chart of preparing a functional layer according to an exemplary embodiment of the present disclosure, Figures 8A-8E They are respectively schematic diagrams of the structures of some film layers during the preparation process according to the embodiments of the present disclosure.

[0117] For example, in the embodiments of the present disclosure, in combination with reference Figure 7-8E The step S3 of forming the functional layer 3 including the semiconductor device on the side of the sacrificial layer 2 away from the substrate 1 may include the following steps S31-S35.

[0118] In step S31, refer to Fig. 8A A first semiconductor layer 31 , a quantum well layer 32 , a second semiconductor layer 33 and a first conductive layer 34 are sequentially formed on a side of the sacrificial layer 2 away from the base substrate 1 .

[0119] Exemplarily, the first semiconductor layer 31 may include N-type gallium nitride, and the second semiconductor layer 33 may include P-type gallium nitride. The first conductive layer 34 may include a transparent conductive material, such as indium tin oxide (ITO).

[0120] Exemplarily, the first conductive layer 34 may serve as a current transport layer, and a thickness H2 of the first conductive layer 34 is in a range of 10 angstroms to 50,000 angstroms.

[0121] In step S32, refer to Figure 8B , a patterning process is performed on the first semiconductor layer 31 , the quantum well layer 32 , the second semiconductor layer 33 and the first conductive layer 34 to form a first mesa P1 on the first semiconductor layer 31 .

[0122] Exemplarily, forming the first mesa P1 in the first semiconductor layer 31 may include: etching the first conductive layer 34, the second semiconductor layer 33, the quantum well layer 32, and the first semiconductor layer 31 in a specified region. By controlling the etching time, the first conductive layer 34, the second semiconductor layer 33, and the quantum well layer 32 in the specified region are completely etched, and the first semiconductor layer 31 is partially etched, so that the first mesa P1 can be formed in the first semiconductor layer 31.

[0123] By way of example, the first conductive layer 34 may be etched by a dry method or a wet method.

[0124] Exemplarily, dry etching may be used for the first semiconductor layer 31, the quantum well layer 32, and the second semiconductor layer 33. For example, the total thickness of the first semiconductor layer 31, the quantum well layer 32, and the second semiconductor layer 33 may be in the range of 0.6 microns to 1.5 microns, ensuring that the second semiconductor layer 33 and the quantum well layer 32 in the designated area are completely etched, and the first semiconductor layer 31 is partially etched, so that the first mesa P1 can be formed on the first semiconductor layer 31.

[0125] It should be noted that the total etched thickness of the first semiconductor layer 31, the quantum well layer 32, and the second semiconductor layer 33 can be optimized and adjusted accordingly according to the total thickness of the first semiconductor layer 31, the quantum well layer 32, and the second semiconductor layer 33 and the specific conditions of the thickness of each film layer to ensure that the second semiconductor layer 33 and the quantum well layer 32 in the designated area are completely etched after etching, and the first semiconductor layer 31 is partially etched.

[0126] For example, after forming the first mesa P1 , the first conductive layer 34 may be annealed, which is beneficial to improving the transmittance of the first conductive layer 34 and also improving the ohmic contact characteristics between the first conductive layer 34 and the second semiconductor layer 33 .

[0127] In step S33, refer to Figure 8C Through thin film deposition technology and patterning process, a second conductive layer 35 is formed on the side of the first table P1 away from the base substrate 1.

[0128] Exemplarily, the second conductive layer 35 is electrically connected to the first semiconductor layer 31 .

[0129] Exemplarily, the orthographic projections of the quantum well layer 32 , the second semiconductor layer 33 and the first conductive layer 34 on the substrate do not overlap with the orthographic projection of the second conductive layer 35 on the substrate.

[0130] Exemplarily, the second conductive layer 35 may be formed by a liftoff process.

[0131] Exemplarily, the material of the second conductive layer 35 may include metals or metal alloys or metal stacks such as titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), chromium (Cr), platinum (Pt), etc. For example, the second conductive layer 35 may include a TiAlNiAu stacked structure or a CrPtAu stacked structure.

[0132] For example, the material in the second conductive layer 35 that is in direct contact with the first semiconductor layer 31 may include titanium or chromium, which is beneficial to improving the ohmic contact characteristics between the second conductive layer 35 and the first semiconductor layer 31 .

[0133] In step S34, refer to Fig.8D , a passivation layer 36 is formed on the side of the first conductive layer 34 and the second conductive layer 35 away from the substrate 1 by thin film deposition technology and patterning process. The passivation layer 36 may include a first opening VH1 exposing at least a portion of the first conductive layer 34, and a second opening VH2 exposing at least a portion of the second conductive layer 35.

[0134] For example, a dry etching process may be used to open holes in the passivation layer 36 to form the first opening VH1 and the second opening VH2 .

[0135] In step S35, refer to Fig. 8E A third conductive layer 37 is formed on the side of the passivation layer 36 away from the substrate 1, and a patterning process is performed to form a third electrode T3 and a fourth electrode T4. The third electrode T3 is electrically connected to the first conductive layer 34, and the fourth electrode T4 is electrically connected to the second conductive layer 35, so as to form a functional layer 3 including a semiconductor device 30.

[0136] Exemplarily, forming the third electrode T3 and the fourth electrode T4 in step S35 may include: performing a patterning process on the third conductive layer 37 using an electron beam lithography technique and a lift-off technique (eg, a liftoff technique) to form the third electrode T3 and the fourth electrode T4.

[0137] Exemplarily, the material of the third conductive layer 37 may include metals or metal alloys or laminated metals such as titanium (Ti), aluminum (Al), gold (Au), tin (Sn), nickel (Ni), platinum (Pt) and chromium (Cr).

[0138] Fig. 9 is a schematic structural diagram of a passivation layer according to an exemplary embodiment of the present disclosure.

[0139] For example, refer to Fig. 8E Forming the passivation layer 36 on the side of both the first conductive layer 34 and the second conductive layer 35 away from the substrate 1 may include: forming a single-layer passivation layer 36 on the side of both the first conductive layer 34 and the second conductive layer 35 away from the substrate 1 .

[0140] Exemplarily, the material of the passivation layer includes a stack of one or more of silicon oxide, silicon nitride and aluminum oxide.

[0141] Exemplarily, the passivation layer may also include other types of materials, such as a stack of one or more materials such as titanium oxide and niobium oxide.

[0142] For example, in conjunction with reference Fig. 8E and Fig. 9 Forming the passivation layer 36 on the side of the first conductive layer 34 and the second conductive layer 35 away from the substrate 1 may include: forming alternately stacked first sub-passivation layers 361 and second sub-passivation layers 362 on the side of the first conductive layer 34 and the second conductive layer 35 away from the substrate 1 .

[0143] Exemplarily, the number of layers of the first sub-passivation layer 361 and the second sub-passivation layer 362 may be the same or differ by 1.

[0144] For example, the alternately stacked first sub-passivation layer 361 and the second sub-passivation layer 362 may form a DBR structure. The DBR structure may be used for light reflection to improve the light extraction efficiency of the semiconductor device.

[0145] For example, the passivation layer 36 may include a DBR structure formed by alternating silicon oxide and silicon nitride; or, the passivation layer 36 may include a DBR structure formed by alternating silicon oxide and titanium oxide; or, the passivation layer 36 may include a DBR structure formed by alternating silicon oxide and niobium oxide. The passivation layer 36 may also include a DBR structure composed of two other insulating materials with a large refractive index difference.

[0146] Fig.10 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure.

[0147] For example, in the embodiments of the present disclosure, referring to Fig.10 , the method for preparing a semiconductor device may further include:

[0148] Before forming the sacrificial layer 2, a seed layer 11 is formed on the substrate 1. The seed layer 11 can be used as an epitaxial substrate for the sacrificial layer 2 and the functional layer 3, which is beneficial to further improve the crystal quality of the semiconductor material crystal in the functional layer.

[0149] Exemplarily, the semiconductor device may include gallium nitride (GaN). The material of the seed layer may include aluminum nitride (AlN). Compared with sapphire substrates or silicon carbide substrates, AlN has higher thermal matching and chemical compatibility with GaN, and less stress between the substrate and the epitaxial layer. Therefore, when AlN crystal is used as a GaN epitaxial substrate, it can greatly reduce the defect density in the device and improve the performance of the device. It has a good application prospect in the preparation of high-temperature, high-frequency, and high-power electronic devices.

[0150] Fig.11 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure.

[0151] For example, in the embodiments of the present disclosure, referring to Fig.11 The method for preparing a semiconductor device may further include: before forming the sacrificial layer 2, forming a buffer layer 12 and a transition layer 13 on the base substrate 1. Exemplarily, the buffer layer 12 may include gallium nitride, and the transition layer 13 may include undoped gallium nitride.

[0152] Through such a design, on the one hand, the surface morphology and crystal quality of gallium nitride can be further improved, and on the other hand, the resistance of the transition layer 13 can be greater than the resistance of the sacrificial layer 2, so that the sacrificial layer 2 can be corroded preferentially during the electrochemical corrosion process.

[0153] Fig.12 is a schematic structural diagram of an overall device according to an exemplary embodiment of the present disclosure.

[0154] For example, in the embodiments of the present disclosure, referring to Fig.12 In step S3, making the functional layer 3 expose the first portion 21 of the sacrificial layer 2 may include: etching the edge region of the first semiconductor layer 31 in the functional layer 3 to expose the first portion 21 of the sacrificial layer 2. For example, the first portion 21 may be in a ring shape, which is convenient for contacting with the ring electrode, thereby improving the efficiency of electrochemical corrosion.

[0155] Fig.13A and Fig. 13B is a schematic diagram of substrate peeling according to an exemplary embodiment of the present disclosure.

[0156] For example, in the embodiments of the present disclosure, in combination with reference Fig.13A and Fig. 13B After the sacrificial layer 2 is etched, separating the functional layer 3 from the base substrate 1 by using the transfer substrate 100 includes:

[0157] The first surface 101 of the transfer substrate 100 is used to bond the surface 301 of the functional layer 3 away from the base substrate, and then the functional layer 3 is separated from the base substrate 1 by a mechanical method.

[0158] Exemplarily, the transfer substrate 100 may include an adhesive tape or a substrate with adhesive glue.

[0159] Exemplarily, the transfer substrate 100 may include a flexible substrate or a rigid substrate.

[0160] The substrate is peeled off by combining electrochemical corrosion with mechanical transfer, which not only has low equipment requirements, but also has high transfer efficiency and high yield, which can reduce costs.

[0161] In another aspect of the present disclosure, a semiconductor device 30 is provided. The semiconductor device 30 can be manufactured by using the method described in any of the above embodiments. It should be understood that the semiconductor device has the same beneficial effects as the semiconductor device manufacturing method provided in the above embodiments.

[0162] Some embodiments of the disclosed general inventive concept have been shown and described, and it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the disclosed general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: providing a substrate base plate; forming a sacrificial layer on the substrate; forming a functional layer including a semiconductor device on a side of the sacrificial layer away from the substrate, wherein the functional layer exposes a first portion of the sacrificial layer; Etching the sacrificial layer by electrochemical etching; and The functional layer is separated from the base substrate using a transfer substrate.

2. The preparation method according to claim 1, wherein The electrochemical etching to etch the sacrificial layer comprises: connecting a first portion of the sacrificial layer to a first electrode; Immersing the entire device including the substrate, the sacrificial layer and the functional layer in an electrolyte; providing a second electrode, and immersing at least a portion of the second electrode in the electrolyte; Respectively electrically connecting the first electrode and the second electrode to the positive and negative electrodes of a power source; and The sacrificial layer is corroded by adjusting the voltage value and power-on time provided by the power supply.

3. The preparation method according to claim 1 or 2, wherein The forming of a sacrificial layer on the base substrate comprises: forming a sacrificial body layer on one side of the base substrate; and doping the sacrificial main layer with a first doping material to form a sacrificial layer, The functional layer includes at least one semiconductor layer, and the doping concentration of the first doping material in the sacrificial layer is higher than the doping concentration of the semiconductor layer in the functional layer.

4. The preparation method according to claim 3, wherein The doping concentration of the first doping material is 10 18 -10 20 cm -3 within the scope; and / or, The first doping material includes silicon.

5. The preparation method according to claim 3 or 4, wherein The thickness of the sacrificial layer in a first direction is in a range from 5 nanometers to 10 micrometers, wherein the first direction is parallel to a direction from the base substrate toward the sacrificial layer.

6. The preparation method according to claim 2, wherein: The electrolyte includes one of an acidic electrolyte and an alkaline electrolyte; and / or, The material of the second electrode includes a metal conductive material or a non-metal conductive material; and / or, The voltage value provided by the power supply is in the range of 5 to 50V.

7. The preparation method according to any one of claims 1 to 6, wherein: The forming of a functional layer including a semiconductor device on a side of the sacrificial layer away from the substrate includes: Forming a first semiconductor layer, a quantum well layer, a second semiconductor layer and a first conductive layer in sequence on a side of the sacrificial layer away from the substrate; Performing a patterning process on the first semiconductor layer, the quantum well layer, the second semiconductor layer and the first conductive layer to form a first mesa on the first semiconductor layer; Forming a second conductive layer on a side of the first table away from the substrate by thin film deposition technology and patterning process; Forming a passivation layer on a side of both the first conductive layer and the second conductive layer away from the substrate by thin film deposition technology and patterning process, wherein the passivation layer comprises a first opening exposing at least a portion of the first conductive layer, and a second opening exposing at least a portion of the second conductive layer; and A third conductive layer is formed on a side of the passivation layer away from the substrate, and a patterning process is performed to form a third electrode and a fourth electrode, wherein the third electrode is electrically connected to the first conductive layer, and the fourth electrode is electrically connected to the second conductive layer, so as to form a functional layer including a semiconductor device.

8. The preparation method according to claim 1, wherein The semiconductor device includes at least one of gallium nitride, silicon carbide, zinc oxide, gallium indium nitride, aluminum gallium indium nitride, aluminum gallium indium phosphide and diamond.

9. The preparation method according to claim 8, wherein: The method further comprises: Before forming the sacrificial layer, a seed layer is formed on the base substrate, and the material of the seed layer includes aluminum nitride.

10. The preparation method according to claim 8, wherein: The method further comprises: Before forming the sacrificial layer, a buffer layer and a transition layer are formed on the base substrate, wherein the buffer layer comprises gallium nitride and the transition layer comprises undoped gallium nitride.

11. The preparation method according to claim 7, wherein: Exposing the first portion of the sacrificial layer through the functional layer comprises: An edge region of the first semiconductor layer in the functional layer is etched to expose a first portion of the sacrificial layer.

12. The preparation method according to claim 7, wherein: The forming of the first mesa on the first semiconductor layer comprises: The first conductive layer, the second semiconductor layer, the quantum well layer and the first semiconductor layer in a designated area are etched, wherein the first conductive layer, the second semiconductor layer and the quantum well layer in the designated area are completely etched.

13. The preparation method according to any one of claims 1 to 12, wherein: The step of separating the functional layer from the base substrate by using a transfer substrate comprises: The surface of the functional layer away from the base substrate is bonded by using the first surface of the transfer substrate, so that the functional layer is separated from the base substrate.

14. The preparation method according to claim 1, wherein: The substrate includes a sapphire substrate and a silicon substrate.

15. The preparation method according to claim 7, wherein: The forming of the third electrode and the fourth electrode comprises: The third conductive layer is patterned using electron beam lithography and lift-off techniques to form the third electrode and the fourth electrode, wherein the material of the third conductive layer includes metals such as titanium, aluminum, gold, tin, nickel, platinum, chromium, or metal alloys or laminated metals.

16. The preparation method according to claim 7, wherein: The forming of a passivation layer on a side of the first conductive layer and the second conductive layer away from the substrate comprises: A single-layer passivation layer is formed on the side of both the first conductive layer and the second conductive layer away from the substrate, wherein the material of the passivation layer includes a stack of one or more of silicon oxide, silicon nitride and aluminum oxide; and / or, Alternatingly stacked first and second sub-passivation layers are formed on the sides of the first and second conductive layers away from the substrate.

17. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method according to any one of claims 1 to 16.

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