Stress relief saw cut quad flat no-lead semiconductor package

Abstract

The invention relates to a stress relief sawn quad flat no-lead semiconductor package. A semiconductor package (100) has a release recess (118) in a molding compound (114) that extends around a perimeter (124) over a lead (104). The release notch (118) has a release width greater than a thickness (126) of the lead (104) below the release notch. A top surface of the lead may be exposed at the release recess, or may be covered by the molding compound (114) below the release recess. In both cases, a height difference (134) between the molding compound (114) below the release recess and the lead (104) below the release recess is less than the thickness (126) of the lead (104) below the release recess. A majority of the exposed sides (132) of the leads (104) have features of a sawn surface including the leads (104) having no vertical stripes or burrs along the bottom edge. The semiconductor package (100) is singulated by sawing the leads (104).

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging. More particularly, but not exclusively, the present disclosure relates to quad flat no-lead semiconductor packages. Background Art

[0002] Quad flat no-lead (QFN) packages have become a popular choice for compact, high-performance integrated circuit packaging. QFN packages have metal pads on the bottom surface of the package, enabling higher pin density in a smaller form factor. QFN packages exhibit shorter electrical paths, resulting in lower inductance, reduced parasitic capacitance, and enhanced high-frequency performance. QFN packages offer simplified assembly processes, increased automation compatibility, and reduced material costs. Summary of the invention

[0003] A semiconductor package has leads around the periphery of the semiconductor package and a microelectronic assembly electrically coupled to a plurality of the leads. An electrically insulating molding compound contacts the leads and the microelectronic assembly. The molding compound is recessed around the periphery to provide a release notch above a portion of each of the leads. The release notch has a release width greater than the thickness of the lead below the release notch. In one aspect, the top surface of the lead may be exposed at the release notch. In another aspect, the top surface of the lead may be covered by the molding compound below the release notch. In two aspects, the height difference between the molding compound below the release notch and the lead below the release notch is less than the thickness of the lead below the release notch. The exposed side of most of the leads has the characteristics of a sawing surface. In one aspect, the characteristics of having a sawing surface may include that the exposed side of most of the leads has no vertical stripes. In another aspect, the characteristics of having a sawing surface may include that the exposed side of most of the leads has burrs along the bottom edge.

[0004] The semiconductor package is formed by electrically coupling the microelectronic assembly to the leads and forming the molding compound on the leads and the microelectronic assembly. A release notch is formed in the molding compound around the perimeter above the leads such that the molding compound is laterally recessed around the perimeter to provide the release notch. The semiconductor package is singulated by sawing the leads. In one aspect, the molding compound may be laterally recessed prior to singulating the semiconductor package. In another aspect, the molding compound may be laterally recessed after singulating the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A to Figure 1H are top, cross-sectional, and perspective views of a semiconductor package with a release recess depicted in successive stages of an example formation method.

[0006] Figures 2A to 2H are top, cross-sectional, and perspective views of another semiconductor package having a release recess depicted in successive stages of an example formation method.

[0007] Figures 3A to 3D are cross-sectional and perspective views of another semiconductor package having a release notch depicted in successive stages of an example formation method.

[0008] Figure 4A and Figure 4B is a cross-sectional view of another semiconductor package having a release recess depicted in successive stages of an example formation method.

[0009] FIG. 5A to FIG. 5C is a cross-sectional view of another semiconductor package having a release recess depicted in successive stages of an example formation method.

[0010] FIG. 6A to FIG. 6C is a cross-sectional view of another semiconductor package having a release recess depicted in successive stages of an example formation method.

[0011] Figure 7 It is a cross-sectional view of a semiconductor package singulated by a punching process.

[0012] Figure 8 is a cross-sectional view of a semiconductor package having exposed sides of leads having features of sawn surfaces. DETAILED DESCRIPTION

[0013] The present disclosure is described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided only for illustrating the present disclosure. Several aspects of the present disclosure are described below with reference to example applications for illustrative purposes. It should be understood that many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the order in which the actions or events are described, because some actions may occur in different orders and / or simultaneously with other actions or events. In addition, implementation of the method according to the present disclosure does not require all described actions or events.

[0014] A semiconductor package has leads around the periphery of the semiconductor package. The leads are attached to a lead frame. A microelectronic assembly is electrically coupled to the plurality of leads. An electrically insulating molding compound is formed on the leads and the microelectronic assembly. The molding compound is recessed around the periphery to provide a release notch above a portion of each of the leads. The release notch has a release width in a direction perpendicular to the periphery that is greater than the thickness of the lead below the release notch. In one version, the release notch may be formed so that the top surface of the lead may be exposed at the release notch. In another version, the release notch may be formed so that the top surface of the lead may be covered by the molding compound below the release notch. The height difference between the molding compound below the release notch and the lead below the release notch is less than the thickness of the lead below the release notch.

[0015] The semiconductor package is singulated by sawing the leads. Singulation by sawing enables the use of a lead frame to form multiple semiconductor packages simultaneously because molding compound can be formed on all semiconductor packages in one operation, which is not cost-effective for punching (stamping) singulation. The exposed sides of most of the leads have the characteristics of sawing surfaces. In one aspect, the characteristics of having sawing surfaces may include that the exposed sides of most of the leads have no vertical stripes. In another aspect, the characteristics of having sawing surfaces may include that the exposed sides of most of the leads have burrs along the bottom edge. In one version, the molding compound may be laterally recessed before singulating the semiconductor package. In another version, the molding compound may be laterally recessed after singulating the semiconductor package.

[0016] In electronic systems containing semiconductor packages, leads are attached to a substrate such as a printed circuit board, where solder joints connect the leads to terminals of the substrate. Due to the thermal expansion mismatch between the semiconductor package and the substrate, stress is generated in the solder joints. Relief notches can advantageously reduce stress by reducing the transmission of stress in the molding compound to the leads.

[0017] Note that terms such as top, bottom, over, and under may be used in the present disclosure. These terms should not be understood as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements.

[0018] Figure 1A to Figure 1H are top, cross-sectional, and perspective views of a semiconductor package with a release recess depicted in successive stages of an example formation method. Figure 1A is a top view of a semiconductor package, and Figure 1B yes Figure 1A A cross-sectional view of a semiconductor package at a first stage of formation. Figure 1A and Figure 1B , the semiconductor package 100 is formed using a lead frame 102. The lead frame 102 of this example accommodates an additional semiconductor package 100a adjacent to the semiconductor package 100.

[0019] The semiconductor package 100 includes a plurality of leads 104 of a lead frame 102. Similarly, the additional semiconductor package 100a also includes a plurality of additional leads 104a of the lead frame 102. The semiconductor package 100 of this example includes a die pad 106 of the lead frame 102. Similarly, the additional semiconductor package 100a also includes an additional die pad that is not specifically shown.

[0020] A microelectronic component 108 is attached to the die pad 106. For example, the microelectronic component 108 may be embodied as an integrated circuit, a discrete component such as a power transistor, a passive component such as a transformer or a filter, a microelectromechanical system (MEMS) component, a sensor, an actuator, a microfluidic component, or an electro-optical component such as a micromirror array component. The microelectronic component 108 may be attached to the die pad 106 by a die attach material 110 such as solder, a conductive adhesive, an electrically insulating adhesive, or a eutectic metal alloy. Additional microelectronic components, not specifically shown, are attached to additional die pads of additional semiconductor packages 100a.

[0021] Electrical connections 112 are formed between microelectronic assembly 108 and leads 104. Electrical connections 112 may be implemented as wire bonds 112, such as Figure 1A and Figure 1B Alternatively, electrical connections 112 may be implemented as tape bonds, clips, wire leads on resin coated copper, or solder bumps, for example.

[0022] Molding compound 114 is formed on lead frame 102, including on leads 104 and additional leads 104a, microelectronic components 108, and electrical connections 112. In this example, molding compound 114 is formed between bottom mold plate 116a and top mold plate 116b. Bottom mold plate 116a contacts the bottom surface of leads 104. Molding compound 114 is electrically insulating. For example, molding compound 114 may include epoxy resin. Molding compound 114 may include filler particles such as silica particles or alumina particles to reduce the thermal expansion coefficient of molding compound 114.

[0023] Figure 1C is a top view of the semiconductor package 100, and Figure 1D yes Figure 1C FIG. 1 is a cross-sectional view of a semiconductor package 100 at a subsequent formation stage. Figure 1C and Figure 1D, the molding material 114 is laterally recessed to provide a relief notch 118 in the molding material 114 above the lead 104, and to provide an additional relief notch 118a in the molding material 114 above the additional lead 104a. In this example, the relief notch 118 and the additional relief notch 118a are formed by a release sawing operation using a release saw blade 120. The relief notch 118 has a relief width 122 in a direction perpendicular to a perimeter 124 of the semiconductor package 100 that is greater than a lead thickness 126 of the lead 104 below the relief notch 118. The release saw blade 120 can form the relief notch 118 and the additional relief notch 118a in a single pass, such as in Figure 1D . Alternatively, the release notch 118 and the additional release notch 118a can be formed by two or more passes of the release saw blade 120. Forming the release notch 118 by a release sawing operation can advantageously provide flexibility for accommodating a variety of package sizes and can advantageously provide low manufacturing costs compared to using a package-specific mold to form the release notch 118. In this example, the top surface of the lead 104 is not exposed by the formation of the release notch 118, that is, a portion of the molding compound 114 remains above the lead 104 below the release notch 118, which can advantageously protect the lead 104 from contamination or chemical degradation.

[0024] Figure 1E is a top view of the semiconductor package 100, and Figure 1F yes Figure 1E FIG. 1 is a cross-sectional view of a semiconductor package 100 at a subsequent formation stage. Figure 1E and Figure 1F , the semiconductor package 100 and the additional semiconductor package 100a are mounted on a saw belt 128, also referred to as a saw film 128. The semiconductor package 100 is singulated from the additional semiconductor package 100a by a singulation sawing process using a singulation saw blade 130. The singulation sawing process cuts through and separates the leads 104 of the semiconductor package 100 and the additional leads 104a of the additional semiconductor package 100a, as well as the molding compound 114 between the semiconductor package 100 and the additional semiconductor package 100a. The semiconductor package 100 and the additional semiconductor package 100a are then removed from the saw belt 128. The singulation sawing process produces exposed side surfaces 132 of the leads 104. Most of the exposed side surfaces 132 have the characteristics of a sawn surface. Reference Figure 8 The exposed side surface 132 is disclosed to have details of features of a saw cut surface.

[0025] Figure 1G is a perspective view of the semiconductor package 100 after singulation, and Figure 1H yes Figure 1G 1 is a cross-sectional view of a semiconductor package 100. Figure 1G and Figure 1H, the height difference 134 between the molding compound 114 below the release notch 118 and the leads 104 below the release notch 118 is less than the lead thickness 126 of the leads 104 below the release notch 118, which can advantageously reduce stress in the molding compound 114 and the leads 104 compared to similar semiconductor packages with thicker molding compound above the leads. The upper portion 138 of the release notch 118 along the side 136 of the molding compound 114 can be vertical relative to the top surface 140 of the molding compound 114, thereby providing a larger area for the top surface 140, which can advantageously facilitate subsequent vacuum pick-and-place operations when soldering the semiconductor package 100 to a circuit board. Figure 1H , the interior corners 142 of the relief notch 118 may have a rounded profile, which may advantageously reduce stress concentrations in the molding compound 114 and the leads 104 .

[0026] Figures 2A to 2H are top, cross-sectional, and perspective views of another semiconductor package having a release recess depicted in successive stages of an example formation method. Figure 2A is a top view of a semiconductor package, and Figure 2B yes Figure 2A A cross-sectional view of a semiconductor package at a first stage of formation. Figure 2A and Figure 2B , the semiconductor package 200 is formed using a lead frame 202. The lead frame 202 of this example accommodates an additional semiconductor package 200a adjacent to the semiconductor package 200. The semiconductor package 200 includes a plurality of leads 204 of the lead frame 202. Similarly, the additional semiconductor package 200a also includes a plurality of additional leads 204a of the lead frame 202.

[0027] Microelectronic assembly 208 is attached to leads 204 via electrical connections 212. In this example, electrical connections 212 may be implemented as solder bumps, such as in Figure 2A and Figure 2B Additional microelectronic components, not specifically shown, are attached to additional leads 204a of additional semiconductor package 200a.

[0028] Molding compound 214 is formed on lead frame 202, including on leads 204 and additional leads 204a, microelectronic components 208, and electrical connections 212. In this example, molding compound 214 is formed between bottom mold plate 216a and top mold plate 216b. In this example, compressible mold release film 244 is located between bottom mold plate 216a and the bottom surface of leads 204. Molding compound 214 is electrically insulating. Compressible mold release film 244 is compressed between bottom mold plate 216a and leads 204, thereby recessing molding compound 214 from the bottom surface of leads 204, so that leads 204 extend below the bottom surface of molding compound 214.

[0029] Figure 2C is a top view of the semiconductor package 200, and Figure 2D yes Figure 2C FIG. 2 is a cross-sectional view of a semiconductor package 200 at a subsequent formation stage. Figure 2C and Figure 2D , a relief notch 218 is formed in the molding material 214 above the lead 204, and an additional relief notch 218a is formed in the molding material 214 above the additional lead 204a. In this example, similar to the reference Figure 1C and Figure 1D In the disclosed process, the relief notch 218 and the additional relief notch 218a are formed by a relief sawing operation using a relief saw blade 220. In this example, the relief saw blade 220 cuts down to the lead 204, thereby exposing the top surface of the lead 204 below the relief notch 218, which can advantageously provide further stress relief compared to a similar semiconductor package having a molding compound covering the lead. In this example, the relief saw blade 220 can optionally remove a portion of the lead 204. The relief notch 218 has a relief width 222 that is greater than the lead thickness 226 of the lead 204 below the relief notch 218 in a direction perpendicular to the perimeter 224 of the semiconductor package 200.

[0030] Figure 2E is a top view of the semiconductor package 200, and Figure 2F yes Figure 2E FIG. 2 is a cross-sectional view of a semiconductor package 200 at a subsequent formation stage. Figure 2E and Figure 2F , the semiconductor package 200 and the additional semiconductor package 200a are mounted on the saw belt 228. The semiconductor package 200 is singulated from the additional semiconductor package 200a by a singulation sawing process using a singulation saw blade 230. The singulation sawing process cuts through the leads 204 of the semiconductor package 200 and separates the leads 204 of the semiconductor package 200 from the lead frame 202, and is similar for the additional leads 204a of the additional semiconductor package 200a. The sawing process also cuts through and separates the molding compound 214 between the semiconductor package 200 and the additional semiconductor package 200a. The semiconductor package 200 and the additional semiconductor package 200a are subsequently removed from the saw belt 228. The singulation sawing process produces exposed side surfaces 232 of the leads 204. Most of the exposed side surfaces 232 have the characteristics of a sawing surface.

[0031] Figure 2G is a perspective view of the semiconductor package 200 after singulation, and Figure 2H yes Figure 2G 2 is a cross-sectional view of a semiconductor package 200. Figure 2G and Figure 2HDue to the release sawing operation that cuts down to the leads 204, thereby exposing the top surfaces of the leads 204, the molding compound 214 below the release notch 218 and the leads 204 below the release notch 218 are substantially coplanar. Therefore, the height difference between the molding compound 214 below the release notch 218 and the leads 204 below the release notch 218 is approximately zero, and in any case, is much smaller than the lead thickness 226 of the leads 204 below the release notch 218, which can advantageously reduce stress in the molding compound 214 and the leads 204.

[0032] Figures 3A to 3D are cross-sectional and perspective views of another semiconductor package having a release notch depicted in successive stages of an example formation method. Figure 3A is a cross-sectional view of a semiconductor package at a first stage of formation. Figure 3A , semiconductor package 300 is formed using lead frame 302. The lead frame 302 of this example can accommodate an additional semiconductor package 300a adjacent to semiconductor package 300. Semiconductor package 300 includes a plurality of leads 304 and a die pad 306 of lead frame 302. Similarly, the additional semiconductor packages 300a each include a plurality of additional leads 304a and an additional die pad (not shown) of lead frame 302.

[0033] Microelectronic assembly 308 is attached to die pad 306 by die attach material 310. Additional microelectronic assembly, not specifically shown, is attached to additional die pad of additional semiconductor package 300a. Electrical connections 312, implemented as wire bonds 312 in this example, are formed between microelectronic assembly 308 and leads 304. Additional electrical connections are formed between additional microelectronic assembly and additional leads 304a.

[0034] Molding material 314 is formed on lead frame 302, including on leads 304 and additional leads 304a, microelectronic components 308 and additional microelectronic components, and electrical connections 312 and additional electrical connections. Molding material 314 may be formed using a mold plate, as described in reference to FIG. Figure 1B The molding compound 314 is electrically insulating.

[0035] Figure 3B31 is a cross-sectional view of semiconductor package 300 at a subsequent formation stage. Molding material 314 is laterally recessed to provide a release notch 318 above lead 304 and an additional release notch 318a above additional lead 304a. In this example, release notch 318 and additional release notch 318a can be formed by an ablation process operation using a laser ablation tool 346 to remove material from molding material 314. Release notch 318 has a release width 322 in a direction perpendicular to a perimeter 324 of semiconductor package 300 that is greater than a lead thickness 326 of lead 304 below release notch 318. In one version of this example, laser ablation tool 346 can move in two orthogonal directions above semiconductor package 300 while semiconductor package 300 remains stationary to form release notch 318. In another version, laser ablation tool 346 can remain stationary while semiconductor package 300 moves in two orthogonal directions below laser ablation tool 346. In another version, laser ablation tool 346 may be moved in a first direction while semiconductor package 300 is moved in a second orthogonal direction. In this example, the top surface of lead 304 is not exposed by the formation of release notch 318, that is, a portion of molding compound 314 remains above lead 304 below release notch 318, which may advantageously protect lead 304 from contamination or chemical degradation. Forming release notch 318 by an ablation process operation using laser ablation tool 346 may advantageously increase throughput and reduce breakage compared to sawing.

[0036] Subsequently, the semiconductor package 300 is singulated from the additional semiconductor package 300a by a singulation sawing process using a saw blade not specifically shown. The singulation sawing process cuts through the leads 304 of the semiconductor package 300 and separates the leads 304 of the semiconductor package 300 from the lead frame 302, and similarly for the additional leads 304a of the additional semiconductor package 300a. The sawing process also cuts through and separates the molding compound 314 between the semiconductor package 300 and the additional semiconductor package 300a. The singulation sawing process produces a single-cut lead 304. Figure 3C The exposed side 332 shown in FIG. 3 , most of the exposed side 332 has the characteristics of a saw cut surface.

[0037] Figure 3C is a perspective view of the semiconductor package 300 after singulation, and Figure 3D yes Figure 3C FIG. 3 is a cross-sectional view of a semiconductor package 300. Figure 3C and Figure 3D The height difference 334 between the molding material 314 under the release notch 318 and the lead 304 under the release notch 318 is smaller than the lead thickness 326 of the lead 304 under the release notch 318 , which can bring the advantage of reduced stress in the molding material 314 and the lead 304 .

[0038] Figure 4A and Figure 4B is a cross-sectional view of another semiconductor package having a release notch depicted in successive stages of an example formation method. Figure 4A , semiconductor package 400 is formed using lead frame 402. Lead frame 402 of this example accommodates additional semiconductor package 400a adjacent to semiconductor package 400. Semiconductor package 400 includes a plurality of leads 404 of lead frame 402. Similarly, additional semiconductor package 400a also includes a plurality of additional leads 404a of lead frame 402.

[0039] Microelectronic component 408 is attached to leads 404 by electrical connections 412. In this example, electrical connections 412 may be implemented as solder bumps. Additional microelectronic components, not specifically shown, are attached to additional leads 404a of additional semiconductor package 400a.

[0040] Molding compound 414 is formed over lead frame 402, including over leads 404 and additional leads 404a, microelectronic components 408 and additional microelectronic components, and electrical connections 412 and additional electrical connections. Molding compound 414 is electrically insulating.

[0041] The release notch 418 is formed in the molding material 414 above the lead 404, and the additional release notch 418a is formed in the molding material 414 above the additional lead 404a. In this example, the release notch 418 and the additional release notch 418a are formed by a machining operation using a cutting tool 448 that removes the molding material 414. Compared with other methods, forming the release notch 418 by a machining operation can advantageously provide lower equipment costs and higher throughput. The machining operation can cover the top surface of the lead 404 with a portion of the molding material 414 below the release notch 418. Alternatively, the top surface of the lead 404 can be exposed by forming the release notch 418. The release notch 418 has a release width 422 that is larger than the lead thickness 426 of the lead 404 below the release notch 418 in a direction perpendicular to the periphery 424 of the semiconductor package 400.

[0042] refer to Figure 4B , the semiconductor package 400 is singulated by a sawing operation, and the sawing operation produces exposed side surfaces 432 of the leads 404. At least a majority of the exposed side surfaces 432 have the characteristics of a sawing surface. The height difference 434 between the molding material 414 under the relief notch 418 and the leads 404 under the relief notch 418 is less than the lead thickness 426 of the leads 404 under the relief notch 418, which can bring the advantage of reduced stress in the molding material 414 and the leads 404.

[0043] FIG. 5A to FIG. 5Cis a cross-sectional view of another semiconductor package having a release recess depicted in successive stages of an example formation method. Referring to FIG. 5 , a semiconductor package 500 depicted in a first formation stage Figure 5A , a semiconductor package 500 is formed using a lead frame 502. The lead frame 502 of this example can accommodate an additional semiconductor package 500a adjacent to the semiconductor package 500. The semiconductor package 500 includes a plurality of leads 504 and a die pad 506. Similarly, the additional semiconductor packages 500a each include a plurality of additional leads 504a and additional die pads that are not specifically shown.

[0044] Microelectronic assembly 508 is attached to die pad 506 by die attach material 510. Additional microelectronic assembly, not specifically shown, is attached to additional die pad of additional semiconductor package 500a. Electrical connections 512, which may be implemented as wire bonds 512, are formed between microelectronic assembly 508 and leads 504. Additional electrical connections, not specifically shown, are formed between additional microelectronic assembly and additional leads 504a.

[0045] Molding compound 514 is formed on lead frame 502, including on leads 504 and additional leads 504a, microelectronic components 508 and additional microelectronic components, and electrical connections 512 and additional electrical connections. Molding compound 514 is electrically insulating. Molding compound 514 is formed between bottom mold plate 516a and top mold plate 516b. Top mold plate 516b of this example includes release notch protrusion 550, which extends vertically downward near leads 504 and additional leads 504a in the area for release notch 518 above leads 504 and additional release notch 518a above additional leads 504a. Bottom mold plate 516a contacts the bottom surface of leads 504.

[0046] refer to Figure 5B , the bottom mold plate 516a and the top mold plate 516b are separated from the semiconductor package 500 and the additional semiconductor package 500a. The release recess 518 and the additional release recess 518a are formed by the release recess protrusion 550. Figure 5B , the release recess 518 and the additional release recess 518a may have a tapered profile to facilitate separation of the top mold plate 516b from the semiconductor package 500 and the additional semiconductor package 500a. Forming the release recess 518 using the release recess protrusion 550 of the top mold plate 516b while forming the molding compound 514 may advantageously reduce manufacturing costs and improve throughput compared to forming the release recess 518 by a separate operation.

[0047] refer to Figure 5C, the semiconductor package 500 is singulated by a sawing operation, which produces exposed side surfaces 532 of the leads 504. At least a majority of the exposed side surfaces 532 have the characteristics of a sawing surface. Figure 8 Details of features having a sawn surface are disclosed.

[0048] FIG. 6A to FIG. 6C is a cross-sectional view of another semiconductor package having a release notch depicted in successive stages of an example formation method. Fig. 6A , depicting a semiconductor package 600 at a first stage of formation. The semiconductor package 600 is formed using a lead frame 602, which can accommodate an additional semiconductor package 600a adjacent to the semiconductor package 600. The semiconductor package 600 includes a plurality of leads 604 and a die pad 606, and the additional semiconductor packages 600a each include a plurality of additional leads 604a and additional die pads that are not specifically shown.

[0049] Microelectronic assembly 608 is attached to die pad 606 by die attach material 610, and additional microelectronic assembly, not specifically shown, is attached to additional die pad of additional semiconductor package 600a. Electrical connections 612 are formed between microelectronic assembly 608 and leads 604, and additional electrical connections, not specifically shown, are formed between additional microelectronic assembly and additional leads 604a.

[0050] Molding compound 614 is formed on lead frame 602, including on leads 604 and additional leads 604a, microelectronic components 608 and additional microelectronic components, and electrical connections 612 and additional electrical connections. Molding compound 614 is electrically insulating. Molding compound 614 can be formed between bottom mold plate 616a and top mold plate 616b.

[0051] refer to Figure 6B , the semiconductor package 600 is singulated from the additional semiconductor package 600a by a singulation sawing process using a singulation saw blade 630. The singulation sawing process cuts through and separates the leads 604 of the semiconductor package 600 and the additional leads 604a of the additional semiconductor package 600a, as well as the molding compound 614 between the semiconductor package 600 and the additional semiconductor package 600a. The semiconductor package 600 and the additional semiconductor package 600a may be mounted on a saw blade or other substrate for the singulation sawing process. The singulation sawing process produces exposed side surfaces 632 of the leads 604; most of the exposed side surfaces 632 have the characteristics of a sawing surface.

[0052] refer to Figure 6C After singulating the semiconductor package 600, a release recess 618 is formed in the molding compound 614 above the lead 604. The release recess 618 may be formed by an ablation operation using a laser ablation tool 646, such as Figure 6C, or may be formed by another process such as a machining operation or a release sawing operation. The release notch 618 has a release width 622 in a direction perpendicular to a perimeter 624 of the semiconductor package 600 that is greater than a lead thickness 626 of the lead 604 below the release notch 618 .

[0053] exist Figure 6C In a version of this example depicted in FIG, the top surface of the lead 604 may be covered by the portion of the molding compound 614 below the release notch 618. Such that the height difference 634 between the molding compound 614 below the release notch 618 and the lead 604 below the release notch 618 is less than the lead thickness 626 of the lead 604 below the release notch 618. In another version, the top surface of the lead 604 may be exposed by the formation of the release notch 618, in which case the height difference 634 between the molding compound 614 and the lead 604 is still less than the lead thickness 626 of the lead 604.

[0054] Forming release notches 618 after singulating semiconductor packages 600 may advantageously enable forming release notches in semiconductor packages held in inventory that have been singulated as needed, for example, based on product.

[0055] Figure 7 is a cross-sectional view of a semiconductor package singulated by a punching process. The semiconductor package 700 includes a molding compound 714 and leads 704 extending to a perimeter 724 of the semiconductor package 700. The leads 704 have exposed sides 732 with vertical stripes 752 resulting from the punching singulation process.

[0056] Figure 8 8 is a cross-sectional view of a semiconductor package having an exposed side with a sawing surface characteristic of a lead. The semiconductor package 800 includes a molding compound 814 and a lead 804 extending to a periphery 824 of the semiconductor package 800. Due to singulation by a singulation sawing process, the lead 804 has an exposed side 832 without vertical stripes. During the subsequent assembly of the semiconductor package 800 to a substrate such as a printed circuit board, leaving the exposed side 832 without vertical stripes can provide a more uniform solder distribution on the exposed side 832, which can advantageously provide a more uniform solder joint between the lead 804 and the substrate compared to the lead with vertical stripes, thereby improving board-level reliability. The lead 804 has a burr 854 along the bottom edge. The burr 854 is formed by a singulation sawing process. The burr 854 can advantageously reduce lateral movement of the semiconductor package 800 during the subsequent assembly of the semiconductor package 800 to the substrate by adhering more firmly to the solder paste on the substrate than the lead without burrs.

[0057] Various features of the examples disclosed herein may be combined in other manifestations of the example semiconductor package. For example, any of the release recesses 118 to 618 may be formed by a release sawing process, an ablation process, or a machining process. Any of the release recesses 118 to 618 may be formed to cover the leads 104 to 604 with the molding compound 114 to 614, respectively. Any of the release recesses 118 to 618 may be formed to expose the top surface of the leads 104 to 604, respectively. Any of the release recesses 118 to 618 may be formed to have an inner corner with a rounded profile.

[0058] Although various embodiments of the present disclosure have been described above, it should be understood that they are given by way of example only and not limitation. Without departing from the spirit or scope of the present disclosure, many changes may be made to the disclosed embodiments according to the disclosure herein. Therefore, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. On the contrary, the scope of the present disclosure should be defined according to the attached claims and their equivalents.

Claims

1. A semiconductor package, comprising: leads surrounding a periphery of the semiconductor package; a microelectronic assembly electrically coupled to a plurality of said leads; a molding compound contacting the leads and the microelectronic assembly, wherein: The molding compound is electrically insulating; The molding compound is recessed around the perimeter to provide a relief notch, the relief notch having a relief width greater than a thickness of the lead below the relief notch; A height difference between the molding compound under the release notch and the lead under the release notch is less than the thickness of the lead under the release notch; and The exposed sides of a majority of the leads are characterized by saw cut surfaces. 2 . The semiconductor package according to claim 1 , wherein an upper portion of the relief recess along a side surface of the molding compound is vertical with respect to a top surface of the molding compound. The semiconductor package according to claim 1 , wherein the lead is exposed at the release notch. The semiconductor package according to claim 1 , wherein a top surface of the lead is exposed below the relief recess. 5 . The semiconductor package according to claim 1 , wherein a top surface of the lead is covered by the molding compound below the relief recess. 6 . The semiconductor package of claim 1 , wherein the feature that the exposed sides of the majority of the leads have a sawn surface includes that the exposed sides of the majority of the leads have no vertical stripes. 7 . The semiconductor package of claim 1 , wherein the feature that the exposed sides of the majority of the leads have a sawn surface comprises that the exposed sides of the majority of the leads have burrs along bottom edges. 8 . The semiconductor package of claim 1 , wherein the leads extend below a bottom surface of the molding compound.

9. A method of forming a semiconductor package, comprising: electrically coupling a microelectronic assembly to leads extending to a perimeter of the semiconductor package; forming a molding compound on the leads and on the microelectronic assembly, the molding compound being electrically insulating; recessing the molding compound laterally around the perimeter to provide a relief notch having a relief width greater than a thickness of the lead beneath the relief notch; as well as The semiconductor packages are singulated by sawing the leads.

10. The method of claim 9, wherein laterally recessing the molding compound creates a height difference between the molding compound under the relief notch and the lead under the relief notch, the height difference being less than the thickness of the lead under the relief notch. 11 . The method of claim 9 , wherein laterally recessing the molding compound is performed before singulating the semiconductor packages. 12 . The method of claim 9 , wherein laterally recessing the molding compound is performed by removing a portion of the molding compound using a sawing process.

13. The method of claim 9, wherein laterally recessing the molding compound is performed by removing a portion of the molding compound using an ablation process.

14. The method of claim 9, wherein laterally recessing the molding compound is performed by removing a portion of the molding compound using a machining process.

15. The method of claim 9, wherein laterally recessing the molding compound is performed by molding the molding compound using a mold plate having ridges corresponding to the relief recesses.

16. The method of claim 9, wherein the molding compound is recessed laterally to expose the leads.

17. The method of claim 9, wherein recessing the molding compound laterally removes top portions of the leads.

18. The method of claim 9, wherein the molding compound is formed such that the leads extend below a bottom surface of the molding compound.

19. The method of claim 9, wherein laterally recessing the molding compound is performed after singulating the semiconductor packages.

20. A semiconductor package, comprising: leads surrounding a periphery of the semiconductor package; a microelectronic assembly electrically coupled to a plurality of said leads; as well as a molding compound contacting the leads and the microelectronic assembly, wherein: The molding compound is electrically insulating; The molding compound is recessed around the perimeter to provide a relief notch; The relief notch has a relief width greater than a thickness of the lead below the relief notch; An upper portion of the release recess along a side of the molding compound is vertical relative to a top surface of the molding compound; The inner corners of the release recess have a rounded profile; A height difference between the molding compound under the release notch and the lead under the release notch is less than the thickness of the lead under the release notch; and The exposed sides of a majority of the leads are characterized by saw cut surfaces.

21. A method of forming a plurality of semiconductor packages, comprising: electrically coupling a plurality of microelectronic assemblies to leads of a lead frame, the leads extending to a perimeter of the plurality of semiconductor packages; forming a molding compound on the leads and on the plurality of microelectronic components simultaneously, the molding compound being electrically insulating; recessing the molding compound laterally around the perimeter to provide a relief notch having a relief width greater than a thickness of the lead beneath the relief notch; as well as The semiconductor packages are singulated by sawing the leads.

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