Package and method of forming same

Abstract

A method of forming a package includes forming a device die, the forming the device die including forming an integrated circuit on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and in contact with the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar. The embodiment of the invention also relates to a package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to packages and methods of forming the same. Background Art

[0002] As the integration of integrated circuits becomes higher and higher, more and more devices are compressed into a smaller area. At the same time, in order to increase the speed of integrated circuits, the driving current of integrated circuits has also become higher. Therefore, the heat dissipation of integrated circuits has become more demanding. Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a package, the method comprising:

[0004] forming a first device die, the forming of the first device die comprising: forming an integrated circuit on a first semiconductor substrate; and forming a thermally conductive column extending into the first semiconductor substrate; and

[0005] A cooling medium is attached over and in contact with the first semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillars.

[0006] Another embodiment of the present disclosure provides a package, the package comprising:

[0007] a first device die, the first device die comprising: a first semiconductor substrate; an integrated circuit located on the first semiconductor substrate; a dielectric layer located below the first semiconductor substrate; and a thermally conductive column extending into the first semiconductor substrate; and

[0008] A cooling medium is located above the first semiconductor substrate and contacts the first semiconductor substrate, wherein the cooling medium contacts the thermally conductive pillars.

[0009] Another embodiment of the present disclosure provides a package, comprising:

[0010] A device die, the device die comprising: a semiconductor substrate; a plurality of dielectric layers located below the semiconductor substrate; a thermally conductive column penetrating the semiconductor substrate, wherein the thermally conductive column extends into one of the plurality of dielectric layers; and

[0011] A thermal interface material is located above and contacts the semiconductor substrate, wherein the thermally conductive pillar is in physical contact with the thermal interface material.

[0012] The present disclosure also relates to a heat dissipation structure and a method for forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0014] Figure 1A , Figure 1B , Figure 2 , Figure 3 and Figure 4 A cross-sectional view is shown of an intermediate stage in the formation of a package including thermally conductive pillars in accordance with some embodiments.

[0015] Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Figure 8 and Fig. 9 A cross-sectional view is shown of an intermediate stage in the formation of a package including thermally conductive pillars in accordance with some embodiments.

[0016] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E Views showing portions of a package and corresponding thermally conductive pillars according to some embodiments.

[0017] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D Views showing portions of a package and corresponding thermally conductive pillars according to some embodiments.

[0018] Fig.12 , Fig.13A and Fig. 13B Views of packages and corresponding thermally conductive pillars are shown according to some embodiments.

[0019] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E A top view of a thermally conductive column is shown in accordance with some embodiments.

[0020] Fig.15 A process flow for forming a package including thermally conductive pillars is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] A heat dissipation structure and a method for forming the same are provided. According to some embodiments of the present disclosure, a heat-conducting column is formed to extend into a semiconductor substrate. The heat-conducting column includes a heat-conducting material having a better thermal conductivity than silicon. The heat-conducting column can penetrate the semiconductor substrate of the device die so that it can conduct the heat in the device die away and conduct it to a heat sink or a heat sink. The embodiments discussed herein are intended to provide examples of the subject matter of the present disclosure that can be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of different embodiments. In various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0024] Figure 1A , Figure 1B and Figures 2 to 4 2 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure. This process is also referred to as a pillar-first process because the thermally conductive pillar is formed before the thinning of the semiconductor substrate 24. The corresponding process is also schematically reflected in Fig.15 The process flow shown in .

[0025] Figure 1A 2 shows a cross-sectional view of the formation of the package assembly 20. The corresponding process is shown as follows Fig.15Process 202 in process flow 200 is shown. According to some embodiments, package assembly 20 is or includes a device wafer, which includes active devices and possible passive devices, which are shown as integrated circuit devices 26. A plurality of dies 20' may be included in package assembly 20, where details of one of dies 20' are shown. According to alternative embodiments, package assembly 20 is or includes a package such as an integrated fan-out (InFO) package. For example, package assembly 20 may be a reconstructed wafer, which includes device dies and / or wafers bonded together and possibly an encapsulant (such as a molding compound).

[0026] In the ensuing discussion, a device wafer is used as an example of the package assembly 20, and the package assembly 20 may also be referred to hereinafter as the wafer 20. The embodiments may also be applied to reconstituted wafers, discrete packages, discrete device dies, and the like.

[0027] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and features formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0028] According to some embodiments, integrated circuit device 26 is formed at a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit device 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit device 26 are not shown here.

[0029] An interlayer dielectric (ILD) 28 is formed over semiconductor substrate 24 and fills spaces between gate stacks of transistors (not shown) in integrated circuit device 26. According to some embodiments, ILD 28 is formed of phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, fluorine-doped silicate glass (FSG), silicon oxide, silicon oxynitride, silicon nitride, etc. ILD 28 may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0030] Contact plug 30 is formed in ILD 28 and is used to electrically connect integrated circuit device 26 to the above metal lines and vias. According to some embodiments, contact plug 30 is formed of or includes a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof.

[0031] According to some embodiments, thermally conductive pillars 22 are formed to extend into semiconductor substrate 24. According to some embodiments, thermally conductive pillars 22 are formed at a time after forming ILD 28. Formation of thermally conductive pillars 22 may include etching ILD 28 and semiconductor substrate 24 to form openings, and filling the openings with thermally conductive materials. A planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed to remove excess portions of the material filled in the openings, thereby forming thermally conductive pillars 22.

[0032] It should be understood that although Figure 1A The top surface of the thermally conductive pillar 22 is shown to be at the same level as the top surface of the conductive plug 30 , but the top surface of the thermally conductive pillar 22 may be at other levels, such as at the same level as the top surface of the overlying metal line or via.

[0033] Figure 1B FIG. 2 shows an enlarged view of a thermally conductive column 22 according to some embodiments. The thermally conductive column 22 shown can be Figure 1A The thermally conductive column 22 may include a dielectric liner 22L for preventing leakage and a core 22C having a thermal conductivity higher than that of silicon, for example, about 4 W / cm-K. The barrier 22B may or may not be present, and the barrier 22B also has a high thermal conductivity higher than that of silicon.

[0034] In addition, the thermal conductivity of dielectric liner 22L can be lower than, equal to, or greater than the thermal conductivity of silicon. However, due to the higher thermal conductivity of thermally conductive core 22C and barrier 22B (if formed), the overall thermal conductivity (ability to conduct heat vertically) of thermally conductive pillar 22 is higher than the thermal conductivity of silicon.

[0035] According to some embodiments, the dielectric liner 22L is formed of or includes silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, etc. The barrier 22B may be formed of or include Ti, TiN, Ta, TaN, etc. The thermally conductive core 22C may have a thermal conductivity higher than about 10 watts / cm-K, higher than about 50 watts / cm-K, or higher than about 100 watts / cm-K. The material of the thermally conductive core 22C may include copper, tungsten, silver, nickel, aluminum, etc. or alloys thereof. According to some embodiments, the thermal conductivity TC22C of the thermally conductive core 22C is higher than the thermal conductivity TC22B of the barrier 22B. The thermal conductivity TC22B may also be higher than the thermal conductivity TC22CL of the dielectric liner 22L.

[0036] Return to reference Figure 1A, interconnect structure 32 is formed over ILD 28 and contact plug 30. Interconnect structure 32 may include metal lines 34 and vias 36 formed in dielectric layer 38 (also referred to as intermetallic dielectric (IMD)). Metal lines at the same level are collectively referred to as metal layers hereinafter. According to some embodiments, interconnect structure 32 includes a plurality of metal layers interconnected by vias 36. Metal lines 34 and vias 36 may be formed of copper, copper alloys and / or other metals. According to some embodiments, dielectric layer 38 is formed of a low-k dielectric material. For example, the dielectric constant (k value) of the low-k dielectric material may be lower than about 3.0. Dielectric layer 38 may include a low-k dielectric material containing carbon.

[0037] According to some embodiments, the formation of metal lines 34 and vias 36 may include a single damascene process or a dual damascene process. According to some embodiments, the formation of the bottom metal layer (including metal lines 34) may be performed by a single damascene process, which includes depositing a dielectric layer 38, etching the dielectric layer 38 to form a trench, filling the trench with a conductive material, and then performing a planarization process such as a CMP process to remove excess portions of the conductive material. The upper metal lines and vias may be formed by a dual damascene process, which includes forming a dielectric layer, forming a via opening and a trench in the dielectric layer, filling the via opening and the trench with a conductive material, and performing a planarization process.

[0038] According to some embodiments, the top ends of some or all thermally conductive pillars 22 are in contact with metal lines 34. According to some embodiments, some thermally conductive pillars 22 may not have metal lines above, and the top surfaces of these thermally conductive pillars 22 are in contact with the bottom surface of the upper dielectric layer 38 to form a horizontal interface. For example, according to some embodiments, the metal lines 34 in the region 35 may not (or may) be formed, and thus the region 35 is filled with a portion of the dielectric layer 38. Therefore, according to some embodiments, the corresponding lower thermally conductive pillars 22 are not in contact with any metal lines 34. According to these embodiments, the corresponding thermally conductive pillars 22 may be electrically floating.

[0039] According to some embodiments, thermally conductive pillars 22 are formed where the corresponding device die is hot, for example, the corresponding portion of integrated circuit device 26 generates the most heat per unit chip area than other portions of integrated circuit device 26. Thermally conductive pillars 22 may be arranged in an array, a honeycomb pattern (hexagonal), or any other regular or irregular pattern.

[0040] A passivation layer 42 may be included above the interconnect structure 32, which may be formed of a non-low-k dielectric material. The passivation layer 42 may be formed of or include undoped silicate glass (USG), silicon nitride, silicon oxide, etc., or multiple layers thereof. There may also be a metal pad (such as an aluminum copper pad) 40, a post-passivation interconnect (PPI), a metal pad, etc., which are referred to as conductive features.

[0041] A bonding film 44 is deposited over the metal pad 40 and the interconnect structure 32. The top surfaces of the bonding film 44 are coplanar. When deposited, the bonding film 44 may be a blanket dielectric layer in which there are no conductive components (such as wires and conductive pads). According to some embodiments, the bonding film 44 may be formed of a silicon-based dielectric material, which may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc.

[0042] Bonding pad 46 is formed in bonding film 44 and may have a top surface coplanar with a top surface of bonding film 44. According to some embodiments, bonding pad 46 is formed using a damascene process including etching bonding film 44 to form an opening, filling the opening with a conductive material, and performing a planarization process.

[0043] Figure 2 A backside thinning process is shown to thin the semiconductor substrate 24 from the back side of the semiconductor substrate 24. The corresponding process is shown as Fig.15 The process 204 in the process flow 200 shown in FIG. The backside thinning process may be performed by a CMP process or a mechanical grinding process. According to some embodiments, the backside thinning process is stopped before the thermally conductive pillar 22 is exposed from the back side of the semiconductor substrate 24. As an example, Figure 1A 24B1 of the semiconductor substrate 24 is shown in FIG. According to these embodiments, the backside thinning process is stopped after the thermally conductive pillars 22 are exposed from the backside of the semiconductor substrate 24. Some exposed portions of the thermally conductive pillars 22 are also polished. As an example, Figure 2 The corresponding bottom surface 24B2 of the semiconductor substrate 24 is shown in FIG. Figure 1A Shown in.

[0044] Figure 3 FIG. 2 shows a wafer 20 after a recessing process of a semiconductor substrate 24 according to some embodiments. The corresponding process is shown as follows: Fig.15 The process 206 in the process flow 200 is shown. According to some embodiments, the corresponding back surface of the semiconductor substrate 24 is denoted as 24B3, which is also Figure 2The recessing process may be performed by an anisotropic etching process or an isotropic etching process. Figure 3 As shown, the recessing is selective, such that at least the core 22C of the thermally conductive column 22 is not recessed, and the thermally conductive column 22 includes a protruding portion 22P.

[0045] According to some embodiments, in the recess, the entire thermally conductive column 22 is not recessed, and therefore, the thermally conductive core 22C ( Figure 1B ), portions of the blocking member 22B and the dielectric liner 22L all protrude beyond the rear surface 24B3 of the semiconductor substrate 24. According to an alternative embodiment, the protruding portion of the dielectric liner 22L is also recessed so that the bottom end of the dielectric liner 22L is at the same level as the rear surface 24B3. The recessing of the dielectric liner 22L can be performed in the same recessing process of the semiconductor substrate 24, or can be performed in a separate etching process (using a different etching chemistry) different from the recessing of the semiconductor substrate 24.

[0046] According to another optional embodiment, the barrier 22B may be recessed, or may not be recessed. When the barrier 22B is recessed, it may be recessed in the same recessing process as the recessing of the semiconductor substrate 24 or in a different recessing process. When the barrier 22B is recessed, it may be recessed in the same recessing process as the recessing of the dielectric liner 22L or in a different recessing process. Since the thermal conductivity of the thermally conductive core 22C may be higher than the thermal conductivity of the barrier 22B (the thermal conductivity of the barrier 22B may also be higher than the thermal conductivity of the dielectric liner 22L), the recessed dielectric liner 22L or even the barrier 22B may allow the sidewalls of the thermally conductive core 22C or the barrier 22B in the protrusion 22P to be in direct contact with the cooling medium 54 ( Figure 4 ), so that better heat dissipation can be achieved.

[0047] Figure 4 FIG. 5 shows the bonding of wafer 20 (and die 20 ′) with other packaging components to form reconstituted wafer 50 according to some embodiments. The corresponding process is shown as follows Fig.15 Process 208 in process flow 200 is shown. According to some embodiments, bonding is performed at the wafer level, where wafer 20 is bonded to package components 120 and 320 by wafer-on-wafer bonding. According to an alternative embodiment, wafer 20 is first divided into discrete dies 20', for example, in a die sawing process. The resulting discrete dies 20' can be bonded to dies 120' and 320' in a die-on-die bonding process, or can be bonded to wafer 120 and / or 320 by a wafer-on-die bonding process.

[0048] According to some example embodiments, package assemblies 120 and 320 have a similar structure to wafer 20. The structures and materials of components in package assemblies 120 and 320 may be found with reference to the discussion of similar components in wafer 20, wherein similar components in package assemblies 120 or 320 are indicated by prefixing the reference numerals of the corresponding components in wafer 20 with the numeral "1" or "3". For example, the substrate in wafer 20 is indicated as 24, and therefore, the substrates in package assemblies 120 and 320 are indicated as 124 and 324, respectively.

[0049] The package assembly 120 may include an integrated circuit device 126, an ILD 128, a contact plug 130, an interconnect structure 132, a dielectric layer 138, a metal line 134, a through hole 136, a bonding film 144, a bonding pad 146, and a bonding pad 146'. The package assembly 320 may include an integrated circuit device 326, an ILD 328, a contact plug 330, an interconnect structure 332, a dielectric layer 338, a metal line 334, a through hole 336, a bonding film 344, and a bonding pad 346. The details of these components may be similar to the corresponding components in the wafer 20 and are not repeated here. According to some embodiments, the package assembly 320 may also include a bonding pad 148 and a bonding film 149 at the bottom, so that in a further packaging process, for example, when bonded to an interposer or a packaging substrate, the resulting package 50' can be electrically connected to other package components.

[0050] According to some embodiments, the bonding of wafer 20 to package component 120 is by hybrid bonding, which includes bonding bonding film 44 to a bonding film in package component 120 by fusion bonding (e.g., forming Si-O-Si bonds), and bonding bonding pad 46 to bonding pad 146' by metal-to-metal direct bonding. Bonding of package component 120 to package component 320 may also be by hybrid bonding, which includes bonding bonding film 144 to bonding film 344 by fusion bonding (e.g., forming Si-O-Si bonds), and bonding bonding pad 146 to bonding pad 346 by metal-to-metal direct bonding.

[0051] According to some embodiments, reconstituted wafer 50 is sawn into discrete (and identical) packages 50', where each package 50' includes one of device dies 20', one of device dies 120', and one of device die 320'. The corresponding process is shown as follows Fig.15 Process 210 of process flow 200 is shown. Package 50' may then be bonded to other packaging components (such as an interposer, a packaging substrate, etc.).

[0052] According to some embodiments, Figure 4As shown, a cooling medium 54 is attached to the semiconductor substrate 24 as part of the resulting package 50' and may be in contact with the thermally conductive pillars 22. The corresponding process is shown as follows Fig.15 Process 212 in process flow 200 is shown. According to some embodiments, the cooling medium 54 has good thermal conductivity, and according to some embodiments, the thermal conductivity may also be higher than the thermal conductivity of silicon. For example, the thermal conductivity of the cooling medium 54 may be higher than 4 W / cm-K, higher than about 10 W / cm-K, higher than about 20 W / cm-K, or higher.

[0053] According to some embodiments, the cooling medium 54 includes a thermal interface material (TIM) that can be dispensed in a flowable form and then cured into a solid form. The cooling medium 54 may also include a base material (thermal paste or thermal adhesive) that may include a polymer, a resin, an epoxy, etc. According to some embodiments, thermally conductive particles (e.g., formed of aluminum oxide, magnesium oxide, aluminum nitride, boron nitride, or diamond powder) may also be present in the base material to improve thermal conductivity and thermal expansion coefficient.

[0054] According to some embodiments, where the cooling medium 54 is a thermal interface material, there may be a heat sink (heat sink plate) 56 attached to the cooling medium 54 above the cooling medium 54. Therefore, curing of the cooling medium 54 is performed after the heat sink 56 is attached to the cooling medium 54, so that the cooling medium 54 also serves as an adhesive for attaching the heat sink 56. According to some embodiments, the heat sink (heat sink plate) 56 may be formed of copper, nickel, silver, aluminum, etc. According to an alternative embodiment, the cooling medium 54 is formed of a metal such as copper and is a heat sink.

[0055] like Figure 4 As shown, the thermally conductive pillar 22 can effectively conduct heat in the device die 20' (and the semiconductor substrate 24) to the cooling medium 54 because the thermal conductivity of the thermally conductive pillar 22 is higher than that of silicon. According to some embodiments, the thermally conductive pillar 22 has a Figure 3 The process shown has their dielectric liner 22L recessed ( Figure 1B ), so that the thermally conductive core 22C or the barrier 22B directly contacts the cooling medium 54, and the thermally conductive core 22C or the barrier 22B has a higher thermal conductivity value than the dielectric liner 22L. Therefore, the heat conduction from the substrate 24 and the dielectric layer in the device tube core 20' through the thermally conductive pillar 22 to the cooling medium 54 is further improved (indicated by arrow 58).

[0056] According to some embodiments, package assemblies 120 and 320 further include thermally conductive pillars 122 and 322, respectively. Thermally conductive pillars 122 and 322 may have similar structures and be formed of similar materials as thermally conductive pillars 22, and the details are not repeated here.

[0057] According to some embodiments, the package components 120 and 320 further include (electrical) through-holes 121 and 321 for conducting voltage, current and / or electrical signals. According to some embodiments, the through-hole 121 can electrically interconnect the device die 20' and the device die 320', and can electrically connect the integrated circuit device 126 to the integrated circuit device 26 and the integrated circuit device 326. The through-hole 321 can also electrically connect the integrated circuit device 326 to the package component 120. Therefore, the integrated circuit device 26 in the device die 20' and the integrated circuit device 126 in the device die 120' can be electrically connected to the bonding pad 148 in the package component 320.

[0058] According to some embodiments, through-hole 121 and thermally conductive pillar 122 are formed in the same manufacturing process. Through-hole 321 and thermally conductive pillar 322 may also be formed in the same manufacturing process. Thermally conductive pillar 122 may be electrically decoupled from integrated circuit devices 26, 126, and 326. This may be accomplished by using a dielectric liner (such as Figure 1B The dielectric liner 22L in the heat conductive core 122C can be used to electrically insulate the heat conductive core 122C from the corresponding contact metal parts. For example, the upper end or the lower end of the heat conductive core 122C can include a horizontal portion of the dielectric liner 22L, so that the heat conductive column 122 is electrically decoupled from the upper bonding pad 146 or the lower metal line 134 (although physically in contact).

[0059] The thermally conductive pillars 22, 122, and / or 322 may be electrically floating (when the package 50' is powered on). Alternatively, the thermally conductive pillars 22, 122, and / or 322 may be terminal (end) components electrically connected to portions of the corresponding integrated circuit device 26, 126, or 326. According to these embodiments, the thermally conductive pillars 22, 122, and / or 322 have the same voltage as the connected portions of the integrated circuit device 26, 126, or 326, but no current flows through the thermally conductive pillars 22 and / or 332.

[0060] Alternatively, the electrical decoupling of the thermally conductive core 122C may be achieved by not forming some through holes / metal lines. Figure 4 When vias or metal lines are not formed in region 64-1 (in device die 320'), region 64-2 (in device die 120') and / or region 64-3 (in device chip 20'), thermally conductive pillars 22, 122 and / or 322 will be electrically decoupled from integrated circuit devices 26, 126 and 326.

[0061] Figure 4A heat conduction path 60 is shown, which includes a first heat conduction path (including heat conduction pillar 322) in device die 320', a second heat conduction path (including heat conduction pillar 122) in device die 120', and a third heat conduction path (including heat conduction pillar 22) in device die 20'. Therefore, the heat generated in device die 320' and 120' and device die 20' can be effectively conducted to cooling medium 54.

[0062] Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Figure 8 and Fig. 9 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure is shown. These processes are called post-pillar processes because the thermally conductive pillars are formed after the front-side interconnect structure is formed. Unless otherwise stated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the previous embodiments. Whenever applicable, the details about materials, structures, and formation processes provided in each embodiment described throughout can be applied to any other embodiment.

[0063] Figure 5 The initial structure is shown. The initial steps of these embodiments are similar to Figure 1A is substantially the same as shown in Figure 1A and Figure 1B The heat conducting pillars 22 shown are not yet formed.

[0064] Figure 6 FIG. 2 shows a backside thinning process for thinning the semiconductor substrate 24. In the subsequent process, Fig. 7A As shown, thermally conductive pillars 22 are formed from the back side of semiconductor substrate 24. The formation process may include etching semiconductor substrate 24 and front side dielectric layers (such as ILD 28) to expose metal lines 34, filling the openings with dielectric liners, barrier layers, and core thermally conductive materials, and performing a planarization process.

[0065] Figure 7B and Figure 7C 2 shows an enlarged view of a thermally conductive column 22 according to some embodiments. Figure 7B As shown, the dielectric liner 22L has a top horizontal portion that separates the barrier 22B and the thermally conductive core 22C from the upper metal line 34. Therefore, the barrier 22B and the thermally conductive core 22C are electrically decoupled from the upper metal line 34. According to an alternative embodiment, after depositing the dielectric liner 22L and before filling the barrier 22B and the thermally conductive core 22C, an anisotropic etching process may be performed to remove the horizontal portion of the dielectric liner 22L, thereby forming a dielectric layer 34 as shown in FIG. Figure 7CThe structure shown.

[0066] Figure 8 The semiconductor substrate 24 is shown thinned from the back side. The details of the thinning process have been referred to in Figure 3 and will not be repeated here. Fig. 9 As shown, the wafer 20 is flipped upside down and bonded to the package components 120 and 320 to form a reconstructed wafer 50. A sawing process may then be performed to saw the reconstructed wafer 50 into packages 50'. A cooling medium 54 and a heat sink 56 may also be attached to form the top portion of the package 50'. These structures may be similar to those shown in FIG. Figure 4 The package 50' shown is identical except for some details which may differ due to the post-pillar process. Fig. 9 In the package 50' shown, the bottom portion of the dielectric liner 22L may have a horizontal portion, and the corresponding thermally conductive pillar 22 may be aligned with the bottom portion of the dielectric liner 22L. Fig. 10D In addition, due to the first column process, Figure 4 The thermally conductive pillar 22 in the embodiment may have a top width WT1 that is smaller than the corresponding bottom width WB1. On the other hand, due to the post-pillar process, Fig. 9 The thermally conductive pillars 22 in FIG. 4 may have a top width WT2 that is greater than a corresponding bottom width WB2 .

[0067] Fig. 10A Shows Figure 4 or Fig. 9 Detail of the portion of the wafer 20 (and / or device die 20') and the corresponding thermally conductive pillar 22. According to some embodiments, the thermally conductive pillar 22 has a protruding portion extending into the cooling medium 54, as shown in FIG. Figure 4 As shown. The top end of the thermally conductive pillar 22 is shown as the top end 22T1. According to an optional embodiment, the top end 22T2 of the thermally conductive pillar 22 is coplanar with the top surface of the cooling medium 54. According to another optional embodiment, the thermally conductive pillar 22 extends into the cooling medium 54, and the top end 22T3 of the thermally conductive pillar 22 is higher than the top surface of the cooling medium 54. According to another optional embodiment, the top end 22T4 of the thermally conductive pillar 22 is coplanar with the rear surface of the semiconductor substrate 24. According to another optional embodiment, the top end 22T5 of the thermally conductive pillar 22 is embedded in the semiconductor substrate 24. According to these embodiments, a horizontal portion of the dielectric liner 22L may exist, such as Fig.10E As shown, the thermally conductive pillars 22 are not polished.

[0068] Fig. 10B , Fig. 10C , Fig. 10D and Fig.10E FIG. 2 shows an enlarged view of a heat conductive column 22 and components above and below it according to some embodiments. The dashed rectangle indicates that the heat conductive core 22C may (or may not) extend into the cooling medium 54. Fig. 10B As shown, the heat conductive core 22C of the heat conductive column 22 is in physical contact with both the cooling medium 54 and the metal wire 34. Fig. 10B In the embodiment, due to the first pillar process, the top width WT1 of the thermal conductive pillar 22 is smaller than the corresponding bottom width WB1.

[0069] Fig. 10C and Fig. 10D FIG. 2 shows possible structures of the heat-conducting pillar 22 and the components above and below it formed by the post-pillar process according to some embodiments. Fig. 10C As shown, the thermally conductive core 22C of the thermally conductive pillar 22 is in physical contact with both the cooling medium 54 and the metal line 34. To form this structure, a liner opening process is performed to remove the horizontal portion of the dielectric liner 22L. Fig. 10D 2 shows a structure in which the dielectric liner 22L has a horizontal portion that separates the thermally conductive core 22C of the thermally conductive pillar 22 from the metal line 34. Fig. 10C and Fig. 10D In the embodiment, due to the post-pillar process, the top width WT2 of the thermal conductive pillar 22 is greater than the corresponding bottom width WB2.

[0070] Fig.10E 2 shows a thermally conductive column 22 separated from a cooling medium 54 by a portion of a semiconductor substrate 24 according to some embodiments. The thermally conductive column 22 has a Fig. 10A The top end 22T5 is shown.

[0071] Fig.11A An enlarged view of wafer 20 (and device die 20') according to an alternative embodiment is shown. These embodiments are similar to Fig. 10A In the embodiment, the top surface of the heat conductive column 22 is coplanar with the bottom surface of the cooling medium 54.

[0072] Fig. 11B , Fig. 11C and Fig.11D Shows the corresponding Fig.11A An enlarged view of the thermally conductive column 22 is shown. Fig. 11B The structure formed by the first pillar process is shown. Fig. 11B In the embodiment, due to the first pillar process, the top width WT1 of the thermal conductive pillar 22 is smaller than the corresponding bottom width WB1. Fig. 11C and Fig.11D shows possible structures that can be formed by the post-pillar process. Fig. 11C and Fig.11D In the embodiment, due to the post-pillar process, the top width WT2 of the thermal conductive pillar 22 is greater than the corresponding bottom width WB2.

[0073] Fig.12 20 (and device die 20 ') according to alternative embodiments are shown. According to these embodiments, a backside thinning process ( Figure 2 ). Thus, portions of semiconductor substrate 24 will cover embedded thermally conductive pillars 22. Next, an etching process is performed to remove portions of semiconductor substrate 24 covering embedded thermally conductive pillars 22. Dielectric liner 22L will thus be exposed. According to some embodiments, the exposed horizontal portions of dielectric liner 22L are etched to reveal the horizontal portions of barrier 22B below (see FIG. 1 ). Fig. 13B ). The exposed horizontal portion of the barrier 22B may also be etched to expose the underlying thermally conductive core 22C, or may not be etched. According to an alternative embodiment, the exposed horizontal portion of the dielectric liner 22L is not etched.

[0074] A cooling medium 54 may then be dispensed and fill the opening formed by etching the semiconductor substrate 24. According to some embodiments where the dielectric liner 22L is not etched, the cooling medium 54 contacts the horizontal portion of the dielectric liner 22L. The horizontal portion of the dielectric liner 22L thus electrically decouples the thermally conductive core 22C from the cooling medium 54. According to some embodiments where the dielectric liner 22L is etched, the cooling medium 54 contacts the horizontal portion of the barrier 22B (when the barrier 22B is not etched) or the thermally conductive core 22C.

[0075] Fig.13A and Fig. 13B Wafer 20 (and device die 20 ′) and enlarged thermally conductive pillars 22 are shown, respectively. Fig. 13B The structure shown in Fig.13A In area 70. Fig.13A and Fig. 13B Thermally conductive pillars 22 are shown separated from cooling medium 54 by portions of semiconductor substrate 24 .

[0076] Fig.14A , Fig. 14B , Fig. 14C , Fig.14D and Fig.14E A top view of a thermally conductive column 22 according to various embodiments is shown. In these embodiments, the shape of the thermally conductive column 22 is selected so that the surface area (total length of the periphery) is large and thus the heat transfer efficiency is improved. Fig.14A The thermally conductive pillar 22 is shown to have a circular top view shape. Fig. 14B The thermally conductive pillar 22 is shown to have a cross top view shape. Fig. 14C The thermally conductive pillar 22 is shown to have a ring-shaped top view shape. Fig.14D The thermally conductive pillar 22 is shown to have a rectangular top view shape. Fig.14E The thermally conductive pillar 22 is shown to include a plurality of sections extending forward and backward.

[0077] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, and the test pad allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes intermediate verification of known good dies to improve yield and reduce costs.

[0078] The embodiments of the present disclosure have some advantageous features. By forming a heat-conducting column with high thermal conductivity to conduct heat to a cooling medium and a heat sink, better heat dissipation can be achieved.

[0079] According to some embodiments of the present disclosure, a method includes: forming a first device die, the forming the first device die including forming an integrated circuit on a first semiconductor substrate; and forming a thermally conductive pillar extending into the first semiconductor substrate; and attaching a cooling medium over and in contact with the first semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar. In an embodiment, attaching the cooling medium includes dispensing the cooling medium in a flowable form; and curing to harden the cooling medium.

[0080] In an embodiment, the method further comprises attaching a heat sink to a cooling medium, wherein the thermally conductive pillar penetrates the cooling medium to contact the heat sink. In an embodiment, the thermally conductive pillar penetrates the first semiconductor substrate, and the thermally conductive pillar is in physical contact with the cooling medium. In an embodiment, the method further comprises polishing the first semiconductor substrate to expose a surface of the thermally conductive pillar, wherein a first top surface of the thermally conductive pillar and a second top surface of the first semiconductor substrate are coplanar.

[0081] In an embodiment, the method further comprises, after polishing, recessing the first semiconductor substrate so that a protruding portion of the thermally conductive pillar protrudes beyond the first semiconductor substrate to extend into the cooling medium. In an embodiment, the thermally conductive pillar is electrically floating. In an embodiment, the method further comprises bonding a second device die to the first device die, wherein the second device die is an additional portion of the package, wherein the second device die comprises a second semiconductor substrate and an additional thermally conductive pillar penetrating the second semiconductor substrate, wherein the additional thermally conductive pillar is electrically and thermally coupled to the thermally conductive pillar.

[0082] In an embodiment, forming the thermally conductive pillar comprises: etching the first semiconductor substrate to form an opening; depositing a dielectric liner in the opening; and depositing a metal material in the opening and on the dielectric liner. In an embodiment, the method further comprises performing an anisotropic etching process on the dielectric liner after depositing the dielectric liner and before depositing the metal material.

[0083] According to some embodiments of the present disclosure, a structure includes: a first device die, the first device die including a first semiconductor substrate and an integrated circuit located on the first semiconductor substrate and a dielectric layer located below the first semiconductor substrate and a thermally conductive column extending into the first semiconductor substrate; and a cooling medium, the cooling medium is located above the first semiconductor substrate and contacts the first semiconductor substrate, wherein the cooling medium contacts the thermally conductive column. In an embodiment, the cooling medium includes an adhesive, the adhesive includes a polymer; and thermally conductive filler particles in the polymer. In an embodiment, the thermally conductive column contacts the cooling medium.

[0084] In an embodiment, the thermally conductive column extends into the cooling medium. In an embodiment, the structure further comprises a heat sink, wherein the thermally conductive column penetrates the cooling medium to contact the heat sink. In an embodiment, the thermally conductive column is electrically floating.

[0085] In an embodiment, the structure further includes a second device die bonded to the first device die, and the second device die includes a second semiconductor substrate and an additional thermally conductive pillar penetrating the second semiconductor substrate, wherein the additional thermally conductive pillar is electrically and thermally coupled to the thermally conductive pillar.

[0086] According to some embodiments of the present disclosure, a structure includes: a device die, the device die including a semiconductor substrate and a plurality of dielectric layers located below the semiconductor substrate and a thermally conductive column passing through the semiconductor substrate, wherein the thermally conductive column extends into one of the plurality of dielectric layers; and a thermal interface material, the thermal interface material is located above the semiconductor substrate and contacts the semiconductor substrate, wherein the thermally conductive column is in physical contact with the thermal interface material. In an embodiment, the thermally conductive column is electrically floating. In an embodiment, the thermally conductive column includes a metal core, and the metal core is in physical contact with the thermal interface material.

[0087] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a package, comprising: Forming a first device die, wherein forming the first device die comprises: forming an integrated circuit on a first semiconductor substrate; and forming a thermally conductive column extending into the first semiconductor substrate; and A cooling medium is attached over and in contact with the first semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillars.

2. The method for forming a package according to claim 1, wherein: Attaching the cooling medium comprises: dispensing the cooling medium in a flowable form; and Curing hardens the cooling medium.

3. The method of forming a package according to claim 2, further comprising attaching a heat sink to the cooling medium, wherein: The heat conductive column penetrates the cooling medium to contact the heat sink.

4. The method for forming a package according to claim 1, wherein: The thermally conductive pillar penetrates the first semiconductor substrate, and the thermally conductive pillar is in physical contact with the cooling medium.

5. The method for forming a package according to claim 4, further comprising polishing the first semiconductor substrate to expose the surface of the thermally conductive pillar, wherein The first top surface of the thermally conductive pillar is coplanar with the second top surface of the first semiconductor substrate.

6. The method for forming a package according to claim 4, further comprising: After the polishing, the first semiconductor substrate is recessed so that the protruding portion of the thermally conductive pillar protrudes from the first semiconductor substrate to extend into the cooling medium.

7. The method for forming a package according to claim 1, wherein: The thermally conductive pillar is electrically floating.

8. The method of forming a package according to claim 1, further comprising bonding a second device die to the first device die, wherein: The second device die is an additional part of the package, wherein the second device die includes: a second semiconductor substrate; and An additional thermally conductive column penetrates the second semiconductor substrate, wherein the additional thermally conductive column is electrically and thermally coupled to the thermally conductive column.

9. A package comprising: A first device die, wherein the first device die comprises: a first semiconductor substrate; an integrated circuit, located on the first semiconductor substrate; a dielectric layer disposed below the first semiconductor substrate; and a thermally conductive column extending into the first semiconductor substrate; and A cooling medium is located above the first semiconductor substrate and contacts the first semiconductor substrate, wherein the cooling medium contacts the thermally conductive pillars.

10. A package comprising: A device die, the device die comprising: Semiconductor substrate; A plurality of dielectric layers disposed below the semiconductor substrate; a thermally conductive column penetrating the semiconductor substrate, wherein the thermally conductive column extends into one of the plurality of dielectric layers; and A thermal interface material is located above and contacts the semiconductor substrate, wherein the thermally conductive pillar is in physical contact with the thermal interface material.

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