Wire bonding electroplating structure of full-cutting wettable side face structure for SON packaging
By forming temporary bonding wires in the lead frame panel array of electronic devices, the problem of insufficient lead conductivity during electroplating is solved, efficient solder connection and miniaturization design are achieved, and the increase in additional tie structure is avoided.
Patent Information
- Application Number
- CN202411343427.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-31
- Filing Date
- 2024-09-25
- Publication Date
- 2025-02-14
AI Technical Summary
The conductivity of the lead structure during the plating process of existing electronic devices leads to poor solder connections, and the addition of additional tie-in structures will limit the increase in device size and component density.
Wire-bonded plating technology using a fully cut wettable side structure, connecting the conductive leads and the semiconductor dies by forming temporary first and second bonding wires in the lead frame panel array, and providing temporary during plating Electrical connection avoids additional tie-up structure.
The use capability of existing lead frames is achieved without increasing device size and cost, and the reliability of plating quality and solder connections is not required without redesigning the lead frame.
Smart Images
Figure CN119447072A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates generally to electronic systems, and more particularly to wire bond plating structures for fully cut wettable flank structures of SON packages. Background Art
[0002] Solder wetting is important in the manufacture of electronic systems for providing good solder connections between electronic devices and host systems such as printed circuit boards (PCBs). The conductive leads of electronic devices can be coated before being mounted on the circuit board to reduce corrosion and facilitate solder connections when the device is soldered to the circuit board. Coating by electroplating is an effective technique for applying tin or other materials to the bottom and sidewalls of small outline leadless (SON) electronic devices during manufacturing. However, insufficient conductivity of the lead structure during electroplating may inhibit effective coating of the lead surface. Providing tie rods and other conductive structures permanently connected to the inner portion of the intended device leads in the lead frame panel array can help the intended leads to be grounded or otherwise electrically referenced during electroplating. However, such electrical grounding structures increase the area of the electronic device and hinder the reduction of the size of the device and / or the increase of the components and / or power density of the electronic device and the host system. For example, adding an additional tie rod structure may greatly limit the size of the die paddle or die attach pad used to mount the semiconductor die in the device. Other solutions may involve cumbersome leadframe redesign and in many cases result in the die being a chip-on-lead (COL) package that necessitates the use of a non-conductive die attach film (DAF), which inhibits the ability to use existing leadframes and increases manufacturing cost and complexity. Summary of the invention
[0003] In one aspect, an electronic device comprises: a semiconductor die; conductive leads in a first row and a second row along respective opposite sides of a package structure; a first bonding wire having a first end connected to a first one of the conductive leads and a second end connected to the semiconductor die; and a second bonding wire having a first end connected to a second one of the conductive leads and an unterminated second end exposed along another side of the package structure.
[0004] On the other hand, an electronic device includes: a small outline leadless package having a molded package structure and conductive leads, the conductive leads having plated sidewalls exposed along opposite lateral sides of the package structure; and a semiconductor die at least partially surrounded by the molded package structure; a first bonding wire surrounded by the molded package structure and connected between a first conductive lead among the conductive leads and the semiconductor die; and a second bonding wire having a first end and an unterminated second end exposed along another side of the package structure.
[0005] In another aspect, a method for manufacturing an electronic device includes: for a first cell region of a lead frame panel array having cell regions arranged in rows along a first direction and in columns along an orthogonal second direction, forming a first bonding wire to connect a first conductive lead of the first cell region to a semiconductor die of the first cell region; and for the first cell region, forming a second bonding wire to connect a second conductive lead of the first cell region to a conductive feature of a second cell region of the lead frame panel array. The method includes: cutting the conductive feature of the lead frame panel array between the first cell region and an adjacent third cell region of the lead frame panel array along the first direction to separate the conductive lead of the first cell region from the conductive structure of the adjacent third cell region of the lead frame panel array; and performing an electroplating process, the electroplating process forming a plated surface on the sidewalls of the conductive lead of the first cell region and separating a packaged electronic device from the lead frame panel array. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 is a top plan view of an electronic device with unterminated bond wires.
[0007] Figure 1A It is along Figure 1 A cross-sectional side view of the electronic device taken along line 1A-1A.
[0008] Figure 1B It is along Figure 1 A cross-sectional side view of the electronic device taken along line 1B-1B.
[0009] Figure 1C yes Figure 1 A side view of an electronic device showing cut ends of unterminated bond wires exposed along a sidewall of a molded package structure of the device.
[0010] Figure 2 is a flow chart of a method of manufacturing an electronic device.
[0011] Figures 3 to 9 yes Figure 1 Electronic devices based on Figure 2 A top plan view of a manufacturing process for an embodiment of a method of performing a manufacturing process in a panel array having rows and columns of cell areas. DETAILED DESCRIPTION
[0012] In the drawings, the same reference numerals refer to the same elements throughout the text, and various features do not have to be drawn to scale. In addition, the term "coupling (couple)" or "coupling (couples)" includes indirect or direct electrical or mechanical connections or combinations thereof. For example, if the first device is coupled to the second device or is coupled with the second device, the connection can be via a direct electrical connection, or via an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems and / or components in the context of function, which are generated by the configuration and / or interconnection of various structures when the circuit system is powered on and operated in some cases. Unless otherwise specified, the "about", "approximately" or "roughly" in front of the value means + / -10% of the stated value. The following describes one or more operating characteristics of various circuits, systems and / or components in the context of function, which are generated by the configuration and / or interconnection of various structures when the circuit system is powered on and operated in some cases. For ease of description in conjunction with particular figures, one or more structures, features, aspects, components, etc. may be referred to herein as first, second, third, etc., such as first and second terminals, first, second and third wells, etc., which should not be construed as limitations on the claims.
[0013] Figures 1 to 1C An example electronic device 100 is shown in an example position in a three-dimensional space having a first direction X ( Figures 1 to 1B ), the second direction Y( Figure 1 and 1C ) and the third direction Z( Figures 1A to 1C ), the third direction is perpendicular (orthogonal) to the corresponding first direction X and second direction Y. Structures or features along any two of these directions are orthogonal to each other. Figure 1 shows a top view of the electronic device 100, Figure 1A Shown along Figure 1 A cross-sectional side view taken along line 1A-1A of Figure 1B Shown along Figure 1 A cross-sectional side view taken along line 1B-1B. Figure 1C is a side view of electronic device 100 showing cut ends of unterminated bond wires exposed along a sidewall of the device's molded package structure.
[0014] like Figures 1A to 1CAs best shown in FIG. 1 , the electronic device 100 has opposite first and second sides 101 and 102 (e.g., bottom side 101 and top side 102), respectively, spaced apart from each other along a third direction Z. The electronic device 100 has opposite third and fourth sides 103 and 104 (e.g., bottom side 101 and top side 102), spaced apart from each other along a first direction X and extending along a second direction Y. Figures 1 to 1B The electronic device 100 further includes a fifth side 105 and a sixth side 106 ( Figure 1 and 1C ).
[0015] The electronic device 100 has a molded encapsulation structure 118 that forms part of the device sides 101-106. In the example shown, the respective sides 101-106 are substantially planar, with the bottom side 101 and the top side 102 extending in respective XY planes, and the sides 103 and 104 extending in respective YZ planes in the second direction Y and the third direction Z. In one example, the sides 101-106 have a substantially planar outer surface. In other examples (not shown), one or more of the sides 101-106 have curves, sloped features, or other non-planar surface features.
[0016] The electronic device 100 is a small outline no-lead (SON, also known as a dual-row quad flat no-lead (QFN)) device having multiple rows of conductive leads along opposing lateral sides 105 and 106. The electronic device 100 includes a semiconductor die 107 ( 108 ) attached to a die attach pad 116, for example using an adhesive (not shown). Figure 1 and 1B ). Semiconductor die 107 includes one or more electronic circuit components and top-side conductive features (eg, bonding pads, not shown) for electrical connection of the one or more circuit components in the circuit.
[0017] like Figure 1 As shown, each row of conductive leads includes conductive end leads 108 at opposite ends of the respective row and one or more intermediate leads 110 between the conductive end leads 108. In the example shown, a first row of conductive leads 108, 110 extends along the fifth side 105, and a second row of conductive leads 108, 110 extends along the sixth side 106 of the package structure 118.
[0018] Each of the first and second rows of conductive end leads 108 has a plated surface 109 exposed along the respective sides 105 and 106 of the package structure 118, and each of the first and second rows of conductive intermediate leads 110 has a plated surface 111 exposed along the respective sides 105 and 106. In one example, the leads 108 and 110 are also exposed along the bottom side 101 of the electronic device, and the exposed bottom of the leads 108 and 110 has a plated surface. In the example shown, the bottom side of the die attach pad also has a plated surface. In one example, the conductive leads 108 and 110 are or include copper, and the die attach pad 116 is or includes copper. In this example or another example, the plated surfaces 109 and 111 are or include tin (Sn) with a matte finish.
[0019] like Figure 1 As further shown, one or more of the leads 108, 110 are connected to corresponding respective conductive features (e.g., bond pads) of the semiconductor die 107 via respective first bond wires 112. The first bond wires 112 provide electrical connections between the respective leads 108, 110 and circuitry or components of the semiconductor die 107. Individual first bond wires 112 have first ends connected to first conductive leads of the conductive leads 108, 110 and second ends connected to the semiconductor die 107.
[0020] like Figure 1 and 1A As shown, the electronic device 100 also includes one or more unterminated second bond wires 114. The second bond wires 114 are referred to herein as unterminated because they have a second end that is not connected to another circuit feature or component, even if the first end of the respective second bond wire 114 is connected to a lead, a die attach pad, or a tie bar. Individual second bond wires 114 have: a first end that is connected to a respective one of the conductive leads 108, 110 or to another conductive feature of the electronic device (e.g., a tie bar, a die attach pad, etc.); and an unterminated second end 113, 115 that is exposed along a respective one of the third side 103 and the fourth side 104 of the package structure 118.
[0021] The unterminated second bond wire 114 provides a temporary ground or other electrical connection to facilitate electroplating of the plated surfaces 109 and 111 of the leads 108 and 110 during manufacturing, as described below in conjunction with Figure 2As further described. During electroplating after the initial cutting operation that separates the intermediate lead 110 from the rest of the starting lead frame panel array, the unterminated second bond wire 114 facilitates connecting the intermediate lead 110 to the electroplating system. The second bond wire 114 is initially connected between the intermediate lead 110 and a conductive feature (e.g., lead 108, tie bar, die attach pad 116, etc.) of another unit area of the lead frame panel array or strip, and a subsequent cutting or other separation process after electroplating cuts the second bond wire 114, leaving a remaining unterminated second bond wire 114. Such temporary second bond wire 114 can also be used to enhance the electroplating of one or more end leads 108.
[0022] The temporary second bond wire approach provides a solution to enhance plating and achieve fully cut wettable side structures without increasing device size or cost and without the need to redesign existing lead frames for small form factor electronic devices. By wire bonding to adjacent package unit areas on a lead frame strip, a temporary electrical connection structure is formed that will be completely sawn off when the package is fully singulated. This enables the use of existing lead frames without the need for additional tie bar structures that may limit the die attach pad size to accommodate the die. The use of the second bond wire 114 is a simple manufacturing modification to other existing wire bonding processes and does not require lead frame redesign. In addition, once the package is fully singulated, the unterminated second bond wire 114 will be electrically isolated.
[0023] The resulting electronic device 100 provides a small outline leadless package in which the conductive leads 108 and 110 have plated sidewalls exposed along opposite lateral sides 105 and 106 of the package structure 118. In this example, the semiconductor die 107 is at least partially surrounded by the molded package structure 118. In this example, the first bond wires 112 are surrounded by the molded package structure 118 and connected between a respective one of the conductive leads 108, 110 and a corresponding bond pad of the semiconductor die 107. The respective second bond wires 114 include a first end and an unterminated second end (e.g., Figure 1 , 1A and 113 and 115 in 1C), the unterminated second end is exposed along a corresponding one of the third side 103 and the fourth side 104 of the packaging structure 118.
[0024] like Figure 1As shown, one of the second bonding wires 114 has a first end connected to the first conductive intermediate lead 110 in the first row along the fifth side 105, and another of the second bonding wires 114 has a corresponding first end connected to the second conductive intermediate lead 110 in the second row along the sixth side 106. These second bonding wires 114 have corresponding second ends 113, which are exposed outside the package structure 118 along the fourth side 104 and help provide electrical connections to the corresponding conductive intermediate leads 110 by temporarily connecting to conductive features of adjacent cell regions during electroplating to facilitate sufficient plating of the plated surface 111.
[0025] In the example shown, the electronic device 100 also has another one of the second bond wires 114 having a first end connected to one of the conductive terminal leads 108 (eg, Figure 1 ), and another of the second bonding wires 114 has a first end connected to one of the conductive end leads 108 in the second row along the sixth side 106 (eg, Figure 1 These additional second bond wires 114 have corresponding second ends 115 that are exposed outside of the package structure 118 along the third side 103 and provide ground or other electrical connection from the illustrated end conductive lead 108 to intermediate leads of adjacent cell regions during electroplating in a panel or strip arrangement having rows and columns of lead frame cell regions, as further described below.
[0026] Furthermore, in a given embodiment, additional examples of unterminated bond wires 114 may have: a first end connected to a die attach pad 116, a tie bar 117 (e.g., extending from the die attach pad 116 and exposed outside the package structure 118 along one of the sides 103, 104), or other conductive structure; and an unterminated second end exposed along a third side 103 and a fourth side 104 of the package structure 118, such as described below. Figures 5 to 9 In these or other examples, one of the first bond wires 112 may overlie one of the second bond wires 114, or vice versa, examples of which are described below. Figure 5 The position range, height, and termination location of the first and second bond wires 112, 114 can be tailored for a given implementation to avoid shorting any two bond wires 112, 114, including having one bond wire overlying another bond wire without contact therebetween.
[0027] Reference now Figures 2 to 9 On the other hand, a method for manufacturing an electronic device is provided. Figure 2 A method 200 of manufacturing an electronic device is shown, and Figures 3 to 9 The electronic device 100 is shown in accordance with an example embodiment of the method 200 for simultaneously manufacturing multiple electronic devices in a panel array having rows and columns of cell regions. The method 200 is Figure 2 The die attach process begins at 202 . Figure 3 An embodiment of a die attach process 300 is shown performed on an example portion of a starting leadframe panel array or strip 301 (also referred to herein as a leadframe) having rows and columns of cell regions 303, each cell region corresponding to an instance of a subsequently completed electronic device 100. Figure 3 As shown, the starting lead frame 301 has a die attach pad structure 302 in each cell region 303. The lead frame 301 has: a transversely oriented first tie bar 304 having a first width W1, which extends between adjacent rows of the cell regions 303 (e.g., between the first and second cell regions 303). Figure 3 and a vertically oriented second tie bar 306 having a second width W2 that extends between adjacent columns of the cell regions 303 (e.g., from top to bottom in the illustrated orientation). Additionally, in the illustrated example, the first tie bar 304 is wider than the second tie bar 306 (e.g., W1 is greater than W2), although this is not a requirement for all possible implementations.
[0028] Figure 3 The die attach process 300 in FIG. 3 includes attaching an instance of the semiconductor die 107 to a corresponding instance of the die attach pad 302 in each cell region 303. In one example, the die attach process 300 includes dispensing or otherwise providing a die attach film (DAF) or other adhesive onto selected portions of the corresponding die attach pads 302, and then placing the corresponding semiconductor die 107 onto an adhesive film (not shown) over the die attach pad 302 of the corresponding cell region 303, for example, using an automated pick and place device (not shown). The die attach process 300 may include an adhesive curing step, such as heating or other heat treatment, ultraviolet light exposure, etc., to cure the die attach film or adhesive, thereby attaching the semiconductor die 107 to the corresponding die attach pad 302.
[0029] Method 200 Figure 2 Wire bonding is continued at 204 to form a first bonding wire 112 and a second bonding wire 114 . Figure 4 An example of performing a wire bonding process 400 to form a first bonding wire 112 is shown, and Figure 5 A wire bonding process 500 of forming the second bond wire 114 is shown. Figure 5The wire bonding process 500 in FIG. 4 may be a continuation or portion of the wire bonding process 400, or the bonding wires 112 and 114 may be formed by separate wire bonding processes. Figure 4 First bond wires 112 are shown formed to provide desired signal connections between the semiconductor die 107 and certain conductive leads 108 and 110 in each respective cell region 303 according to a desired circuit interconnect design of the electronic device 100 .
[0030] In this embodiment, if Figure 5 As shown, a second bonding wire 114 is formed to provide a temporary electrical connection to the intended intermediate lead position for subsequent electroplating after the rows of the cell area 303 have been separated from each other. Figure 5 As shown, for example, second bond wires 114 in the shown portion of lead frame panel array 301 traverse vertically oriented second tie bars 306 to form electrical connections between each of the intended intermediate lead positions in each cell region 303 and conductive features (e.g., leads, die attach pads, tie bars, etc.) of adjacent cell regions 303 in the same row. In one embodiment, first bond wires 112 (e.g., Figure 4 ), and then sequentially forming the second bonding wires 114 of the entire panel array (eg, Figure 5 ). In another embodiment, the wire bonding tool forms the first bonding wire 112 and the second bonding wire 114 in a given row of the cell area 303 and then starts the next row. In other embodiments, any suitable bonding wire formation sequence may be used.
[0031] The illustrated example shows four complete cell regions 303 and portions of adjacent cell regions, wherein an instance of a second bond wire 114 has one end connected to the intended middle conductive lead in the bottom row of cell regions 303 and the lower left quadrant of the cell regions 303, and crosses (e.g., overlies) one first bond wire 112 connected between a bond pad of a corresponding semiconductor die 107 and a lower right perspective end conductive lead. The other end of this example instance of the second bond wire 114 is connected to a die attach pad 302 of a cell region 303 in the lower right illustrated quadrant.
[0032] Any suitable bond wire interconnect sequence and / or configuration may be used that provides the desired signal connection via the first bond wire 112 and provides temporary electrical interconnect for electroplating via the second bond wire 114, wherein after the first tie bar 304 is cut to separate adjacent rows of the cell area 303, the second bond wire 114 remains intact to provide the desired electrical connection, and then when the second tie bar 306 is cut, the second bond wire is cut to separate the finished electronic device 100 from the rows and columns of the panel array configuration.
[0033] In one instance, Figure 2 The wire bonding process at 204 in the embodiment includes forming one or more instances of first bonding wires 112 to connect corresponding first conductive leads 108, 110 of the first cell region 303 to the semiconductor die 107 of the first cell region 303, and forming one or more instances of second bonding wires 114 to connect second conductive leads 108, 110 of the first cell region 303 to conductive features of a second cell region 303 of the lead frame panel array 301, whether the second cell region 303 is a directly adjacent cell region to the first cell region 303 or another cell region 303 in the same row as the first cell region 303, so as to provide a temporary electrical connection to facilitate subsequent electroplating of the cut side of each of the intended conductive leads 108, 110. In another example, at 204, additional instances of the second wirebond 114 can be formed to provide a temporary electrical connection to one or more of the end conductive leads, and / or multiple instances of the second wirebond 114 can be formed to provide multiple wirebond electrical connections to a given intended end of the intermediate conductive lead, thereby improving the quality of a subsequent electroplating process and its plated surface.
[0034] Prior to cutting the transversely extending first tie rod 304, the method 200 Figure 2 The molding process is continued at 206 in the process. Figure 6 An example of performing a molding process 600 is shown, the molding process forming a molded package structure 118. The example shown provides a single mold cavity for multiple cell regions 303 of an array structure, such as a molded structure formed by a single mold cavity (not shown). In another example, multiple mold cavities can be used for the array structure, such as a column mold cavity (not shown), etc. The molding process 600 forms a molded package structure 118 in each cell region 303, the molded package structure surrounds the semiconductor die 107 and the instance of the first bond wire 112 of the cell region 303, and also surrounds the instance of the second bond wire 114 in the cell region 303.
[0035] exist Figure 2 At 208 , method 200 continues with cutting along a row direction (eg, a first direction). Figure 7 An example is shown in which a first cutting process 700 is performed using one or more cutting saws, lasers or other cutting tools (not shown) to sever the transversely extending first tie rods 304 along lines 702. The cutting process 700 includes cutting along a first direction (e.g., in Figure 7The conductive tie bar feature 304 of the lead frame panel array 301 is cut between a given unit area 303 of the lead frame panel array 301 and a corresponding adjacent unit area 303 to separate the conductive leads 108, 110 of the given unit area 303 from the conductive structures of the adjacent unit areas 303 of the lead frame panel array 301.
[0036] In one embodiment, the first cutting process 700 uses a first wide saw (not shown) that separates adjacent rows of cell regions 303 and removes the original laterally extending tie bars 304. In this example, the first cutting process 700 is performed from the back side of the lead frame panel array 301 so that the one or more cutting saws do not completely cut through the molding compound of the molded package structure 318, but instead cut through the lead frame metal (e.g., the above-described Figures 3 to 6 Tie bars 304) are used to separate the conductive leads 108, 110 of adjacent array rows from each other, such as Figure 7 This cutting process 700 forms exposed cut sidewalls of the conductive leads 108 and 110 along the first and second rows of each corresponding cell region 303 to allow subsequent electroplating operations to form the above-mentioned combined Figure 1 The corresponding plated surfaces 109 and 111 are depicted. In one example, the cutting process 700 is performed so that the lateral (e.g., left and right) ends of each row remain connected to a single integral frame that surrounds the rows and columns of the lead frame panel array 301, for example, to facilitate single-point grounding or other reference connection to the conductive features of the cell area 303 and subsequent plating operations.
[0037] Method 200 Figure 2 Electroplating is continued at 210. Figure 8 An example of performing an electroplating process 800 is shown, which forms plated surfaces 109 and 111 on the sidewalls of the corresponding conductive leads 108 and 110 of each unit area 303 of the panel array structure. In one embodiment, the ground or other electrical reference of an electroplating tool (not shown) is connected to the outer frame (not shown) of the lead frame panel array 301, and the electroplating tool provides a controlled electric field in a chamber with a suitable gas content (e.g., a tin precursor) to plate the exposed metal features of the lead frame panel array with the desired plating code, thereby forming the plated surfaces 109 and 111 of the corresponding conductive leads 108 and 110.
[0038] exist Figure 2At 212 in the method 200, the package separation process is continued. In the embodiments described above, the package separation at 212 includes a second lateral cutting operation (not shown), for example, using a narrower or thinner cutting saw blade (not shown) to cut off the remaining portion of the molded package structure 118 between adjacent rows of the unit area 303. In one example, the second lateral cutting operation does not separate the individual rows of the unit area 303 from the frame that laterally surrounds the array structure to facilitate further handling and processing of the lead frame panel array configuration. In this example or another example, the package separation at 212 further includes vertical separation, for example, using one or more cutting saw blades, lasers, or other separation equipment (not shown). Fig. 9 An example of performing a vertical cutting process 900 is shown, which cuts off the vertically extending second tie bars 306 and portions of the molded package structure 118 along lines 902 to separate individual finished packaged electronic devices 100 from the array structure. In one embodiment, a panel-wise final device probe testing (not shown) can be performed before the final cutting process 900. In addition, the vertical cutting process 900 cuts the second bonding wires 114 of each of the electronic devices 100, thereby leaving unterminated ends 113 and 115 along the respective sides 104 and 103 of the finished electronic devices, as described above in conjunction with Figure 1 , 1A and as described in 1C.
[0039] Modifications are possible in the described examples and other implementations are possible within the scope of the claims.
Claims
1. An electronic device, comprising: Semiconductor die; conductive leads in first and second rows along respective opposite sides of the package structure; a first bond wire having a first end connected to a first one of the conductive leads and a second end connected to the semiconductor die; as well as A second bonding wire has a first end connected to a second one of the conductive leads and an unterminated second end exposed along the other side of the package structure.
2. The electronic device according to claim 1, having a small outline no-lead SON package, wherein: The package structure has: a first side and a second side opposite to each other; a third side and a fourth side opposite to each other; and a fifth side and a sixth side opposite to each other, the third side and the fourth side are spaced apart from each other along a first direction, the fifth side and the sixth side are spaced apart from each other along a second direction orthogonal to the first direction, and the first side and the second side are spaced apart from each other along a third direction orthogonal to the first direction and the second direction; said first row of conductive leads extending along said fifth side; said second row of conductive leads extending along said sixth side; and The unterminated second end of the second bond wire is exposed along one of the third side and the fourth side of the package structure.
3. The electronic device according to claim 2, wherein: said first row of conductive leads comprising first conductive end leads at opposite respective ends of said first row and first conductive intermediate leads between said first conductive end leads; said second row of conductive leads comprises second conductive end leads at opposite respective ends of said second row and second conductive intermediate leads between said second conductive end leads; and The first end of the second bonding wire is connected to one of the first conductive intermediate lead and the second conductive intermediate lead. 4 . The electronic device of claim 3 , comprising another bonding wire having a first end connected to one of the first conductive terminal lead and the second conductive terminal lead and an unterminated second end exposed along the other side of the package structure. 5 . The electronic device of claim 3 , comprising another bond wire having a first end connected to one of the die attach pad and the tie bar and an unterminated second end exposed along the other side of the package structure.
6. The electronic device according to claim 1, wherein: said first row of conductive leads comprising first conductive end leads at opposite respective ends of said first row and first conductive intermediate leads between said first conductive end leads; said second row of conductive leads comprises second conductive end leads at opposite respective ends of said second row and second conductive intermediate leads between said second conductive end leads; and The first end of the second bonding wire is connected to one of the first conductive intermediate lead and the second conductive intermediate lead. 7 . The electronic device of claim 6 , comprising another bonding wire having a first end connected to one of the first conductive terminal lead and the second conductive terminal lead and an unterminated second end exposed along the other side of the package structure. 8 . The electronic device of claim 6 , comprising another bond wire having a first end connected to one of the die attach pad and the tie bar and an unterminated second end exposed along the other side of the package structure. 9 . The electronic device of claim 1 , comprising another bond wire having a first end connected to one of the conductive terminal leads and an unterminated second end exposed along the other side of the package structure. 10 . The electronic device of claim 1 , comprising another bond wire having a first end connected to one of the die attach pad and the tie bar and an unterminated second end exposed along the other side of the package structure. 11 . The electronic device of claim 1 , wherein one of the first bonding wire and the second bonding wire overlies the other of the first bonding wire and the second bonding wire.
12. The electronic device according to claim 1, wherein: said first and second rows of said conductive leads comprising conductive end leads at opposite ends of said respective rows and conductive intermediate leads between said conductive end leads of said respective rows; and Each of the conductive leads of the first and second rows has a plated surface exposed along a respective side of the package structure.
13. An electronic device comprising: A small outline no-lead SON package having a molded package structure and conductive leads having plated sidewalls exposed along opposite lateral sides of the package structure; a semiconductor die at least partially surrounded by the molded package structure; a first bonding wire surrounded by the molded package structure and connected between a first one of the conductive leads and the semiconductor die; as well as A second bonding wire has a first end and an unterminated second end exposed along another side of the package structure.
14. The electronic device according to claim 13, wherein: The conductive leads include conductive end leads at opposite ends of respective lateral sides and conductive intermediate leads between the conductive end leads; and The first end of the second bonding wire is connected to one of the first conductive intermediate lead and the second conductive intermediate lead.
15. The electronic device according to claim 13, wherein: The conductive leads include conductive end leads at opposite ends of respective lateral sides and conductive intermediate leads between the conductive end leads; and The first end of the second bond wire is connected to one of the conductive terminal leads. 16 . The electronic device of claim 13 , wherein the first end of the second bond wire is connected to one of a die attach pad and a tie bar.
17. A method of manufacturing an electronic device, the method comprising: For a first cell region of a lead frame panel array having cell regions arranged in rows along a first direction and in columns along an orthogonal second direction, forming a first bond wire to connect a first conductive lead of the first cell region to a semiconductor die of the first cell region; For the first cell region, forming a second bond wire to connect a second conductive lead of the first cell region to a conductive feature of a second cell region of the lead frame panel array; cutting a conductive feature of the lead frame panel array between the first unit region and an adjacent third unit region of the lead frame panel array along a first direction to separate the conductive leads of the first unit region from the conductive structures of the adjacent third unit region of the lead frame panel array; performing an electroplating process that forms a plated surface on a sidewall of the conductive lead in the first cell region; as well as The packaged electronic devices are separated from the lead frame panel array.
18. The method according to claim 17, further comprising: Before cutting the conductive features of the lead frame panel array, a molding process is performed to form a molded package structure that surrounds the semiconductor die and the first bond wires of the first cell region and surrounds the second bond wires.
19. The method of claim 18, wherein separating the packaged electronic device from the lead frame panel array cuts the second bond wire.
20. The method of claim 17, wherein separating the packaged electronic device from the lead frame panel array cuts the second bond wire.