Frame product packaging structure and method

Abstract

The invention provides a frame type product packaging structure and method, and the structure comprises a lead frame which is provided with a slide holder and conductive pins; a chip and N resistor assemblies are arranged on the slide holder, the first end of the ith resistor assembly is connected to the conductive pin of the lead frame through the ith bonding wire, the second end of the ith resistor assembly is connected to the ith power supply pin of the chip through the (N + i) th bonding wire, and i is greater than or equal to 1 and less than or equal to N; the voltage drop corresponding to the ith power supply circuit is the ith target voltage drop, and the ith power supply circuit comprises the ith bonding wire, the ith resistor assembly and the (N + i) th bonding wire. External power supply is converted through power supply lines with different target voltage drops, single external power supply is converted into diversified different internal power supply, and the requirements of multiple power supplies are met on the premise that compatibility is not affected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a packaging structure and method for frame-type products. Background Art

[0002] Currently, chip autonomy is advocated, and autonomous control is a general environmental requirement. Involving a large number of independent in-situ replacement products, the package size, pin definition, external use environment, etc. of the replaced products are fixed, so there are many limitations on independently developed chips. For example, for some framework-type single-voltage products, independent development and replacement will encounter the problem that the self-developed chip needs multi-voltage power supply, but the packaged finished product has only single voltage power supply.

[0003] How to solve the problem of converting an external single voltage into an internal multi-voltage power supply while ensuring packaging compatibility and in-situ replacement has become a difficult problem that plagues technical personnel in this field. Summary of the invention

[0004] The object of the present invention is to provide a frame product packaging structure and method to improve the above-mentioned problems.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows: In a first aspect, an embodiment of the present invention provides a frame-type product packaging structure, the frame-type product packaging structure comprising: A lead frame, on which a wafer carrier and conductive pins are arranged; A chip and N resistor components are arranged on the wafer stage, a first end of the i-th resistor component is connected to a conductive pin of the lead frame through an i-th bonding wire, and a second end of the i-th resistor component is connected to an i-th power supply pin of the chip through an N+i-th bonding wire, 1≤i≤N; The voltage drop corresponding to the ith power supply line is the ith target voltage drop, and the ith power supply line includes the ith bonding wire, the ith resistance component, and the N+ith bonding wire.

[0006] The external power supply is converted through power supply lines with different target voltage drops to achieve conversion from a single external power supply to a variety of different internal power supplies, meeting multiple power supply needs without affecting its compatibility.

[0007] Optionally, the resistor component is a chip resistor, and N groups of mounting areas are provided on the chip carrier, and each mounting area is insulated and isolated from the chip carrier; The two ends of the i-th chip resistor are mounted on the first mounting area and the second mounting area of ​​the i-th group of mounting areas respectively; The i-th bonding wire is connected to the first mounting area in the i-th group of mounting areas; The N+i th bonding wire is connected to the second mounting area in the i th group of mounting areas.

[0008] Because each mounting area is insulated and isolated from the wafer carrier, the current connected to the mounting area will not be directly short-circuited from the mounting area to the metal conductive wafer carrier, avoiding affecting the voltage conversion.

[0009] In a second aspect, an embodiment of the present invention provides a method for packaging a frame product, the method further comprising: Opening a mounting area, and opening N groups of mounting areas on a wafer carrier set on a lead frame, each mounting area is insulated and isolated from the wafer carrier; Perform resistor mounting, mounting the two ends of the i-th chip resistor on the first mounting area and the second mounting area of ​​the i-th group of mounting areas, respectively, 1≤i≤N; Perform chip mounting, mounting the chip on a designated area on the wafer stage; Performing gold wire bonding, including: connecting a first mounting area in the i-th group of mounting areas to a conductive pin of the lead frame through an i-th bonding wire, and connecting a second mounting area in the i-th group of mounting areas to an i-th power supply pin of the chip through an N+i-th bonding wire; The voltage drop corresponding to the ith power supply line is the ith target voltage drop, and the ith power supply line includes the ith bonding wire, the ith resistance component, and the N+ith bonding wire.

[0010] The external power supply is converted through power supply lines with different target voltage drops to achieve conversion from a single external power supply to a variety of different internal power supplies, meeting multiple power supply needs without affecting its compatibility.

[0011] Optionally, the step of opening the mounting area includes: etching N groups of target areas pre-planned on the carrier to obtain N groups of etching areas; plastic-sealing and curing the etching areas to form N groups of insulating isolation areas; and silvering the wiring areas in the insulating isolation areas to obtain N groups of mounting areas.

[0012] Because the insulation isolation area cannot realize resistor mounting, the wire bonding area in the insulation isolation area needs to be silvered, and the wire bonding area after silvering is the mounting area. The edge of the wire bonding area and the edge of the insulation isolation area are at least separated by a preset distance to avoid short circuit between the silvered packaging area and the wafer stage.

[0013] Optionally, the etch thickness is half the thickness of the wafer stage.

[0014] It should be understood that the target area on the upper surface of the carrier (the side away from the lead frame) is etched with half the thickness, and the shape of the lower surface of the carrier remains unchanged. After the packaging is completed, the lower surface will be completely exposed, and the external dimensions of the package pad will not be changed, ensuring the appearance and welding compatibility.

[0015] Optionally, after the gold wire bonding is completed, the method further comprises: plastic-sealing the lead frame on which the gold wire bonding is completed as a whole, and the plastic-sealing material used for the overall plastic-sealing is the same as the plastic-sealing material used for plastic-sealing and curing the etched area.

[0016] The subsequent overall encapsulation material is the same as the encapsulation material used for encapsulation and curing of the etched area. Because the materials used for encapsulation molding are consistent, the delamination problem caused by different CTE (coefficient of thermal expansion) of the materials is avoided, and the packaging reliability is improved.

[0017] Optionally, before packaging the lead frame, the method further comprises: Performing simulation modeling on the lead frame and the chip to obtain a simulation model; Simulation iterations are performed according to the simulation model to determine the i-th target path, the i-th target path is the i-th simulated power supply line between the lead frame and the chip in the simulation model, the voltage drop corresponding to the i-th target path is the i-th target voltage drop, and the i-th target path includes position information of the i-th group of target areas on the wafer stage.

[0018] The relevant information of each target path is determined through simulation to ensure that each power supply line completed subsequently can achieve the corresponding voltage drop and ensure the accuracy of the voltage conversion results.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic structural diagram of a lead frame provided by an embodiment of the present invention.

[0022] Figure 2 One of the flow charts of the frame product packaging method provided in the embodiment of the present invention.

[0023] Figure 3 A schematic diagram of a frame product packaging structure provided in an embodiment of the present invention.

[0024] Figure 4 A schematic diagram of etching results provided by an embodiment of the present invention.

[0025] Figure 5 A schematic diagram of the plastic encapsulation curing results provided by an embodiment of the present invention.

[0026] Figure 6 This is a schematic diagram of the silverization results provided by an embodiment of the present invention.

[0027] Figure 7 A schematic diagram of resistor mounting results provided by an embodiment of the present invention.

[0028] Figure 8 A schematic diagram of chip mounting results provided by an embodiment of the present invention.

[0029] Fig. 9 A schematic diagram of a gold wire bonding result provided in an embodiment of the present invention.

[0030] Fig.10 The second flowchart of the frame product packaging method provided in the embodiment of the present invention.

[0031] Fig.11 The third flowchart of the frame product packaging method provided in the embodiment of the present invention.

[0032] Fig.12 The fourth flowchart of the frame product packaging method provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0036] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0037] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0039] It should be noted that the lead frame is usually made of a layer of copper foil, and the circuit and structure are very simple. It is difficult to place devices in it using conventional processes. For details, please refer to Figure 1 . Figure 1 A schematic structural diagram of a lead frame provided by an embodiment of the present invention.

[0040] The lead frame is surrounded by wire bonding pins (also called wire bonding pins, including but not limited to conductive pins). The lead frame is small in size and there is no place to mount resistors. The only way to mount resistors is to use the chip carrier in the middle (also called the heat sink pad, on which the bare chip is also mounted). However, the chip carrier is a whole piece of metal. If the resistor is mounted directly on it, the two terminals will be short-circuited, and voltage conversion cannot be achieved.

[0041] To this end, the embodiment of the present invention provides a method for packaging frame products, which uses etching and plastic sealing curing processes to achieve an insulating isolation area of ​​the wafer stage. After silvering, resistor mounting can be achieved without short circuit, thereby achieving the effect of converting an external single voltage into an internal multi-voltage power supply. For details, please refer to Figure 2 and Figure 3, Figure 2 One of the flow charts of the frame product packaging method provided in the embodiment of the present invention, Figure 3 A schematic diagram of a frame product packaging structure provided in an embodiment of the present invention. Figure 3 In the example, the value of N is 2, but it is not limited to this. Figure 2 As shown, the frame product packaging method also includes: S110, S120, S130 and S150, which are described in detail as follows.

[0042] S110, opening a mounting area, and opening N groups of mounting areas on a wafer carrier set on the lead frame.

[0043] Each mounting area is insulated and isolated from the wafer carrier, and the current connected to the mounting area will not be directly short-circuited from the mounting area to the metal conductive wafer carrier.

[0044] S120 , performing resistor mounting, mounting two ends of the i-th chip resistor on the first mounting area and the second mounting area of ​​the i-th group of mounting areas respectively.

[0045] Wherein, 1≤i≤N, N is a positive integer greater than or equal to 1. When N=1, based on the frame product packaging method provided in the embodiment of the present invention, the frame product packaging structure obtained can complete the single-phase voltage conversion; when N is greater than 1, based on the frame product packaging method provided in the embodiment of the present invention, the frame product packaging structure obtained can complete the conversion from single-phase voltage to multiple voltages.

[0046] S130, performing chip mounting, mounting the chip on a designated area on the wafer carrier.

[0047] S150, perform gold wire bonding, connect the first mounting area in the i-th group of mounting areas to the conductive pin of the lead frame through the i-th bonding wire, and connect the second mounting area in the i-th group of mounting areas to the i-th power supply pin of the chip through the N+i-th bonding wire.

[0048] The voltage drop corresponding to the ith power supply line is the ith target voltage drop, and the ith power supply line includes the ith bonding wire, the ith resistor component, and the N+ith bonding wire. The ith target voltage drop is the difference between the input voltage of the conductive pin and the standard voltage corresponding to the ith power supply pin of the chip.

[0049] like Figure 3 As shown, the conductive pin of the lead frame corresponds to the external power supply V1. After the first power supply line and the second power supply line, the first power supply pin of the chip corresponds to the internal power supply V2, and the second power supply pin of the chip corresponds to the internal power supply V3. It can realize the conversion from a single external power supply V1 to a variety of different internal power supplies V2 and V3.

[0050] On the basis of the above, regarding the content in S110, the embodiment of the present invention further provides an optional implementation, please refer to the following: S110, the step of opening a mounting area, includes: S111, S112 and S113, which are specifically as follows.

[0051] S111, performing etching processing on N groups of target areas pre-planned on the wafer stage to obtain N groups of etching areas.

[0052] Please refer to Figure 4 , Figure 4 A schematic diagram of etching results provided by an embodiment of the present invention.

[0053] In an optional embodiment, half etching is performed on N groups of target areas pre-planned on the wafer stage, and the etching thickness is half of the thickness of the wafer stage.

[0054] It should be understood that the target area on the upper surface of the carrier (the side away from the lead frame) is etched with half the thickness, and the shape of the lower surface of the carrier remains unchanged. After the packaging is completed, the lower surface will be completely exposed, and the external dimensions of the package pad will not be changed, ensuring the appearance and welding compatibility.

[0055] Of course, the etching thickness can also be one third or two thirds of the thickness of the wafer carrier.

[0056] S112, performing plastic sealing and curing on the etched area to form N groups of insulating isolation regions.

[0057] Please refer to Figure 5 , Figure 5 A schematic diagram of the plastic encapsulation curing results provided by an embodiment of the present invention.

[0058] The etched area is cured by plastic encapsulation to form an insulating isolation area. In an optional embodiment, the plastic encapsulation material used for subsequent overall plastic encapsulation is the same as the plastic encapsulation material used for plastic encapsulation and curing of the etched area. Because the materials used for plastic encapsulation molding are consistent, the stratification problem caused by different CTE (coefficient of thermal expansion) of the materials is avoided, and the packaging reliability is improved.

[0059] S113, silvering the wire bonding area in the insulating isolation area to obtain N groups of mounting areas.

[0060] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the silverization results provided by an embodiment of the present invention.

[0061] It should be noted that, because the insulating isolation area cannot realize resistor mounting, the wire bonding area in the insulating isolation area needs to be silvered, and the wire bonding area after silvering is the mounting area. The edge of the wire bonding area and the edge of the insulating isolation area are at least separated by a preset distance, so as to avoid short circuit between the packaging area after silvering and the wafer stage.

[0062] After the placement area is opened, S120 can be executed to place resistors. The resistor placement results are as follows: Figure 7 As shown, Figure 7 A schematic diagram of resistor mounting results provided by an embodiment of the present invention.

[0063] After the resistor mounting is completed, S130 can be executed to mount the chip. The chip mounting result is as follows: Figure 8 As shown, Figure 8 A schematic diagram of chip mounting results provided by an embodiment of the present invention.

[0064] After the chip is mounted, S150 can be executed to perform wire bonding. The wire bonding result is as follows: Fig. 9 As shown, Fig. 9 A schematic diagram of a gold wire bonding result provided in an embodiment of the present invention.

[0065] exist Figure 2 Based on this, the embodiment of the present invention also provides an optional implementation method, please refer to Fig.10 , Fig.10 The second flow chart of the frame product packaging method provided by the embodiment of the present invention is as follows: After the gold wire bonding is completed, the frame product packaging method further includes: S160, which is as follows.

[0066] S160, the lead frame that has completed the gold wire bonding is plastic-sealed as a whole.

[0067] The plastic encapsulation material used for the overall plastic encapsulation is the same as the plastic encapsulation material used for the plastic encapsulation and curing of the etched area. Because the materials used for plastic encapsulation molding are consistent, the delamination problem caused by different CTE (coefficient of thermal expansion) of the materials is avoided, and the packaging reliability is improved.

[0068] In an optional implementation, after the overall plastic packaging is completed, it can be cut to form a finished product with a single package.

[0069] exist Figure 2 Based on this, the embodiment of the present invention also provides an optional implementation method, please refer to Fig.11 , Fig.11 The third flow chart of the frame product packaging method provided by the embodiment of the present invention is as follows: Before performing the gold wire bonding, the frame product packaging method further includes: S140, which is specifically as follows.

[0070] S140, performing silver treatment on the conductive pins of the lead frame.

[0071] Optionally, the lead frame material is copper, which cannot be wired, and the copper needs to contain silver, so the conductive pins of the lead frame are silvered, and the resulting silvered areas can be wired.

[0072] In the frame product packaging method provided in the embodiment of the present invention, the wafer stage forms an insulating isolation area through half-etching, dispensing and curing processes. After the surface is silvered, the device can be mounted without short-circuiting with the metal of the wafer stage. The external power supply V1 is connected to resistors of different resistance values ​​through different gold wire bonding, and then connected to the power supply pad of the bare core through gold wire bonding. Different voltages V2, V3, etc. can be converted to the bare chip in the package, thereby achieving the purpose of voltage conversion power supply.

[0073] Based on the above, regarding how to determine the relevant information of the power supply line, the embodiment of the present invention also provides an optional implementation method, please refer to Fig.12 , Fig.12 The fourth flow chart of the method for packaging frame products provided by the embodiment of the present invention is as follows: Before packaging the lead frame, the method for packaging frame products further includes: S210 and S220, which are described in detail as follows.

[0074] S210, performing simulation modeling on the lead frame and the chip to obtain a simulation model.

[0075] S220, performing simulation iterations according to the simulation model to determine the i-th target path.

[0076] The i-th target path is the i-th simulated power supply line between the lead frame and the chip in the simulation model, the voltage drop corresponding to the i-th target path is the i-th target voltage drop, and the i-th target path includes the position information of the i-th group of target areas on the wafer stage.

[0077] Optionally, the i-th target path also includes bonding wire property information of the i-th bonding wire, bonding wire property information of the N+i-th bonding wire, and resistance value information of the i-th chip resistor, wherein the bonding wire property information includes wire diameter and wire length. The bonding wire property information of the i-th bonding wire, the bonding wire property information of the N+i-th bonding wire, and resistance value information of the i-th chip resistor can be used as the execution standard of the subsequent packaging process.

[0078] The relevant information of each target path is determined through simulation to ensure that each power supply line completed subsequently can achieve the corresponding voltage drop and ensure the accuracy of the voltage conversion results.

[0079] The embodiment of the present invention also provides a frame product packaging structure, such as Figure 3 As shown. The packaging structure of frame products includes: The lead frame is provided with a wafer carrier and conductive pins.

[0080] A chip and N resistor components are arranged on a wafer carrier, the first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the N+i-th bonding wire, 1≤i≤N.

[0081] The voltage drop corresponding to the ith power supply line is the ith target voltage drop, and the ith power supply line includes the ith bonding wire, the ith resistance component, and the N+ith bonding wire.

[0082] Optionally, the resistor component is a chip resistor, and N groups of mounting areas are opened on the chip carrier, and each mounting area is insulated and isolated from the chip carrier.

[0083] Two ends of the i-th chip resistor are mounted on the first mounting area and the second mounting area of ​​the i-th group of mounting areas respectively.

[0084] The i-th bonding wire is connected to the first mounting area in the i-th group of mounting areas; the N+i-th bonding wire is connected to the second mounting area in the i-th group of mounting areas.

[0085] Optionally, the mounting area includes: an etching area arranged on the wafer carrier, an insulating isolation area formed by plastic sealing and curing; a silvered area arranged on the upper layer of the insulating isolation area, the silvered area is insulated and isolated from the wafer carrier, and the silvered area is used for resistor mounting and connecting bonding wires.

[0086] In summary, an embodiment of the present invention provides a frame-type product packaging structure and method, wherein the frame-type product packaging structure includes: a lead frame, on which a wafer carrier and conductive pins are arranged; a chip and N resistor components are arranged on the wafer carrier, the first end of the i-th resistor component is connected to the conductive pin of the lead frame through the i-th bonding wire, and the second end of the i-th resistor component is connected to the i-th power supply pin of the chip through the N+i-th bonding wire, 1≤i≤N; the voltage drop corresponding to the i-th power supply line is the i-th target voltage drop, and the i-th power supply line includes the i-th bonding wire, the i-th resistor component and the N+i-th bonding wire. The external power supply is converted through power supply lines with different target voltage drops, so as to realize the conversion from a single external power supply to a variety of different internal power supplies, and meet the needs of multiple power supplies without affecting its compatibility.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0088] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A frame product packaging structure, characterized in that: The frame product packaging structure includes: A lead frame, on which a wafer carrier and conductive pins are arranged; A chip and N resistor components are arranged on the wafer stage, a first end of the i-th resistor component is connected to a conductive pin of the lead frame through an i-th bonding wire, and a second end of the i-th resistor component is connected to an i-th power supply pin of the chip through an N+i-th bonding wire, 1≤i≤N; The voltage drop corresponding to the i-th power supply line is the i-th target voltage drop, and the i-th power supply line includes the i-th bonding wire, the i-th resistor component and the N+i-th bonding wire; The resistor component is a chip resistor, and N groups of mounting areas are provided on the chip carrier, and each mounting area is insulated and isolated from the chip carrier; The two ends of the i-th chip resistor are mounted on the first mounting area and the second mounting area of ​​the i-th group of mounting areas respectively; The i-th bonding wire is connected to the first mounting area in the i-th group of mounting areas; The N+i th bonding wire is connected to the second mounting area in the i th group of mounting areas.

2. The frame product packaging structure according to claim 1, characterized in that: The mounting area includes: An insulating isolation area is provided in the etching area on the wafer stage and formed by plastic sealing and curing; A silvering area is arranged on the upper layer of the insulating isolation area, the silvering area is insulated and isolated from the wafer carrier, and the silvering area is used for resistor mounting and connecting bonding wires.

3. A method for packaging frame products, characterized in that: The method comprises: Opening a mounting area, and opening N groups of mounting areas on a wafer carrier set on the lead frame, each mounting area is insulated and isolated from the wafer carrier; Perform resistor mounting, mounting the two ends of the i-th chip resistor on the first mounting area and the second mounting area of ​​the i-th group of mounting areas, respectively, 1≤i≤N; Perform chip mounting, mounting the chip on a designated area on the wafer stage; Performing gold wire bonding, including: connecting a first mounting area in the i-th group of mounting areas to a conductive pin of the lead frame through an i-th bonding wire, and connecting a second mounting area in the i-th group of mounting areas to an i-th power supply pin of the chip through an N+i-th bonding wire; The voltage drop corresponding to the ith power supply line is the ith target voltage drop, and the ith power supply line includes the ith bonding wire, the ith resistance component, and the N+ith bonding wire.

4. The frame product packaging method according to claim 3, characterized in that: The step of opening a mounting area includes: Etching N groups of target areas pre-planned on the wafer stage to obtain N groups of etched areas; Plastic-sealing and curing the etched areas to form N groups of insulating isolation areas; Silver treatment is performed on the wire bonding area in the insulating isolation area to obtain N groups of mounting areas.

5. The frame product packaging method according to claim 4, characterized in that: The etching thickness is half of the thickness of the wafer stage.

6. The frame product packaging method according to claim 4, characterized in that: After the gold wire bonding is completed, the method further comprises: The lead frame after gold wire bonding is integrally encapsulated, and the encapsulation material used for the overall encapsulation is the same as the encapsulation material used for encapsulating and curing the etched area.

7. The frame product packaging method according to claim 4, characterized in that: Before performing gold wire bonding, the method further includes: The conductive pins of the lead frame are silvered.

8. The frame product packaging method according to claim 4, characterized in that: Before packaging the lead frame, the method further comprises: Performing simulation modeling on the lead frame and the chip to obtain a simulation model; Simulation iterations are performed according to the simulation model to determine the i-th target path, the i-th target path is the i-th simulated power supply line between the lead frame and the chip in the simulation model, the voltage drop corresponding to the i-th target path is the i-th target voltage drop, and the i-th target path includes position information of the i-th group of target areas on the wafer stage.

9. The frame product packaging method according to claim 8, characterized in that: The i-th target path also includes bonding wire attribute information of the i-th bonding wire, bonding wire attribute information of the N+i-th bonding wire, and resistance value information of the i-th chip resistor, and the bonding wire attribute information includes wire diameter and wire length.

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