Intelligent power module and electronic equipment

Abstract

The invention discloses an intelligent power module and electronic equipment. The intelligent power module comprises a packaging body; a driving circuit board; a power side substrate; a power side substrate; the power pin, the three second jumper wire areas and the three first jumper wire areas are selectively and simultaneously electrically connected in a one-to-one correspondence mode, and the three voltage source switching bonding pads are selectively and simultaneously electrically connected with emitter bonding pads on the three insulated gate bipolar transistors in a one-to-one correspondence mode. The three voltage source switching bonding pads and the three second jumper areas are selectively and simultaneously electrically connected in a one-to-one correspondence mode. Therefore, the length of the electric connection between the driving chip and the high-voltage power chip can be selectively adjusted according to the magnitude of the current between the driving chip and the high-voltage power chip so as to change the gate-emitter inductance of the high-voltage power chip, so that the switching loss and the peak voltage of the high-voltage power chip can be relatively balanced; and the two are in a relatively excellent range, so that the performance of the intelligent power module can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an intelligent power module and electronic equipment. Background Art

[0002] When designing intelligent power module products with different current specifications in the same series, chips with different current specifications are usually adapted in the same frame layout structure, so as to form intelligent power module products with different current specifications under a certain series while reducing costs.

[0003] In the prior art, the wiring method between the driver chip and the power chip in the same frame layout structure is single. When the current specifications of the power chips are different, it will lead to the inability to achieve a relative balance between the switching loss and the peak voltage of the power chip. Often, only one side's value can be within a better range, which will make the performance of the intelligent power module poor. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide an intelligent power module, which has good performance.

[0005] The present invention further provides an electronic device.

[0006] According to an embodiment of the present invention, the intelligent power module comprises: a package body; a driving circuit board, on which a driving chip is arranged; a power side substrate, which is arranged in the package body and is spaced apart from the driving circuit board in the second direction, the power side substrate is provided with high-voltage power pads and low-voltage power pads spaced apart in the first direction, and the high-voltage power pads are provided with three high-voltage power chips spaced apart in the first direction; a power pin, which is arranged in the package body and is located on the side of the power side substrate away from the driving circuit board in the second direction, and the power pin includes high-voltage power pads spaced apart in the first direction. rate pin and low voltage power pin, there are three high voltage power pins, and the three high voltage power pins are arranged at intervals in the first direction; each of the high voltage power chips includes an insulated gate bipolar transistor and a fast recovery diode arranged at intervals in the second direction, and the insulated gate bipolar transistor is provided with a gate pad and an emitter pad. In each of the high voltage power chips, compared with the fast recovery diode, the insulated gate bipolar transistor is closer to the driving circuit board in the second direction, and the emitter pads on the three insulated gate bipolar transistors are electrically connected to the three fast recovery diodes in a one-to-one correspondence. The three fast recovery diodes are electrically connected to the three high The power pins are electrically connected one by one; one of the driver chips is arranged in the middle of the driver circuit board; the projections of the three high-voltage power chips in the second direction are spaced apart from the projection of the driver chip in the second direction and are located on the side away from the low-voltage power pad in the first direction; three high-voltage output pads and three voltage source pads are arranged on the driver chip; three high-voltage output transfer pads and three voltage source transfer pads are arranged on the driver circuit board; the three high-voltage output transfer pads and the three voltage source transfer pads are spaced apart on the side of the driver chip in the second direction facing the power side substrate; the three high-voltage output transfer pads The projections of the three voltage source transfer pads in the second direction are spaced apart on the side of the projection of the driver chip in the second direction away from the low voltage power pad in the first direction, and the three high voltage output transfer pads and the three voltage source transfer pads correspond to the three high voltage power chips in the second direction; the three high voltage output pads on the driver chip are electrically connected to the three high voltage output transfer pads in a one-to-one correspondence, and the three voltage source pads on the driver chip are electrically connected to the three voltage source transfer pads in a one-to-one correspondence; the three high voltage output transfer pads are electrically connected to the gate pads on the three insulated gate bipolar transistors in a one-to-one correspondence;The power side substrate is provided with three first jumper areas and three second jumper areas, the three first jumper areas are selectively and simultaneously electrically connected to the three fast recovery diodes in one-to-one correspondence, the three first jumper areas are selectively and simultaneously electrically connected to the three high voltage power pins in one-to-one correspondence, the three second jumper areas are selectively and simultaneously electrically connected to the three first jumper areas in one-to-one correspondence, the three voltage source transfer pads are selectively and simultaneously electrically connected to the emitter pads on the three insulated gate bipolar transistors in one-to-one correspondence, and the three voltage source transfer pads are selectively and simultaneously electrically connected to the three second jumper areas in one-to-one correspondence. ;

[0007] Therefore, the length of the electrical connection between the driver chip and the high-voltage power chip can be selectively adjusted according to the current between the driver chip and the high-voltage power chip to change the gate-emitter inductance of the high-voltage power chip. This can achieve a relative balance between the switching loss and the peak voltage of the high-voltage power chip, so that both are within a relatively optimal range, which can improve the performance of the intelligent power module.

[0008] In some examples of the present invention, when the three first jumper areas are electrically connected to the three high-voltage power pins in a one-to-one correspondence at the same time, the three first jumper areas are not electrically connected to the three fast recovery diodes, the three voltage source transfer pads are not electrically connected to the emitter pads on the three insulated gate bipolar transistors, the three second jumper areas are electrically connected to the three first jumper areas in a one-to-one correspondence at the same time, and the three voltage source transfer pads are electrically connected to the three second jumper areas in a one-to-one correspondence at the same time.

[0009] In some examples of the present invention, the current between the driving chip and the high-voltage power chip in the package is set to I1, and I1 satisfies the relationship: I1<20A.

[0010] In some examples of the present invention, when the three voltage source transfer pads are electrically connected one-to-one with the emitter pads on the three insulated gate bipolar transistors, there is no electrical connection between the three first jumper areas and the three fast recovery diodes, there is no electrical connection between the three first jumper areas and the three high-voltage power pins, there is no electrical connection between the three second jumper areas and the three first jumper areas, and there is no electrical connection between the three voltage source transfer pads and the three second jumper areas.

[0011] In some examples of the present invention, the current between the driving chip and the high-voltage power chip in the package is set to I2, and I2 satisfies the relationship: 30A<I2≤50A.

[0012] In some examples of the present invention, when the three first jumper areas are electrically connected one-to-one with the three fast recovery diodes at the same time, the three first jumper areas are not electrically connected to the three high-voltage power pins, the three second jumper areas are electrically connected one-to-one with the three first jumper areas at the same time, the three voltage source transfer pads are electrically connected one-to-one with the three second jumper areas at the same time, and the three voltage source transfer pads are not electrically connected to the emitter pads on the three insulated gate bipolar transistors.

[0013] In some examples of the present invention, the current between the driving chip and the high-voltage power chip in the package is set to I3, and I3 satisfies the relationship: 20A≤I3<30A.

[0014] In some examples of the present invention, the three first jumper areas are respectively a first sub-jumper area, a second sub-jumper area and a third sub-jumper area, the three high-voltage power chips are respectively a first high-voltage power chip, a second high-voltage power chip and a third high-voltage power chip, compared with the second high-voltage power chip and the third high-voltage power chip, the first high-voltage power chip is closer to the low-voltage power pad in the first direction, and the second high-voltage power chip is spaced between the first high-voltage power chip and the second high-voltage power chip in the first direction; the first sub-jumper area is spaced between the first high-voltage power chip and the low-voltage power pad in the first direction, and the second sub-jumper area is set in the second direction The projection on the second sub-jumper area is set as the projection of the second sub-jumper area, the projection of the third sub-jumper area in the second direction is set as the projection of the third sub-jumper area, the projection of the first high-voltage power chip in the second direction is set as the projection of the first high-voltage power chip, the projection of the second high-voltage power chip in the second direction is set as the projection of the second high-voltage power chip, and the projection of the third high-voltage power chip in the second direction is set as the projection of the third high-voltage power chip; the center of the projection of the second sub-jumper area is located between the projection of the first high-voltage power chip and the projection of the second high-voltage power chip in the first direction, and the center of the projection of the third sub-jumper area is located between the projection of the second high-voltage power chip and the projection of the third high-voltage power chip in the first direction.

[0015] In some examples of the present invention, the projection of the second sub-jumper area at least partially overlaps with the projection of the first high-voltage power chip, and the projection of the second sub-jumper area at least partially overlaps with the projection of the second high-voltage power chip; the projection of the third sub-jumper area at least partially overlaps with the projection of the second high-voltage power chip, and the projection of the third sub-jumper area at least partially overlaps with the projection of the third high-voltage power chip.

[0016] In some examples of the present invention, the second sub-jump area is spaced apart from the insulated gate bipolar transistor and the fast recovery diode of the first high-voltage power chip in the second direction, and the second sub-jump area is spaced apart from the insulated gate bipolar transistor and the fast recovery diode of the second high-voltage power chip in the second direction; the third sub-jump area is spaced apart from the insulated gate bipolar transistor and the fast recovery diode of the second high-voltage power chip in the second direction, and the third sub-jump area is spaced apart from the insulated gate bipolar transistor and the fast recovery diode of the third high-voltage power chip in the second direction.

[0017] In some examples of the present invention, three of the second jumper areas are arranged in one-to-one correspondence with the three high-voltage power chips, and the second jumper areas are arranged at intervals on a side of the high-voltage power chip in a second direction toward the driving circuit board.

[0018] In some examples of the present invention, the three second jumper areas are respectively a fourth sub-jumper area, a fifth sub-jumper area and a sixth sub-jumper area. Compared with the fifth sub-jumper area and the sixth sub-jumper area, the fourth sub-jumper area is closer to the low-voltage power pad in the first direction, and the fifth sub-jumper area is spaced between the fourth sub-jumper area and the sixth sub-jumper area in the first direction; the fourth sub-jumper area, the fifth sub-jumper area and the sixth sub-jumper area are located on the driving side substrate and are spaced from the high-voltage drive pad in the second direction, the first sub-jumper area is located on the driving side substrate and is spaced from the high-voltage drive pad in the first direction, and the first sub-jumper area is connected to the fourth sub-jumper area; the second sub-jumper area and the third sub-jumper area are both located on the high-voltage drive pad, the second sub-jumper area and the fifth sub-jumper area are spaced from each other in the second direction, and the third sub-jumper area and the sixth sub-jumper area are spaced from each other in the second direction.

[0019] In some examples of the present invention, the fourth sub-jump area, the fifth sub-jump area and the sixth sub-jump area are all in the shape of long strips and extend in the first direction; the first sub-jump area is in the shape of long strips and extend in the second direction, the second sub-jump area and the third sub-jump area are both block-shaped, and a side of the high-voltage power pad that is closer to the low-voltage power pad in the first direction is at least partially provided with an avoidance gap, and the first sub-jump area is arranged in the avoidance gap.

[0020] In some examples of the present invention, the gate pad of the insulated gate bipolar transistor is located on a side of the insulated gate bipolar transistor that is farther away from the low-voltage power pad along the first direction; the gate pad of the insulated gate bipolar transistor is located on a side of the insulated gate bipolar transistor that is closer to the driving circuit board along the second direction.

[0021] In some examples of the present invention, the three high-voltage output pads and the three voltage source pads on the driver chip together constitute three pad groups, each pad group includes one high-voltage output pad and one voltage source pad spaced apart from each other, the three high-voltage output transfer pads and the three voltage source transfer pads together constitute three transfer pad groups, each transfer pad group includes one high-voltage output transfer pad and one voltage source transfer pad spaced apart from each other in a first direction, the three transfer pad groups correspond one-to-one to the three pad groups, and the three high-voltage power chips correspond one-to-one to the three transfer pad groups; the three transfer pad groups are spaced apart in the first direction, and in each pad group, the high-voltage output transfer pad is spaced apart from the first pad. The voltage source transfer pad is further away from the low-voltage power pad in the first direction; the three pad groups include a first pad group, a second pad group and a third pad group, the first pad group and the second pad group are arranged on the side of the driving chip adjacent to the power side substrate in the second direction, the first pad group and the second pad group are spaced apart in the first direction, and in the first pad group and the second pad group, the high-voltage output pad is further away from the low-voltage power pad in the first direction than the voltage source pad; the third pad group is located on the side of the driving chip that is further away from the low-voltage power pad in the first direction, and in the third pad group, the high-voltage output pad is further away from the power side substrate in the second direction than the voltage source pad.

[0022] An electronic device according to an embodiment of the present invention includes: the above-mentioned intelligent power module.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] Figure 1 is a schematic diagram of an intelligent power module according to a first embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of an intelligent power module according to a second embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of an intelligent power module according to a second embodiment of the present invention;

[0028] Figure 4FIG. 4 is a schematic diagram of an intelligent power module according to a third embodiment of the present invention.

[0029] Reference numerals:

[0030] 100. Intelligent power module;

[0031] 10. Driver circuit board; 101. Driver chip; 102. High voltage output transfer pad; 103. Voltage source transfer pad;

[0032] 20. Power side substrate; 201. High voltage power pad; 202. Low voltage power pad; 203. First jumper area; 204. Second jumper area;

[0033] 2011, high-voltage power chip; 2012, insulated gate bipolar transistor; 2013, fast recovery diode; 2014, gate pad; 2015, emitter pad; 2016, avoidance gap;

[0034] 20111, a first high-voltage power chip; 20112, a second high-voltage power chip; 20113, a third high-voltage power chip;

[0035] 2051, a first sub-jumping area; 2052, a second sub-jumping area; 2053, a third sub-jumping area; 2054, a fourth sub-jumping area; 2055, a fifth sub-jumping area; 2056, a sixth sub-jumping area;

[0036] 30, power pin; 301, high voltage power pin; 302, low voltage power pin;

[0037] 40. Encapsulation body. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0039] Reference below Figure 1-Figure 4 The intelligent power module 100 according to the embodiment of the present invention is described. The intelligent power module 100 can be applied to electronic devices.

[0040] Combination Figure 1 and Figure 4As shown, the intelligent power module 100 according to the present invention can mainly include: a package body 40, a driving circuit board 10, a power side substrate 20 and a power pin 30, wherein a driving chip 101 is arranged on the driving circuit board 10, the power side substrate 20 is arranged in the package body 40 and is spaced apart from the driving circuit board 10 in the second direction, a high-voltage power pad 201 and a low-voltage power pad 202 spaced apart in the first direction are arranged on the power side substrate 20, three high-voltage power chips 2011 spaced apart in the first direction are arranged on the high-voltage power pad 201, the power pin 30 is arranged in the package body 40 and is located on the side of the power side substrate 20 away from the driving circuit board 10 in the second direction, the power pin 30 includes a high-voltage power pin 301 and a low-voltage power pin 302 spaced apart in the first direction, there are three high-voltage power pins 301, and the three high-voltage power pins 301 are spaced apart in the first direction.

[0041] Each high-voltage power chip 2011 includes an insulated gate bipolar transistor 2012 and a fast recovery diode 2013 spaced apart in the second direction. A gate pad 2014 and an emitter pad 2015 are provided on the insulated gate bipolar transistor 2012. In each high-voltage power chip 2011, compared with the fast recovery diode 2013, the insulated gate bipolar transistor 2012 is closer to the driving circuit board 10 in the second direction. The emitter pads 2015 on the three insulated gate bipolar transistors 2012 are electrically connected to the three fast recovery diodes 2013 in a one-to-one correspondence. The three fast recovery diodes 2013 are electrically connected to the three high-voltage power pins 301 in a one-to-one correspondence. The chip 101 is arranged in the middle of the driving circuit board 10, and the projections of the three high-voltage power chips 2011 in the second direction are all arranged at intervals on the projection of the driving chip 101 in the second direction and are located on the side away from the low-voltage power pad 202 in the first direction. Three high-voltage output pads and three voltage source pads are arranged on one driving chip 101, and three high-voltage output transfer pads 102 and three voltage source transfer pads 103 are arranged on the driving circuit board 10. The three high-voltage output transfer pads 102 and the three voltage source transfer pads 103 are all arranged at intervals on the side of the driving chip 101 facing the power substrate in the second direction. The three high-voltage output transfer pads 102 and the three voltage source transfer pads The projections of 103 in the second direction are spaced apart on the side of the projection of the driver chip 101 in the second direction away from the low-voltage power pad 202 in the first direction. The three high-voltage output transfer pads 102 and the three voltage source transfer pads 103 correspond to the three high-voltage power chips 2011 in the second direction; the three high-voltage output pads on the driver chip 101 and the three high-voltage output transfer pads 102 are electrically connected one-to-one, and the three voltage source pads on the driver chip 101 and the three voltage source transfer pads 103 are electrically connected one-to-one; the three high-voltage output transfer pads 102 are electrically connected one-to-one with the gate pads 2014 on the three insulated gate bipolar transistors 2012, and the power Three first jumper areas 203 and three second jumper areas 204 are provided on the rate-side substrate 20, the three first jumper areas 203 are selectively and simultaneously electrically connected to the three fast recovery diodes 2013 in one-to-one correspondence, the three first jumper areas 203 are selectively and simultaneously electrically connected to the three high-voltage power pins 301 in one-to-one correspondence, the three second jumper areas 204 are selectively and simultaneously electrically connected to the three first jumper areas 203 in one-to-one correspondence, the three voltage source transfer pads 103 are selectively and simultaneously electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012 in one-to-one correspondence, and the three voltage source transfer pads 103 are selectively and simultaneously electrically connected to the three second jumper areas 204 in one-to-one correspondence.

[0042] Specifically, first, the emitter pads 2015 on the three insulated gate bipolar transistors 2012 are electrically connected to the three fast recovery diodes 2013 in a one-to-one correspondence, the three fast recovery diodes 2013 are electrically connected to the three high-voltage power pins 301 in a one-to-one correspondence, and the three high-voltage output transfer pads 102 are electrically connected to the gate pads 2014 on the three insulated gate bipolar transistors 2012 in a one-to-one correspondence. It should be noted that when the current between the driving chip 101 and the high-voltage power chip 2011 in the package body 40 is in different ranges, the above components are still electrically connected. In the embodiment of the present invention, By selectively and simultaneously connecting the three first jumper areas 203 and the three fast recovery diodes 2013 in one-to-one correspondence, the three first jumper areas 203 and the three high-voltage power pins 301 in one-to-one correspondence, the three second jumper areas 204 and the three first jumper areas 203 in one-to-one correspondence, the three voltage source transfer pads 103 and the emitter pads 2015 on the three insulated gate bipolar transistors 2012 in one-to-one correspondence, and the three voltage source transfer pads 103 and the three second jumper areas 204 in one-to-one correspondence.

[0043] It should be noted that when the current between the driving chip 101 and the high-voltage power chip 2011 in the intelligent power module 100 is smaller, the switching speed of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is faster, which will cause the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 to have a relatively large peak voltage when it is turned off. Since the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is proportional to the current level, the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is relatively small. At this time, it is necessary to balance the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off. Therefore, it can be achieved by increasing The length of the electrical connection line between the driving chip 101 and the high-voltage power chip 2011 in the intelligent power module 100 is increased to increase the gate-emitter inductance of the high-voltage power chip 2011, thereby reducing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and further reducing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011. Although this reduces the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, which increases the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011 is relatively small at low currents, so that both the switching loss and the peak voltage can be within a relatively optimal range.

[0044] Similarly, when the current between the driving chip 101 and the high-voltage power chip 2011 in the intelligent power module 100 is larger, the switching speed of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is slower, which will cause the peak voltage of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 to be relatively small when it is turned off. Since the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is proportional to the current level, the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is relatively large. At this time, it is necessary to balance the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off. Therefore, the intelligent power module 100 can be reduced by The length of the electrical connection line between the driving chip 101 and the high-voltage power chip 2011 in the power module 100 is reduced to reduce the gate-emitter inductance of the high-voltage power chip 2011, thereby increasing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and further increasing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011. Although this increases the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011 and reduces the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011 is relatively large at high currents, so that both the switching loss and the peak voltage are within a relatively optimal range.

[0045] Therefore, it can be understood that in the process of production and manufacturing, by selectively setting the electrical connection relationship between the first jumper area 203, the second jumper area 204, the fast recovery diode 2013, the high-voltage power pin 301, the voltage source transfer pad 103 and the emitter pad 2015 on the insulated gate bipolar transistor 2012, the length of the electrical connection line between the driver chip 101 and the high-voltage power chip 2011 in the intelligent power module 100 can be changed, thereby changing the size of the gate-emitter inductance of the high-voltage power chip 2011, thereby balancing the relationship between the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off when different current specifications are met, so that the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off are both within a better range.

[0046] Therefore, the length of the electrical connection between the driver chip 101 and the high-voltage power chip 2011 can be selectively adjusted according to the current between the driver chip 101 and the high-voltage power chip 2011 to change the gate-emitter inductance of the high-voltage power chip 2011. This can achieve a relative balance between the switching loss and the peak voltage of the high-voltage power chip 2011, so that both are within a relatively optimal range, which can improve the performance of the intelligent power module 100.

[0047] In some embodiments of the present invention, Figure 1 As shown, when the three first jumper areas 203 are electrically connected to the three high-voltage power pins 301 in a one-to-one correspondence at the same time, the three first jumper areas 203 are not electrically connected to the three fast recovery diodes 2013, the three voltage source transfer pads 103 of the driver chip 101 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012, the three second jumper areas 204 are electrically connected to the three first jumper areas 203 in a one-to-one correspondence at the same time, and the three voltage source transfer pads 103 of the driver chip 101 are electrically connected to the three second jumper areas 204 in a one-to-one correspondence at the same time.

[0048] Specifically, when the three first jumper areas 203 are electrically connected to the three high-voltage power pins 301 in a one-to-one correspondence at the same time, the three second jumper areas 204 can be electrically connected to the three first jumper areas 203 in a one-to-one correspondence at the same time, and the three voltage source transfer pads 103 of the driver chip 101 are electrically connected to the three second jumper areas 204 in a one-to-one correspondence at the same time, and the three first jumper areas 203 are not electrically connected to the three fast recovery diodes 2013, and the three voltage source transfer pads 103 of the driver chip 101 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012. The electrical connection method between the driver chip 101 and the high-voltage power chip 2011 in the embodiment is suitable for the case of smaller current specifications. In the intelligent power module 100 in this embodiment, the length of the electrical connection line between the driver chip 101 and the high-voltage power chip 2011 is longer, which can increase the gate-emitter inductance of the high-voltage power chip 2011, thereby reducing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, thereby reducing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and both the switching loss and the peak voltage can be within a relatively optimal range.

[0049] Combination Figure 1As shown, the current between the driver chip 101 and the high-voltage power chip 2011 in the package body 40 is set to I1, and I1 satisfies the relationship: I1<20A. Specifically, in the first embodiment above, the current between the driver chip 101 and the high-voltage power chip 2011 is set within a reasonable smaller range, which can further optimize the balance between the switching loss and the peak voltage, thereby further optimizing the performance of the intelligent power module 100.

[0050] In other embodiments of the present invention, Figure 2 As shown, when the three voltage source transfer pads 103 of the driver chip 101 are electrically connected one by one with the emitter pads 2015 on the three insulated gate bipolar transistors 2012, there is no electrical connection between the three first jumper areas 203 and the three fast recovery diodes 2013, there is no electrical connection between the three first jumper areas 203 and the three high-voltage power pins 301, there is no electrical connection between the three second jumper areas 204 and the three first jumper areas 203, and there is no electrical connection between the three voltage source transfer pads 103 of the driver chip 101 and the three second jumper areas 204.

[0051] Specifically, when the three voltage source transfer pads 103 of the driver chip 101 are electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012 in a one-to-one correspondence, the three first jumper areas 203 are not electrically connected to the three high-voltage power pins 301, the three second jumper areas 204 are not electrically connected to the three first jumper areas 203, the three voltage source transfer pads 103 of the driver chip 101 are not electrically connected to the three second jumper areas 204, and the three voltage source transfer pads 103 of the driver chip 101 are not electrically connected to the three second jumper areas 204. In this embodiment, The electrical connection method between the middle driver chip 101 and the high-voltage power chip 2011 is suitable for situations with larger current specifications. In this embodiment, the length of the electrical connection line between the driver chip 101 and the high-voltage power chip 2011 in the intelligent power module 100 is relatively short, which can reduce the gate-emitter inductance of the high-voltage power chip 2011, thereby increasing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, thereby increasing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and can make both the switching loss and the peak voltage within a relatively optimal range.

[0052] Combination Figure 2As shown, the current between the driver chip 101 and the high-voltage power chip 2011 in the package body 40 is set to I2, and I2 satisfies the relationship: 30A<I2≤50A. Specifically, in the above second embodiment, the current between the driver chip 101 and the high-voltage power chip 2011 is set within a reasonable and large range, which can further optimize the balance between the switching loss and the peak voltage, thereby further optimizing the performance of the intelligent power module 100.

[0053] In some embodiments of the present invention, Figure 4 As shown, when the three first jumper areas 203 are electrically connected to the three fast recovery diodes 2013 at the same time, the three first jumper areas 203 are not electrically connected to the three high-voltage power pins 301, the three second jumper areas 204 are electrically connected to the three first jumper areas 203 at the same time, the three voltage source transfer pads 103 of the driver chip 101 are electrically connected to the three second jumper areas 204 at the same time, and the three voltage source transfer pads 103 of the driver chip 101 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012.

[0054] Specifically, when the three first jumper areas 203 are electrically connected to the three fast recovery diodes 2013 in a one-to-one correspondence at the same time, the three second jumper areas 204 are electrically connected to the three first jumper areas 203 in a one-to-one correspondence at the same time, and the three voltage source transfer pads 103 of the driver chip 101 are electrically connected to the three second jumper areas 204 in a one-to-one correspondence at the same time, so that the three first jumper areas 203 and the three high-voltage power pins 301 are not electrically connected, and the three voltage source transfer pads 103 of the driver chip 101 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012. The electrical connection method between the driver chip 101 and the high-voltage power chip 2011 in this embodiment is suitable for the case where the current specification is moderate. The length of the electrical connection line between the driver chip 101 and the high-voltage power chip 2011 in the intelligent power module 100 in this embodiment is moderate, so that the switching loss and the peak voltage will not be too large or too small, and both the switching loss and the peak voltage can be within a relatively optimal range.

[0055] Combination Figure 4 As shown, the current between the driver chip 101 and the high-voltage power chip 2011 in the package body 40 is set to I3, and I3 satisfies the relationship: 20A≤I3<30A. Specifically, in the third embodiment, the current between the driver chip 101 and the high-voltage power chip 2011 is set within a reasonable and moderate range, which can further optimize the balance between the switching loss and the peak voltage, thereby further optimizing the performance of the intelligent power module 100.

[0056] Combination Figure 1-Figure 4 As shown, the three first jumper areas 203 are respectively the first sub-jumper area 2051, the second sub-jumper area 2052 and the third sub-jumper area 2053, the three high-voltage power chips 2011 are respectively the first high-voltage power chip 20111, the second high-voltage power chip 20112 and the third high-voltage power chip 20113, compared with the second high-voltage power chip 20112 and the third high-voltage power chip 20113, the first high-voltage power chip 20111 is closer to the low-voltage power pad 202 in the first direction, the second high-voltage power chip 20112 is spaced between the first high-voltage power chip 20111 and the second high-voltage power chip 20112 in the first direction, the first sub-jumper area 2051 is spaced between the first high-voltage power chip 20111 and the low-voltage power pad 202 in the first direction, and the second sub-jumper area 2052 is set in the second The projection in the second direction is set as the projection of the second sub-jumper area 2052, the projection of the third sub-jumper area 2053 in the second direction is set as the projection of the third sub-jumper area 2053, the projection of the first high-voltage power chip 20111 in the second direction is set as the projection of the first high-voltage power chip 20111, the projection of the second high-voltage power chip 20112 in the second direction is set as the projection of the second high-voltage power chip 20112, and the projection of the third high-voltage power chip 20113 in the second direction is set as the projection of the third high-voltage power chip 20113. The center of the projection of the second sub-jumper area 2052 is located between the projection of the first high-voltage power chip 20111 and the projection of the second high-voltage power chip 20112 in the first direction, and the center of the projection of the third sub-jumper area 2053 is located between the projection of the second high-voltage power chip 20112 and the projection of the third high-voltage power chip 20113 in the first direction.

[0057] Such an arrangement can make the arrangement of the three first jumper areas 203 on the power side substrate 20 more reasonable, and will not occupy too much space on the power side substrate 20. Under the premise of ensuring that the arrangement of the first jumper area 203 will not affect the normal installation and arrangement of the high-voltage power chip 2011, it can not only improve the stability and reliability of the installation and arrangement of the first jumper area 203, but also further ensure the stability of the electrical connection between the first jumper area 203 and the high-voltage power pin 301 or the fast recovery diode 2013, and prevent the electrical connection wire between the first jumper area 203 and the high-voltage power pin 301 or the fast recovery diode 2013 from being too long, resulting in unreliable electrical connection between the first jumper area 203 and the high-voltage power pin 301 or the fast recovery diode 2013.

[0058] Combination Figure 1-Figure 4As shown, the projection of the second sub-jumper area 2052 at least partially overlaps with the projection of the first high-voltage power chip 20111, the projection of the second sub-jumper area 2052 at least partially overlaps with the projection of the second high-voltage power chip 20112, the projection of the third sub-jumper area 2053 at least partially overlaps with the projection of the second high-voltage power chip 20112, and the projection of the third sub-jumper area 2053 at least partially overlaps with the projection of the third high-voltage power chip 20113.

[0059] Specifically, by making the projection of the second sub-jumper area 2052 at least partially overlap with the projection of the first high-voltage power chip 20111, the projection of the second sub-jumper area 2052 at least partially overlap with the projection of the second high-voltage power chip 20112, the projection of the third sub-jumper area 2053 at least partially overlap with the projection of the second high-voltage power chip 20112, and the projection of the third sub-jumper area 2053 at least partially overlap with the projection of the third high-voltage power chip 20113, the first jumper area 203 and the three high-voltage side power chips can be made more compact, thereby improving the space utilization of the power side substrate 20. The setting of the first jumper area 203 will not increase the volume of the power side substrate 20, and the miniaturization of the intelligent power module 100 can be ensured.

[0060] Combination Figure 1-4 As shown, the second sub-jump area 2052 is spaced apart from the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 of the first high-voltage power chip 20111 in the second direction, and the second sub-jump area 2052 is spaced apart from the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 of the second high-voltage power chip 20112 in the second direction; the third sub-jump area 2053 is spaced apart from the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 of the second high-voltage power chip 20112 in the second direction, and the third sub-jump area 2053 is spaced apart from the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 of the third high-voltage power chip 20113 in the second direction.

[0061] Specifically, since the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 of the high-voltage power chip 2011 are spaced apart in the second direction, the second sub-jump area 2052 and the third sub-jump area 2053 are both arranged between the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 in the second direction. This can not only make full use of the space between the insulated gate bipolar transistor 2012 and the fast recovery diode 2013, but also further improve the space utilization rate of the intelligent power module 100, and will not affect the electrical connection between other components, and can optimize the structural layout on the power side substrate 20.

[0062] Combination Figure 1-4As shown, three second jumper areas 204 are arranged in one-to-one correspondence with three high-voltage power chips 2011 , and the second jumper areas 204 are arranged at intervals on the side of the high-voltage power chip 2011 facing the driving circuit board 10 in the second direction.

[0063] Specifically, the three second jumper areas 204 are arranged in one-to-one correspondence with the three high-voltage power chips 2011, and the second jumper areas 204 are arranged at intervals on the side of the high-voltage power chip 2011 in the second direction toward the driver circuit board 10. This not only facilitates the electrical connection between the second jumper area 204 and the voltage source transfer pad 103, but also can make full use of the space between the driver circuit board 10 and the power side substrate 20, thereby improving the space utilization rate of the intelligent power module 100.

[0064] Combination Figure 1-4 As shown, the three second jumper areas 204 are respectively a fourth sub-jumper area 2054, a fifth sub-jumper area 2055 and a sixth sub-jumper area 2056. Compared with the fifth sub-jumper area 2055 and the sixth sub-jumper area 2056, the fourth sub-jumper area 2054 is closer to the low-voltage power pad 202 in the first direction, and the fifth sub-jumper area 2055 is spaced between the fourth sub-jumper area 2054 and the sixth sub-jumper area 2056 in the first direction; the fourth sub-jumper area 2054, the fifth sub-jumper area 2055 and the sixth sub-jumper area 2056 are located at the bottom of the circuit. On the driving side substrate and spaced apart from the high-voltage driving pad in the second direction, the first sub-jump area 2051 is located on the driving side substrate and spaced apart from the high-voltage driving pad in the first direction, and the first sub-jump area 2051 is connected to the fourth sub-jump area 2054; the second sub-jump area 2052 and the third sub-jump area 2053 are both located on the high-voltage driving pad, the second sub-jump area 2052 and the fifth sub-jump area 2055 are spaced apart in the second direction, and the third sub-jump area 2053 and the sixth sub-jump area 2056 are spaced apart in the second direction.

[0065] Specifically, by reasonably setting the positions of the first jumper area 203 and the second jumper area 204, while ensuring that the first jumper area 203 and the second jumper area 204 do not occupy too much space on the power side substrate 20, not only can the electrical connection between the first jumper area 203 and the second jumper area 204 be facilitated, but also the electrical connection between the first jumper area 203, the second jumper area 204 and other components can be facilitated, which can further optimize the structural design of the intelligent power module 100.

[0066] Furthermore, since the first sub-jumper area 2051 and the fourth sub-jumper area 2054 are adjacent to each other at the edge of the power pad, the first sub-jumper area 2051 and the fourth sub-jumper area 2054 can be directly connected, without affecting other components. When an electrical connection is required between the first jumper area 203 and the second jumper area 204, the electrical connection wire between the first sub-jumper area 2051 and the fourth sub-jumper can be omitted, which can further optimize the structural design of the intelligent power module 100.

[0067] Combination Figure 1-4 As shown, the fourth sub-jumper area 2054, the fifth sub-jumper area 2055 and the sixth sub-jumper area 2056 are all in the shape of long strips and extend in the first direction; the first sub-jumper area 2051 is in the shape of long strips and extend in the second direction, the second sub-jumper area 2052 and the third sub-jumper area 2053 are both block-shaped, and the side of the high-voltage power pad 201 that is closer to the low-voltage power pad 202 in the first direction is at least partially provided with an avoidance gap 2016, and the first sub-jumper area 2051 is arranged in the avoidance gap 2016.

[0068] Specifically, the fourth sub-jumper area 2054, the fifth sub-jumper area 2055 and the sixth sub-jumper area 2056 are all in the shape of long strips and extend in the first direction. This can reduce the difficulty of electrical connection between the second jumper area 204 and the first jumper area 203, or reduce the difficulty of electrical connection between the second jumper area 204 and the voltage source transfer pad 103.

[0069] Furthermore, the first sub-jumper area 2051 is also configured to be in a long strip shape, so that the electrical connection between the first sub-jumper area 2051 and the fourth sub-jumper area 2054 can be facilitated, and the second sub-jumper area 2052 and the third sub-jumper area 2053 are both configured to be in a block shape, which not only facilitates the electrical connection operation at the first sub-jumper area 2051, but also improves the space utilization rate of the high-voltage power pad 201, making the layout of the high-voltage power pad 201 more reasonable.

[0070] Furthermore, a side of the high-voltage power pad 201 that is closer to the low-voltage power pad 202 in the first direction is at least partially provided with an avoidance gap 2016, and the first sub-jumper area 2051 is arranged in the avoidance gap 2016. In this way, not only can the first sub-jumper area 2051 be directly electrically connected to the fourth sub-jumper area 2054, making the electrical connection between the first sub-jumper area 2051 and the fourth sub-jumper area 2054 more stable and reliable, but also the space utilization rate of the power side substrate 20 can be improved, making the structural layout of the power side substrate 20 more compact, and the structural design of the intelligent power module 100 can be further optimized.

[0071] Combination Figure 1-4As shown, the gate pad 2014 of the insulated gate bipolar transistor 2012 is located on a side of the insulated gate bipolar transistor 2012 that is further away from the low voltage power pad 202 along the first direction; the gate pad 2014 of the insulated gate bipolar transistor 2012 is located on a side of the insulated gate bipolar transistor 2012 that is closer to the driving circuit board 10 along the second direction.

[0072] Specifically, due to the layout positions of the driving chip 101 and the high-voltage power chip 2011, the gate pad 2014 of the insulated gate bipolar transistor 2012 is arranged on a side of the insulated gate bipolar transistor 2012 that is farther away from the low-voltage power pad 202 along the first direction, and the gate pad 2014 of the insulated gate bipolar transistor 2012 is arranged on a side of the insulated gate bipolar transistor 2012 that is closer to the driving circuit board 10 along the second direction. This can facilitate the electrical connection between the gate pad 2014 of the insulated gate bipolar transistor 2012 and the high-voltage output transfer pad 102 on the driving chip 101.

[0073] Combination Figure 1-4 As shown, the three high-voltage output pads and the three voltage source pads on the driver chip 101 together constitute three pad groups, each pad group includes a high-voltage output pad and a voltage source pad spaced apart from each other, the three high-voltage output transfer pads 102 and the three voltage source transfer pads 103 together constitute three transfer pad groups, each transfer pad group includes a high-voltage output transfer pad 102 and a voltage source transfer pad 103 spaced apart from each other in a first direction, the three transfer pad groups correspond to the three pad groups one by one, and the three high-voltage power chips 2011 correspond to the three transfer pad groups one by one; the three transfer pad groups are spaced apart in the first direction, and in each pad group, the high-voltage output transfer pad 102 is spaced apart from the voltage source pad 103. The source transfer pad 103 is further away from the low-voltage power pad 202 in the first direction; the three pad groups include a first pad group, a second pad group and a third pad group, the first pad group and the second pad group are arranged on the side of the driving chip 101 adjacent to the power side substrate 20 in the second direction, the first pad group and the second pad group are spaced apart in the first direction, in the first pad group and the second pad group, the high-voltage output pad is further away from the low-voltage power pad 202 in the first direction than the voltage source pad; the third pad group is located on the side of the driving chip 101 that is further away from the low-voltage power pad 202 in the first direction, and in the third pad group, the high-voltage output pad is further away from the power side substrate 20 in the second direction than the voltage source pad.

[0074] Specifically, each pad group includes a high-voltage output pad and a voltage source pad spaced apart from each other, and each transfer pad group includes a high-voltage output transfer pad 102 and a voltage source transfer pad 103 spaced apart from each other in a first direction. By making the three transfer pad groups correspond one-to-one with the three pad groups, and the three high-voltage power chips 2011 correspond one-to-one with the three transfer pad groups, the pins of the driver chip 101 can be electrically connected to the high-voltage power chip 2011 through the transfer pad groups, the structural design of the intelligent power module 100 can be optimized, and the electrical connection between the driver chip 101 and the high-voltage power chip 2011 can be facilitated.

[0075] Furthermore, the gate pad 2014 of the insulated gate bipolar transistor 2012 is arranged on a side of the insulated gate bipolar transistor 2012 that is farther away from the low voltage power pad 202 along the first direction, and the gate pad 2014 of the insulated gate bipolar transistor 2012 is arranged on a side of the insulated gate bipolar transistor 2012 that is closer to the driving circuit board 10 along the second direction. Therefore, the high-voltage output transfer pad 102 in each transfer pad group is arranged farther away from the low voltage power pad 202 in the first direction compared to the voltage source transfer pad 103. This can further facilitate the electrical connection between the transfer pad group and the high voltage power chip 2011, and can further optimize the structural design of the intelligent power module 100.

[0076] Furthermore, the third pad group is located on a side of the driver chip 101 that is further away from the low-voltage power pad 202 in the first direction. In the third pad group, the high-voltage output pad is further away from the power side substrate 20 in the second direction than the voltage source pad. This can not only improve the utilization rate of the space around the driver chip 101, make the layout of the pad group more reasonable, and make the structural layout on the driver circuit board 10 more neat and clear, but also reduce the wiring difficulty on the driver circuit board 10, and can further optimize the structural design of the intelligent power module 100.

[0077] The electronic device according to the present invention may mainly include: the above-mentioned intelligent power module 100. Applying the above-mentioned intelligent power module 100 to the electronic device can improve the versatility of the electronic device.

[0078] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0079] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0080] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An intelligent power module, characterized in that: include: Encapsulation body (40); A driving circuit board (10), wherein a driving chip (101) is arranged on the driving circuit board (10); A power-side substrate (20), the power-side substrate (20) being arranged in the packaging body (40) and spaced apart from the driving circuit board (10) in the second direction, the power-side substrate (20) being provided with a high-voltage power pad (201) and a low-voltage power pad (202) spaced apart in the first direction, and the high-voltage power pad (201) being provided with three high-voltage power chips (2011) spaced apart in the first direction; A power pin (30), the power pin (30) being arranged in a package body (40) and located on a side of the power side substrate (20) in a second direction away from the driving circuit board (10), the power pin (30) comprising a high-voltage power pin (301) and a low-voltage power pin (302) arranged at intervals in a first direction, the high-voltage power pins (301) being three, and the three high-voltage power pins (301) being arranged at intervals in the first direction; Each of the high-voltage power chips (2011) comprises an insulated gate bipolar transistor (2012) and a fast recovery diode (2013) arranged at intervals in the second direction, the insulated gate bipolar transistor (2012) being provided with a gate pad (2014) and an emitter pad (2015), in each of the high-voltage power chips (2011), compared with the fast recovery diode (2013), the insulated gate bipolar transistor (2012) is closer to the driving circuit board (10) in the second direction, the emitter pads (2015) on the three insulated gate bipolar transistors (2012) are electrically connected to the three fast recovery diodes (2013) in a one-to-one correspondence, and the three fast recovery diodes (2013) are electrically connected to the three high-voltage power pins (301) in a one-to-one correspondence; One of the driver chips (101) is arranged in the middle of the driver circuit board (10); the projections of the three high-voltage power chips (2011) in the second direction are arranged at intervals from the projections of the driver chip (101) in the second direction and are located on a side away from the low-voltage power pad (202) in the first direction; three high-voltage output pads and three voltage source pads are arranged on one of the driver chips (101); three high-voltage output transfer pads (102) and three voltage source transfer pads (103) are arranged on the driver circuit board (10); and the three high-voltage output transfer pads (10 2) and the three voltage source transfer pads (103) are all arranged at intervals on the side of the driver chip (101) facing the power side substrate (20) in the second direction, and the projections of the three high-voltage output transfer pads (102) and the three voltage source transfer pads (103) in the second direction are all arranged at intervals on the side of the projection of the driver chip (101) in the second direction away from the low-voltage power pad (202) in the first direction, and the three high-voltage output transfer pads (102) and the three voltage source transfer pads (103) correspond to the three high-voltage power chips (2011) in the second direction; The three high-voltage output pads on the driver chip (101) and the three high-voltage output transfer pads (102) are electrically connected in a one-to-one correspondence, and the three voltage source pads on the driver chip (101) and the three voltage source transfer pads (103) are electrically connected in a one-to-one correspondence; The three high-voltage output transfer pads (102) are electrically connected to the gate pads (2014) on the three insulated gate bipolar transistors (2012) in a one-to-one correspondence; The power side substrate (20) is provided with three first jumper areas (203) and three second jumper areas (204); the three first jumper areas (203) are selectively and simultaneously electrically connected to the three fast recovery diodes (2013) in a one-to-one correspondence; the three first jumper areas (203) are selectively and simultaneously electrically connected to the three high-voltage power pins (301) in a one-to-one correspondence; the three second jumper areas (204) are selectively and simultaneously electrically connected to the three first jumper areas (203); the three voltage source transfer pads (103) are selectively and simultaneously electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012); and the three voltage source transfer pads (103) are selectively and simultaneously electrically connected to the three second jumper areas (204).

2. The intelligent power module according to claim 1, characterized in that: When the three first jumper areas (203) are electrically connected to the three high-voltage power pins (301) in a one-to-one correspondence at the same time, the three first jumper areas (203) are not electrically connected to the three fast recovery diodes (2013), the three voltage source transfer pads (103) are not electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012), the three second jumper areas (204) are electrically connected to the three first jumper areas (203) in a one-to-one correspondence at the same time, and the three voltage source transfer pads (103) are electrically connected to the three second jumper areas (204) in a one-to-one correspondence at the same time.

3. The intelligent power module according to claim 2, characterized in that: The current between the driving chip (101) and the high-voltage power chip (2011) in the package (40) is set to I1, and I1 satisfies the relationship: I1<20A.

4. The intelligent power module according to claim 1, characterized in that: When the three voltage source transfer pads (103) are electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012) in a one-to-one correspondence, the three first jumper areas (203) are not electrically connected to the three fast recovery diodes (2013), the three first jumper areas (203) are not electrically connected to the three high-voltage power pins (301), the three second jumper areas (204) are not electrically connected to the three first jumper areas (203), and the three voltage source transfer pads (103) are not electrically connected to the three second jumper areas (204).

5. The intelligent power module according to claim 4, characterized in that: The current between the driving chip (101) and the high-voltage power chip (2011) in the package (40) is set to I2, and I2 satisfies the relationship: 30A<I2≤50A.

6. The intelligent power module according to claim 1, characterized in that: When the three first jumper areas (203) are electrically connected to the three fast recovery diodes (2013) in a one-to-one correspondence at the same time, the three first jumper areas (203) are not electrically connected to the three high-voltage power pins (301), the three second jumper areas (204) are electrically connected to the three first jumper areas (203) in a one-to-one correspondence at the same time, the three voltage source transfer pads (103) are electrically connected to the three second jumper areas (204) in a one-to-one correspondence at the same time, and the three voltage source transfer pads (103) are not electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012).

7. The intelligent power module according to claim 6, characterized in that: The current between the driving chip (101) and the high-voltage power chip (2011) in the package (40) is set to I3, and I3 satisfies the relationship: 20A≤I3<30A.

8. The intelligent power module according to claim 1, characterized in that: The three first jumper areas (203) are respectively a first sub-jumper area (2051), a second sub-jumper area (2052) and a third sub-jumper area (2053); the three high-voltage power chips (2011) are respectively a first high-voltage power chip (20111), a second high-voltage power chip (20112) and a third high-voltage power chip (20113); compared with the second high-voltage power chip (20112) and the third high-voltage power chip (20113), the first high-voltage power chip (20111) is closer to the low-voltage power pad (202) in the first direction; the second high-voltage power chip (20112) is spaced between the first high-voltage power chip (20111) and the second high-voltage power chip (20112) in the first direction; The first sub-jumper area (2051) is arranged between the first high-voltage power chip (20111) and the low-voltage power pad (202) in the first direction, the projection of the second sub-jumper area (2052) in the second direction is set as the projection of the second sub-jumper area (2052), the projection of the third sub-jumper area (2053) in the second direction is set as the projection of the third sub-jumper area (2053), the projection of the first high-voltage power chip (20111) in the second direction is set as the projection of the first high-voltage power chip (20111), the projection of the second high-voltage power chip (20112) in the second direction is set as the projection of the second high-voltage power chip (20112), and the projection of the third high-voltage power chip (20113) in the second direction is set as the projection of the third high-voltage power chip (20113); The center of the projection of the second sub-jumper area (2052) is located between the projection of the first high-voltage power chip (20111) and the projection of the second high-voltage power chip (20112) in the first direction, and the center of the projection of the third sub-jumper area (2053) is located between the projection of the second high-voltage power chip (20112) and the projection of the third high-voltage power chip (20113) in the first direction.

9. The intelligent power module according to claim 8, characterized in that: The projection of the second sub-jumper area (2052) at least partially overlaps with the projection of the first high-voltage power chip (20111), and the projection of the second sub-jumper area (2052) at least partially overlaps with the projection of the second high-voltage power chip (20112); The projection of the third sub-jumper area (2053) at least partially overlaps with the projection of the second high-voltage power chip (20112), and the projection of the third sub-jumper area (2053) at least partially overlaps with the projection of the third high-voltage power chip (20113).

10. The intelligent power module according to claim 9, characterized in that: The second sub-jumper area (2052) is spaced apart from the insulated gate bipolar transistor (2012) and the fast recovery diode (2013) of the first high-voltage power chip (20111) in a second direction, and the second sub-jumper area (2052) is spaced apart from the insulated gate bipolar transistor (2012) and the fast recovery diode (2013) of the second high-voltage power chip (20112) in a second direction; The third sub-jump line area (2053) is spaced apart from the insulated gate bipolar transistor (2012) and the fast recovery diode (2013) of the second high-voltage power chip (20112) in the second direction, and the third sub-jump line area (2053) is spaced apart from the insulated gate bipolar transistor (2012) and the fast recovery diode (2013) of the third high-voltage power chip (20113) in the second direction.

11. The intelligent power module according to claim 10, characterized in that: The three second jumper areas (204) are arranged in one-to-one correspondence with the three high-voltage power chips (2011), and the second jumper areas (204) are arranged at intervals on a side of the high-voltage power chip (2011) facing the driving circuit board (10) in the second direction.

12. The intelligent power module according to claim 11, characterized in that: The three second jumper areas (204) are respectively a fourth sub-jumper area (2054), a fifth sub-jumper area (2055) and a sixth sub-jumper area (2056); compared with the fifth sub-jumper area (2055) and the sixth sub-jumper area (2056), the fourth sub-jumper area (2054) is closer to the low-voltage power pad (202) in the first direction, and the fifth sub-jumper area (2055) is arranged between the fourth sub-jumper area (2054) and the sixth sub-jumper area (2056) in the first direction; The fourth sub-jumper area (2054), the fifth sub-jumper area (2055) and the sixth sub-jumper area (2056) are located on the drive side substrate and are spaced apart from the high voltage driving pad in the second direction, the first sub-jumper area (2051) is located on the drive side substrate and is spaced apart from the high voltage driving pad in the first direction, and the first sub-jumper area (2051) is connected to the fourth sub-jumper area (2054); The second sub-jump area (2052) and the third sub-jump area (2053) are both located on the high-voltage driving pad, the second sub-jump area (2052) and the fifth sub-jump area (2055) are spaced apart in the second direction, and the third sub-jump area (2053) and the sixth sub-jump area (2056) are spaced apart in the second direction.

13. The intelligent power module according to claim 12, characterized in that: The fourth sub-jumper area (2054), the fifth sub-jumper area (2055) and the sixth sub-jumper area (2056) are all in the shape of long strips and are extended in the first direction; The first sub-jumper area (2051) is in the shape of an elongated strip and is extended in the second direction, the second sub-jumper area (2052) and the third sub-jumper area (2053) are both in the shape of a block, and a side of the high-voltage power pad (201) that is closer to the low-voltage power pad (202) in the first direction is at least partially provided with an avoidance gap (2016), and the first sub-jumper area (2051) is arranged in the avoidance gap (2016).

14. The intelligent power module according to claim 1, characterized in that: The gate pad (2014) of the insulated gate bipolar transistor (2012) is located on a side of the insulated gate bipolar transistor (2012) that is further away from the low-voltage power pad (202) along the first direction; The gate pad (2014) of the insulated gate bipolar transistor (2012) is located on a side of the insulated gate bipolar transistor (2012) that is closer to the driving circuit board (10) along the second direction.

15. The intelligent power module according to claim 14, characterized in that: The three high-voltage output pads and the three voltage source pads on the driver chip (101) together form three pad groups, each pad group includes one high-voltage output pad and one voltage source pad spaced apart from each other, the three high-voltage output transfer pads (102) and the three voltage source transfer pads (103) together form three transfer pad groups, each transfer pad group includes one high-voltage output transfer pad (102) and one voltage source transfer pad (103) spaced apart from each other in a first direction, the three transfer pad groups correspond one-to-one to the three pad groups, and the three high-voltage power chips (2011) correspond one-to-one to the three transfer pad groups; The three transfer pad groups are arranged at intervals in the first direction, and in each of the pad groups, the high-voltage output transfer pad (102) is farther away from the low-voltage power pad (202) in the first direction than the voltage source transfer pad (103); The three pad groups include a first pad group, a second pad group and a third pad group, the first pad group and the second pad group are arranged on a side of the driver chip (101) adjacent to the power side substrate (20) in the second direction, the first pad group and the second pad group are arranged at intervals in the first direction, and in the first pad group and the second pad group, the high-voltage output pad is farther away from the low-voltage power pad (202) in the first direction than the voltage source pad; The third pad group is located on a side of the driver chip (101) that is further away from the low-voltage power pad (202) in the first direction, and in the third pad group, the high-voltage output pad is further away from the power-side substrate (20) than the voltage source pad in the second direction.

16. An electronic device, characterized in that: The intelligent power module (100) comprises any one of claims 1-15.

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