Intelligent power module and electronic equipment

Abstract

The invention discloses an intelligent power module and electronic equipment. The intelligent power module comprises a packaging body; a drive-side frame; a power side substrate; a power pin; the three second jumper regions are selectively and simultaneously electrically connected with the three first jumper regions in a one-to-one correspondence manner, the three voltage source pins are selectively and simultaneously electrically connected with emitter pads on the three insulated gate bipolar transistors in a one-to-one correspondence manner, and the three voltage source pins are selectively and simultaneously electrically connected with the three second jumper regions in a one-to-one correspondence manner. Therefore, the length of the electric connection between the high-side driving chip and the high-side power chip can be selectively adjusted according to the magnitude of the current between the high-side driving chip and the high-side power chip so as to change the gate-emitter inductance of the high-side power chip, so that the switching loss and the peak voltage of the high-side power chip can be relatively balanced; and the two are in a relatively excellent range, so that the performance of the intelligent power module can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an intelligent power module and electronic equipment. Background Art

[0002] When designing intelligent power module products with different current specifications in the same series, chips with different current specifications are usually adapted in the same frame layout structure, so as to form intelligent power module products with different current specifications under a certain series while reducing costs.

[0003] In the prior art, the wiring method between the driver chip and the power chip in the same frame layout structure is single. When the current specifications of the power chips are different, it will lead to the inability to achieve a relative balance between the switching loss and the peak voltage of the power chip. Often, only one side's value can be within a better range, which will make the performance of the intelligent power module poor. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide an intelligent power module, which has good performance.

[0005] The present invention further provides an electronic device.

[0006] According to an embodiment of the present invention, an intelligent power module comprises: a package body; a drive side frame, the drive side frame is arranged in the package body, and the drive side frame is provided with high-voltage drive pads and low-voltage drive pads spaced apart in a first direction, the low-voltage drive pad is one, and a low-voltage drive chip is arranged on each low-voltage drive pad, and the high-voltage drive pads are three, and the three high-voltage drive pads are spaced apart in the first direction; a power side substrate, the power side substrate is arranged in the package body and spaced apart from the drive side frame in a second direction, the power side substrate is provided with high-voltage power pads and low-voltage power pads spaced apart in the first direction, and the high-voltage power pads are provided with three first-direction power pads. A high-voltage power chip spaced apart in the first direction; a power pin, wherein the power pin is arranged in the package body and is located on the side of the power-side substrate away from the drive-side frame in the second direction, the power pin comprises a high-voltage power pin and a low-voltage power pin spaced apart in the first direction, the number of the high-voltage power pins is three, and the three high-voltage power pins are spaced apart in the first direction; each of the high-voltage power chips comprises an insulated gate bipolar transistor and a fast recovery diode spaced apart in the second direction, the insulated gate bipolar transistor is provided with a gate pad and an emitter pad, and in each of the high-voltage power chips, the insulated gate bipolar transistor is closer to the drive-side frame in the second direction than the fast recovery diode. The frame is provided with a first-side frame, the emitter pads on the three insulated gate bipolar transistors are electrically connected to the three fast recovery diodes in a one-to-one correspondence, and the three fast recovery diodes are electrically connected to the three high-voltage power pins in a one-to-one correspondence; a high-voltage driving chip is respectively arranged on the three high-voltage driving pads, and each of the high-voltage driving chips is provided with a high-voltage output pad and a voltage source pad, and the driving side frame is provided with three high-voltage output pins and three voltage source pins, and the three high-voltage output pins are electrically connected to the high-voltage output pads on the three high-voltage driving chips in a one-to-one correspondence, and the three voltage source pins are electrically connected to the voltage source pads on the three high-voltage driving chips in a one-to-one correspondence, and the three high-voltage driving chips are electrically connected to the three high-voltage driving chips in a one-to-one correspondence. The voltage output pin is electrically connected to the gate pads on the three insulated gate bipolar transistors in a one-to-one correspondence; three first jumper areas and three second jumper areas are arranged on the power side substrate, the three first jumper areas are selectively and simultaneously electrically connected to the three fast recovery diodes in a one-to-one correspondence, the three first jumper areas are selectively and simultaneously electrically connected to the three high-voltage power pins in a one-to-one correspondence, the three second jumper areas are selectively and simultaneously electrically connected to the three first jumper areas in a one-to-one correspondence, the three voltage source pins are selectively and simultaneously electrically connected to the emitter pads on the three insulated gate bipolar transistors in a one-to-one correspondence, and the three voltage source pins are selectively and simultaneously electrically connected to the three second jumper areas in a one-to-one correspondence.

[0007] Therefore, the length of the electrical connection between the high-side driver chip and the high-side power chip can be selectively adjusted according to the current between the high-side driver chip and the high-side power chip to change the gate-emitter inductance of the high-side power chip. This can achieve a relative balance between the switching loss and the peak voltage of the high-side power chip, so that both are within a relatively optimal range, which can improve the performance of the intelligent power module.

[0008] In some examples of the present invention, when the three first jumper areas are electrically connected to the three high-voltage power pins in a one-to-one correspondence at the same time, the three first jumper areas are not electrically connected to the three fast recovery diodes, the three voltage source pins are not electrically connected to the emitter pads on the three insulated gate bipolar transistors, the three second jumper areas are electrically connected to the three first jumper areas in a one-to-one correspondence at the same time, and the three voltage source pins are electrically connected to the three second jumper areas in a one-to-one correspondence at the same time.

[0009] In some examples of the present invention, the current between the high-voltage driver chip and the high-voltage power chip in the package is set to I1, and I1 satisfies the relationship: I1<20A.

[0010] In some examples of the present invention, when the three voltage source pins are electrically connected one-to-one with the emitter pads on the three insulated gate bipolar transistors, there is no electrical connection between the three first jumper areas and the three fast recovery diodes, there is no electrical connection between the three first jumper areas and the three high-voltage power pins, there is no electrical connection between the three second jumper areas and the three first jumper areas, and there is no electrical connection between the three voltage source pins and the three second jumper areas.

[0011] In some examples of the present invention, the current between the high-voltage driver chip and the high-voltage power chip in the package is set to I2, and I2 satisfies the relationship: 30A<I2≤50A.

[0012] In some examples of the present invention, when the three first jumper areas are electrically connected one-to-one with the three fast recovery diodes at the same time, the three first jumper areas are not electrically connected to the three high-voltage power pins, the three second jumper areas are electrically connected one-to-one with the three first jumper areas at the same time, the three voltage source pins are electrically connected one-to-one with the three second jumper areas at the same time, and the three voltage source pins are not electrically connected to the emitter pads on the three insulated gate bipolar transistors.

[0013] In some examples of the present invention, the current between the high-voltage driver chip and the high-voltage power chip in the package is set to I3, and I3 satisfies the relationship: 20A≤I3<30A.

[0014] In some examples of the present invention, the three first jumper areas are respectively a first sub-jumper area, a second sub-jumper area and a third sub-jumper area, the three high-voltage power chips are respectively a first high-voltage power chip, a second high-voltage power chip and a third high-voltage power chip, compared with the second high-voltage power chip and the third high-voltage power chip, the first high-voltage power chip is closer to the low-voltage power pad in the first direction, and the second high-voltage power chip is spaced between the first high-voltage power chip and the second high-voltage power chip in the first direction; the first sub-jumper area is spaced between the first high-voltage power chip and the low-voltage power pad in the first direction, and the second sub-jumper area is set in the second direction The projection on the second sub-jumper area is set as the projection of the second sub-jumper area, the projection of the third sub-jumper area in the second direction is set as the projection of the third sub-jumper area, the projection of the first high-voltage power chip in the second direction is set as the projection of the first high-voltage power chip, the projection of the second high-voltage power chip in the second direction is set as the projection of the second high-voltage power chip, and the projection of the third high-voltage power chip in the second direction is set as the projection of the third high-voltage power chip; the center of the projection of the second sub-jumper area is located between the projection of the first high-voltage power chip and the projection of the second high-voltage power chip in the first direction, and the center of the projection of the third sub-jumper area is located between the projection of the second high-voltage power chip and the projection of the third high-voltage power chip in the first direction.

[0015] In some examples of the present invention, the second sub-jump area is spaced apart between the fast recovery diode of the first high-voltage power chip and the fast recovery diode of the second high-voltage power chip in the first direction.

[0016] In some examples of the present invention, a side of the high-voltage power pad that is closer to the low-voltage power pad in the first direction is at least partially protruded toward the low-voltage power pad to form a protrusion, and the fast recovery diode of the first high-voltage power chip is correspondingly arranged at the protrusion, and a jumper area accommodating space is formed between the fast recovery diode of the first high-voltage power chip and the fast recovery diode of the second high-voltage power chip, and the second sub-jumper area is arranged in the jumper area accommodating space.

[0017] In some examples of the present invention, the third sub-jumper area is spaced apart and arranged on a side of the fast recovery diode of the third high-voltage power chip that is away from the low-voltage power pad in the first direction, and the fast recovery diode of the third high-voltage power chip is protruded relative to the fast recovery diode of the second high-voltage power chip on a side that is away from the driving side frame in the second direction, and the third sub-jumper area is spaced apart and arranged on a side of the fast recovery diode of the third high-voltage power chip that is toward the driving side frame in the second direction.

[0018] In some examples of the present invention, three of the second jumper areas are arranged in one-to-one correspondence with the three high-voltage power chips, and the second jumper areas are arranged at intervals on a side of the high-voltage power chip in a second direction toward the driving side frame.

[0019] In some examples of the present invention, the three second jumper areas are respectively a fourth sub-jumper area, a fifth sub-jumper area and a sixth sub-jumper area. Compared with the fifth sub-jumper area and the sixth sub-jumper area, the fourth sub-jumper area is closer to the low-voltage power pad in the first direction, and the fifth sub-jumper area is spaced between the fourth sub-jumper area and the sixth sub-jumper area in the first direction; the fourth sub-jumper area, the fifth sub-jumper area and the sixth sub-jumper area are located on the driving side substrate and are spaced from the high-voltage drive pad in the second direction, the first sub-jumper area is located on the driving side substrate and is spaced from the high-voltage drive pad in the first direction, and the first sub-jumper area is connected to the fourth sub-jumper area; the second sub-jumper area and the third sub-jumper area are both located on the high-voltage drive pad, the second sub-jumper area and the fifth sub-jumper area are spaced from each other in the second direction, and the third sub-jumper area and the sixth sub-jumper area are spaced from each other in the second direction.

[0020] In some examples of the present invention, the fourth sub-jump area, the fifth sub-jump area and the sixth sub-jump area are all in the shape of long strips and extend in the first direction; the first sub-jump area is in the shape of long strips and extend in the second direction, the second sub-jump area and the third sub-jump area are both block-shaped, and a side of the high-voltage power pad that is closer to the low-voltage power pad in the first direction is at least partially protruded toward the low-voltage power pad to form a protrusion, the fast recovery diode of the first high-voltage power chip is correspondingly arranged at the protrusion, the first sub-jump area is spaced above the protrusion, and a side of the first sub-jump area that is adjacent to the low-voltage power pad in the first direction is flush with a side of the protrusion that is adjacent to the low-voltage power pad in the first direction.

[0021] In some examples of the present invention, the gate pad of the insulated gate bipolar transistor is located on a side of the insulated gate bipolar transistor that is closer to the driving side frame along the second direction; the gate pad of the insulated gate bipolar transistor is located in the middle of the insulated gate bipolar transistor in the first direction.

[0022] In some examples of the present invention, the three high-voltage drive pads are respectively a first high-voltage drive pad, a second high-voltage drive pad and a third high-voltage drive pad. Compared with the second high-voltage drive pad and the third high-voltage drive pad, the first high-voltage drive pad is closer to the low-voltage drive pad in the first direction, and the second high-voltage drive pad is spaced between the first high-voltage drive pad and the third high-voltage drive pad in the first direction; the three voltage source pins are respectively a first voltage source pin, a second voltage source pin and a third voltage source pin, and the three high-voltage output pins are respectively a first high-voltage output pin, a second high-voltage output pin and a third high-voltage output pin, the first voltage source pin and the first high-voltage output pin are arranged between the first high-voltage drive pad and the second high-voltage drive pad, the second voltage source pin and the second high-voltage output pin are arranged between the second high-voltage drive pad and the third high-voltage drive pad, and the third voltage source pin and the third high-voltage output pin are spaced on the side of the third high-voltage drive pad away from the second high-voltage drive pad in the first direction.

[0023] In some examples of the present invention, the first high-voltage output pin, the second high-voltage output pin and the third high-voltage output pin each include a first pin portion and a second pin portion, the first pin portion is extended in the first direction and is electrically connected to the high-voltage output pad, the second pin portion is arranged on a side of the first pin portion that is further away from the power substrate in the second direction and is extended in the second direction, and one end of the second pin portion that is further away from the power substrate in the second direction is suitable for being electrically connected to the outside; the first voltage source pin, the second voltage source pin and the third voltage source pin each include a third pin portion, a fourth pin portion and a fifth pin portion, and in each of the voltage source pins, the third pin portion and the fifth pin portion are both extended in the second direction. , compared with the fifth pin portion, the third pin portion is arranged closer to the low-voltage drive pad in the first direction, the fifth pin portion is suitable for being electrically connected to the outside, the high-voltage drive pad is spaced apart at a side of the corresponding third pin portion away from the power substrate in the second direction, the voltage source pad is electrically connected to the third pin portion, the fourth pin portion is extended in the first direction, the first end of the fourth pin portion is connected to an end of the third pin portion adjacent to the power substrate in the second direction, and the second end of the fourth pin portion is connected to an end of the fifth pin portion adjacent to the power substrate in the second direction; the third pin portion, the fourth pin portion and the fifth pin portion jointly define an avoidance groove, and the first pin portion is arranged in the avoidance groove.

[0024] In some examples of the present invention, the three high-voltage output pads and the three voltage source pads on the high-voltage driver chip together form three pad groups, each pad group includes one high-voltage output pad and one voltage source pad spaced apart from each other, the three pad groups and the three high-voltage power chips are arranged in one-to-one correspondence, and the high-voltage output pad in each pad group is farther away from the low-voltage power pad in the first direction than the voltage source pad.

[0025] An electronic device according to an embodiment of the present invention includes: the above-mentioned intelligent power module.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1 is a schematic diagram of an intelligent power module according to a first embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of an intelligent power module according to a second embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of an intelligent power module according to a second embodiment of the present invention;

[0031] Figure 4 FIG. 4 is a schematic diagram of an intelligent power module according to a third embodiment of the present invention.

[0032] Reference numerals:

[0033] 100. Intelligent power module;

[0034] 10. Drive side frame; 101. High voltage drive pad; 102. Low voltage drive pad; 103. High voltage output pin; 104. Voltage source pin;

[0035] 1011, high-voltage driving chip; 1012, first high-voltage driving pad; 1013, second high-voltage driving pad; 1014, third high-voltage driving pad;

[0036] 1021, low voltage driver chip;

[0037] 1031, a first high-voltage output pin; 1032, a second high-voltage output pin; 1033, a third high-voltage output pin; 1034, a first pin portion; 1035, a second pin portion;

[0038] 1041, a first voltage source pin; 1042, a second voltage source pin; 1043, a third voltage source pin; 1044, a third pin portion; 1045, a fourth pin portion; 1046, a fifth pin portion;

[0039] 20. Power side substrate; 201. High voltage power pad; 202. Low voltage power pad; 203. First jumper area; 204. Second jumper area;

[0040] 2011, high-voltage power chip; 2012, insulated gate bipolar transistor; 2013, fast recovery diode; 2014, gate pad; 2015, emitter pad; 2016, avoidance gap;

[0041] 20111, a first high-voltage power chip; 20112, a second high-voltage power chip; 20113, a third high-voltage power chip;

[0042] 2051, a first sub-jumping area; 2052, a second sub-jumping area; 2053, a third sub-jumping area; 2054, a fourth sub-jumping area; 2055, a fifth sub-jumping area; 2056, a sixth sub-jumping area;

[0043] 30, power pin; 301, high voltage power pin; 302, low voltage power pin;

[0044] 40. Encapsulation body;

[0045] 50. Avoidance groove. DETAILED DESCRIPTION

[0046] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0047] Reference below Figure 1-Figure 4 The intelligent power module 100 according to the embodiment of the present invention is described. The intelligent power module 100 can be applied to electronic devices.

[0048] Combination Figure 1 and Figure 4As shown, the intelligent power module 100 according to the present invention may mainly include: a package body 40, a drive side frame 10, a power side substrate 20 and a power pin 30, wherein the drive side frame 10 is arranged in the package body 40, and the drive side frame 10 is provided with a high voltage driving pad 101 and a low voltage driving pad 102 arranged at intervals in a first direction, the low voltage driving pad 102 is one, and a low voltage driving chip 1021 is arranged on each low voltage driving pad 102, and the high voltage driving pad 101 is three, and the three high voltage driving pads 101 are arranged at intervals in the first direction; the power side substrate 20 is arranged in the package body 40 and is spaced apart from the power pin 30. The drive side frame 10 is arranged at intervals in the second direction, the power side substrate 20 is provided with high voltage power pads 201 and low voltage power pads 202 arranged at intervals in the first direction, and the high voltage power pads 201 are provided with three high voltage power chips 2011 arranged at intervals in the first direction; the power pins 30 are arranged in the package body 40 and are located on the side of the power side substrate 20 away from the drive side frame 10 in the second direction, the power pins 30 include high voltage power pins 301 and low voltage power pins 302 arranged at intervals in the first direction, there are three high voltage power pins 301, and the three high voltage power pins 301 are arranged at intervals in the first direction;

[0049] Each of the high-voltage power chips 2011 includes an insulated gate bipolar transistor 2012 and a fast recovery diode 2013 spaced apart in the second direction, a gate pad 2014 and an emitter pad 2015 are provided on the insulated gate bipolar transistor 2012, in each of the high-voltage power chips 2011, compared with the fast recovery diode 2013, the insulated gate bipolar transistor 2012 is closer to the drive side frame 10 in the second direction, the emitter pads 2015 on the three insulated gate bipolar transistors 2012 are electrically connected to the three fast recovery diodes 2013 in a one-to-one correspondence, and the three fast recovery diodes 2013 are electrically connected to the three high-voltage power pins 301 in a one-to-one correspondence; A high-voltage driving chip 1011 is respectively provided on the three high-voltage driving pads 101, and each of the high-voltage driving chips 1011 is provided with a high-voltage output pad and a voltage source pad. The driving side frame 10 is provided with three high-voltage output pins 103 and three voltage source pins 104. The three high-voltage output pins 103 are electrically connected to the high-voltage output pads on the three high-voltage driving chips 1011 in a one-to-one correspondence, and the three voltage source pins 104 are electrically connected to the voltage source pads on the three high-voltage driving chips 1011 in a one-to-one correspondence. The three high-voltage output pins 103 are electrically connected to the gate pads 2014 on the three insulated gate bipolar transistors 2012 in a one-to-one correspondence.

[0050] Three first jumper areas 203 and three second jumper areas 204 are provided on the power side substrate 20, the three first jumper areas 203 are selectively and simultaneously electrically connected to the three fast recovery diodes 2013 in one-to-one correspondence, the three first jumper areas 203 are selectively and simultaneously electrically connected to the three high-voltage power pins 301 in one-to-one correspondence, the three second jumper areas 204 are selectively and simultaneously electrically connected to the three first jumper areas 203 in one-to-one correspondence, the three voltage source pins 104 are selectively and simultaneously electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012 in one-to-one correspondence, and the three voltage source pins 104 are selectively and simultaneously electrically connected to the three second jumper areas 204 in one-to-one correspondence.

[0051] Specifically, first, the three high-voltage output pins 103 are electrically connected to the high-voltage output pads on the three high-voltage driver chips 1011 in a one-to-one correspondence, the three voltage source pins 104 are electrically connected to the voltage source pads on the three high-voltage driver chips 1011 in a one-to-one correspondence, and the three high-voltage output pins 103 are electrically connected to the gate pads 2014 on the three insulated gate bipolar transistors 2012 in a one-to-one correspondence. It should be noted that when the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the package body 40 is in different ranges, the above components are still electrically connected. In the embodiment of the present invention, , by selectively and simultaneously connecting the three first jumper areas 203 to the three fast recovery diodes 2013 in one-to-one correspondence, the three first jumper areas 203 to the three high-voltage power pins 301 in one-to-one correspondence, the three second jumper areas 204 to the three first jumper areas 203 in one-to-one correspondence, the three voltage source pins 104 to the three emitter pads 2015 on the insulated gate bipolar transistors 2012 in one-to-one correspondence, and the three voltage source pins 104 to the three second jumper areas 204 in one-to-one correspondence.

[0052] It should be noted that when the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 is smaller, the switching speed of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is faster, which will cause the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 to have a relatively large peak voltage when it is turned off. Since the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is proportional to the current level, the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is relatively small. At this time, it is necessary to balance the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off. Therefore, it can be achieved by increasing The length of the electrical connection line between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 is increased to increase the gate-emitter inductance of the high-voltage power chip 2011, thereby reducing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and further reducing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011. Although this reduces the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, which increases the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011 is relatively small at low currents, so that both the switching loss and the peak voltage can be within a relatively optimal range.

[0053] Similarly, when the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 is larger, the switching speed of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is slower, which will cause the peak voltage of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 to be relatively small when it is turned off. Since the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is proportional to the current level, the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 is relatively large. At this time, it is necessary to balance the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off. Therefore, the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 can be reduced by The length of the electrical connection line between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the power module 100 can be reduced to reduce the gate-emitter inductance of the high-voltage power chip 2011, thereby improving the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and further improving the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011. Although this improves the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011 and reduces the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, the switching loss of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011 is relatively large at high currents, so that both the switching loss and the peak voltage can be within a relatively optimal range.

[0054] Therefore, it can be understood that in the process of production and manufacturing, by selectively setting the electrical connection relationship between the first jumper area 203, the second jumper area 204, the fast recovery diode 2013, the high-voltage power pin 301, the voltage source pin 104 and the emitter pad 2015 on the insulated gate bipolar transistor 2012, the length of the electrical connection line between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 can be changed, thereby changing the size of the gate-emitter inductance of the high-voltage power chip 2011, thereby balancing the relationship between the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off when different current specifications are met, so that the switching loss of the insulated gate bipolar transistor 2012 in the high-voltage power chip 2011 and the peak voltage of the insulated gate bipolar transistor 2012 when it is turned off are both within a better range.

[0055] Therefore, the length of the electrical connection between the high-side driver chip and the high-side power chip can be selectively adjusted according to the current between the high-side driver chip and the high-side power chip to change the gate-emitter inductance of the high-side power chip. This can achieve a relative balance between the switching loss and the peak voltage of the high-side power chip, so that both are within a relatively optimal range, thereby improving the performance of the intelligent power module 100.

[0056] In some embodiments of the present invention, Figure 1 As shown, when the three first jumper areas 203 are electrically connected to the three high-voltage power pins 301 at the same time, the three first jumper areas 203 are not electrically connected to the three fast recovery diodes 2013, the three voltage source pins 104 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012, the three second jumper areas 204 are electrically connected to the three first jumper areas 203 at the same time, and the three voltage source pins 104 are electrically connected to the three second jumper areas 204 at the same time.

[0057] Specifically, when the three first jumper areas 203 are electrically connected to the three high-voltage power pins 301 in a one-to-one correspondence, the three second jumper areas 204 can be electrically connected to the three first jumper areas 203 in a one-to-one correspondence, and the three voltage source pins 104 are electrically connected to the three second jumper areas 204 in a one-to-one correspondence, and the three first jumper areas 203 are not electrically connected to the three fast recovery diodes 2013, and the three voltage source pins 104 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012. In this embodiment, the high-voltage driver chip 1011 The electrical connection method between the high-voltage power chip 2011 and the high-voltage power chip 2011 is suitable for the case of smaller current specifications. In this embodiment, the length of the electrical connection line between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 is longer, which can increase the gate-emitter inductance of the high-voltage power chip 2011, thereby reducing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, thereby reducing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and can make both the switching loss and the peak voltage within a relatively optimal range.

[0058] Combination Figure 1 As shown, the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the package body 40 is set to I1, and I1 satisfies the relationship: I1<20A. Specifically, in the first embodiment above, the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 is set within a reasonable smaller range, which can further optimize the balance between the switching loss and the peak voltage, thereby further optimizing the performance of the intelligent power module 100.

[0059] In other embodiments of the present invention, Figure 2 As shown, when the three voltage source pins 104 are electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012 one by one, there is no electrical connection between the three first jumper areas 203 and the three fast recovery diodes 2013, there is no electrical connection between the three first jumper areas 203 and the three high-voltage power pins 301, there is no electrical connection between the three second jumper areas 204 and the three first jumper areas 203, and there is no electrical connection between the three voltage source pins 104 and the three second jumper areas 204.

[0060] Specifically, when the three voltage source pins 104 are electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012 in a one-to-one correspondence, the three first jumper areas 203 are not electrically connected to the three high-voltage power pins 301, the three second jumper areas 204 are not electrically connected to the three first jumper areas 203, and the three voltage source pins 104 are not electrically connected to the three second jumper areas 204. In this embodiment, the high-voltage driver chip 1011 and the high-voltage power chip 301 are not electrically connected. The electrical connection method between 2011 is suitable for situations with larger current specifications. In this embodiment, the length of the electrical connection line between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 is relatively short, which can reduce the gate-emitter inductance of the high-voltage power chip 2011, thereby increasing the switching speed of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, thereby increasing the peak voltage of the insulated gate bipolar transistor 2012 of the high-voltage power chip 2011, and can make both the switching loss and the peak voltage within a relatively optimal range.

[0061] Combination Figure 2 As shown, the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the package body 40 is set to I2, and I2 satisfies the relationship: 30A<I2≤50A. Specifically, in the above second embodiment, the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 is set within a reasonable and large range, which can further optimize the balance between the switching loss and the peak voltage, thereby further optimizing the performance of the intelligent power module 100.

[0062] In some embodiments of the present invention, Figure 4As shown, when the three first jumper areas 203 are electrically connected to the three fast recovery diodes 2013 in a one-to-one correspondence at the same time, the three first jumper areas 203 are not electrically connected to the three high-voltage power pins 301, the three second jumper areas 204 are electrically connected to the three first jumper areas 203 in a one-to-one correspondence at the same time, the three voltage source pins 104 are electrically connected to the three second jumper areas 204 in a one-to-one correspondence at the same time, and the three voltage source pins 104 are not electrically connected to the emitter pads 2015 on the three insulated gate bipolar transistors 2012.

[0063] Specifically, when the three first jumper areas 203 are electrically connected to the three fast recovery diodes 2013 in a one-to-one correspondence at the same time, the three second jumper areas 204 are electrically connected to the three first jumper areas 203 in a one-to-one correspondence at the same time, and the three voltage source pins 104 are electrically connected to the three second jumper areas 204 in a one-to-one correspondence at the same time, so that the three first jumper areas 203 and the three high-voltage power pins 301 are not electrically connected, and the three voltage source pins 104 and the emitter pads 2015 on the three insulated gate bipolar transistors 2012 are not electrically connected. The electrical connection method between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in this embodiment is suitable for the case where the current specification is moderate. In this embodiment, the length of the electrical connection line between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the intelligent power module 100 is moderate, so that the switching loss and the peak voltage will not be too large or too small, and both the switching loss and the peak voltage can be within a relatively optimal range.

[0064] Combination Figure 4 As shown, the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 in the package body 40 is set to I3, and I3 satisfies the relationship: 20A≤I3<30A. Specifically, in the third embodiment, the current between the high-voltage driver chip 1011 and the high-voltage power chip 2011 is set within a reasonable and moderate range, which can further optimize the balance between the switching loss and the peak voltage, thereby further optimizing the performance of the intelligent power module 100.

[0065] Combination Figure 1-Figure 4As shown, the three first jumper areas 203 are respectively the first sub-jumper area 2051, the second sub-jumper area 2052 and the third sub-jumper area 2053, the three high-voltage power chips 2011 are respectively the first high-voltage power chip 20111, the second high-voltage power chip 20112 and the third high-voltage power chip 20113, compared with the second high-voltage power chip 20112 and the third high-voltage power chip 20113, the first high-voltage power chip 20111 is closer to the low-voltage power pad 202 in the first direction, the second high-voltage power chip 20112 is spaced between the first high-voltage power chip 20111 and the second high-voltage power chip 20112 in the first direction, the first sub-jumper area 2051 is spaced between the first high-voltage power chip 20111 and the low-voltage power pad 202 in the first direction, and the second sub-jumper area 2052 is set in the second The projection in the second direction is set as the projection of the second sub-jumper area 2052, the projection of the third sub-jumper area 2053 in the second direction is set as the projection of the third sub-jumper area 2053, the projection of the first high-voltage power chip 20111 in the second direction is set as the projection of the first high-voltage power chip 20111, the projection of the second high-voltage power chip 20112 in the second direction is set as the projection of the second high-voltage power chip 20112, and the projection of the third high-voltage power chip 20113 in the second direction is set as the projection of the third high-voltage power chip 20113. The center of the projection of the second sub-jumper area 2052 is located between the projection of the first high-voltage power chip 20111 and the projection of the second high-voltage power chip 20112 in the first direction, and the center of the projection of the third sub-jumper area 2053 is located between the projection of the second high-voltage power chip 20112 and the projection of the third high-voltage power chip 20113 in the first direction.

[0066] Such an arrangement can make the arrangement of the three first jumper areas 203 on the power side substrate 20 more reasonable, and will not occupy too much space on the power side substrate 20. Under the premise of ensuring that the arrangement of the first jumper area 203 will not affect the normal installation and arrangement of the high-voltage power chip 2011, it can not only improve the stability and reliability of the installation and arrangement of the first jumper area 203, but also further ensure the stability of the electrical connection between the first jumper area 203 and the high-voltage power pin 301 or the fast recovery diode 2013, and prevent the electrical connection wire between the first jumper area 203 and the high-voltage power pin 301 or the fast recovery diode 2013 from being too long, resulting in unreliable electrical connection between the first jumper area 203 and the high-voltage power pin 301 or the fast recovery diode 2013.

[0067] Combination Figure 1-Figure 4 As shown, the second sub-jump area 2052 is spaced between the fast recovery diode 2013 of the first high-voltage power chip 20111 and the fast recovery diode 2013 of the second high-voltage power chip 20112 in the first direction.

[0068] Specifically, by spacing the second sub-jumper area 2052 in the first direction between the fast recovery diode 2013 of the first high-voltage power chip 20111 and the fast recovery diode 2013 of the second high-voltage power chip 20112, the second sub-jumper area 2052 can make full use of the space between the fast recovery diode 2013 of the first high-voltage power chip 20111 and the fast recovery diode 2013 of the second high-voltage power chip 20112, thereby improving the space utilization on the power pad.

[0069] Combination Figure 1-Figure 4 As shown, a side of the high-voltage power pad 201 that is closer to the low-voltage power pad 202 in the first direction is at least partially protruded toward the low-voltage power pad 202 to form a protrusion, and the fast recovery diode 2013 of the first high-voltage power chip 20111 is correspondingly arranged at the protrusion, and a jumper area accommodating space is formed between the fast recovery diode 2013 of the first high-voltage power chip 20111 and the fast recovery diode 2013 of the second high-voltage power chip 20112, and the second sub-jumper area 2052 is arranged in the jumper area accommodating space. Specifically, by making the side of the high-voltage power pad 201 that is closer to the low-voltage power pad 202 in the first direction at least partially protrude toward the low-voltage power pad 202 to form a protrusion, the fast recovery diode 2013 of the first high-voltage power chip 20111 can be moved toward the side of the low-voltage power pad 202 that is closer to the second direction, thereby increasing the distance between the fast recovery diode 2013 of the first high-voltage power chip 20111 and the fast recovery diode 2013 of the second high-voltage power chip 20112, and further forming a jumper area accommodating space between the fast recovery diode 2013 of the first high-voltage power chip 20111 and the fast recovery diode 2013 of the second high-voltage power chip 20112, and setting the second sub-jumper area 2052 in the jumper area accommodating space, thereby ensuring the stability of the installation of the second sub-jumper area 2052.

[0070] Combination Figure 1As shown, the intelligent power module 100 according to claim 10 is characterized in that the third sub-jumper area 2053 is spaced apart at a side of the fast recovery diode 2013 of the third high-voltage power chip 20113 away from the low-voltage power pad 202 in the first direction, the fast recovery diode 2013 of the third high-voltage power chip 20113 is protruded relative to the fast recovery diode 2013 of the second high-voltage power chip 20112 toward a side away from the driving side frame 10 in the second direction, and the third sub-jumper area 2053 is spaced apart at a side of the fast recovery diode 2013 of the third high-voltage power chip 20113 toward the driving side frame 10 in the second direction.

[0071] Specifically, since pressure rods are provided on both side edges of the power side substrate 20 in the first direction, and the pressure rods cooperate with the two side edges of the power side substrate 20 in the first direction in the middle of the second direction, the pressure rods and the fast recovery diode 2013 in the third high-voltage power chip 20113 are close to each other and are easy to interfere with each other. Therefore, in order to prevent the fast recovery diode 2013 in the third high-voltage power chip 20113 from interfering with the pressure rods, the fast recovery diode 2013 in the third high-voltage power chip 20113 is compared with the fast recovery diode 2013 in the first high-voltage power chip 20111 and the second high-voltage power chip 20112. It is protruding toward the side away from the driving side frame 10 in the second direction, so that the fast recovery diode 2013 in the third high-voltage power chip 20113 is away from the pressure rod in the second direction. Therefore, the third sub-jumper area 2053 is spaced apart at the side of the fast recovery diode 2013 of the third high-voltage power chip 20113 toward the driving side frame 10 in the second direction, so that the third sub-jumper area 2053 can make full use of the area between the insulated gate bipolar transistor 2012 and the fast recovery diode 2013 in the third high-voltage power chip 20113, and can improve the space utilization rate of the intelligent power module 100.

[0072] Combination Figure 1-4 As shown, three second jumper areas 204 are arranged in one-to-one correspondence with three high-voltage power chips 2011 , and the second jumper areas 204 are arranged at intervals on the side of the high-voltage power chip 2011 facing the driving side frame 10 in the second direction.

[0073] Specifically, the three second jumper areas 204 are arranged in one-to-one correspondence with the three high-voltage power chips 2011, and the second jumper areas 204 are arranged at intervals on the side of the high-voltage power chip 2011 in the second direction toward the drive side frame 10. This not only facilitates the electrical connection between the second jumper areas 204 and the voltage source pads, but also makes full use of the space between the drive side frame 10 and the power side substrate 20, thereby improving the space utilization of the intelligent power module 100.

[0074] Combination Figure 1-4 As shown, the three second jumper areas 204 are respectively a fourth sub-jumper area 2054, a fifth sub-jumper area 2055 and a sixth sub-jumper area 2056. Compared with the fifth sub-jumper area 2055 and the sixth sub-jumper area 2056, the fourth sub-jumper area 2054 is closer to the low-voltage power pad 202 in the first direction, and the fifth sub-jumper area 2055 is arranged between the fourth sub-jumper area 2054 and the sixth sub-jumper area 2056 in the first direction; the fourth sub-jumper area 2054, the fifth sub-jumper area 2055 and the sixth sub-jumper area 2056 are located at the driving side base. The first sub-jump area 2051 is located on the driving side substrate and is spaced apart from the high-voltage driving pad 101 in the first direction, and the first sub-jump area 2051 is connected to the fourth sub-jump area 2054; the second sub-jump area 2052 and the third sub-jump area 2053 are both located on the high-voltage driving pad 101, the second sub-jump area 2052 and the fifth sub-jump area 2055 are spaced apart in the second direction, and the third sub-jump area 2053 and the sixth sub-jump area 2056 are spaced apart in the second direction.

[0075] Specifically, by reasonably setting the positions of the first jumper area 203 and the second jumper area 204, while ensuring that the first jumper area 203 and the second jumper area 204 do not occupy too much space on the power side substrate 20, not only can the electrical connection between the first jumper area 203 and the second jumper area 204 be facilitated, but also the electrical connection between the first jumper area 203, the second jumper area 204 and other components can be facilitated, which can further optimize the structural design of the intelligent power module 100.

[0076] Furthermore, since the first sub-jumper area 2051 and the fourth sub-jumper area 2054 are adjacent to each other at the edge of the power pad, the first sub-jumper area 2051 and the fourth sub-jumper area 2054 can be directly connected, without affecting other components. When an electrical connection is required between the first jumper area 203 and the second jumper area 204, the electrical connection wire between the first sub-jumper area 2051 and the fourth sub-jumper can be omitted, which can further optimize the structural design of the intelligent power module 100.

[0077] Combination Figure 1-4As shown, the fourth sub-jump area 2054, the fifth sub-jump area 2055 and the sixth sub-jump area 2056 are all in the shape of long strips and extend in the first direction; the first sub-jump area 2051 is in the shape of long strips and extends in the second direction, the second sub-jump area 2052 and the third sub-jump area 2053 are both in block shape, and the side of the high-voltage power pad 201 that is closer to the low-voltage power pad 202 in the first direction is at least partially protruded toward the low-voltage power pad 202 to form a protrusion, and the fast recovery diode 2013 of the first high-voltage power chip 20111 is correspondingly arranged on the protrusion, and the first sub-jump area 2051 is spaced above the protrusion, and the side of the first sub-jump area 2051 that is adjacent to the low-voltage power pad 202 in the first direction is flush with the side of the protrusion that is adjacent to the low-voltage power pad 202 in the first direction.

[0078] Specifically, the fourth sub-jump area 2054, the fifth sub-jump area 2055 and the sixth sub-jump area 2056 are all in the shape of long strips and extend in the first direction. This can reduce the difficulty of electrical connection between the second jumper area 204 and the first jumper area 203, or reduce the difficulty of electrical connection between the second jumper area 204 and the voltage source pad.

[0079] Furthermore, the first sub-jumper area 2051 is also configured to be in a long strip shape, which can facilitate the connection between the first sub-jumper area 2051 and the fourth sub-jumper area 2054, and the second sub-jumper area 2052 and the third sub-jumper area 2053 are both configured to be in a block shape, which can facilitate the installation and setting of the second sub-jumper area 2052 and the third sub-jumper area 2053.

[0080] In addition, a side of the high-voltage power pad 201 that is closer to the low-voltage power pad 202 in the first direction is at least partially protruded toward the low-voltage power pad 202 to form a protrusion, and the fast recovery diode 2013 of the first high-voltage power chip 20111 is correspondingly arranged on the protrusion, and the first sub-jump area 2051 is spaced above the protrusion, and a side of the first sub-jump area 2051 that is adjacent to the low-voltage power pad 202 in the first direction is flush with a side of the protrusion that is adjacent to the low-voltage power pad 202 in the first direction, so that the first sub-jump area 2051 and the power pad can be made more compact.

[0081] Combination Figure 1-4 As shown, the gate pad 2014 of the IGBT 2012 is located on a side of the IGBT 2012 that is closer to the driving side frame 10 along the second direction, and the gate pad 2014 of the IGBT 2012 is located in the middle of the IGBT 2012 in the first direction.

[0082] Specifically, due to the layout positions of the high-voltage driving chip 1011 and the high-voltage power chip 2011, the gate pad 2014 of the insulated gate bipolar transistor 2012 is located on a side of the insulated gate bipolar transistor 2012 that is closer to the driving side frame 10 along the second direction, and the gate pad 2014 of the insulated gate bipolar transistor 2012 is located in the middle of the insulated gate bipolar transistor 2012 in the first direction, so that the electrical connection between the gate pad 2014 of the insulated gate bipolar transistor 2012 and the high-voltage output pin 103 can be facilitated.

[0083] Combination Figure 1-Figure 4 As shown, the three high-voltage driving pads 101 are respectively a first high-voltage driving pad 1012, a second high-voltage driving pad 1013 and a third high-voltage driving pad 1014. Compared with the second high-voltage driving pad 1013 and the third high-voltage driving pad 1014, the first high-voltage driving pad 1012 is closer to the low-voltage driving pad 102 in the first direction, and the second high-voltage driving pad 1013 is spaced between the first high-voltage driving pad 1012 and the third high-voltage driving pad 1014 in the first direction; the three voltage source pins 104 are respectively a first voltage source pin 1041, a second voltage source pin 1042 and a third voltage source pin 1043, and the three high-voltage output Pins 103 are respectively a first high-voltage output pin 1031, a second high-voltage output pin 1032 and a third high-voltage output pin 1033, the first voltage source pin 1041 and the first high-voltage output pin 1031 are arranged between the first high-voltage driving pad 1012 and the second high-voltage driving pad 1013, the second voltage source pin 1042 and the second high-voltage output pin 1032 are arranged between the second high-voltage driving pad 1013 and the third high-voltage driving pad 1014, and the third voltage source pin 1043 and the third high-voltage output pin 1033 are spaced apart and arranged on the side of the third high-voltage driving pad 1014 in the first direction away from the second high-voltage driving pad 1013.

[0084] Specifically, by reasonably setting the positions of the voltage source pin 104 and the high-voltage output pin 103, it is not only convenient to connect the voltage source pin 104 with the voltage source pad, and it is convenient to connect the high-voltage output pin 103 with the high-voltage output pad, but also it is possible to prevent the length of the wire directly electrically connecting the high-voltage driver chip 1011 and the high-voltage power chip 2011 from being too long and unstable. Further, this can also make the structural arrangement of the drive side frame 10 more compact, and can optimize the structural design of the drive side frame 10.

[0085] Combination Figure 1As shown, the first high-voltage output pin 1031, the second high-voltage output pin 1032 and the third high-voltage output pin 1033 all include a first pin portion 1034 and a second pin portion 1035, the first pin portion 1034 is extended in the first direction and is electrically connected to the high-voltage output pad, the second pin portion 1035 is arranged on a side of the first pin portion 1034 that is further away from the power substrate in the second direction and is extended in the second direction, and one end of the second pin portion 1035 that is further away from the power substrate in the second direction is suitable for being electrically connected to the outside, the first voltage source pin 1041, the second voltage source pin 1042 and the third voltage source pin 1043 all include a third pin portion 1044, a fourth pin portion 1045 and a fifth pin portion 1046, and in each of the voltage source pins 104, the third pin portion 1044 and the fifth pin portion 1046 are both extended in the second direction, Compared with the fifth pin portion 1046, the third pin portion 1044 is arranged closer to the low-voltage drive pad 102 in the first direction, the fifth pin portion 1046 is suitable for being electrically connected to the outside, the high-voltage drive pad 101 is spaced apart at a side of the corresponding third pin portion 1044 away from the power substrate in the second direction, the voltage source pad is electrically connected to the third pin portion 1044, the fourth pin portion 1045 is extended in the first direction, the first end of the fourth pin portion 1045 is connected to an end of the third pin portion 1044 adjacent to the power substrate in the second direction, and the second end of the fourth pin portion 1045 is connected to an end of the fifth pin portion 1046 adjacent to the power substrate in the second direction; the third pin portion 1044, the fourth pin portion 1045 and the fifth pin portion 1046 jointly define an avoidance groove 50, and the first pin portion 1034 is arranged in the avoidance groove 50.

[0086] Specifically, by extending the fourth pin portion 1045 in the first direction, the first end of the fourth pin portion 1045 is connected to an end of the third pin portion 1044 adjacent to the power substrate in the second direction, and the second end of the fourth pin portion 1045 is connected to an end of the fifth pin portion 1046 adjacent to the power substrate in the second direction; the third pin portion 1044, the fourth pin portion 1045 and the fifth pin portion 1046 jointly define an avoidance groove 50, and the first pin portion 1034 is located in the avoidance groove 50, so that the structural compactness between the voltage source pin 104 and the high-voltage output pad can be further improved while ensuring the stable electrical connection between the high-voltage output pin 103 and the high-voltage output pad, and while ensuring the stable electrical connection between the voltage source pin 104 and the voltage source output pad.

[0087] Combination Figure 1-4As shown, the three high-voltage output pads and the three voltage source pads on the high-voltage driver chip 1011 together constitute three pad groups, each pad group includes a high-voltage output pad and a voltage source pad spaced apart from each other, and the three pad groups and the three high-voltage power chips 2011 are arranged in a one-to-one correspondence, and the high-voltage output pad in each pad group is farther away from the low-voltage power pad 202 in the first direction than the voltage source pad.

[0088] Specifically, the gate pad 2014 of the insulated gate bipolar transistor 2012 is located on a side of the insulated gate bipolar transistor 2012 that is closer to the driving side frame 10 along the second direction, and the gate pad 2014 of the insulated gate bipolar transistor 2012 is located in the middle of the insulated gate bipolar transistor 2012 in the first direction. Therefore, the high-voltage output pad in each pad group is arranged farther away from the low-voltage power pad 202 in the first direction compared to the voltage source pad, which can further facilitate the electrical connection between the high-voltage driving chip 1011 and the high-voltage power chip 2011, and can further optimize the structural design of the intelligent power module 100.

[0089] The electronic device according to the present invention may mainly include: the above-mentioned intelligent power module 100. Applying the above-mentioned intelligent power module 100 to the electronic device can improve the versatility of the electronic device.

[0090] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0092] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. An intelligent power module, characterized in that: include: Encapsulation body (40); A driving side frame (10), the driving side frame (10) being arranged in the packaging body (40), the driving side frame (10) being provided with high-voltage driving pads (101) and low-voltage driving pads (102) arranged at intervals in a first direction, the number of the low-voltage driving pad (102) being one, one low-voltage driving pad (102) being provided with a low-voltage driving chip (1021), the number of the high-voltage driving pads (101) being three, and the three high-voltage driving pads (101) being arranged at intervals in the first direction; A power-side substrate (20), the power-side substrate (20) being arranged in the packaging body (40) and spaced apart from the drive-side frame (10) in the second direction, the power-side substrate (20) being provided with a high-voltage power pad (201) and a low-voltage power pad (202) spaced apart in the first direction, and the high-voltage power pad (201) being provided with three high-voltage power chips (2011) spaced apart in the first direction; A power pin (30), the power pin (30) being arranged in the package body (40) and located on a side of the power side substrate (20) in the second direction away from the drive side frame (10), the power pin (30) comprising a high voltage power pin (301) and a low voltage power pin (302) arranged at intervals in the first direction, the high voltage power pins (301) being three, and the three high voltage power pins (301) being arranged at intervals in the first direction; Each of the high-voltage power chips (2011) comprises an insulated gate bipolar transistor (2012) and a fast recovery diode (2013) arranged at intervals in the second direction, a gate pad (2014) and an emitter pad (2015) being arranged on the insulated gate bipolar transistor (2012), and in each of the high-voltage power chips (2011), the insulated gate bipolar transistor (2012) is closer to the drive side frame (10) in the second direction than the fast recovery diode (2013), the emitter pads (2015) on the three insulated gate bipolar transistors (2012) are electrically connected to the three fast recovery diodes (2013) in a one-to-one correspondence, and the three fast recovery diodes (2013) are electrically connected to the three high-voltage power pins (301) in a one-to-one correspondence; A high-voltage driving chip (1011) is respectively arranged on each of the three high-voltage driving pads (101), and each of the high-voltage driving chips (1011) is arranged on a high-voltage output pad and a voltage source pad. The driving side frame (10) is provided with three high-voltage output pins (103) and three voltage source pins (104). The three high-voltage output pins (103) are electrically connected to the high-voltage output pads on the three high-voltage driving chips (1011) in a one-to-one correspondence, and the three voltage source pins (104) are electrically connected to the voltage source pads on the three high-voltage driving chips (1011) in a one-to-one correspondence. The three high-voltage output pins (103) are electrically connected to the gate pads (2014) on the three insulated gate bipolar transistors (2012) in a one-to-one correspondence. The power side substrate (20) is provided with three first jumper areas (203) and three second jumper areas (204); the three first jumper areas (203) are selectively and simultaneously electrically connected to the three fast recovery diodes (2013) in a one-to-one correspondence; the three first jumper areas (203) are selectively and simultaneously electrically connected to the three high voltage power pins (301) in a one-to-one correspondence; the three second jumper areas (204) are selectively and simultaneously electrically connected to the three first jumper areas (203); the three voltage source pins (104) are selectively and simultaneously electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012); and the three voltage source pins (104) are selectively and simultaneously electrically connected to the three second jumper areas (204).

2. The intelligent power module according to claim 1, characterized in that: When the three first jumper areas (203) are electrically connected to the three high-voltage power pins (301) in a one-to-one correspondence at the same time, the three first jumper areas (203) are not electrically connected to the three fast recovery diodes (2013), the three voltage source pins (104) are not electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012), the three second jumper areas (204) are electrically connected to the three first jumper areas (203) in a one-to-one correspondence at the same time, and the three voltage source pins (104) are electrically connected to the three second jumper areas (204) in a one-to-one correspondence at the same time.

3. The intelligent power module according to claim 2, characterized in that: The current between the high-voltage driving chip (1011) and the high-voltage power chip (2011) in the package (40) is set to I1, and I1 satisfies the relationship: I1<20A.

4. The intelligent power module according to claim 1, characterized in that: When the three voltage source pins (104) are electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012) in a one-to-one correspondence, the three first jumper areas (203) are not electrically connected to the three fast recovery diodes (2013), the three first jumper areas (203) are not electrically connected to the three high-voltage power pins (301), the three second jumper areas (204) are not electrically connected to the three first jumper areas (203), and the three voltage source pins (104) are not electrically connected to the three second jumper areas (204).

5. The intelligent power module according to claim 4, characterized in that: The current between the high-voltage driving chip (1011) and the high-voltage power chip (2011) in the package (40) is set to I2, and I2 satisfies the relationship: 30A<I2≤50A.

6. The intelligent power module according to claim 1, characterized in that: When the three first jumper areas (203) are electrically connected to the three fast recovery diodes (2013) in a one-to-one correspondence at the same time, the three first jumper areas (203) are not electrically connected to the three high-voltage power pins (301), the three second jumper areas (204) are electrically connected to the three first jumper areas (203) in a one-to-one correspondence at the same time, the three voltage source pins (104) are electrically connected to the three second jumper areas (204) in a one-to-one correspondence at the same time, and the three voltage source pins (104) are not electrically connected to the emitter pads (2015) on the three insulated gate bipolar transistors (2012).

7. The intelligent power module according to claim 6, characterized in that: The current between the high-voltage driving chip (1011) and the high-voltage power chip (2011) in the package (40) is set to I3, and I3 satisfies the relationship: 20A≤I3<30A.

8. The intelligent power module according to claim 1, characterized in that: The three first jumper areas (203) are respectively a first sub-jumper area (2051), a second sub-jumper area (2052) and a third sub-jumper area (2053); the three high-voltage power chips (2011) are respectively a first high-voltage power chip (20111), a second high-voltage power chip (20112) and a third high-voltage power chip (20113); compared with the second high-voltage power chip (20112) and the third high-voltage power chip (20113), the first high-voltage power chip (20111) is closer to the low-voltage power pad (202) in the first direction; the second high-voltage power chip (20112) is spaced between the first high-voltage power chip (20111) and the second high-voltage power chip (20112) in the first direction; The first sub-jumper area (2051) is arranged between the first high-voltage power chip (20111) and the low-voltage power pad (202) in the first direction, the projection of the second sub-jumper area (2052) in the second direction is set as the projection of the second sub-jumper area (2052), the projection of the third sub-jumper area (2053) in the second direction is set as the projection of the third sub-jumper area (2053), the projection of the first high-voltage power chip (20111) in the second direction is set as the projection of the first high-voltage power chip (20111), the projection of the second high-voltage power chip (20112) in the second direction is set as the projection of the second high-voltage power chip (20112), and the projection of the third high-voltage power chip (20113) in the second direction is set as the projection of the third high-voltage power chip (20113); The center of the projection of the second sub-jumper area (2052) is located between the projection of the first high-voltage power chip (20111) and the projection of the second high-voltage power chip (20112) in the first direction, and the center of the projection of the third sub-jumper area (2053) is located between the projection of the second high-voltage power chip (20112) and the projection of the third high-voltage power chip (20113) in the first direction.

9. The intelligent power module according to claim 8, characterized in that: The second sub-jump line area (2052) is arranged in a first direction at intervals between the fast recovery diode (2013) of the first high-voltage power chip (20111) and the fast recovery diode (2013) of the second high-voltage power chip (20112).

10. The intelligent power module according to claim 9, characterized in that: A side of the high-voltage power pad (201) that is closer to the low-voltage power pad (202) in the first direction is at least partially protruded toward the low-voltage power pad (202) to form a protruding portion, and the fast recovery diode (2013) of the first high-voltage power chip (20111) is correspondingly arranged at the protruding portion, and a jumper area accommodating space is formed between the fast recovery diode (2013) of the first high-voltage power chip (20111) and the fast recovery diode (2013) of the second high-voltage power chip (20112), and the second sub-jumper area (2052) is arranged in the jumper area accommodating space.

11. The intelligent power module according to claim 10, characterized in that: The third sub-jumper area (2053) is arranged at intervals on a side of the fast recovery diode (2013) of the third high-voltage power chip (20113) away from the low-voltage power pad (202) in the first direction, and the fast recovery diode (2013) of the third high-voltage power chip (20113) is protruded relative to the fast recovery diode (2013) of the second high-voltage power chip (20112) toward a side away from the drive side frame (10) in the second direction, and the third sub-jumper area (2053) is arranged at intervals on a side of the fast recovery diode (2013) of the third high-voltage power chip (20113) toward the drive side frame (10) in the second direction.

12. The intelligent power module according to claim 11, characterized in that: The three second jumper areas (204) are arranged in one-to-one correspondence with the three high-voltage power chips (2011), and the second jumper areas (204) are arranged at intervals on the side of the high-voltage power chip (2011) facing the driving side frame (10) in the second direction.

13. The intelligent power module according to claim 12, characterized in that: The three second jumper areas (204) are respectively a fourth sub-jumper area (2054), a fifth sub-jumper area (2055) and a sixth sub-jumper area (2056); compared with the fifth sub-jumper area (2055) and the sixth sub-jumper area (2056), the fourth sub-jumper area (2054) is closer to the low-voltage power pad (202) in the first direction, and the fifth sub-jumper area (2055) is arranged between the fourth sub-jumper area (2054) and the sixth sub-jumper area (2056) in the first direction; The fourth sub-jumper area (2054), the fifth sub-jumper area (2055) and the sixth sub-jumper area (2056) are located on the drive side substrate and are spaced apart from the high voltage driving pad (101) in the second direction; the first sub-jumper area (2051) is located on the drive side substrate and is spaced apart from the high voltage driving pad (101) in the first direction; the first sub-jumper area (2051) is connected to the fourth sub-jumper area (2054); The second sub-jumper area (2052) and the third sub-jumper area (2053) are both located on the high-voltage driving pad (101), the second sub-jumper area (2052) and the fifth sub-jumper area (2055) are spaced apart in the second direction, and the third sub-jumper area (2053) and the sixth sub-jumper area (2056) are spaced apart in the second direction.

14. The intelligent power module according to claim 13, characterized in that: The fourth sub-jumper area (2054), the fifth sub-jumper area (2055) and the sixth sub-jumper area (2056) are all in the shape of long strips and are extended in the first direction; The first sub-jumper area (2051) is in the shape of an elongated strip and is extended in the second direction, the second sub-jumper area (2052) and the third sub-jumper area (2053) are both in the shape of a block, the side of the high-voltage power pad (201) that is closer to the low-voltage power pad (202) in the first direction is at least partially protruded toward the low-voltage power pad (202) to form a protruding portion, the fast recovery diode (2013) of the first high-voltage power chip (20111) is correspondingly arranged on the protruding portion, the first sub-jumper area (2051) is arranged above the protruding portion at intervals, and the side of the first sub-jumper area (2051) that is closer to the low-voltage power pad (202) in the first direction is flush with the side of the protruding portion that is closer to the low-voltage power pad (202) in the first direction.

15. The intelligent power module according to claim 1, characterized in that: The gate pad (2014) of the insulated gate bipolar transistor (2012) is located on a side of the insulated gate bipolar transistor (2012) that is closer to the driving side frame (10) along the second direction; The gate pad (2014) of the insulated gate bipolar transistor (2012) is located in the middle of the insulated gate bipolar transistor (2012) in a first direction.

16. The intelligent power module according to claim 15, characterized in that: The three high-voltage driving pads (101) are respectively a first high-voltage driving pad (1012), a second high-voltage driving pad (1013) and a third high-voltage driving pad (1014); compared with the second high-voltage driving pad (1013) and the third high-voltage driving pad (1014), the first high-voltage driving pad (1012) is closer to the low-voltage driving pad (102) in the first direction, and the second high-voltage driving pad (1013) is arranged between the first high-voltage driving pad (1012) and the third high-voltage driving pad (1014) in the first direction; The three voltage source pins (104) are respectively a first voltage source pin (1041), a second voltage source pin (1042) and a third voltage source pin (1043); the three high voltage output pins (103) are respectively a first high voltage output pin (1031), a second high voltage output pin (1032) and a third high voltage output pin (1033); the first voltage source pin (1041) and the first high voltage output pin (1031) are arranged between the first high voltage driving pad (1012) and the second high voltage driving pad (1013); the second voltage source pin (1042) and the second high voltage output pin (1032) are arranged between the second high voltage driving pad (1013) and the third high voltage driving pad (1014); the third voltage source pin (1043) and the third high voltage output pin (1033) are arranged at intervals on a side of the third high voltage driving pad (1014) away from the second high voltage driving pad (1013) in a first direction.

17. The intelligent power module according to claim 16, characterized in that: The first high-voltage output pin (1031), the second high-voltage output pin (1032) and the third high-voltage output pin (1033) all comprise a first pin portion (1034) and a second pin portion (1035), the first pin portion (1034) extending in a first direction and electrically connected to the high-voltage output pad, the second pin portion (1035) being arranged on a side of the first pin portion (1034) further away from the power substrate in a second direction and extending in the second direction, and an end of the second pin portion (1035) further away from the power substrate in the second direction being suitable for being electrically connected to the outside; The first voltage source pin (1041), the second voltage source pin (1042) and the third voltage source pin (1043) each include a third pin portion (1044), a fourth pin portion (1045) and a fifth pin portion (1046). In each of the voltage source pins (104), the third pin portion (1044) and the fifth pin portion (1046) are both extended in the second direction. Compared with the fifth pin portion (1046), the third pin portion (1044) is arranged closer to the low voltage driving pad (102) in the first direction. 6) suitable for being electrically connected to the outside, the high-voltage driving pad (101) is arranged at intervals on the side of the corresponding third pin portion (1044) away from the power substrate in the second direction, the voltage source pad is electrically connected to the third pin portion (1044), the fourth pin portion (1045) is extended in the first direction, the first end of the fourth pin portion (1045) is connected to an end of the third pin portion (1044) adjacent to the power substrate in the second direction, and the second end of the fourth pin portion (1045) is connected to an end of the fifth pin portion (1046) adjacent to the power substrate in the second direction; The third pin portion (1044), the fourth pin portion (1045) and the fifth pin portion (1046) jointly define an avoidance groove (50), and the first pin portion (1034) is disposed in the avoidance groove (50).

18. The intelligent power module according to claim 17, characterized in that: The three high-voltage output pads and the three voltage source pads on the high-voltage driver chip (1011) together form three pad groups, each pad group includes a high-voltage output pad and a voltage source pad spaced apart from each other, the three pad groups and the three high-voltage power chips (2011) are arranged in a one-to-one correspondence, and the high-voltage output pad in each pad group is farther away from the low-voltage power pad (202) in the first direction than the voltage source pad.

19. An electronic device, characterized in that: The intelligent power module (100) comprises any one of claims 1-18.

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