Capacitor device and method of manufacturing the same

Abstract

The application provides a capacitor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, wherein a first metal line, a second metal line and an insulating layer are formed in the substrate; forming a plurality of grooves in the insulating layer; sequentially forming a first electrode material layer, a first dielectric material layer and a second electrode material layer to cover the insulating layer and the grooves; performing a patterning process to form a first electrode, a first dielectric layer and a second electrode, and expose the surface of the second electrode and part of the first electrode; forming a second dielectric layer; forming a plurality of through holes in the second dielectric layer and the insulating layer, and forming a third metal line to electrically connect the first metal line and the second electrode, and forming a fourth metal line to electrically connect the second metal line and the first electrode. In the application, the two electrodes of the capacitor are led downward by using the first metal line and the second metal line in the substrate, which reduces the difficulty of process integration and is beneficial to improve the design freedom of the capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, and in particular to a capacitor device and a manufacturing method thereof. BACKGROUND

[0002] Capacitors are a kind of conventional passive components, which are widely used in the field of integrated circuits. In some special applications, a capacitor with a large unit capacitance is required to improve product performance, such as storing signals, reducing noise, and reducing coupling. A planar capacitor needs to occupy a large area to obtain a large capacitance, which will sacrifice the design area. Therefore, a trench capacitor becomes the best choice for a large capacitor.

[0003] In the related art, the electrodes of the capacitor device are usually electrically led upward, and the trench needs to be filled with metal, which leads to a relatively complicated structure and process of electrically leading out the trench capacitor, and is not conducive to the design of the trench capacitor. SUMMARY

[0004] The purpose of the present application is to provide a capacitor device and a manufacturing method thereof to optimize the structure and manufacturing process of the trench capacitor.

[0005] To solve the above technical problems, the manufacturing method of the capacitor device provided by the present application comprises:

[0006] A substrate is provided, wherein the substrate is formed with a first metal line, a second metal line arranged in the same layer, and an insulating layer covering the first metal line and the second metal line;

[0007] A plurality of trenches are formed in the insulating layer between the first metal line and the second metal line;

[0008] A first electrode material layer, a first dielectric material layer, and a second electrode material layer are sequentially formed to conformally cover the surface of the insulating layer and the inner wall of the trench;

[0009] A patterning process is performed on the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form a first electrode, a first dielectric layer, and a second electrode covering the trench and the insulating layer around the trench, and to expose the surface of the second electrode and part of the first electrode;

[0010] A second dielectric layer is formed to cover the insulating layer, the first electrode, the second electrode, and the trench;

[0011] A plurality of through holes are formed in the second dielectric layer and the insulating layer to respectively expose the first electrode, the second electrode, the first metal line, and the second metal line, a third metal line is formed to electrically connect the first metal line and the second electrode, and a fourth metal line is formed to electrically connect the second metal line and the first electrode.

[0012] Optionally, a dielectric barrier layer is further provided between the first metal line and the second metal line and the insulating layer.

[0013] Optionally, a capacitor region is provided on the insulating layer between the first metal line and the second metal line, and the step of forming the plurality of grooves in the capacitor region comprises:

[0014] a first mask is formed to cover the surface of the insulating layer, and a plurality of openings are formed in the capacitor region;

[0015] the first mask is used to dry-etch the insulating layer with the dielectric barrier layer as an etching stop layer, so as to form a plurality of grooves in the capacitor region;

[0016] the first mask is removed.

[0017] Optionally, the capacitor region has a first side and a second side close to the first metal line and the second metal line respectively, and the step of forming the second electrode and the first dielectric layer comprises:

[0018] a second mask is formed to cover the second electrode material layer of the capacitor region, and the second mask extends to cover the second electrode material layer close to the first side;

[0019] the second mask is used to etch the second electrode material layer and the first dielectric material layer, so as to expose the surface of the first electrode material layer, and the remaining second electrode material layer is used as the second electrode, and the remaining first dielectric material layer is used as the first dielectric layer;

[0020] the second mask is removed.

[0021] Optionally, the step of forming the first electrode comprises:

[0022] a third mask is formed to cover the second electrode, and the third mask extends to cover the first electrode material layer close to the second side;

[0023] the third mask is used to etch the first electrode material layer, so as to expose the surface of the insulating layer, and the remaining first electrode material layer is used as the first electrode;

[0024] the third mask is removed.

[0025] Optionally, the step of forming a plurality of through holes comprises:

[0026] a plurality of first through holes are formed in the second dielectric layer to respectively expose the first electrode and the second electrode;

[0027] Forming a plurality of second through holes in the insulating layer and the second dielectric layer to respectively expose the first metal line and the second metal line.

[0028] Optionally, the step of forming the third metal line and the fourth metal line comprises:

[0029] forming a metal material layer to cover the surface of the second dielectric layer, the first through hole and the inner wall of the second through hole;

[0030] performing a patterning process on the metal material layer to form the third metal line electrically connecting the first metal line and the second electrode, and form the fourth metal line electrically connecting the second metal line and the first electrode.

[0031] Optionally, when performing the patterning process on the metal material layer, a metal pad is also formed on the surface of the insulating layer at the same time, for connecting with an external circuit.

[0032] Optionally, the material of the first electrode material layer and the second electrode material layer comprises one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

[0033] Based on another aspect of the present application, a capacitor device is also provided, comprising:

[0034] a substrate;

[0035] a first metal line and a second metal line arranged in the same layer in the substrate;

[0036] an insulating layer covering the first metal line and the second metal line, a plurality of grooves being formed in the insulating layer between the first metal line and the second metal line, and a plurality of second through holes being formed in the insulating layer on the first metal line and the second metal line to respectively expose the first metal line and the second metal line;

[0037] a capacitor formed in the grooves and on the insulating layer around the grooves, comprising a first electrode, a first dielectric layer and a second electrode formed in sequence and conformally;

[0038] a second dielectric layer covering the capacitor, a plurality of first through holes being formed in the second dielectric layer to respectively expose the first electrode and the second electrode;

[0039] a third metal line and a fourth metal line, the third metal line electrically connecting the first metal line and the second electrode and the fourth metal line electrically connecting the second metal line and the first electrode, by means of the first through holes and the second through holes.

[0040] In summary, the application forms a plurality of grooves in the insulating layer between the first metal line and the second metal line, and forms a capacitor in the grooves and on the insulating layer around the grooves, the capacitor comprising a first electrode, a first dielectric layer and a second electrode formed in sequence in a conformal manner, the first electrode and the second electrode respectively extend to both sides of the capacitor and are both exposed upward, a second dielectric layer is further formed to cover the capacitor and the insulating layer, and a via hole is formed in the second dielectric layer and the insulating layer to respectively expose the first metal line, the second metal line, the first electrode and the second electrode, a third metal line is further formed by using the via hole to electrically connect the second electrode and the first metal line, and a fourth metal line is further formed to electrically connect the first electrode and the second metal line, so that the two electrodes of the capacitor are completed to be drawn downward by using the first metal line and the second metal line in the substrate, the drawing of the capacitor in the capacitor device and the wiring of the metal line on the insulating layer are completed without additional process steps, so that the drawing structure is simple, the process integration difficulty is reduced, and the capacitance density and the design freedom of the capacitor in the capacitor device are improved. In addition, compared with the way of filling the grooves with metal in the related art, the two electrodes of the groove capacitor in the embodiment extend to both sides to realize electrical drawing, without filling metal, i.e. allowing the existence of hollows, so as to improve the design freedom of the capacitor in the capacitor device. BRIEF DESCRIPTION OF DRAWINGS

[0041] Those skilled in the art will understand that the drawings provided are for a better understanding of the application, and do not constitute any limitation on the scope of the application.

[0042] Figure 1 is a flowchart of the manufacturing method of the capacitor device provided in embodiment one;

[0043] Figures 2a-2l is a structure schematic diagram corresponding to the respective steps of the manufacturing method of the capacitor device provided in embodiment one.

[0044] In the drawings:

[0045] 10-substrate; 11-first metal line; 12-second metal line; AA-capacitor area; A1-first side; A2-second side; 21-dielectric barrier layer; 22-insulating layer; 23-groove; 24-first electrode material layer; 24a-first electrode; 25-first dielectric material layer; 25a-first dielectric layer; 26-second electrode material layer; 26a-second electrode; 27-second mask; 28-third mask; 31-second dielectric layer; 32-first via hole; 33-second via hole; 34-metal material layer; 35-third metal line; 36-fourth metal line. DETAILED DESCRIPTION

[0046] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0047] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise. Example 1

[0048] Figure 1 4 is a flow chart of a method for manufacturing a capacitor device provided in Example 1.

[0049] like Figure 1 As shown, the manufacturing method of the capacitor device provided in this embodiment includes:

[0050] S01: providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed on the substrate;

[0051] S02: forming a plurality of trenches in the insulating layer between the first metal line and the second metal line;

[0052] S03: forming a first electrode material layer, a first dielectric material layer, and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the trench;

[0053] S04: performing a patterning process on the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form a second electrode covering the trench and the insulating layer around the trench, a first dielectric layer, and a first electrode, and exposing surfaces of the second electrode and a portion of the first electrode;

[0054] S05: forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench;

[0055] S06: forming a plurality of through holes in the second dielectric layer and the insulating layer to respectively expose the first electrode, the second electrode, the first metal line and the second metal line, and forming a third metal line to electrically connect the first metal line and the second electrode, and forming a fourth metal line to electrically connect the second metal line and the first electrode.

[0056] Figures 2a-2l The corresponding structural schematic diagram of the corresponding steps of the manufacturing method of the capacitor device provided in the present embodiment is shown in FIG. 1. Next, the manufacturing method of the capacitor device will be described in detail in combination with Figures 2a-2l The manufacturing method of the capacitor device will be described in detail in combination with

[0057] First, referring to FIG. 1, Figure 2a , step S01 is performed to provide a substrate 10, in which first metal lines 11, second metal lines 12 and an insulating layer 22 covering the first metal lines 11 and the second metal lines 12 are arranged in the same layer.

[0058] The substrate 10 can be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator, stacked silicon-on-insulator, stacked germanium-silicon-on-insulator, germanium-silicon-on-insulator, and germanium-on-insulator. In the present embodiment, the material of the substrate 10 is taken as an example to be described as silicon (silicon substrate).

[0059] The substrate 10 has a device layer and an interconnection layer electrically connected to the device layer, and the interconnection layer is located above the device layer and can be formed by damascene process. The first metal lines 11 and the second metal lines 12 can be two metal wires arranged at intervals in the Nth layer (N is greater than or equal to 1) of the interconnection layer, and the material thereof can include copper, for example. In the present embodiment, the first metal lines 11 and the second metal lines 12 can be two top metal wires arranged at intervals. The dielectric barrier layer 21 and the insulating layer 22 are sequentially formed on the first metal lines 11 and the second metal lines 12, the material of the dielectric barrier layer 21 is used to block the escape of metal ions and to act as an etching stop layer during etching, and the material thereof can include silicon nitride or silicon carbon nitride, for example. The material of the insulating layer 22 is different from that of the dielectric barrier layer 21, and the material thereof can include silicon oxide or silicon oxynitride, for example.

[0060] In addition, in other examples of the present embodiment, a plurality of (at least two) first metal lines 11 and a plurality of second metal lines 12 can also be provided as needed, and the plurality of same metal lines are in parallel state; other metal lines can also be arranged between the first metal lines 11 and the second metal lines 12.

[0061] Next, referring to FIG. 2, Figure 2b , step S02 is performed to form a plurality of grooves 23 in the insulating layer 22 between the first metal lines 11 and the second metal lines 12.

[0062] The insulating layer 22 between the first metal line 11 and the second metal line 12 is provided with a capacitor region AA, and a plurality of grooves 23 are formed in the capacitor region AA for forming a single-layer capacitor thereon. Specifically, a first mask (not shown) is first formed to cover the surface of the insulating layer 22, and the first mask is provided with a plurality of openings in the capacitor region AA; the insulating layer 22 is dry-etched using the first mask and the dielectric barrier layer 21 as an etching stop layer, so as to form a plurality of grooves 23 in the capacitor region AA; and then the first mask is removed. The capacitor region AA can include the plurality of grooves 23 and the partial insulating layer 22 around the grooves 23. Of course, in other examples of the embodiment, the grooves 23 can not penetrate the insulating layer 22.

[0063] In addition, the capacitor region AA can also extend into the insulating layer 22 on the first metal line 11 and / or the second metal line 12 as needed, i.e., the grooves 23 are also formed in the insulating layer 22 on the first metal line 11 and / or the second metal line 12.

[0064] Next, referring to Figure 2c , a step S03 is performed to form a first electrode material layer 24, a first dielectric material layer 25 and a second electrode material layer 26 successively to cover the surface of the insulating layer 22 and the inner wall of the groove 23 conformally. The first electrode material layer 24 can be formed by any suitable process, and can include one or more thin-film conductive layers, which can be made of one or more of titanium, titanium nitride, tantalum or tantalum nitride, and can be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition, and the thickness of the first electrode material layer 24 can be, for example, 100-400 angstroms. The first dielectric material layer 25 can be made of a dielectric material with a high dielectric constant, such as silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide or rhodium oxide, and the dielectric constant can be greater than or equal to 3.9. The second electrode material layer 26 can be made of a material similar to that of the first electrode material layer 24.

[0065] Next, a step S04 is performed to perform a patterning process on the second electrode material layer 26, the first dielectric material layer 25 and the first electrode material layer 24, so as to form the first electrode 24a, the first dielectric layer 25a and the second electrode 26a covering the groove 23 and the insulating layer 22 around the groove 23, and expose the surface of the second electrode 26a and part of the first electrode 24a.

[0066] Specifically, referring to Figure 2d, the capacitor region AA has a first side A1 and a second side A2 (opposite) close to the first metal line 11 and the second metal line 12 respectively, a second mask 27 is formed to cover the second electrode material layer 26 of the capacitor region AA, and the second mask 27 can also preferably extend to cover the second electrode material layer 26 close to the first side A1 to facilitate subsequent electrical lead-out. It should be noted that the second mask is preferably avoided to extend above the first metal line 11 or the second metal line 12 to prevent short circuit. In the embodiment, the first side A1 of the capacitor region AA is close to the first metal line 11, and the second mask 27 can cover the second electrode material layer 26 of the capacitor region AA and the second electrode material layer 26 between the capacitor region AA and the first metal line 11.

[0067] Please refer to Figure 2e , the second electrode material layer 26 and the first dielectric material layer 25 are etched in sequence by using the second mask 27 to expose the surface of the first electrode material layer 24, and the remaining second electrode material layer 26 is used as the second electrode 26a, and the remaining first dielectric material layer 25 is used as the first dielectric layer 25a, and then the second mask 27 is removed. The second electrode 26a and the first dielectric layer 25a have an overlapping area as close as possible, both covering the capacitor region AA and the region close to the first side A1.

[0068] Please refer to Figure 2f , a third mask 28 is formed to cover the second electrode 26a, and the third mask 28 extends to cover the first electrode material layer 24 close to the second side A2. Preferably, the edge of the third mask 28 near the first side A1 can be aligned with the second electrode 26a as much as possible, and the edge of the third mask 28 near the other side (the second side A2) of the capacitor region AA can extend to the first electrode material layer 24, that is, the third mask 28 can extend to cover the first electrode material layer 24 near the second side A2.

[0069] Please refer to Figure 2g , the first electrode material layer 24 is etched by using the third mask 28 to expose the surface of the insulating layer 22, and the remaining first electrode material layer 24 is used as the first electrode 24a, and then the third mask 28 is removed. The first electrode 24a includes the first electrode material layer 24 under the second electrode 26a (or the first dielectric layer 25a) and the remaining first electrode material layer 24 on the insulating layer 22 close to the second side A2.

[0070] Thus, the trench capacitor composed of the first electrode 24a, the first dielectric layer 25a and the second electrode 26a is formed on the insulating layer 22 in the trench 23 and around the trench 23 (the capacitor region AA) to increase the capacitance value (capacitance density) on the same substrate 10 area. Moreover, the first electrode 24a and the second electrode 26a extend from the capacitor region AA to the first metal line 11 and the second metal line 12 respectively to be exposed to facilitate subsequent electrical lead-out.

[0071] Then, referring to Figure 2h , a second dielectric layer 31 is formed to cover the insulating layer 22, the first electrode 24a, the second electrode 26a and the trench 23. The second dielectric layer 31 can include a single layer or multiple layers of dielectric material, which can include silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride or other suitable insulating material, and can be formed by a suitable process such as chemical vapor deposition or atomic layer deposition. In addition to covering the insulating layer 22, the first electrode 24a and the second electrode 26a, the second dielectric layer 31 also fills the trench 23. Compared with the related art in which the trench 23 for forming the capacitor is filled with electrode material, the embodiment fills the trench 23 with the second dielectric layer 31, which not only saves electrode material but also provides greater freedom for the design of the trench capacitor. It should be understood that the trench capacitor in the embodiment does not draw electrodes out of the trench 23, so it is not necessary to fill the trench 23 with electrode material, i.e., the embodiment allows the trench capacitor to have a hollow (which can be filled with the second dielectric layer later).

[0072] Then, referring to

[0073] , a plurality of through holes are formed in the second dielectric layer 31 and the insulating layer 22 to respectively expose the first electrode 24a, the second electrode 26a, the first metal line 11 and the second metal line 12, and a third metal line 35 is formed to electrically connect the first metal line 11 and the first electrode 24a, and a fourth metal line 36 is formed to electrically connect the second metal line 12 and the second electrode 26a. Figure 2i , a plurality of first through holes 32 are formed in the second dielectric layer 31 to respectively expose the first electrode 24a and the second electrode 26a. Some of the first through holes 32 are located in the second dielectric layer 31 near the first side A1 to expose one of the first electrode 24a and the second electrode 26a, and the other first through holes 32 are located in the second dielectric layer 31 near the second side A2 to expose the other of the first electrode 24a and the second electrode 26a. In the embodiment, the first through holes 32 near the first side A1 can expose the first electrode 24a, and the first through holes 32 near the second side A2 can expose the second electrode 26a.

[0074] Figure 2j ​A plurality of second vias 33 are formed in the insulating layer 22 and the second dielectric layer 31 to respectively expose the first metal line 11 and the second metal line 12. Some of the second vias 33 can be located above the first metal line 11 to expose the first metal line 11, and some of the second vias 33 can be located above the second metal line 12 to expose the second metal line 12. In the embodiment, the second vias 33 also penetrate the dielectric barrier layer 21 under the insulating layer 22. When the second vias 33 are etched, the dielectric barrier layer 21 can also act as an etching stop layer for etching the second dielectric layer 31 and the insulating layer 22, so as to reduce damage to the metal lines.

[0075] Please refer to Figure 2k A metal material layer 34 is formed to cover the surface of the second dielectric layer 31, the first vias 32 and the inner walls of the second vias 33. The metal material layer 34 can be a metal material suitable for connecting with external circuits, such as aluminum or aluminum alloy. In the embodiment, the materials of the first metal line 11 and the second metal line 12 include copper, and the metal material layer 34 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer and a titanium nitride layer which are sequentially conformally formed. In practice, since the size (depth and opening width) of the first vias 32 is smaller than that of the second vias 33, the metal material layer 34 can fill the first vias 32, and the metal material layer 34 can only cover the inner walls of the second vias 33 without filling the second vias 33.

[0076] Please refer to Figure 2l A patterning process is performed on the metal material layer 34 to form a third metal line 35 connecting the first metal line 11 and the second electrode 26a, and a fourth metal line 36 connecting the second metal line 12 and the first electrode 24a. Specifically, the patterning process on the metal material layer 34 includes disconnecting the metal material layer 34 on both sides of the capacitor region AA, using the metal material layer 34 covering the second vias 33 on the first metal line 11 to the first via 32 close to the first side A1 as the third metal line 35, and using the metal material layer 34 covering the second vias 33 on the second metal line 12 to the first via 32 close to the second side A2 as the fourth metal line 36.

[0077] In addition, during the patterning process on the metal material layer 34, the metal material layer 34 can also be used to synchronously form a metal pad on the second dielectric layer 31, and other top metal lines can be electrically led out to the metal pad for connection with external circuits. In other words, the electrical leading out (downward leading out) of the trench capacitor in the embodiment can be achieved in the step of forming the metal pad, and no additional device structure and process step is needed.

[0078] It is worth mentioning that in other examples of the embodiment, the first electrode of the trench capacitor can also extend from the capacitor region to a length of the first metal line extension, and the second electrode extends from the capacitor region to a length of the second metal line extension, so that the third metal line formed is electrically connected to the first metal line and the first electrode, and the fourth metal line is electrically connected to the second metal line and the second electrode. Embodiment Two

[0079] Embodiment Two provides a capacitor device.

[0080] Figure 2l A structural schematic diagram of a capacitor device provided for Embodiment Two.

[0081] The capacitor device provided by the embodiment can be formed by using the method provided by Embodiment One. Specifically, as shown in Figure 2l The capacitor device can include a substrate 10, a first metal line 11 and a second metal line 12, an insulating layer 22, a capacitor, a second dielectric layer 31, a third metal line 35 and a fourth metal line 36. The first metal line 11 and the second metal line 12 are arranged in the same layer in the substrate 10. The insulating layer 22 covers the first metal line 11 and the second metal line 12, and a plurality of trenches 23 are formed in the insulating layer 22 between the first metal line 11 and the second metal line 12. The capacitor is formed in the trench 23 and the insulating layer 22 (capacitor region AA) around the trench 23, and includes a first electrode 24a, a first dielectric layer 25a and a second electrode 26a formed in sequence. The first electrode 24a extends from the capacitor region AA to a length of the second metal line 12 (i.e., the second side A2), and the second electrode 26a and the first dielectric layer 25a extend from the capacitor region AA to a length of the first metal line 11 (i.e., the first side A1). The second dielectric layer 31 covers the surface of the capacitor and the insulating layer 22, and a plurality of first vias 32 are formed in the second dielectric layer 31 to expose the first electrode 24a and the second electrode 26a, respectively. A plurality of second vias 33 are formed in the second dielectric layer 31 and the insulating layer 22 on the first metal line 11 and the second metal line 12 to expose the first metal line 11 and the second metal line 12, respectively. The third metal line 35 is electrically connected to the first metal line 11 and the second electrode 26a by using the first via 32 and the second via 33 close to the first metal line 11, and the fourth metal line 36 is electrically connected to the second metal line 12 and the first electrode 24a by using the first via 32 and the second via 33 close to the second metal line 12.

[0082] In summary, the application forms a plurality of grooves in the insulating layer between the first metal line and the second metal line, and forms a capacitor in the grooves and on the insulating layer around the grooves, the capacitor comprising a first electrode, a first dielectric layer and a second electrode formed in sequence in a conformal manner, the first electrode and the second electrode extend to both sides of the capacitor respectively and are both exposed upward, a second dielectric layer is further formed to cover the capacitor and the insulating layer, and a via hole is formed in the second dielectric layer and the insulating layer to expose the first metal line, the second metal line, the first electrode and the second electrode respectively, a third metal line is further formed by the via hole to electrically connect the second electrode and the first metal line, and a fourth metal line is further formed by the via hole to electrically connect the first electrode and the second metal line, thus the two electrodes of the capacitor are completed to be led downward by the first metal line and the second metal line in the substrate, the leading-out of the capacitor in the capacitor device and the wiring of the metal line on the insulating layer are completed without additional process steps, so that the leading-out structure is simple, the process integration difficulty is reduced, and the capacitance density and the design freedom of the capacitor in the capacitor device are improved. In addition, compared with the way of filling the grooves with metal in the related art, the two electrodes of the capacitor in the embodiment extend to both sides to realize electrical leading-out, without the need to fill the metal, i.e. allowing the existence of hollows, so as to improve the design freedom of the capacitor in the capacitor device.

[0083] The above description is only a description of the preferred embodiments of the application, and does not limit the scope of the application in any way. Any modification or improvement made by a person skilled in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A method for manufacturing a capacitor device, characterized in that: include: Providing a substrate, wherein a first metal line and a second metal line arranged in the same layer and an insulating layer covering the first metal line and the second metal line are formed on the substrate; forming a plurality of trenches in the insulating layer between the first metal line and the second metal line; forming a first electrode material layer, a first dielectric material layer, and a second electrode material layer in sequence to conformally cover the surface of the insulating layer and the inner wall of the trench; Performing a patterning process on the second electrode material layer, the first dielectric material layer, and the first electrode material layer to form a first electrode, a first dielectric layer, and a second electrode covering the trench and the insulating layer around the trench, and exposing the second electrode and a portion of the first electrode; forming a second dielectric layer to cover the insulating layer, the first electrode, the second electrode and the trench; A plurality of through holes are formed in the second dielectric layer and the insulating layer to expose the first electrode, the second electrode, the first metal wire and the second metal wire respectively, and a third metal wire is formed to electrically connect the first metal wire and the second electrode, and a fourth metal wire is formed to electrically connect the second metal wire and the first electrode.

2. The method for manufacturing a capacitive device according to claim 1, wherein: A dielectric barrier layer is further provided between the first metal wire, the second metal wire and the insulating layer.

3. The method for manufacturing a capacitive device according to claim 2, wherein: A capacitor region is provided on the insulating layer between the first metal line and the second metal line, and the step of forming the plurality of trenches in the capacitor region includes: forming a first mask to cover the surface of the insulating layer and to form a plurality of openings in the capacitor region; Using the first mask and the dielectric barrier layer as an etch stop layer, dry-etching the insulating layer to form a plurality of trenches in the capacitor region; The first mask is removed.

4. The method for manufacturing a capacitive device according to claim 3, wherein: The capacitor region has a first side and a second side respectively close to the first metal line and the second metal line, and the steps of forming the second electrode and the first dielectric layer include: forming a second mask to cover the second electrode material layer in the capacitor region, wherein the second mask extends to cover the second electrode material layer close to the first side; Using the second mask, etching the second electrode material layer and the first dielectric material layer to expose the surface of the first electrode material layer, and using the remaining second electrode material layer as the second electrode and the remaining first dielectric material layer as the first dielectric layer; The second mask is removed.

5. The method for manufacturing a capacitive device according to claim 4, wherein: The step of forming the first electrode includes: forming a third mask to cover the second electrode, wherein the third mask extends to cover the first electrode material layer close to the second side; Using the third mask, etching the first electrode material layer to expose the surface of the insulating layer, and using the remaining first electrode material layer as the first electrode; The third mask is removed.

6. The method for manufacturing a capacitive device according to claim 1, wherein: The steps of forming the plurality of through holes include: forming a plurality of first through holes in the second dielectric layer to expose the first electrode and the second electrode respectively; A plurality of second through holes are formed in the insulating layer and the second dielectric layer to expose the first metal line and the second metal line respectively.

7. The method for manufacturing a capacitive device according to claim 6, wherein: The steps of forming the third metal line and the fourth metal line include: forming a metal material layer to cover the surface of the second dielectric layer, the first through hole, and the inner wall of the second through hole; A patterning process is performed on the metal material layer to form the third metal line electrically connecting the first metal line and the second electrode, and to form the fourth metal line electrically connecting the second metal line and the first electrode.

8. The method for manufacturing a capacitive device according to claim 7, wherein: When the patterning process is performed on the metal material layer, a metal pad is also formed on the surface of the insulating layer simultaneously for connecting with an external circuit.

9. The method for manufacturing a capacitive device according to claim 1, wherein: The materials of the first electrode material layer and the second electrode material layer include one or more of titanium, titanium nitride, tantalum and tantalum nitride.

10. A capacitor device, characterized in that: include: substrate; A first metal line and a second metal line are arranged in the substrate in the same layer; an insulating layer covering the first metal line and the second metal line, wherein a plurality of grooves are formed in the insulating layer between the first metal line and the second metal line, and a plurality of second through holes are formed in the insulating layer above the first metal line and the second metal line to expose the first metal line and the second metal line respectively; a capacitor formed in the trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer, and a second electrode that are conformally formed in sequence; a second dielectric layer covering the capacitor, wherein a plurality of first through holes are formed in the second dielectric layer to expose the first electrode and the second electrode respectively; The third metal wire and the fourth metal wire utilize the first through-hole and the second through-hole. The third metal wire electrically connects the first metal wire and the second electrode, and the fourth metal wire electrically connects the second metal wire and the first electrode.

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