A Power Device PCM Monitoring Structure and Monitoring Method

Abstract

The present invention discloses a power device PCM monitoring structure and a monitoring method, which relate to the field of power devices. In the present invention, a plurality of resistor bars stacked are designed and arranged in the scribing lane of a wafer. The resistor bars are connected to two adjacent p-columns in an SJ MOS. The number of resistor bars is the same as the number of p-type ion implantation times of the p-columns. By testing the resistance values of the resistor bars in the scribing lane, the detection of any one layer or any multiple layers of pillar resistances of the p-columns of the SJ MOS in wafers of different Lots is realized. By comparing the differences in the resistance values of any one layer or any multiple layers of pillar resistances of the p-columns of the SJ MOS in wafers of different Lots, the corresponding relationship between pillar doping and BVDSS stability is confirmed. Through the comparison results, the factors causing BVDSS fluctuations can be accurately and quickly found, and the stability of the mass production process can be better realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of power devices, and particularly relates to a power device PCM (Process Control Monitor) monitoring structure and a monitoring method. Background Art

[0002] In the multiple epitaxial implantation process of SJ MOS (Super Junction MOSFET), in order to form a matching p-type structure in the multiple epitaxial processes, it is necessary to perform multiple epitaxial layer growths and p-type ion implantations, and the number of growths is directly proportional to the cost. Although the multiple epitaxial implantation process has a high cost, it is possible to control parameters such as different implantation energies and implantation doses after each epitaxy, and form different p-type region distributions at different depths according to requirements.

[0003] The mass production of SJ MOS requires precise control of the charge balance problem between n-type and p-type. How to precisely control the charge balance is of great significance for the mass production of SJ MOS, and it significantly affects the level of BVDSS (Breakdown Voltage between Drain and Source).

[0004] In the current situation of mass production of SJ MOS with multiple epitaxies, it is necessary to monitor the stability of doping in one or more layers of pillars to synchronously monitor the stability of BVDSS of SJ MOS. In current mass production, the stability of ion implantation RS (Sheet Resistance) is mainly monitored to ensure the stability of doping. In the existing monitoring methods, for every 0.1e13 difference in boron ion implantation, there is an overlap in RS, resulting in a low monitoring accuracy. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a power device PCM monitoring structure and a monitoring method. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] The present invention provides a power device PCM monitoring structure, including: a plurality of resistive strips stacked in the dicing channel of the wafer, the resistive strips being connected to two adjacent p-columns in the SJ MOS, and the number of the resistive strips being the same as the number of p-type ion implantations of the p-columns.

[0007] In an embodiment of the present invention, the resistive strip is a cuboid structure formed by epitaxial layer growth and p-type ion implantation.

[0008] In an embodiment of the present invention, the width-to-length ratio of the resistive strip is 10 / 1000.

[0009] In an embodiment of the present invention, the p-column includes a plurality of pillars stacked from bottom to top, and the pillars are formed by epitaxial layer growth and p-type ion implantation.

[0010] In one embodiment of the present invention, the p-type ion implantation dose of the resistor bar is the same as the p-type ion implantation dose of the corresponding pillar in the p-column.

[0011] In one embodiment of the present invention, it further includes two contact holes arranged in the ILD layer, and the two contact holes correspond to the positions of two adjacent p-columns one by one.

[0012] In one embodiment of the present invention, a metal lead is arranged in the contact hole, one end of the metal lead is connected to the p-column, and the other end is connected to the pad.

[0013] The present invention provides a monitoring method for a power device PCM monitoring structure as described in any one of the above embodiments, including:

[0014] Exposing the resistor bar corresponding to the pillar to be monitored in the SJ MOS;

[0015] Applying a voltage on the pad to test the resistance value of the exposed resistor bar, and obtaining the resistance detection value of the pillar to be monitored;

[0016] Comparing the resistance detection values of the pillars to be monitored in the SJ MOS of wafers from different Lots, and judging whether the BVDSS of the SJ MOS is stable according to the comparison result.

[0017] In one embodiment of the present invention, when the difference between the resistance detection values of the pillars to be monitored in the SJ MOS of wafers from different Lots is greater than a preset threshold, the BVDSS of the SJ MOS is unstable.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] For the power device PCM monitoring structure of the present invention, by designing and arranging multiple stacked resistor bars in the scribing lane of the wafer, the resistor bar is connected to two adjacent p-columns in the SJ MOS, and the number of resistor bars is the same as the number of p-type ion implantation times of the p-column. By testing the resistance value of the resistor bar in the scribing lane, the detection of any one layer or any multiple layers of pillar resistors of the p-column in the SJ MOS of wafers from different Lots is realized. By comparing the differences in the resistance values of any one layer or any multiple layers of pillar resistors of the p-column in the SJ MOS of wafers from different Lots, the corresponding relationship between pillar doping and BVDSS stability is confirmed. Through the comparison result, the factors causing BVDSS fluctuation can be accurately and quickly found, the stability of the mass production process can be better realized, the BVDSS fluctuation can be reduced, and thus the economic loss caused by the BVDSS fluctuation can be reduced.

[0020] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following preferred embodiments are specifically given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0021] Figure 1 is a schematic diagram of a power device PCM monitoring structure provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of monitoring the resistance value of the first layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar + the fourth layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar + the fourth layer of pillar + the fifth layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0027] Figure 7 is a schematic diagram of monitoring the resistance value of the second layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0028] Figure 8 is a schematic diagram of monitoring the resistance value of the second layer of pillar + the third layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0029] Figure 9 is a schematic diagram of monitoring the resistance value of the second layer of pillar + the third layer of pillar + the fourth layer of pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention;

[0030] Figure 10 It is a schematic diagram of monitoring the resistance value of the third layer of pillar in the p-pillar through the power device PCM monitoring structure provided by the embodiment of the present invention;

[0031] Figure 11 It is a schematic diagram of monitoring the resistance value of the third layer of pillar + the fourth layer of pillar in the p-pillar through the power device PCM monitoring structure provided by the embodiment of the present invention.

[0032] Icon: 10 - Resistance bar; 20 - p-pillar; 21 - First layer of pillar; 22 - Second layer of pillar; 23 - Third layer of pillar; 24 - Fourth layer of pillar; 25 - Fifth layer of pillar; 26 - Sixth layer of pillar; 30 - ILD layer; 31 - Contact hole; 32 - Metal lead; 40 - Pad. Detailed implementation manners

[0033] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following combines the accompanying drawings and specific implementation manners to detail a power device PCM monitoring structure and monitoring method proposed according to the present invention.

[0034] The foregoing and other technical contents, features, and effects of the present invention can be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific implementation manners, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solutions of the present invention.

[0035] In the first aspect, the embodiment of the present invention provides a power device PCM monitoring structure. Please refer to Figure 1 , Figure 1 which is a schematic diagram of a power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 1 shown, the power device PCM monitoring structure of this embodiment includes: a plurality of resistance bars 10 stacked in the scribing lane of the wafer, the resistance bars 10 are connected to two adjacent p-pillars 20 in the SJ MOS, and the number of the resistance bars 10 is the same as the number of p-type ion implantation times of the p-pillars 20.

[0036] In the process of manufacturing an SJ MOS, the p-column is formed by multiple epitaxial layer growths and p-type ion implantations. The p-column can be regarded as composed of multiple pillars stacked from bottom to top. In this embodiment, when manufacturing the p-column, a rectangular parallelepiped structure formed by simultaneously performing epitaxial layer growth and p-type ion implantation in the scribing lane of the wafer is used as the resistor bar 10. The p-type ion implantation dose of the resistor bar 10 is the same as that of the corresponding pillar in the p-column 20.

[0037] Exemplarily, as Figure 1 shown, the p-column in the SJ MOS includes 6 pillars stacked from bottom to top, namely, the first layer pillar 21, the second layer pillar 22, the third layer pillar 23, the fourth layer pillar 24, the fifth layer pillar 25, and the sixth layer pillar 26. Then, 6 resistor bars 10 are correspondingly arranged in the power device PCM monitoring structure of this embodiment.

[0038] Optionally, the aspect ratio of the resistor bar 10 is 10 / 1000.

[0039] Please continue to refer to Figure 1 , the power device PCM monitoring structure of this embodiment further includes two contact holes 31 provided in the ILD (InterLayer Dielectric) layer 30. Metal leads 32 are provided in the contact holes 31. One end of the metal lead 32 is connected to the p-column 20, and the other end is connected to the pad 40.

[0040] In this embodiment, by applying a voltage across the two ends of the pad 40, the resistance value of the resistor bar 10 can be measured.

[0041] For the power device PCM monitoring structure of this embodiment, since the p-type ion implantation dose of the resistor bar 10 is the same as that of the corresponding pillar in the p-column 20, the resistance value of the corresponding pillar in the p-column 20 can be monitored by measuring the resistance value of the resistor bar 10, thereby determining the doping stability. For example, the resistance value of the resistor bar 10 corresponding to the first layer pillar 21, that is, the bottommost resistor bar 10, can be measured to monitor the resistance value of the first layer pillar 21, thereby determining the stability of the first doping of the p-column 20; the resistance value of the resistor bar 10 corresponding to the first layer pillar 21 and the second layer pillar 22, that is, the bottommost two resistor bars 10, can be measured to monitor the resistance values of the first layer pillar 21 and the second layer pillar 22, thereby determining the stability of the superposition of the first and second dopings of the p-column 20.

[0042] The PCM monitoring structure of the power device in this embodiment can monitor the resistance values of one or more layers of pillars of the p-column 20, solving the problem that the doping of one or more layers of pillars of the p-column 20 cannot be arbitrarily monitored.

[0043] The PCM monitoring structure of the power device according to the embodiment of the present invention designs and arranges multiple resistive strips stacked on the dicing lane of the wafer. The resistive strip is connected to two adjacent p-columns in the SJ MOS. The number of resistive strips is the same as the number of p-type ion implantation times of the p-column. By testing the resistance values of the resistive strips in the dicing lane, the detection of the resistance of any one or any multiple layers of pillars of the p-column of the SJ MOS in wafers of different Lots is realized. By comparing the differences in the resistance values of any one or any multiple layers of pillars of the p-column of the SJ MOS in wafers of different Lots, the corresponding relationship between pillar doping and BVDSS stability is confirmed. Through the comparison results, the factors causing BVDSS fluctuations can be accurately and quickly found, the stability of the mass production process can be better realized, the BVDSS fluctuations can be reduced, and thus the economic losses caused by BVDSS fluctuations can be reduced.

[0044] In a second aspect, the embodiment of the present invention provides a monitoring method for a PCM monitoring structure of a power device, including:

[0045] Step 1: Expose the resistive strip corresponding to the pillar to be monitored in the p-column of the SJ MOS.

[0046] In this embodiment, the pillar to be monitored can be any one or any multiple layers of pillars of the p-column of the SJ MOS.

[0047] Step 2: Apply a voltage on the pad to test the resistance value of the exposed resistive strip, and obtain the resistance detection value of the pillar to be monitored.

[0048] Step 3: Compare the resistance detection values of the pillars to be monitored of the SJ MOS in wafers of different Lots, and judge whether the BVDSS of the SJ MOS is stable according to the comparison results.

[0049] "Lot" refers to a group of wafers or a batch of products in the semiconductor manufacturing process. Usually, when manufacturing wafers, multiple wafers are placed together for the same process treatment, and this group of wafers is a "Lot". In this embodiment, when the difference in the resistance detection values of the pillars to be monitored of the SJ MOS in wafers of different Lots is greater than the preset threshold, the BVDSS of the SJMOS is unstable.

[0050] Furthermore, the monitoring method of the PCM monitoring structure of the power device in this embodiment is described in detail through specific examples.

[0051] Please refer toFigure 2 , Figure 2 is a schematic diagram of monitoring the resistance value of the first layer of pillar in the p-pillar through the power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 2 shown, for monitoring the doping of the first layer of pillar 21 in the p-pillar, first expose the resistor bar 10 corresponding to the first layer of pillar 21 in the p-pillar, that is, the bottommost resistor bar 10, and then apply a voltage on the pad 40 to test the resistance value of the bottommost resistor bar 10, so as to obtain the resistance detection value of the first layer of pillar 21 in the p-pillar. Through the above method, the resistance detection values of the first layer of pillar 21 in the SJ MOS of wafers in different Lots can be detected, and then compared. If the difference in the resistance detection values of the first layer of pillar 21 in the SJ MOS of wafers in different Lots is less than the preset threshold, then the first doping of the p-pillar 20 is stable, otherwise the first doping of the p-pillar 20 is unstable.

[0052] Please refer to Figure 3 , Figure 3 is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar in the p-pillar through the power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 3 shown, for monitoring the doping of the first layer of pillar 21 + the second layer of pillar 22 in the p-pillar, first expose the resistor bars 10 corresponding to the first layer of pillar 21 + the second layer of pillar 22 in the p-pillar, that is, the two bottommost resistor bars 10, and then apply a voltage on the pad 40 to test the resistance values of the two bottommost resistor bars 10, so as to obtain the resistance detection value of the first layer of pillar 21 + the second layer of pillar 22 in the p-pillar. Through the above method, the resistance detection values of the first layer of pillar 21 + the second layer of pillar 22 in the SJ MOS of wafers in different Lots can be detected, and then compared. If the difference in the resistance detection values of the first layer of pillar 21 + the second layer of pillar 22 in the SJ MOS of wafers in different Lots is less than the preset threshold, then the superposition of the first and second dopings of the p-pillar 20 is stable, otherwise the superposition of the first and second dopings of the p-pillar 20 is unstable.

[0053] Please refer to Figure 4 , Figure 4 is a schematic diagram of monitoring the resistance value of the first layer of pillar + the second layer of pillar + the third layer of pillar in the p-pillar through the power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 4As shown in the figure, for monitoring the doping of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 in the p pillar, first, the resistor bars 10 corresponding to the first layer pillar21 + the second layer pillar22 + the third layer pillar23 in the p pillar, that is, the three resistor bars 10 at the bottom layer, are exposed. Then, a voltage is applied to the pad 40 to test the resistance values of the three resistor bars 10 at the bottom layer, so as to obtain the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 in the p pillar. Through the above method, the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 in the p pillar of SJ MOS in wafers of different Lots can be detected, and then compared. If the difference in the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 in the p pillar of SJ MOS in wafers of different Lots is less than the preset threshold, then the first, second, and third doping superpositions of the p pillar 20 are stable; otherwise, the first, second, and third doping superpositions of the p pillar 20 are unstable.

[0054] Please refer to Figure 5 , Figure 5 is a schematic diagram of monitoring the resistance values of the first layer pillar + the second layer pillar + the third layer pillar + the fourth layer pillar in the p pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. As Figure 5As shown, for monitoring the doping of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 in the p pillar, first, the resistor bars 10 corresponding to the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 in the p pillar, that is, the four resistor bars 10 at the bottom layer, are exposed. Then, a voltage is applied on the pad 40 to test the resistance values of the four resistor bars 10 at the bottom layer, so as to obtain the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 in the p pillar. Through the above method, the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 in the p pillar of the SJ MOS in wafers of different Lots can be detected, and then compared. If the difference in the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 in the SJ MOS in wafers of different Lots is less than the preset threshold, then the first, second, third, and fourth doping superpositions of the p pillar 20 are stable; otherwise, the first, second, third, and fourth doping superpositions of the p pillar 20 are unstable.

[0055] Please refer to Figure 6 , Figure 6 is a schematic diagram of monitoring the resistance values of the first layer pillar + the second layer pillar + the third layer pillar + the fourth layer pillar + the fifth layer pillar in the p pillar through the power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 6As shown in the figure, for monitoring the doping of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 + the fifth layer pillar25 in the p pillar, first, expose the resistor bars 10 corresponding to the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 + the fifth layer pillar25 in the p pillar, that is, the five resistor bars 10 at the bottom layer. Then, apply a voltage on the pad 40 to test the resistance values of the five resistor bars 10 at the bottom layer, so as to obtain the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 + the fifth layer pillar25 in the p pillar. By the above method, the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 + the fifth layer pillar25 in the p pillar of SJ MOS in wafers of different Lots can be detected, and then compared. If the difference in the resistance detection values of the first layer pillar21 + the second layer pillar22 + the third layer pillar23 + the fourth layer pillar24 + the fifth layer pillar25 in the p pillar of SJ MOS in wafers of different Lots is less than the preset threshold, then the first, second, third, fourth, and fifth doping superpositions of the p pillar 20 are stable; otherwise, the first, second, third, fourth, and fifth doping superpositions of the p pillar 20 are unstable.

[0056] Please refer to Figure 7 , Figure 7 FIG. is a schematic diagram of monitoring the resistance value of the second layer pillar in the p pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. As Figure 7 shown in the figure, for monitoring the doping of the second layer pillar22 in the p pillar, first, expose the resistor bar 10 corresponding to the second layer pillar22 in the p pillar, that is, the second resistor bar 10 counted from the bottom up. Then, apply a voltage on the pad 40 to test the resistance value of this resistor bar 10, so as to obtain the resistance detection value of the second layer pillar22 in the p pillar. By the above method, the resistance detection values of the second layer pillar22 in the p pillar of SJ MOS in wafers of different Lots can be detected, and then compared. If the difference in the resistance detection values of the second layer pillar22 in the p pillar of SJ MOS in wafers of different Lots is less than the preset threshold, then the second doping of the p pillar 20 is stable; otherwise, the second doping of the p pillar 20 is unstable.

[0057] Please refer to Figure 8 , Figure 8It is a schematic diagram showing the monitoring of the resistance values of the second layer pillar + the third layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. As Figure 8 shown, for monitoring the doping of the second layer pillar 22 + the third layer pillar 23 in the p-pillar, first, the resistance bars 10 corresponding to the second layer pillar 22 + the third layer pillar 23 in the p-pillar, that is, the second and third resistance bars 10 counted from the bottom up, are exposed, and then a voltage is applied on the pad 40 to test the resistance values of these two resistance bars 10, so as to obtain the resistance detection values of the second layer pillar 22 + the third layer pillar 23 in the p-pillar. By the above method, the resistance detection values of the second layer pillar 22 + the third layer pillar 23 in the p-pillar of SJ MOS in wafers of different Lots can be detected, and then compared. If the difference in the resistance detection values of the second layer pillar 22 + the third layer pillar 23 in SJ MOS in wafers of different Lots is less than a preset threshold, then the superposition of the second and third doping of the p-pillar 20 is stable, otherwise the superposition of the second and third doping of the p-pillar 20 is unstable.

[0058] Please refer to Figure 9 , Figure 9 It is a schematic diagram showing the monitoring of the resistance values of the second layer pillar + the third layer pillar + the fourth layer pillar in the p-pillar through the power device PCM monitoring structure provided by an embodiment of the present invention. As Figure 9 shown, for monitoring the doping of the second layer pillar 22 + the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar, first, the resistance bars 10 corresponding to the second layer pillar 22 + the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar, that is, the second, third, and fourth resistance bars 10 counted from the bottom up, are exposed, and then a voltage is applied on the pad 40 to test the resistance values of these three resistance bars 10, so as to obtain the resistance detection values of the second layer pillar 22 + the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar. By the above method, the resistance detection values of the second layer pillar 22 + the third layer pillar 23 + the fourth layer pillar 24 in the p-pillar of SJ MOS in wafers of different Lots can be detected, and then compared. If the difference in the resistance detection values of the second layer pillar 22 + the third layer pillar 23 + the fourth layer pillar 24 in SJ MOS in wafers of different Lots is less than a preset threshold, then the superposition of the second, third, and fourth doping of the p-pillar 20 is stable, otherwise the superposition of the second, third, and fourth doping of the p-pillar 20 is unstable.

[0059] Please refer to Figure 10, Figure 10 It is a schematic diagram of monitoring the resistance value of the third - layer pillar in the p - column through the power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 10 shown, for monitoring the doping of the third - layer pillar 23 in the p - column, first, the resistor bar 10 corresponding to the third - layer pillar 23 in the p - column, that is, the third resistor bar 10 counted from bottom to top, is exposed. Then, a voltage is applied to the pad 40 to test the resistance value of the resistor bar 10, so as to obtain the resistance detection value of the third - layer pillar 23 in the p - column. Through the above method, the resistance detection values of the third - layer pillar 23 in the SJ MOS of wafers in different Lots can be detected, and then compared. If the difference in the resistance detection values of the third - layer pillar 23 in the SJ MOS of wafers in different Lots is less than the preset threshold, then the third doping of the p - column 20 is stable; otherwise, the third doping of the p - column 20 is unstable.

[0060] Please refer to Figure 11 , Figure 11 It is a schematic diagram of monitoring the resistance value of the third - layer pillar + the fourth - layer pillar in the p - column through the power device PCM monitoring structure provided by the embodiment of the present invention. As Figure 11 shown, for monitoring the doping of the third - layer pillar 23+the fourth - layer pillar 24 in the p - column, first, the resistor bars 10 corresponding to the third - layer pillar 23+the fourth - layer pillar 24 in the p - column, that is, the third and fourth resistor bars 10 counted from bottom to top, are exposed. Then, a voltage is applied to the pad 40 to test the resistance values of these two resistor bars 10, so as to obtain the resistance detection value of the third - layer pillar 23+the fourth - layer pillar 24 in the p - column. Through the above method, the resistance detection values of the third - layer pillar 23+the fourth - layer pillar 24 in the SJ MOS of wafers in different Lots can be detected, and then compared. If the difference in the resistance detection values of the third - layer pillar 23+the fourth - layer pillar 24 in the SJ MOS of wafers in different Lots is less than the preset threshold, then the superposition of the third and fourth dopings of the p - column 20 is stable; otherwise, the superposition of the third and fourth dopings of the p - column 20 is unstable.

[0061] Combined with the above examples, it can be seen that when using the power device PCM monitoring structure provided by the present invention for monitoring, by comparing the differences in the resistance values of any one or any multiple layers of the p-pillars of SJ MOS in wafers of different Lots, the corresponding relationship between pillar doping and BVDSS stability can be confirmed. Through the comparison results, the factors causing BVDSS fluctuations can be accurately and quickly found, the mass production process can be better stabilized, BVDSS fluctuations can be reduced, and thus the economic losses caused by BVDSS fluctuations can be reduced.

[0062] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0063] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A power device PCM monitoring structure, characterized in that: include: A plurality of stacked resistor bars are located in a dicing lane of a wafer, the resistor bars are connected to two adjacent p-pillars in an SJ MOS, the number of the resistor bars is the same as the number of p-type ion implantations of the p-pillars, the p-pillars include a plurality of pillars stacked from bottom to top, the pillars are formed by epitaxial layer growth and p-type ion implantation, the p-type ion implantation dosage of the resistor bars is the same as the p-type ion implantation dosage of the corresponding pillar in the p-pillars, and the detection of any one or more layers of pillar resistance of the p-pillars of the SJ MOS in wafers of different lots is achieved by measuring the resistance value of the resistor bars, and the corresponding relationship between pillar doping and BVDSS stability is confirmed by comparing the difference in the resistance value of any one or more layers of pillars of the p-pillars of the SJ MOS in wafers of different lots.

2. The power device PCM monitoring structure according to claim 1, characterized in that: The resistor bar is a rectangular parallelepiped structure formed by epitaxial layer growth and p-type ion implantation.

3. The power device PCM monitoring structure according to claim 2, characterized in that: The width-to-length ratio of the resistor strip is 10 / 1000.

4. The power device PCM monitoring structure according to claim 1, characterized in that: The invention also includes two contact holes arranged in the ILD layer, wherein the two contact holes correspond to positions of two adjacent p-columns in a one-to-one manner.

5. The power device PCM monitoring structure according to claim 4, characterized in that: A metal lead is arranged in the contact hole, one end of the metal lead is connected to the p-column, and the other end is connected to the pad.

6. A monitoring method for a power device PCM monitoring structure according to any one of claims 1 to 5, characterized in that: include: Expose the resistor strip corresponding to the pillar to be monitored in the p-column of the SJ MOS; Loading voltage on the pad to test the resistance value of the exposed resistor strip, and obtaining the resistance detection value of the pillar to be monitored; The resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots are compared, and whether the BVDSS of the SJ MOS is stable is determined according to the comparison result.

7. The monitoring method of the power device PCM monitoring structure according to claim 6, characterized in that: When the difference in resistance detection values ​​of the pillar to be monitored of the SJ MOS in wafers of different lots is greater than a preset threshold, the BVDSS of the SJ MOS is unstable.

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