Semiconductor element arrangement structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor element arrangement structure and a manufacturing method thereof. The semiconductor element arrangement structure comprises a carrier, a first semiconductor element, a second semiconductor element, a first adhesive part and a second adhesive part. The first semiconductor element and the second semiconductor element are located on the carrier separately from each other. The first adhesive portion and a second adhesive portion are separated from each other, the first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier. In a top view, the first adhesion part is provided with a first outer contour, and the first outer contour surrounds the first semiconductor element and is provided with at least one round corner.

Description

Technical Field

[0001] The present invention relates to a semiconductor element arrangement structure, and in particular to a semiconductor element arrangement structure in which semiconductor elements are adhered to a carrier board and a manufacturing method thereof. Background Art

[0002] Semiconductor components such as light-emitting diodes (LEDs) have the advantages of low power consumption, low heat generation, long service life, shock resistance, small size, fast response speed, and good photoelectric properties (such as stable light emission wavelength). Therefore, they are widely used in electronic devices such as household appliances, equipment indicator lights, and displays.

[0003] In order to manufacture different electronic devices, a large number of light-emitting diodes need to be transferred between different substrates. The steps usually include transferring multiple light-emitting diodes from the growth substrate to a temporary substrate, and fixing the multiple light-emitting diodes on it through an adhesive layer on the temporary substrate. After that, an etching process is used to remove the adhesive layer between adjacent light-emitting diodes.

[0004] However, in order to completely remove the adhesive layer between adjacent LEDs during the etching process, the etching process often takes a long time, and the heat generated by the etching process may also cause some LEDs to be skewed in the vertical direction or offset in the horizontal direction. This not only makes the manufacturing process time-consuming and reduces the yield, but is also not conducive to subsequent manufacturing processes. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor device arrangement structure and a manufacturing method thereof to overcome the technical problems encountered in the prior art.

[0006] According to one embodiment of the present invention, a semiconductor element arrangement structure is provided, comprising a carrier, a first semiconductor element, a second semiconductor element, a first adhesive portion, and a second adhesive portion. The first semiconductor element and the second semiconductor element are separated from each other and are located on the carrier. The first adhesive portion and a second adhesive portion are separated from each other, and the first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier. In a top view, the first adhesive portion has a first outer contour, the first outer contour surrounds the first semiconductor element and has at least one rounded corner.

[0007] According to one embodiment of the present invention, a method for manufacturing a semiconductor element arrangement structure is provided, comprising: providing a first supporting substrate, a first semiconductor element, and a second semiconductor element, wherein the first semiconductor element and the second semiconductor element are located on the first supporting substrate and are separated from each other; providing a second supporting substrate, wherein the second supporting substrate comprises a carrier and an adhesive layer disposed on the carrier; moving the first semiconductor element and the second semiconductor element so that the first semiconductor element and the second semiconductor element contact the adhesive layer; heating the adhesive layer so that the adhesive layer is deformed into a first adhesive portion and a second adhesive portion that are separated from each other, and a gap portion is formed between the first adhesive portion and the second adhesive portion to expose the carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to when reading the present invention. The specific embodiments of the present invention are explained in detail through the specific embodiments in this article and with reference to the corresponding drawings, and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the sizes of some features in some drawings may be deliberately enlarged or reduced.

[0009] Figure 1a is a top view of a semiconductor element arrangement structure according to an embodiment of the present invention;

[0010] Figure 1b An embodiment of the present invention Figure 1a A magnified view of a local area;

[0011] Figure 2a An embodiment of the present invention is along the Figure 1b a cross-sectional view depicted along section line AA';

[0012] Figure 2b An embodiment of the present invention is along the Figure 1b a cross-sectional view depicted along section line BB';

[0013] Figure 3a An embodiment of the present invention Figure 2a A magnified view of a local area;

[0014] Figure 3b An embodiment of the present invention Figure 2b A magnified view of a local area;

[0015] Figure 4a Another embodiment of the present invention is along the Figure 1b a cross-sectional view depicted along section line AA';

[0016] Figure 4b This is an embodiment of the present invention Figure 4a A magnified view of a local area;

[0017] Figure 5 is a partial enlarged view of the semiconductor element arrangement structure of some embodiments of the present invention;

[0018] Figure 6 It is a top view of a plurality of semiconductor elements formed on a growth substrate at a certain manufacturing process stage according to an embodiment of the present invention;

[0019] Figure 7 is a cross-sectional view of different stages of a manufacturing process for transferring a plurality of semiconductor elements from a growth substrate to a support substrate according to an embodiment of the present invention;

[0020] Figure 8 is a top view and a cross-sectional view of a second supporting substrate in a certain manufacturing process stage according to an embodiment of the present invention;

[0021] Fig. 9 is a cross-sectional view of different stages of a manufacturing process for transferring a plurality of semiconductor elements from a first supporting substrate to a second supporting substrate according to an embodiment of the present invention;

[0022] Fig.10 is a cross-sectional view of different stages of a fabrication process for transferring a selected semiconductor element from a second support substrate to a third support substrate according to an embodiment of the present invention;

[0023] Fig.11 The invention is a cross-sectional view of different stages of a manufacturing process for transferring a plurality of semiconductor components from a first supporting substrate to a second supporting substrate according to another embodiment of the present invention.

[0024] Explanation of symbols

[0025] 100, 512, 712… carrier

[0026] 101…Compound carrier

[0027] 102, 110a, 402, 502, 602, 702…front

[0028] 103…Exposed surface

[0029] 104, 110b, 216, 404, 504, 604, 704…back

[0030] 110…Semiconductor components

[0031] 110-1 ... first semiconductor element

[0032] 110-2 ... second semiconductor element

[0033] 110-3…third semiconductor element

[0034] 112…Sharp corner

[0035] 114a…first outermost edge

[0036] 114b…second outermost edge

[0037] 120…Component body

[0038] 122…Electrode

[0039] 124…Substrate

[0040] 126…Semiconductor stack

[0041] 128…Depression area

[0042] 130…lower surface

[0043] 130a, 130b…virtual extension cord

[0044] 200…Adhesive part

[0045] 200-1…First adhesive part

[0046] 200-2…Second adhesive part

[0047] 200-3…Third adhesive part

[0048] 202…Rounded Corners

[0049] 204a, 204b…arc-shaped side

[0050] 212…Overflow

[0051] 214…Filling part

[0052] 300…Gap

[0053] 300-1…First gap

[0054] 300-2…Second gap

[0055] 400…Growth substrate

[0056] 500…First supporting substrate

[0057] 514…Joint layer

[0058] 600…Second supporting substrate

[0059] 612…Polymer layer

[0060] 614…Adhesive layer

[0061] 616…Patterned polymer layer

[0062] 700…Third supporting substrate

[0063] 714…Adhesion layer

[0064] 1000…Semiconductor element arrangement structure

[0065] A-A', B-B'... section line

[0066] L1, L2, L3, L1', L2', L3'...shortest distance

[0067] R1, R3, R4, R5…local area

[0068] S100, S102, S104, S106, S108, S110, S112, S112', S114, S114', S116, S116', S117, S118, S120...steps

[0069] T1, T2, T3...Thickness

[0070] T4…Total thickness DETAILED DESCRIPTION

[0071] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only to illustrate, not to limit in any way. Various embodiments in the present invention may use repeated reference symbols and / or text notes. The use of these repeated reference symbols and notes is to make the description more concise and clear, rather than to indicate the relevance between different embodiments and / or configurations.

[0072] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the orientation of each element during use and operation. As the orientation of each element is different (rotated 90 degrees or other orientations), the related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0073] Although the present invention uses the terms first, second, third, etc. to describe elements, components, regions, layers, and / or blocks (Section), it should be understood that these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and / or block from another element, component, region, layer, and / or block, and they themselves do not imply or represent any previous ordinal number of the element, nor do they represent the order of arrangement of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.

[0074] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0075] The terms "coupling", "coupling", and "electrical connection" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0076] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of ordinary technicians in the relevant technical field.

[0077] Figure 1a is a top view of a semiconductor element arrangement structure according to an embodiment of the present invention, Figure 1b yes Figure 1a A partial enlarged view of the arrangement structure of semiconductor components. Figure 1a As shown, the semiconductor device arrangement structure 1000 includes a carrier 100, a plurality of semiconductor devices 110, and a plurality of adhesive portions 200. The plurality of semiconductor devices 110 are separated from each other and are located on the carrier 100. The plurality of adhesive portions 200 are separated from each other and are disposed between the corresponding semiconductor devices 110 and the carrier 100. Figure 1bAs shown, each adhesive portion 200 has an outer contour, and the outer contour surrounds the semiconductor element 110 and has at least one round corner 202 . In contrast, the semiconductor element 110 has at least one sharp corner 112 .

[0078] like Figure 1a As shown in the top view of the carrier 100, the semiconductor element 110 and the adhesive portion 200 are disposed on the front side 102 of the carrier 100. According to an embodiment of the present invention, the carrier 100 is used to support the semiconductor element 110 disposed on the front side 102 thereof. According to an embodiment of the present invention, the carrier 100 may be a non-epitaxial material or a non-growth substrate, such as a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to an embodiment of the present invention, the carrier 100 is a substrate that allows laser penetration, such as a glass substrate, a sapphire substrate, or a quartz substrate, so that the semiconductor element 110 can be separated from the carrier 100 by a laser lift-off (LLO) manufacturing process. According to one embodiment, when performing the laser lift-off process, the laser may be incident from the back side of the carrier 100 into the carrier 100, and penetrate from the front side 102 of the carrier 100 to irradiate the adhesive portion 200 disposed on the front side 102, so that the adhesive portion 200 is partially or entirely decomposed or vaporized, thereby causing the semiconductor element 110 to be lifted off from the carrier 100. In addition, the carrier 100 is electrically insulated from the semiconductor element 110, so that electrical signals are not transmitted between the carrier 100 and the semiconductor element 110.

[0079] The semiconductor element 110 may include a transistor element or a semiconductor light emitting element, such as a light emitting diode element, but is not limited thereto. Figure 1aAs shown, two adjacent semiconductor elements 110 are separated from each other, and in the same column or row, the shortest distance between the two adjacent semiconductor elements 110 is 1 μm to 50 μm. According to one embodiment, the shortest distance between two adjacent semiconductor elements 110 is less than the diagonal length of a single semiconductor element 110 in a top view, for example, the shortest distance between two adjacent semiconductor elements 110 is 1 / 20 to 1 / 5 of the diagonal length of a single semiconductor element 110, but is not limited thereto. A plurality of semiconductor elements 110 are arranged on the carrier 100 into a specific layout or pattern, for example, a plurality of semiconductor elements 110 are arranged on the carrier 100 into an array, but is not limited thereto. According to one embodiment, a plurality of semiconductor elements 110 are arranged into a concentric pattern, for example, concentric circles.

[0080] Two adjacent adhesive portions 200 are separated from each other and are used to fix the corresponding semiconductor element 110 to the carrier 100. The plurality of adhesive portions 200 can be arranged in a specific layout or pattern, and the layout or pattern thereof corresponds to the layout or pattern of the plurality of semiconductor elements 110. According to one embodiment, the plurality of adhesive portions 200 can be arranged in an array or concentric circles, but is not limited thereto. The material of the adhesive portion 200 can be a polymer, for example, the adhesive portion 200 can include polyimide (PI), epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), cycloolefin (COP), or benzocyclobutane (BCB), but is not limited thereto.

[0081] Figure 1b for Figure 1a An enlarged view of region R1 in FIG. In region R1, semiconductor elements 110 are arranged in a 3×3 array (i.e., 3 rows and 3 columns), and gaps 300 are provided between two adjacent rows and between two adjacent columns of semiconductor elements 110, for example, first gaps 300-1 and second gaps 300-2. According to one embodiment, each first gap 300-1 extends along a first direction (e.g., the Y direction), and each second gap 300-2 extends along a second direction (e.g., the X direction) different from the first direction. In addition, as Figure 1b As shown, the first gap portion 300 - 1 and the second gap portion 300 - 2 penetrate the adhesive portion 200 to expose the front surface 102 of the carrier 100 . In short, each semiconductor element 110 and each adhesive portion 200 are surrounded by the gap portion 300 .

[0082] like Figure 1bAs shown, the semiconductor element 110 includes a first semiconductor element 110-1, a second semiconductor element 110-2, a third semiconductor element 110-3, ... and an m-th semiconductor element 110-m, where m is a positive integer greater than 3. The first semiconductor element 110-1 and the second semiconductor element 110-2 are located in the same column and are arranged along the X direction. The first semiconductor element 110-1 and the third semiconductor element 110-3 are located in the same row and are arranged along the Y direction. According to one embodiment, each semiconductor element 110 (e.g., the first semiconductor element 110-1, the second semiconductor element 110-2, and the third semiconductor element 110-3) includes a plurality of outermost edges, for example, two opposite first outermost edges 114a and two opposite second outermost edges 114b, and the first outermost edge 114a and the second outermost edge 114b are adjacent to each other. According to one embodiment, each semiconductor element 110 (e.g., the first semiconductor element 110-1, the second semiconductor element 110-2, and the third semiconductor element 110-3) has a plurality of sharp corners 112, each of which is composed of a first outermost edge 114a and a second outermost edge 114b. According to one embodiment, each semiconductor element 110 has a projected area in the Z direction, and the projected area is 50 μm 2 Up to 5000μm 2 .

[0083] like Figure 1b As shown, the adhesive portion 200 includes a first adhesive portion 200-1, a second adhesive portion 200-2, a third adhesive portion 200-3 ... and an mth adhesive portion 200-m, wherein m is a positive integer greater than 3. The first adhesive portion 200-1 and the second adhesive portion 200-2 are located in the same column and are arranged along the X direction, and the first adhesive portion 200-1 and the third adhesive portion 200-3 are located in the same row and are arranged along the Y direction. Each adhesive portion 200 has an outer contour, the area of ​​the outer contour is greater than the area of ​​the corresponding semiconductor element 110, and the outer contour surrounds the corresponding semiconductor element 110. That is, the first outermost edge 114a and the second outermost edge 114b of the semiconductor element 110 are located within the outer contour of the adhesive portion 200. According to one embodiment, each adhesive portion 200 (for example, the first adhesive portion 200-1, the second adhesive portion 200-2, and the third adhesive portion 200-3) has a plurality of rounded corners. According to one embodiment, each adhesive portion 200 has a projected area in the Z direction, for example, 55 μm 2 Up to 6000μm 2 , this projection area is larger than the projection area of ​​the corresponding semiconductor element 110 in the Z direction.

[0084] Figure 2a and Figure 2b Show along Figure 1bThe cross-sectional view shown by the section line AA' and the section line BB'. Figure 2a As shown, the carrier 100 has a front side 102 and a back side 104 opposite to each other. The first gap portion 300-1 (300) is located between the first semiconductor element 110-1 and the second semiconductor element 110-2, and exposes the front side 102 of the carrier 100. The first outermost edges 114a of the first semiconductor element 110-1 and the second semiconductor element 110-2 face each other, and the shortest distance L1 between the two opposite first outermost edges 114a is 1 μm to 50 μm. According to one embodiment, the first semiconductor element 110-1 and the second semiconductor element 110-2 have the same or similar epitaxial structure. Each semiconductor element 110 includes an element body 120 and at least two electrodes 122. The element body 120 includes a plurality of semiconductor layers stacked on each other (not shown). The electrode 122 is disposed on one side (e.g., the front side) of the element body 120, and the adhesive portion 200 is disposed on the other side (e.g., the back side) of the element body 120. The electrode 122 may include a single-layer or multi-layer metal structure, and the electrode 122 includes at least one material selected from the group consisting of chromium (Cr), nickel (Ni), titanium (Ti), platinum (Pt), palladium (Pd), silver (Ag), gold (Au), aluminum (Al), and copper (Cu).

[0085] The structure of each semiconductor element 110 is not limited to Figure 2a and Figure 2b According to the structure shown in the figure, according to one embodiment, each semiconductor element 110 includes a redistribution layer (RDL) (not shown), which is arranged on the front side of the element body 120. The redistribution layer includes conductive interconnects, vias, and conductive pads. The conductive pads may have a specific layout pattern for forming a specific conductive channel and electrically connecting to an external circuit. In addition, according to one embodiment, each semiconductor element 110 may include a fan-out package structure, so that the element body 120 includes at least one semiconductor chip and a molding material surrounding the chip, but is not limited thereto.

[0086] The adhesive portion 200 is located between the semiconductor element 110 and the carrier 100, for example, the first adhesive portion 200-1 is located between the first semiconductor element 110-1 and the carrier 100, and the second adhesive portion 200-2 is located between the second semiconductor element 110-2 and the carrier 100. According to one embodiment, the adhesive portion 200 is composed of a cross-linked and cured polymer, such as polyimide (PI), epoxy (EPO), polybenzoxazole (PBO), silicone (Polysiloxane), cycloolefin (COP), or benzocyclobutane (BCB), but is not limited thereto. The thickness T1 (or average thickness) of the adhesive portion 200 is 50 nm to 2 μm. When the thickness T1 of the adhesive portion 200 is too thin (depending on the material used), for example, less than 50 nm, the adhesion between the semiconductor element 110 and the carrier 100 may be insufficient, and when the thickness T1 of the adhesive portion 200 is too thick (depending on the material used), for example, greater than 2 μm, two adjacent adhesive portions 200 may easily stick to each other. The shortest distance L1' between the first adhesive portion 200-1 and the second adhesive portion 200-2 is 0.5 μm to 40 μm.

[0087] like Figure 2b As shown, the second gap portion 300-2 (300) is located between the first semiconductor element 110-1 and the third semiconductor element 110-3, and exposes the front side 102 of the carrier 100. The two adjacent second outermost edges 114b of the first semiconductor element 110-1 and the third semiconductor element 110-3 face each other, and the shortest distance L2 between them is 1μm to 50μm. According to one embodiment, the first semiconductor element 110-1 and the third semiconductor element 110-3 have the same or similar epitaxial structure. Each semiconductor element 110 includes an element body 120 and at least one electrode 122. According to one embodiment, the electrode 122 is disposed on one side (e.g., the front side) of the element body 120, and the adhesive portion 200 is disposed on the other side (e.g., the back side) of the element body 120. The adhesive portion 200 is located between the semiconductor element 110 and the carrier 100. For example, the first adhesive portion 200-1 is located between the first semiconductor element 110-1 and the carrier 100, and the third adhesive portion 200-3 is located between the third semiconductor element 110-3 and the carrier 100. The shortest distance L2' between the first adhesive portion 200-1 and the third adhesive portion 200-3 is 0.5 μm to 40 μm.

[0088] Figure 3a and Figure 3b is a cross-sectional view of an embodiment of the present invention, corresponding to Figure 2a and Figure 2b The local area, where Figure 3a The local area R3 corresponds to Figure 2a The local area R3, Figure 3b The local area R4 corresponds to Figure 2b The local area R4. Figure 3a As shown, according to one embodiment, the first semiconductor element 110-1 and the other semiconductor elements 110 are semiconductor light-emitting elements, and the element body 120 of the first semiconductor element 110-1 includes a substrate 124 and a semiconductor stack 126. The semiconductor stack 126 is disposed between the electrode 122 and the substrate 124, and is electrically connected to the electrode 122. According to one embodiment, the semiconductor stack 126 sequentially includes a first semiconductor layer (not shown), a light-emitting layer (not shown), and a second semiconductor layer (not shown), wherein the first semiconductor layer and the second semiconductor layer respectively include dopants of different conductive types, such as n-type dopants and p-type dopants, so that the first semiconductor layer and the second semiconductor layer can supply electrons and holes respectively.

[0089] According to one embodiment, the back side of the substrate 124 includes a plurality of recessed areas 128 facing the carrier 100. The opening diameter of each recessed area 128 is 1 μm to 4 μm, and the depth is 300 nm to 2 μm. The recessed areas 128 have a repeated shape and are distributed on the entire bottom surface of the substrate 124 (distributed along the XY plane). By providing the recessed areas 128, the luminous efficiency of the first semiconductor element 110-1 can be increased or the profile of the light distribution curve can be adjusted. In addition, since the first adhesive portion 200-1 fills or fills each recessed area 128, the adhesion between the first semiconductor element 110-1 and the carrier 100 can be increased without changing the material or overall thickness of the first adhesive portion 200-1.

[0090] According to one embodiment, each adhesive portion 200 (e.g., the first adhesive portion 200-1) includes an overflow portion 212 and a filling portion 214. The overflow portion 212 protrudes from the first outermost edge 114a of the first semiconductor element 110-1 and covers a portion of the first outermost edge 114a, such as covering a portion of the outermost edge of the substrate 124. According to one embodiment, the overflow portion 212 has an arc-shaped side edge 204a corresponding to the first outermost edge 114a, and the arc-shaped side edge 204a is recessed toward the carrier 100. According to one embodiment, the first outermost edge 114a is an inclined surface, and a virtual extension line 130a extending from the first outermost edge 114a to the carrier 100 is located within the arc-shaped side edge 204a. The filling portion 214 is located between the first semiconductor element 110-1 and the carrier 100, and the maximum thickness of the overflow portion 212 is greater than the minimum thickness of the filling portion 214.

[0091] like Figure 3bAs shown, according to one embodiment, the bottom surface of the substrate 124 includes a plurality of recessed areas 128 facing the carrier 100. The recessed areas 128 have a repeated shape and are distributed on the entire bottom surface of the substrate 124 (distributed along the XY plane). According to one embodiment, the overflow portion 212 of the first adhesive portion 200-1 protrudes from the second outermost edge 114b of the first semiconductor element 110-1 and covers a portion of the second outermost edge 114b. According to one embodiment, the overflow portion 212 has an arc-shaped side edge 204b corresponding to the second outermost edge 114b, and the arc-shaped side edge 204b is recessed toward the carrier 100. According to one embodiment, the slope of the second outermost edge 114b is greater than the slope of the first outermost edge 114a, for example, the second outermost edge 114b is a vertical plane, and the virtual extension line 130b of the second outermost edge 114b extending toward the carrier 100 is located within the arc-shaped side edge 204b. The filling portion 214 is located between the lower surface 130 of the first semiconductor element 110 - 1 and the carrier 100 , and the maximum thickness of the overflow portion 212 is greater than the minimum thickness of the filling portion 214 .

[0092] Figure 4a Another embodiment of the present invention is along the Figure 1b The cross-sectional view shown by the section line A-A'. Figure 4a As shown, it is similar to Figure 2a The main difference is that the electrodes 122 of the first semiconductor element 110-1 and the second semiconductor element 110-2 face the carrier 100 instead of being away from the carrier 100, and are separated from the carrier 100 by the first adhesive portion 200-1 and the second adhesive portion 200-2 respectively.

[0093] Figure 4b for Figure 4a A magnified schematic diagram of the local area R5. Figure 4b As shown, it is similar to Figure 3a , the main difference is that the recessed area 128 of the substrate 124 of the first semiconductor element 110-1 is away from the carrier 100, rather than facing the carrier 100. According to one embodiment, the overflow portion 212 of the first adhesive portion 200-1 protrudes from the first outermost edge 114a of the first semiconductor element 110-1, and covers a portion of the first outermost edge 114a, for example, covers a portion of the outermost edge of the semiconductor stack 126. According to one embodiment, the overflow portion 212 has an arc-shaped side edge 204a corresponding to the first outermost edge 114a, and the arc-shaped side edge 204a is recessed toward the carrier 100. According to one embodiment, the first outermost edge 114a is an inclined surface, and a virtual extension line 130a extending from the first outermost edge 114a to the carrier 100 is located within the arc-shaped side edge 204a. The filling portion 214 is located between the lower surface 130 of the first semiconductor element 110 - 1 and the carrier 100 , and the maximum thickness of the overflow portion 212 is greater than the minimum thickness of the filling portion 214 .

[0094] Figure 5 FIG. 1 is a schematic top view of a local area of ​​a semiconductor element arrangement structure in some embodiments of the present invention. Figure 5 As shown, Figure 5 Roughly corresponds to Figure 1a and Figure 1b The local area R1 of the semiconductor device 110 is mainly different in that the number of the sharp corners 112 of the semiconductor device 110 and the number of the rounded corners 202 of the adhesive portion 200 are not 4, but 3 and 6 respectively, and the sharp corners of the semiconductor device 110 are arranged corresponding to the positions of the rounded corners of the adhesive portion 200. According to one embodiment, the number of the sharp corners 112 of the semiconductor device 110 and the number of the rounded corners 202 of the adhesive portion 200 can also be other positive integers. For example, each semiconductor device 110 has n sharp corners, each adhesive portion 200 has n rounded corners, n is a positive integer greater than or equal to 3, and the n sharp corners of the semiconductor device 110 are arranged corresponding to the positions of the n rounded corners of the adhesive portion 200. According to one embodiment, the shortest distances L1 and L2 between adjacent semiconductor devices 110 are 1 μm to 50 μm, and the shortest distances L1' and L2' between adjacent adhesive portions 200 are 0.5 μm to 40 μm.

[0095] In order to enable those skilled in the art to implement the invention, the method for manufacturing the semiconductor element arrangement structure of the invention is further described in detail below.

[0096] Figure 6 FIG. 1 is a top view schematic diagram of a plurality of semiconductor elements disposed on a growth substrate at a certain manufacturing process stage according to an embodiment of the present invention. Figure 6 As shown, in step S100, a growth substrate 400 (which can be regarded as a support substrate) is provided, and a plurality of semiconductor elements 110 are formed on the front surface 402 of the growth substrate 400. According to an embodiment of the present invention, the growth substrate 400 includes an epitaxial material, such as silicon (Si), germanium (Ge), lithium aluminate (LiAlO 2 ), zinc oxide (ZnO), silicon carbide (SiC), sapphire (Sapphire), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium phosphide (InP).

[0097] Adjacent semiconductor elements 110 are separated from each other. According to one embodiment, the shortest distance L3 between adjacent semiconductor elements 110 is 1 μm to 50 μm, and the shortest distance L3 is less than the diagonal length of each semiconductor element 110 in a top view. For example, the distance between adjacent semiconductor elements 110 is 1 / 20 to 1 / 5 of the diagonal length of each semiconductor element 110, but is not limited thereto. Multiple semiconductor elements 110 form a specific arrangement layout, such as being arranged in an array structure on a growth substrate 400, but is not limited thereto. According to one embodiment, multiple semiconductor elements 110 are arranged in a concentric pattern (Concentric Pattern), such as concentric circles.

[0098] Figure 7 It is a cross-sectional schematic diagram of different manufacturing process stages of transferring multiple semiconductor elements from a growth substrate to a support substrate according to an embodiment of the present invention. In step S102, the semiconductor element 110 on the growth substrate 400 faces the first support substrate 500. According to one embodiment, the growth substrate 400 has a front side 402 and a back side 404 opposite to each other, and the semiconductor element 110 is formed on the front side 402 of the growth substrate 400. The semiconductor element 110 has a front side 110a and a back side 110b opposite to each other, the front side 110a is away from the growth substrate 400, and the back side 110b faces the growth substrate 400. The first support substrate 500 has a front side 502 and a back side 504 opposite to each other, the front side 502 faces the growth substrate 400, and the back side 504 is away from the growth substrate 400. The first support substrate 500 may be a non-epitaxial material or a non-growth substrate, for example, a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to one embodiment, the first support substrate 500 includes a carrier 512 and a bonding layer 514. The carrier 512 has sufficient mechanical strength to support the bonding layer 514. The bonding layer 514 has sufficient adhesion to fix the components pressed onto its surface.

[0099] In step S104, at least one of the growth substrate 400 and the first support substrate 500 is moved to make the semiconductor element 110 contact the first support substrate 500 and be fixed to the bonding layer 514. According to one embodiment, the semiconductor element 110 can be fixed to the bonding layer 514 of the first support substrate 500 by using a thermal compression process.

[0100] In step S106, a separation process is performed to separate the growth substrate 400 from the semiconductor element 110, thereby exposing the back side 110b of the semiconductor element 110. According to one embodiment, a laser lift-off process may be used to irradiate a laser from the back side 404 of the growth substrate 400 toward the front side 402 to vaporize the semiconductor material between the semiconductor element 110 and the growth substrate 400, such as gallium nitride, aluminum nitride, or other compound semiconductor materials, thereby separating the semiconductor element 110 from the growth substrate 400.

[0101] In step S106, the semiconductor element 110 is cleaned to remove semiconductor residues or metal residues, such as gallium-containing particles, remaining on the back surface 110b of the semiconductor element 110. Therefore, the semiconductor element 110 is prevented from being affected in light extraction efficiency by residues with low light transmittance.

[0102] Through the above Figure 7 In step S106 to step S108, a plurality of semiconductor elements 110 (including at least a first semiconductor element and a second semiconductor element) are transferred from a growth substrate 400 (which can be regarded as a support substrate) to a first support substrate 500. The plurality of semiconductor elements 110 are located on the first support substrate 500 and are separated from each other. According to one embodiment, the arrangement of the semiconductor elements 110 on the growth substrate 400 is similar to or the same as the arrangement of the semiconductor elements 110 on the first support substrate 500.

[0103] Figure 8 1 is a schematic diagram of a top view and a cross-section view of a second supporting substrate at a certain manufacturing process stage of an embodiment of the present invention. Figure 8As shown, in step S110, a second supporting substrate 600 is provided, the second supporting substrate 600 has a front side 602 and a back side 604 opposite to each other, and includes a carrier 100 and a continuously distributed adhesive layer 614. The adhesive layer 614 is disposed on the front side 102 of the carrier 100, and has a uniform thickness, for example, 50 nm to 2 μm. According to one embodiment, the adhesive layer 614 contains a cross-linking agent and an un-cured polymer, and the un-cured polymer includes polyimide (PI), epoxy resin (EPO), polybenzoxazole (PBO), silicone resin (Polysiloxane), polycycloolefin (COP), or benzocyclobutane (BCB), but is not limited thereto. According to one embodiment, the adhesive layer 614 is manufactured by, for example, spin coating to coat the liquid adhesive material on the front side 102 of the carrier 100 , and then soft baking to remove part of the solvent in the liquid adhesive material to form an adhesive layer 614 without fluidity.

[0104] Fig. 9 1 is a cross-sectional schematic diagram of different manufacturing process stages of transferring a plurality of semiconductor elements from a first supporting substrate to a second supporting substrate according to an embodiment of the present invention. In step S112, the front surface 502 of the first supporting substrate 500 faces the front surface 602 of the second supporting substrate 600, and at least one of the first supporting substrate 500 and the second supporting substrate 600 is moved so that the semiconductor element 110 located on the first supporting substrate 500 contacts the adhesive layer 614 of the second supporting substrate 600. By performing step S112, the thickness of the adhesive layer 614 located between adjacent semiconductor elements 110 will increase slightly, for example, by 5% to 30%. However, when the increased thickness exceeds 50%, it will cause the two adjacent semiconductor elements 110 to be unable to be peeled off from the carrier separately in the subsequent process, which is not conducive to the transfer of the semiconductor elements 110.

[0105] Next, referring to step S112 and step S114, a heating process is performed while the first support substrate 500 and the second support substrate 600 are pressed together, so that the adhesive layer 614 forms the adhesive portions 200 (including the first adhesive portion 200-1 and the second adhesive portion 200-2) separated from each other. According to one embodiment, in the early stage of the heating process, the viscosity of the adhesive layer 614 is reduced and has fluidity. Due to the surface tension of the adhesive layer 614 itself, the adhesive layer 614 is deformed during the heating process and aggregates (or self-aggregates) toward the adjacent semiconductor element 110, and is split from a single continuous layer into at least two separated parts, such as the separated adhesive portions 200, and exposes the front side 102 of the carrier 100 located between the adjacent semiconductor elements 110. In other words, during the heating process, the area of ​​the carrier 100 covered by the adhesive layer 614 is reduced. When the adhesive part 200 is continuously heated, the viscosity of the adhesive part 200 continues to increase due to the gradual increase in the degree of cross-linking between the uncross-linked polymers in the adhesive part 200, until the adhesive part 200 is solidified into a solid adhesive part 200. There are gaps 300 between the solid adhesive parts 200, exposing the front side 102 of the carrier 100.

[0106] According to one embodiment, the back surface 110b of the semiconductor element 110 has a plurality of recessed areas (eg Figure 3a and Figure 3b In the heating stage of step S114 , the adhesive layer 614 having fluidity will fill up the recessed area due to the capillary phenomenon, thereby increasing the adhesion between the semiconductor element 110 and the adhesive portion 200 .

[0107] In step S116, a separation process is performed to separate the first support substrate 500 from the semiconductor element 110 and expose the front surface 110a of the semiconductor element 110. According to one embodiment, a laser lift-off process can be used to irradiate a laser from the back surface 504 of the first support substrate 500 to the front surface 502 to decompose or vaporize the bonding layer 514 between the semiconductor element 110 and the first support substrate 500, so that the semiconductor element 110 is separated from the first support substrate 500, and a similar Figure 1a and Figure 1b A semiconductor device arrangement structure 1000 is shown.

[0108] According to an embodiment of the present invention, adjacent adhesive portions 200 are self-assembled to form a self-isolation structure that is separated from each other, thereby eliminating the need to perform an etching process on the adhesive portions 200 between adjacent semiconductor elements 110, or significantly reducing the time required for performing the etching process. In addition, since the etching process is eliminated or the time required for performing the etching process is reduced, the semiconductor element 110 is prevented from being skewed or offset due to external forces generated by the etching process.

[0109] According to the method for manufacturing the semiconductor element arrangement structure, the semiconductor element 110 is first transferred from the growth substrate 400 to the first support substrate 500, and then to the second support substrate 600, but the present invention is not limited thereto. According to one embodiment, the growth substrate 400 can be regarded as a support substrate, and the semiconductor element 110 can be directly transferred from the growth substrate 400 to the second support substrate 600.

[0110] After the arrangement structure shown in step S116 is completed, some of the semiconductor elements 110 on the second support substrate 600 can be further selectively transferred to other support substrates to group the semiconductor elements 110 with similar or identical electrical or optical specifications. The steps are similar to those shown in FIG. Fig.10 shown.

[0111] Fig.101 is a cross-sectional view of different manufacturing process stages of transferring a semiconductor element from a second supporting substrate to a third supporting substrate according to an embodiment of the present invention. In step S118, the semiconductor element 110 on the carrier 100 is placed facing the third supporting substrate 700. According to one embodiment, the third supporting substrate 700 has a front side 702 and a back side 704 opposite to each other, the front side 702 faces the carrier 100, and the back side 704 is away from the carrier 100. The third supporting substrate 700 can be a non-epitaxial material or a non-growth substrate, for example, a ceramic substrate, a metal substrate, a glass substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to one embodiment, the third supporting substrate 700 includes a carrier 712 and an adhesive layer 714. The carrier 712 has sufficient mechanical strength to support the adhesive layer 714. The adhesive layer 714 has sufficient adhesiveness to fix the components pressed onto its surface. Next, when the front surface 102 of the carrier 100 faces the front surface 702 of the third supporting substrate 700, at least one of the carrier 100 and the third supporting substrate 700 is moved so that the semiconductor element 110 on the carrier 100 contacts the adhesive layer 714 of the third supporting substrate 700.

[0112] In step S120, a separation process is performed to transfer the selected semiconductor element 110 (e.g., the first semiconductor element 110-1) from the carrier 100 to the third supporting substrate 700, and expose the back surface 216 of the first adhesive portion 200-1. The other unselected semiconductor elements 110 (e.g., the second semiconductor element 110-2) remain on the front surface 102 of the carrier 100. According to one embodiment, a laser lift-off process can be used to irradiate the selected first semiconductor element 110-1 with a laser to decompose or vaporize the first adhesive layer 200-1 between the first semiconductor element 110-1 and the carrier 100, so that the first semiconductor element 110 is separated from the carrier 100. The unselected semiconductor elements 110 are not irradiated by the laser, and thus remain on the front surface 102 of the carrier 100. According to one embodiment, in a subsequent manufacturing process, other selected semiconductor elements 110 (e.g., a second semiconductor element 110-2) can continue to be transferred from the carrier 100 to other supporting substrates (not shown), and the transfer manufacturing process can be repeated until all the semiconductor elements 110 located on the carrier 100 are transferred to one or more selected supporting substrates.

[0113] Fig.116 is a cross-sectional view of different stages of the manufacturing process of transferring a plurality of semiconductor elements from a first supporting substrate to a second supporting substrate according to another embodiment of the present invention. In one embodiment, a polymer layer 612 may be additionally disposed between the carrier 100 and the adhesive layer 614. The corresponding manufacturing process may refer to Fig.11 ,and Fig.11 The manufacturing process steps can be regarded as derived from Fig. 9 The manufacturing process steps are described below with reference to the differences between the embodiments.

[0114] In step S112 ′, a plurality of semiconductor devices 110 are located on the first supporting substrate 500 , and the semiconductor devices 110 located on the first supporting substrate 500 contact the adhesive layer 614 of the second supporting substrate 600 .

[0115] The bonding layer 514 of the first supporting substrate 500 may be a viscous elastic body, such as polysiloxane. In addition to being used to fix the semiconductor element 110, the bonding layer 514 may also generate elastic deformation when an external force is applied to the bonding layer 514.

[0116] The second supporting substrate 600 includes a carrier 100, a polymer layer 612 and an adhesive layer 614. The polymer layer 612 is disposed between the carrier 100 and the adhesive layer 614, and is adjacent to the adhesive layer 614. The polymer layer 612 and the carrier 100 can also be regarded as a carrier, such as a composite carrier 101. The thickness T2 of the polymer layer 612 can be greater than, less than or equal to the thickness T3 of the adhesive layer 614. The polymer layer 612 and the adhesive layer 614 can be derived from the same adhesive material, but undergo different processing processes. For example, before performing step S112', the polymer layer 612 has undergone soft baking and hard baking processes, and is completely cross-linked and cured, so even if a heating process or a hot pressing process is subsequently applied, the polymer layer 612 will not have fluidity. In contrast, before performing step S112 ′, the adhesive layer 614 has only undergone the soft baking process and has not yet been completely cross-linked. Therefore, when a heating process or a hot pressing process is subsequently performed, the adhesive layer 614 will have fluidity.

[0117] In step S112', the semiconductor device 110 on the first support substrate 500 contacts the adhesive layer 614 of the second support substrate 600. At this time, the thickness T2 of the polymer layer 612 does not change due to the lamination of the semiconductor device 110, but the thickness T3 of the adhesive layer 614 may change due to the lamination.

[0118] Next, referring to step S112' and step S114', the first support substrate 500 and the second support substrate 600 are pressed together, and a heating process is performed to form the adhesive layer 614 into adhesive portions 200 (including the first adhesive portion 200-1 and the second adhesive portion 200-2) separated from each other. According to one embodiment, in the early stage of the heating process, the viscosity of the adhesive layer 614 is reduced to form adhesive portions 200 separated from each other, and the polymer layer 612 located between two adjacent semiconductor elements 110 is exposed from the gap portion 300. The exposed polymer layer 612 has an exposed surface 103. When the adhesive portion 200 is continuously heated, the viscosity of the adhesive portion 200 continues to increase due to the gradual increase in the degree of cross-linking between the uncross-linked polymers in the adhesive portion 200, until the adhesive portion 200 is cured to become a solid adhesive portion 200.

[0119] By performing this heating process, the thickness T1 of the adhesive portion 200 may be different from the thickness T3 (or average thickness) of the adhesive layer 614 before the heating process. In contrast, the thickness T2 (or average thickness) of the polymer layer 612 remains unchanged before or after the heating process. By providing the polymer layer 612, the total thickness T4 of the polymer layer 612 and the adhesive portion 200 can be increased without increasing the thickness T3 of the adhesive layer 614. Thus, the adhesive layer 614 can be prevented from overflowing due to being too thick, thereby preventing adjacent adhesive portions 200 from being connected to each other.

[0120] On the other hand, since the bonding layer 514 of the first supporting substrate 500 is an elastic body, during the lamination process, the applied force can be evenly dispersed by the elastic body to each semiconductor element 110, so that the thickness T1 of the adhesive portion 200 under each semiconductor element 110 is substantially the same, for example, the thickness deviation value is less than 3%. Therefore, it is beneficial to the subsequent debonding process of each semiconductor element 110.

[0121] In step S116 ′, a separation process is performed to separate the first support substrate 500 from the semiconductor device 110 , thereby exposing the front surface 110 a of the semiconductor device 110 .

[0122] Next, referring to step S116' and step S117, an etching process, such as a plasma etching process, is performed to remove the polymer layer 612 located in the gap portion 300 to form a patterned polymer layer 616. Two adjacent patterned polymer layers 616 are separated from each other, and the front surface 102 of the carrier 100 located between the two adjacent semiconductor elements 110 is exposed. When the etching process is performed, the sidewall of the adhesive portion 200 is also etched, thereby changing its cross-sectional profile.

[0123] exist Fig.11In the embodiment shown, the adhesive portion 200 and the patterned polymer layer 616 are located on the back side 110b of the semiconductor element 110, but the present invention is not limited thereto. According to different manufacturing processes and requirements, the adhesive portion 200 and the patterned polymer layer 616 may also be located on the front side 110a of the semiconductor element 110 instead of the back side 110b.

[0124] After completing the arrangement structure shown in step S117, each semiconductor element 110 on the carrier 100, together with the adhesive portion 200 and the patterned polymer layer 616, can be further transferred to another supporting substrate (not shown) to group semiconductor elements 110 with similar or identical electrical or optical specifications. The adhesive portion 200 and the patterned polymer layer 616 on the semiconductor element 110 are arranged away from the supporting substrate. Afterwards, a dry debonding process, such as a plasma debonding process, can be performed to remove the adhesive portion 200 and the patterned polymer layer 616 located on the semiconductor element 110. For each semiconductor element 110, since the total thickness T4 of the adhesive portion 200 and the patterned polymer layer 616 has high uniformity, when performing the debonding process, it is unlikely that the shielded surfaces of some semiconductor elements 110 (such as the front surface 110a or the back surface 110b) have been exposed to the adhesive portion 200, while the shielded surfaces of other semiconductor elements 110 continue to be covered by the adhesive portion 200. Therefore, the reaction between the surface of the semiconductor element 110 and the plasma can be avoided, and the original electrical performance of the semiconductor element 110 can be maintained.

[0125] According to an embodiment of the present invention, the adhesive layer on the carrier can be heated so that the adhesive layer is deformed due to its own surface tension and gathers toward the adjacent semiconductor element, thereby splitting from the original single continuous layer into separate adhesive portions, and exposing the carrier located between the adjacent semiconductor elements. Since the adjacent adhesive portions will form a self-isolated structure separated from each other by self-aggregation, it is possible to avoid performing an etching process on the adhesive portions between adjacent semiconductor elements when separating each semiconductor element, or greatly reduce the time for performing the etching process. Since the etching process is avoided or the time for performing the etching process is reduced, this also avoids the skewing or displacement of the semiconductor element caused by the external force generated by the etching process.

[0126] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device arrangement structure, comprising: Carrier; The first semiconductor element and the second semiconductor element are separately located on the carrier; and A first adhesive portion and a second adhesive portion are separated from each other, the first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier; in, In a top view, the first adhesive portion has a first outer contour, and the first outer contour surrounds the first semiconductor element and has at least one rounded corner.

2. The semiconductor device arrangement structure according to claim 1, wherein: The projected area of ​​the first semiconductor element is 50 μm 2 Up to 5000μm 2 .

3. The semiconductor device arrangement structure according to claim 1, wherein: The first adhesive portion comprises: an overflow portion protruding from a first outermost edge of the first semiconductor element; and A filling portion, located between the first semiconductor element and the carrier; Wherein, the maximum thickness of the overflow portion is greater than the minimum thickness of the filling portion.

4. The semiconductor device arrangement structure according to claim 1, wherein: In the cross-sectional view, the first semiconductor element has a first outermost edge, the first adhesive portion has an arc-shaped side edge corresponding to the first outermost edge, and a virtual extension line of the first outermost edge extending toward the carrier is located within the arc-shaped side edge.

5. The semiconductor device arrangement structure according to claim 4, wherein: The arc-shaped side edge of the first adhesive portion is recessed toward the carrier.

6. A method for manufacturing a semiconductor device arrangement structure, comprising: Providing a first supporting substrate, a first semiconductor element, and a second semiconductor element, wherein the first semiconductor element and the second semiconductor element are located on the first supporting substrate and are separated from each other; providing a second supporting substrate, the second supporting substrate comprising a carrier and an adhesive layer disposed on the carrier; Making the first semiconductor element and the second semiconductor element contact the adhesive layer; The adhesive layer is heated to deform the adhesive layer into a first adhesive portion and a second adhesive portion separated from each other, and a gap portion is formed between the first adhesive portion and the second adhesive portion to expose the carrier.

7. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: During the heating step, the adhesive layer is split from a single layer into at least two parts, one of which shrinks inwardly under the first semiconductor element.

8. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: The first adhesive portion is located between the first semiconductor element and the carrier, and the second adhesive portion is located between the second semiconductor element and the carrier.

9. The method for manufacturing a semiconductor device arrangement structure according to claim 8, wherein: In a top view, the first adhesive portion has a first outer contour, and the first outer contour surrounds the first semiconductor element and has at least one rounded corner.

10. The method for manufacturing a semiconductor device arrangement structure according to claim 6, wherein: The thickness of the polymer layer is maintained constant before heating the adhesive layer and after heating the adhesive layer.

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