Package structure

Abstract

The invention provides a packaging structure. A conductive substrate of the packaging structure is arranged on a support. The first, second, and third bond pads are disposed on the bracket, and the first and second bond pads are separated from the conductive substrate, while the third bond pad is connected to the conductive substrate. The laterally diffused metal oxide semiconductor transistor is arranged on the conductive substrate and comprises a first drain electrode, a first grid electrode and a first source electrode. The depletion mode III-V transistor is disposed on the conductive substrate and separated from the laterally diffused metal oxide semiconductor transistor, and includes a second drain, a second gate, and a second source. The first drain electrode, the first grid electrode and the first source electrode are respectively connected with the second source electrode, the first bonding pad and the conductive substrate connected with the third bonding pad through corresponding bonding wires, and the second drain electrode and the second grid electrode are respectively connected with the second bonding pad and the conductive substrate connected with the third bonding pad through corresponding bonding wires. The efficiency of the switching device can be improved.

Description

Technical Field

[0001] The present invention relates to a packaging structure, and more particularly to a packaging structure having a tandemly connected LDMOS transistor and a depletion-mode III-V transistor. Background Art

[0002] III-V transistors, such as gallium nitride field effect transistors (GaN FETs), are often used in high-power and high-performance circuit applications due to their high efficiency characteristics and suitability for high-voltage operation. In addition, III-V transistors are often combined with other transistors (such as silicon field effect transistors) to produce high-performance switching devices, such as cascoded switches.

[0003] In general packaging design, multiple components can be placed on the same supporting surface, such as a direct bonding copper (DBC) or ceramic substrate placed on a lead frame. However, placing multiple components on a supporting surface often brings many unexpected non-ideal effects, so it is necessary to avoid unexpected non-ideal effects to improve the performance of the switch device. Summary of the invention

[0004] An embodiment of the present invention provides a packaging structure. The packaging structure includes a bracket, a plurality of bonding wires, a conductive substrate, a first bonding pad, a second bonding pad, a third bonding pad, a lateral diffused metal oxide semiconductor transistor, and a depletion type III-V transistor. The conductive substrate is disposed on the bracket. The first and second bonding pads are disposed on the bracket. The third bonding pad is disposed on the bracket and connected to the conductive substrate. The first and second bonding pads are separated from the third bonding pad of the conductive substrate. The lateral diffused metal oxide semiconductor transistor is disposed on the conductive substrate and includes a first drain, a first gate, and a first source. The depletion type III-V transistor is disposed on the conductive substrate and separated from the lateral diffused metal oxide semiconductor transistor and includes a second drain, a second gate, and a second source. The first drain, the first gate, and the first source are respectively connected to the second source, the first bonding pad, and the conductive substrate connected to the third bonding pad via the corresponding bonding wires, and the second drain and the second gate are respectively connected to the second bonding pad and the conductive substrate connected to the third bonding pad via the corresponding bonding wires.

[0005] Furthermore, an embodiment of the present invention provides a packaging structure. The packaging structure includes a bracket, a plurality of bonding wires, a conductive substrate, a plurality of bonding pads, a chip, and a depletion-type III-V transistor. The conductive substrate is disposed on the bracket. The bonding pad is disposed on the bracket and is separated from the conductive substrate. The chip is disposed on the conductive substrate and includes a lateral diffused metal oxide semiconductor transistor and a gate driver coupled to the gate of the lateral diffused metal oxide semiconductor transistor. The depletion-type III-V transistor is disposed on the conductive substrate and is separated from the chip. The drain and source of the lateral diffused metal oxide semiconductor transistor are respectively connected to the source of the depletion-type III-V transistor and a first bonding pad of the bonding pad via the corresponding bonding wires, and the drain and gate of the depletion-type III-V transistor are respectively connected to a second bonding pad of the bonding pad and the conductive substrate via the corresponding bonding wires.

[0006] The package structure provided by the present invention has the characteristics of high voltage operation, low parasitic capacitance, low on-resistance and reverse recovery current approaching zero, so it is suitable for operation under high frequency and high power density conditions. The present invention can reduce parasitic effects. In addition, the present invention can also reduce the layout complexity and packaging cost of the package structure, reduce excessive electrical stress, and enable rapid discharge when the power transistor is switched (or switched).

[0007] Furthermore, in the packaging structure provided by the present invention, the lateral diffused metal oxide semiconductor transistor is integrated with related circuits (such as gate drivers, controllers, etc.) in the chip, thereby increasing the integration of components. Compared with conventional power transistors, the chip and the depletion type III-V transistor can be directly arranged on the conductive substrate without passing through the substrate, thereby reducing the layout complexity of the packaging structure and the packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a circuit diagram showing a packaging structure according to some embodiments of the present invention;

[0009] Figure 2A It is to show that according to some embodiments of the present invention Figure 1 A top view of the package structure;

[0010] Figure 2B It is to show that according to some embodiments of the present invention Figure 1 A cross-sectional schematic diagram of the packaging structure;

[0011] Figure 3 is a circuit diagram showing a packaging structure according to some embodiments of the present invention;

[0012] Figure 4 It is to show that according to some embodiments of the present invention Figure 3 Top view of the package structure.

[0013] Reference Numbers

[0014] 100, 200: Package structure

[0015] 110: Laterally diffused metal oxide semiconductor transistor

[0016] 120: Depletion-mode III-V transistors

[0017] 130,400: Bracket

[0018] 132: Upper surface

[0019] 141-146, 241-253: Bonding wire

[0020] 152,410: Conductive substrate

[0021] 154, 156, 157, 420, 420_1-420_8: Bonding pads

[0022] 210: Chip

[0023] 220: Drive

[0024] 224, 226: Transistor

[0025] B1, B2: Matrix

[0026] D: Drain terminal

[0027] D1, D2: Drain

[0028] G: Gate terminal

[0029] G1, G2: Gate

[0030] HR, Rg: resistance

[0031] S: Source terminal

[0032] S1, S2: Source

[0033] Sd: driving signal

[0034] VCC: power supply terminal

[0035] VSS: Ground terminal DETAILED DESCRIPTION

[0036] In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, preferred embodiments are given below and described in detail with reference to the accompanying drawings.

[0037] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0039] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0040] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of explanation and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Moreover, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0041] Figure 11 is a circuit diagram showing a package structure 100 according to some embodiments of the present invention. The package structure 100 includes a power transistor, and the power transistor is formed by a cascoded laterally diffused metal oxide semiconductor (LDMOS) transistor 110 and a depletion mode (D-mode) III-V transistor 120. The LDMOS transistor 110 has a low on-resistance characteristic. In this embodiment, the depletion mode III-V transistor 120 is a gallium nitride (GaN) high electron mobility field effect transistor (HEMT), which has the characteristics of high voltage operation, low parasitic capacitance, low on-resistance and near-zero reverse recovery current, and is therefore suitable for operation at high frequency and high power density.

[0042] The power transistor is a switching element and includes a gate terminal G, a source terminal S, and a drain terminal D. In addition, the depletion-type III-V transistor 120 has a drain D2, a gate G2, a source S2, and a bulk B2, and the LDMOS transistor 110 has a drain D1, a gate G1, a source S1, and a bulk B1.

[0043] exist Figure 1 In the embodiment, the drain D2 of the depletion-type III-V transistor 120 is coupled to the drain terminal D. The gate G2 and the body B2 of the depletion-type III-V transistor 120 are coupled to the source terminal S. In this embodiment, the body B2 of the depletion-type III-V transistor 120 is not in a floating state, thereby increasing the dynamic characteristics of the depletion-type III-V transistor 120. In addition, the source S2 of the depletion-type III-V transistor 120 is coupled to the drain D1 of the LDMOS transistor 110.

[0044] exist Figure 1 In the embodiment, the drain D1 of the LDMOS transistor 110 is further coupled to the source terminal S via the resistor HR. In this embodiment, the resistor HR has a high impedance. The gate G1 of the LDMOS transistor 110 is coupled to the gate terminal G. The source S1 and the body B1 of the LDMOS transistor 110 are coupled to the source terminal S.

[0045] Figure 2A It is to show that according to some embodiments of the present invention Figure 1 A top view of the package structure 100, and Figure 2B It is to show that according to some embodiments of the present invention Figure 1FIG. 1 is a cross-sectional schematic diagram of the package structure 100 .

[0046] The package structure 100 includes a frame 130 and a lateral diffused metal oxide semiconductor transistor 110 and a depletion type III-V transistor 120 disposed above the frame 130. A conductive base 152, a bonding pad 154, a bonding pad 156, and a bonding pad 157 are formed on the upper surface 132 of the frame 130, and the conductive substrate 152 and the bonding pad 157 are connected, but the bonding pads 154 and the bonding pads 156 are separated from each other. In some embodiments, the conductive substrate 152 is formed by a metal layer, for example, a layer of metal material is plated on the upper surface 132 of the frame 130. In some embodiments, the bonding pads 154, the bonding pads 156, and the bonding pads 157 can be electrodes formed by metal materials. In some embodiments, the bonding pads 157, the bonding pads 154, and the bonding pads 156 can be disposed on separate lead frames. In addition, the bonding pad 157 , the bonding pad 154 , and the bonding pad 156 are respectively used to couple the source terminal S, the gate terminal G, and the drain terminal D of the power transistor to other circuits outside the package structure 100 .

[0047] The LDMOS transistor 110 and the depletion-mode III-V transistor 120 are both placed and bonded to the conductive substrate 152, and the LDMOS transistor 110 is separated from the depletion-mode III-V transistor 120. In the package structure 100, the LDMOS transistor 110 and the resistor HR are formed on the same silicon substrate. In addition, the resistor HR is electrically connected to the drain D1 of the LDMOS transistor 110 through an internal connection (not shown) on the silicon substrate. Compared to a conventional vertical enhancement-mode transistor (which needs to be connected to an external resistor through a drain disposed at the bottom of the transistor structure), the resistor HR and the LDMOS transistor 110 can be implemented on the same semiconductor substrate.

[0048] As described above, the LDMOS transistor 110 includes a gate G1, a source S1, and a drain D1, while the depletion-type III-V transistor 120 includes a gate G2, a source S2, and a drain D2. For the LDMOS transistor 110, the drain D1 is electrically connected to the source S2 of the depletion-type III-V transistor 120 through a bonding wire 141. The source S1 is electrically connected to the conductive substrate 152 connected to the bonding pad 157 (i.e., the source terminal S of the power transistor) through a bonding wire 142, and the gate G1 is electrically connected to the bonding pad 154 (i.e., the gate terminal G of the power transistor) through a bonding wire 143. In addition, one end of the resistor HR is electrically connected to the drain D1, and the other end of the resistor HR is electrically connected to the conductive substrate 152 connected to the bonding pad 157 through a bonding wire 144.

[0049] For the depletion-mode III-V transistor 120, the drain D2 is electrically connected to the bonding pad 156 (i.e., the drain terminal D of the power transistor) through the bonding wire 146. In addition, the gate G2 is electrically connected to the conductive substrate 152 connected to the bonding pad 157 through the bonding wire 145, and the source S2 is electrically connected to the drain D1 of the LDMOS transistor 110 through the bonding wire 141.

[0050] In the package structure 100, the lateral diffused metal oxide semiconductor transistor 110 and the depletion type III-V transistor 120 are jointly disposed on the conductive substrate 152 and are commonly grounded to the conductive substrate 152 (for example, the substrates of the lateral diffused metal oxide semiconductor transistor 110 and the depletion type III-V transistor 120 are directly in contact with the conductive substrate 152), thereby reducing parasitic effects. In addition, compared with conventional power transistors, the lateral diffused metal oxide semiconductor transistor 110 and the depletion type III-V transistor 120 can be directly disposed on the conductive substrate 152 without passing through a substrate (for example, a direct bonding copper (DBC)) . Therefore, the layout complexity and packaging cost of the package structure 100 can be reduced. In addition, the resistor HR with a high resistance value is integrated in the lateral diffused metal oxide semiconductor transistor 110 and coupled to the source S2 and the conductive substrate 152, which can reduce electrical overstress (EOS) and enable rapid discharge when the power transistor is switched (or switched).

[0051] Figure 32 is a circuit diagram showing a package structure 200 according to some embodiments of the present invention. The package structure 200 includes a depletion-type III-V transistor 120 and a chip 210. The chip 210 includes a driver 220, transistors 224 and 226, a resistor Rg, and a LDMOS transistor 110.

[0052] In the chip 210, the driver 220 provides a driving signal Sd to the gates of the transistors 224 and 226 according to an input control signal (not shown) so as to control whether the transistors 224 and 226 are turned on. In this embodiment, the transistor 224 is a P-type transistor and is coupled between the power supply terminal VCC and the first end of the resistor Rg. The transistor 226 is an N-type transistor and is coupled between the ground terminal VSS and the first end of the resistor Rg. The laterally diffused metal oxide semiconductor transistor 110 can be connected in series with the depletion type III-V transistor 120 located outside the chip 210 to form a power transistor. In this embodiment, the depletion type III-V transistor 120 is a gallium nitride high electron mobility field effect transistor.

[0053] In the package structure 200, the depletion-type III-V transistor 120 has a drain D2, a gate G2, a source S2, and a body B2, and the LDMOS transistor 110 has a drain D1, a gate G1, a source S1, and a body B1. The power transistor is a switch element composed of the LDMOS transistor 110 and the depletion-type III-V transistor 120, and includes a gate terminal G, a source terminal S, and a drain terminal D. In addition, the gate terminal G is disposed in the chip 210 and coupled to the second end of the resistor Rg.

[0054] exist Figure 3 , the drain D2 of the depletion-type III-V transistor 120 is coupled to the drain terminal D. The gate G2 and the body B2 of the depletion-type III-V transistor 120 are coupled to the source terminal S. The body B2 of the depletion-type III-V transistor 120 is not in a floating state, thereby increasing the dynamic characteristics of the depletion-type III-V transistor 120. In addition, the source S2 of the depletion-type III-V transistor 120 is coupled to the drain D1 of the lateral diffused metal oxide semiconductor transistor 110 in the chip 210. The drain D1 of the lateral diffused metal oxide semiconductor transistor 110 is further coupled to the source terminal S via the resistor HR. As previously described, the resistor HR has a high impedance. The gate G1 of the lateral diffused metal oxide semiconductor transistor 110 is coupled to the gate terminal G. The source S1 and the body B1 of the lateral diffused metal oxide semiconductor transistor 110 are coupled to the source terminal S.

[0055] Figure 4 It is to show that according to some embodiments of the present invention Figure 3 FIG. 2 is a top view of the package structure 200. The package structure 200 includes a bracket 400 and a laterally diffused metal oxide semiconductor transistor 110 and a chip 210 disposed above the bracket 400. A conductive substrate 410 and a plurality of bonding pads 420 are formed on the upper surface of the bracket 400. In addition, the bonding pads 420 are disposed around the conductive substrate 410, and each bonding pad 420 and the conductive substrate 410 are separated from each other. In some embodiments, the conductive substrate 410 is formed by a metal layer, for example, a metal material is plated on the upper surface of the bracket 400. In some embodiments, each bonding pad 420 can be an electrode formed by a metal material. In some embodiments, the bracket 400 can be a lead frame. In addition, the bonding pad 420_6 and the bonding pad 420_8 are respectively used to couple the source terminal S and the drain terminal D of the power transistor to other circuits outside the package structure 200. In this embodiment, the number of bonding pads 420 is only for illustration and is not intended to limit the present invention.

[0056] The chip 210 and the depletion-mode III-V transistor 120 are both placed and bonded to the conductive substrate 410, and the chip 210 is separated from the depletion-mode III-V transistor 120. In the package structure 200, the LDMOS transistor 110 and the resistor HR are formed on the chip 210. In addition, the resistor HR is electrically connected to the drain D1 of the LDMOS transistor 110 through an internal connection (not shown) of the chip 210. Compared to a conventional vertical enhancement-mode transistor, the resistor HR and the LDMOS transistor 110 can be implemented on the chip 210 at the same time.

[0057] As previously described, the LDMOS transistor 110 includes a gate G1, a source S1, and a drain D1, while the depletion-type III-V transistor 120 includes a gate G2, a source S2, and a drain D2. For the LDMOS transistor 110, the drain D1 is electrically connected to the source S2 of the depletion-type III-V transistor 120 through a bonding wire 250. The source S1 is electrically connected to the bonding pad 420_6 (i.e., the source terminal S of the power transistor) through a bonding wire 246. In addition, one end of the resistor HR is electrically connected to the drain D1, and the other end of the resistor HR is electrically connected to the conductive substrate 410 through a bonding wire 249. For the depletion-type III-V transistor 120, the drain D2 is electrically connected to the bonding pad 420_8 (i.e., the drain terminal D of the power transistor) through a bonding wire 248. Furthermore, the gate G2 is electrically connected to the conductive substrate 410 through a bonding wire 253 , and the source S2 is electrically connected to the drain D1 of the LDMOS transistor 110 through a bonding wire 250 .

[0058] In the chip 210, the source of the transistor 224 is electrically connected to the bonding pad 420_1 through the bonding wire 241 so as to be connected to the external power supply terminal VCC. The source of the transistor 226 is electrically connected to the conductive substrate 410 through the bonding wire 252. The input signal or control signal of the driver 220 is electrically connected to the bonding pads 420_2 and 420_3 through the bonding wires 242 and 243, respectively. In this embodiment, the input signal or control signal of the driver 220 and the number of the corresponding bonding pads are only for illustration and are not intended to limit the present invention.

[0059] In the package structure 200, the chip 210 and the depletion-type III-V transistor 120 are disposed together on a conductive substrate 410 and are grounded to the conductive substrate 410 (for example, the substrates of the chip 210 and the depletion-type III-V transistor 120 are directly in contact with the conductive substrate 410), thereby reducing parasitic effects. The conductive substrate 410 is electrically connected to the bonding pads 420_4, 420_5, and 420_7 through bonding wires 244, 245, and 247, respectively, so as to be connected to the external ground terminal VSS. In addition, the source terminal S of the power transistor is also connected to the external ground terminal VSS through the bonding pad 420_6. Therefore, through the external ground terminal VSS, the source terminal S of the power transistor (i.e., the source S1 of the LDMOS transistor 110) is electrically connected to the gate G2 of the depletion-type III-V transistor 120.

[0060] In the package structure 200, the LDMOS transistor 110 is integrated with related circuits (e.g., gate driver, controller, etc.) in the chip 210, thereby increasing the integration of components. Compared with conventional power transistors, the chip 210 and the depletion-type III-V transistor 120 can be directly disposed on the conductive substrate 410 without passing through a substrate (e.g., copper-clad ceramic substrate (DBC)). Thus, the layout complexity and packaging cost of the package structure 200 can be reduced.

[0061] Although the present invention has been described above with preferred embodiments, it is not intended to limit the present invention. Any technician in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the preceding claims.

Claims

1. A packaging structure, characterized in that: include: A bracket; a plurality of bonding wires; A conductive substrate is disposed on the support; A first bonding pad and a second bonding pad are disposed on the bracket; a third bonding pad disposed on the bracket and connected to the conductive substrate, wherein the first bonding pad and the second bonding pad are separated from the third bonding pad of the conductive substrate; A lateral diffused metal oxide semiconductor transistor is disposed on the conductive substrate and includes a first drain, a first gate and a first source; as well as a depletion-type III-V transistor disposed on the conductive substrate and separated from the LDMOS transistor, comprising a second drain, a second gate and a second source; The first drain, the first gate and the first source are respectively connected to the second source, the first bonding pad and the conductive substrate connected to the third bonding pad via the corresponding bonding wires, and the second drain and the second gate are respectively connected to the second bonding pad and the conductive substrate connected to the third bonding pad via the corresponding bonding wires.

2. The packaging structure according to claim 1, characterized in that: The conductive substrate is formed by a metal layer, and the LDMOS transistor and the depletion-type III-V transistor are bonded to the metal layer.

3. The packaging structure according to claim 1, characterized in that: The LDMOS transistor and the depletion-type III-V transistor are grounded via the conductive substrate.

4. The packaging structure according to claim 1, characterized in that: The LDMOS transistor further includes a resistor, and the first drain is further coupled to the conductive substrate via the resistor.

5. The packaging structure according to claim 1, characterized in that: The LDMOS transistor and the depletion type III-V transistor are connected in series to form a power transistor.

6. The packaging structure according to claim 5, characterized in that: The power transistor includes a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is coupled to the first bonding pad, the drain terminal is coupled to the second bonding pad, and the source terminal is coupled to the third bonding pad.

7. The packaging structure according to claim 1, characterized in that: The depletion-mode III-V transistor is a gallium nitride high electron mobility field effect transistor.

8. A packaging structure, characterized in that: include: A bracket; a plurality of bonding wires; A conductive substrate is disposed on the support; a plurality of bonding pads disposed on the support and separated from the conductive substrate; a chip disposed on the conductive substrate, comprising a LDMOS transistor and a gate driver coupled to a gate of the LDMOS transistor; as well as a depletion-mode III-V transistor disposed on the conductive substrate and separated from the chip; The drain and source of the laterally diffused metal oxide semiconductor transistor are respectively connected to the source of the depletion type III-V transistor and a first bonding pad of the bonding pad via the corresponding bonding wires, and the drain and gate of the depletion type III-V transistor are respectively connected to a second bonding pad of the bonding pad and the conductive substrate via the corresponding bonding wires.

9. The packaging structure according to claim 8, characterized in that: The conductive substrate is formed by a metal layer, and the chip and the depletion type III-V transistor are bonded to the metal layer.

10. The packaging structure according to claim 8, characterized in that: The chip and the depletion-mode III-V transistor are grounded via the conductive substrate.

11. The packaging structure according to claim 8, characterized in that: The chip further includes a first resistor, and the drain of the LDMOS transistor is coupled to the conductive substrate via the first resistor.

12. The packaging structure according to claim 8, characterized in that: The LDMOS transistor and the depletion type III-V transistor are connected in series to form a power transistor.

13. The packaging structure according to claim 12, characterized in that: The power transistor includes a gate terminal, a source terminal, and a drain terminal, wherein the drain terminal is coupled to the second bonding pad and the source terminal is coupled to the first bonding pad.

14. The packaging structure according to claim 13, characterized in that: The chip further includes a second resistor, and the second resistor is coupled between the gate terminal and the driver.

15. The packaging structure according to claim 8, characterized in that: The depletion-mode III-V transistor is a gallium nitride high electron mobility field effect transistor.

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