Coated silicon negative electrode material and preparation method and application thereof
By coating silicon material with vanadium pentoxide, the volume expansion and interface problems of silicon in lithium-ion batteries are solved, electrical performance and cycling stability are improved, and higher energy density and longer battery life are achieved.
Patent Information
- Application Number
- CN202411527513.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-25
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-14
AI Technical Summary
Volume expansion of silicon in lithium-ion batteries and interface problems with sulfide electrolytes lead to electrode layering, electrical contact loss and unstable solid electrolyte interface phases, limiting the energy density and cycling stability of lithium-ion batteries.
By coating the silicon material with vanadium pentoxide, the interface problem between silicon and sulfide electrolyte is improved, and the volume expansion of silicon is suppressed, thereby improving electrical performance and cycling stability.
The vanadium pentoxide cladding reduces the deposition of lithium on the negative electrode side and the formation of lithium dendrites, improves rate performance and cycle stability, and extends the service life of the battery.
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Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of battery materials, and in particular relates to a coated silicon negative electrode material and a preparation method and application thereof. Background Art
[0002] With the rapid growth of demand for energy storage systems, lithium-ion batteries (LIBs) have been widely used in portable electronic products, electric vehicles and grid-scale energy storage systems. Their higher energy density, faster charge and discharge speed, and longer life have also entered a new stage. In order to further expand the market, batteries must have higher energy density and safety performance than the current ones. Given that the current lithium-ion batteries using liquid electrolytes cannot meet the greatly increased demand for energy density and safety, it is of great significance to develop a new generation of batteries. Sulfide all-solid-state lithium batteries are based on non-flammable sulfide solid electrolytes and are expected to improve energy density and solve safety issues through a unique bipolar stacking method. However, batteries based on traditional graphite anodes have reached the theoretical limit of energy density. The use of high-capacity electrode materials is an urgent need for the development of high-energy sulfide all-solid-state lithium batteries.
[0003] Silicon (Si) is the most promising anode material for achieving high energy density in lithium-ion batteries because of its high theoretical capacity (Li 4.4 Si up to 4200mAh / g), low working potential (<0.4V vs.Li / Li + ) and rich element storage. However, in Li + During the insertion and extraction process, excessive volume expansion (up to 300%) occurs, leading to particle crushing, electrode delamination, and electrical contact loss, hindering practical applications. In particular, interfacial side reactions on newly exposed and highly active surfaces lead to the formation of an unstable, compositionally inhomogeneous solid electrolyte interface (SEI), which is highly dynamic, brittle, and inherently non-passivating. This uncontrolled and continuous SEI growth depletes the limited Li source, causing continuous capacity decay.
[0004] In the prior art, there is an interface problem between silicon and sulfide electrolyte. During the cycle process, lithium ions are reduced on the low-potential silicon surface to generate lithium metal deposited on the silicon surface, forming lithium dendrites, which can easily lead to capacity decay and short circuit problems.
[0005] Silicon undergoes a large volume expansion during the cycle, and its contact with the sulfide electrolyte continues to deteriorate. As the cycle progresses, silicon undergoes a volume expansion of about 300% during the lithium insertion and delithiation process, resulting in the continuous expansion of the gap between silicon and the sulfide solid electrolyte, and the continuous deterioration of the contact between the two, which makes the electron and ion transmission performance between the two deteriorate, resulting in rapid performance decay. Summary of the invention
[0006] The present invention aims to solve at least one of the technical problems existing in the above-mentioned prior art. To this end, the present invention proposes a coated silicon negative electrode material and a preparation method and application thereof, which can solve the interface problem between silicon and sulfide electrolyte and the problem of silicon volume expansion.
[0007] The present invention improves the interface problem between silicon and sulfide electrolyte by coating with vanadium pentoxide, thereby improving the electrical properties of silicon. Vanadium pentoxide is an excellent lithium storage material. When it is coated on the surface of silicon material as a coating material, the interface problem between silicon and sulfide electrolyte can be improved, lithium deposition on the negative electrode side can be reduced, lithium dendrites can be generated, and rate performance can be improved. In addition, the volume expansion of vanadium pentoxide is small during the process of lithium insertion and delithiation. When it is coated on silicon, the volume expansion of silicon can be suppressed, the damage to the contact between silicon and sulfide solid electrolyte caused by the volume change during the process of silicon lithiation and delithiation can be reduced, and the material cycle stability and rate performance can be improved, so that the silicon material can be better applied to sulfide solid-state batteries.
[0008] The low expansion shell of vanadium pentoxide material can reduce the impact of silicon volume expansion on the electrode structure, inhibit the increase of porosity in coated silicon negative electrode materials, reduce the contact failure between coated silicon negative electrode materials and sulfide solid electrolytes, improve the problem of accelerated capacity attenuation of coated silicon negative electrode materials during long-term cycles, and improve the rate performance of sulfide solid-state batteries.
[0009] A first aspect of the present invention provides a coated silicon negative electrode material.
[0010] Specifically, a coated silicon negative electrode material includes silicon and a coating layer coating the silicon, wherein the coating layer includes vanadium pentoxide.
[0011] Preferably, the coating layer has a thickness of 5-100 nm, more preferably 10-80 nm.
[0012] Preferably, the mass of the silicon accounts for 80-95% of the total mass of the coated silicon negative electrode material, and more preferably 88-90%.
[0013] Preferably, the particle size of the silicon is 30 nm-100 μm, more preferably 30 nm-50 μm. A suitable particle size of silicon can achieve a smaller porosity control.
[0014] A second aspect of the present invention provides a method for preparing a coated silicon negative electrode material.
[0015] Specifically, a method for preparing a coated silicon negative electrode material comprises the following steps:
[0016] Mixing and dispersing silicon with water to obtain a silicon dispersion;
[0017] Add ammonium vanadate to the silicon dispersion, mix, remove water, dry to obtain powder, and calcine to obtain the coated silicon negative electrode material.
[0018] Preferably, the mass volume ratio of silicon to water is 1 g: (80-200) mL, and more preferably 1 g: (100-120) mL.
[0019] Preferably, the water is deionized water.
[0020] Preferably, the mass ratio of silicon to ammonium vanadate is 100:(1-10), more preferably 100:(1-5).
[0021] Preferably, the mixing and dispersing method includes stirring or ultrasound.
[0022] Preferably, ammonium vanadate is added to the dispersion at a mixing speed of 500-1000 rpm, more preferably 700-800 rpm, and the mixing time is 0.01-1 h, more preferably 0.2-0.5 h.
[0023] Preferably, the method of removing water includes at least one of rotary evaporation, freeze drying, and centrifugal washing, and rotary evaporation is more preferred.
[0024] Preferably, the drying temperature is 60-100°C, more preferably 80-100°C.
[0025] Preferably, the drying time is 6-48 hours, more preferably 12-24°C.
[0026] Preferably, the vacuum pressure during drying is -0.04 to -0.1 MPa, more preferably -0.05 to -0.1 MPa.
[0027] Preferably, the calcination temperature is 300-800°C, more preferably 500-700°C.
[0028] Preferably, the calcination time is 2-24 h, more preferably 6-12 h.
[0029] Preferably, the calcination process is: under a protective gas atmosphere, first heating to 300-350° C. and keeping warm for 0.5-1.5 h, then heating to 550-650° C. and keeping warm for 4-6 h.
[0030] Preferably, the protective gas atmosphere includes nitrogen or a rare gas, such as argon or helium.
[0031] Preferably, during the calcination process, the heating rate is 1-8°C / min, more preferably 2-5°C / min.
[0032] Preferably, after the calcination, a washing and drying process is also included.
[0033] A third aspect of the present invention provides an application of a coated silicon negative electrode material.
[0034] A solid-state battery comprises the above-mentioned coated silicon negative electrode material.
[0035] Preferably, the solid-state battery comprises a sulfide solid electrolyte.
[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0037] (1) The present invention improves the interface problem between silicon and sulfide electrolyte by coating with vanadium pentoxide, thereby improving the electrical properties of silicon. Vanadium pentoxide is an excellent lithium storage material. When it is coated on the surface of silicon material as a coating material, the interface problem between silicon and sulfide electrolyte can be improved, lithium deposition on the negative electrode side can be reduced, lithium dendrites can be generated, and rate performance can be improved. In addition, the volume expansion of vanadium pentoxide is small during the process of lithium insertion and delithiation. When it is coated on silicon, the volume expansion of silicon can be suppressed, and the damage to the contact between silicon and sulfide solid electrolyte caused by the volume change during the process of silicon lithiation and delithiation can be reduced, thereby improving the material cycle stability and rate performance, so that silicon material can be better applied to sulfide solid-state batteries.
[0038] (2) The preparation method of the present invention utilizes ammonium vanadate and silicon to be uniformly dispersed in water, so that ammonium vanadate is uniformly dispersed on the silicon surface, and then the water is removed, and silicon@vanadium pentoxide is obtained by high-temperature calcination. The uniformly coated vanadium pentoxide can avoid the contact between silicon and sulfide solid electrolyte, and its higher lithium storage capacity can reduce the deposition of lithium on the negative electrode side and the formation of lithium dendrites, thereby improving the cycle performance and safety performance of the silicon negative electrode in the sulfide solid-state battery; secondly, the hard shell formed by vanadium pentoxide can alleviate the volume expansion and contraction during the lithium delithiation process of silicon, inhibit the contact failure between silicon and sulfide solid electrolyte, and effectively improve the cycle stability and rate performance of silicon negative electrode materials in sulfide solid-state batteries. The use of vanadium pentoxide to uniformly coat the silicon surface improves many shortcomings of silicon in sulfide solid-state batteries, which is of great significance for the commercialization of sulfide solid-state batteries. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 The scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) test results of the coated silicon negative electrode material prepared in Example 1;
[0040] Figure 2The scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) test results of the coated silicon negative electrode material prepared in Comparative Example 2;
[0041] Figure 3 The rate performance results of the half-cell composed of the coated silicon negative electrode material prepared in Example 1. DETAILED DESCRIPTION
[0042] In order to make the technical scheme of the present invention more clearly understood by those skilled in the art, the following embodiments are listed for illustration. It should be pointed out that the following embodiments do not limit the protection scope of the present invention.
[0043] Unless otherwise specified, the raw materials, reagents or devices used in the following examples can be obtained from conventional commercial sources or by existing known methods.
[0044] Example 1
[0045] A coated silicon negative electrode material comprises silicon and a coating layer coating the silicon, wherein the coating layer is composed of vanadium pentoxide.
[0046] A method for preparing a coated silicon negative electrode material comprises the following steps:
[0047] Take 1 g of silicon (particle size 100 nm), dissolve it in 100 mL of deionized water, and disperse it by ultrasonic stirring to obtain a silicon dispersion;
[0048] 0.05 g of ammonium vanadate was added to the silicon dispersion, and ultrasonic stirring was performed for 30 min to obtain a mixture;
[0049] The mixture was rotary evaporated to remove water, and then dried in a vacuum oven at 80°C under -0.1 MPa for 24 h to obtain a powder;
[0050] The obtained powder was subjected to high temperature calcination to obtain a calcined material. The specific high temperature calcination procedure was as follows: maintaining at 300°C for 1 hour in a N2 atmosphere, then heating to 600°C at a heating rate of 5°C / min and maintaining for 6 hours;
[0051] The obtained calcined material was washed by centrifugation with deionized water, and then dried in a vacuum oven at 80° C. and at −0.1 MPa for 24 h to obtain a coated silicon negative electrode material (which can be recorded as silicon@vanadium pentoxide).
[0052] Example 2
[0053] Compared with Example 1, the only difference in Example 2 is that the mass of ammonium vanadate used is 0.1 g, and the other processes are the same as those in Example 1.
[0054] Example 3
[0055] Compared with Example 1, the only difference of Example 3 is that the particle size of silicon is 1 μm, and the other processes are the same as Example 1.
[0056] Comparative Example 1
[0057] Compared with Example 1, the difference of Comparative Example 1 is that the mass of ammonium vanadate used is 1 g, and the other processes are the same as those of Example 1.
[0058] Comparative Example 2
[0059] Compared with Example 1, the difference of Comparative Example 2 is that an equal amount of sodium vanadate is used instead of ammonium vanadate, and the other processes are the same as those of Example 1.
[0060] Comparative Example 3
[0061] Compared with Example 1, the difference of Comparative Example 3 is that an equal amount of ammonium borate is used instead of ammonium vanadate, and the other processes are the same as those of Example 1.
[0062] Comparative Example 4
[0063] Compared with Example 1, the difference of Comparative Example 4 is that an equal amount of ammonium phosphate is used instead of ammonium vanadate, and the other processes are the same as those of Example 1.
[0064] Comparative Example 5
[0065] Compared with Example 1, the difference of Comparative Example 5 is that an equal amount of ammonium arsenate is used instead of ammonium vanadate, and the other processes are the same as those of Example 1.
[0066] Product effect testing
[0067] 1. Structural characterization of coated silicon anode materials
[0068] Figure 1 The scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) test results of the coated silicon negative electrode material prepared in Example 1; Figure 2 These are the scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) test results of the coated silicon negative electrode material prepared in Comparative Example 2.
[0069] Through SEM testing, Figure 1 It can be seen that the coated silicon negative electrode material prepared in Example 1 is composed of a core silicon and an outer shell vanadium pentoxide. The small vanadium pentoxide particles are evenly distributed on the silicon surface, which firmly coats the silicon, can effectively reduce the contact between silicon and the sulfide solid electrolyte, and improve the interface problem between silicon and the sulfide electrolyte.
[0070] And from Figure 2 There is no vanadium element in the silicon, and there is an obvious phenomenon of vanadium pentoxide not being coated. This is attributed to the fact that sodium vanadate cannot generate vanadium pentoxide, which adheres to the silicon surface and is finally removed by centrifugal washing with deionized water.
[0071] 2. Electrochemical performance test
[0072] The coated silicon negative electrode materials prepared in Examples 1-3 and Comparative Examples 1-5 were used as active materials, respectively, and the active materials were mixed with LiP6S5Cl and PTFE (polytetrafluoroethylene) in a mass ratio of 60:40:1 to form a composite negative electrode, and the negative electrode sheet was obtained through a roller pressing and slicing process. The negative electrode sheet was placed in a polyetheretherketone tube with a diameter of 10 mm, and then 100 mg of LiP6S5Cl was weighed and added to the polyetheretherketone tube. The tube was pressed and molded at a pressure of 12 MPa and tightly contacted with the negative electrode sheet. Finally, an indium sheet and a lithium sheet were added to the other side of the solid electrolyte, and the tube was pressed and molded at a pressure of 360 MPa to prepare a half-cell with a three-layer structure (composite negative electrode / solid electrolyte / Li-In alloy).
[0073] Test conditions: Charge and discharge tests were performed at 60°C with currents of 0.1C, 0.3C, 0.5C, 0.8C and 1C and cut-off voltages from -0.61 to 0.2V, and half cells were tested at a pressure of 15MPa.
[0074] 2.1 Electrochemical impedance spectroscopy
[0075] The internal resistance of the half-cell was tested by electrochemical impedance spectroscopy (EIS), and the contact between the obtained coated silicon negative electrode material and the sulfide solid electrolyte and the lithium conductivity were determined. The internal resistance of the half-cell composed of the coated silicon negative electrode materials obtained in Examples 1-3 and Comparative Examples 1-5 is shown in Table 1.
[0076] Table 1: Internal resistance of half-cells composed of coated silicon negative electrode materials obtained in Examples 1-3 and Comparative Examples 1-5
[0077]
[0078] By comparing the internal resistance of the half-cell composed of the coated silicon negative electrode material obtained in Examples 1-3 and Comparative Examples 1-5, it can be found that the coated silicon negative electrode material in Example 1 has the best contact with the sulfide solid electrolyte, and the combination of the two achieves a better and lowest internal resistance, and the vanadium pentoxide coating performance is better than that of boron trioxide, phosphorus pentoxide, and arsenic trioxide. The coated silicon negative electrode material in Example 1 well realizes the coating of vanadium pentoxide on silicon, effectively inhibits the contact between silicon and the sulfide solid electrolyte, and at the same time, vanadium pentoxide as an intermediate layer can quickly transfer lithium ions.
[0079] 2.2 Cyclic performance test
[0080] The half-cell prepared according to the above method was subjected to a cycle performance test and cycled 100 times at 1C to obtain its capacity retention rate after 100 cycles. The results are shown in Table 2.
[0081] Table 2: Capacity retention rate of half-cells composed of coated silicon negative electrode materials obtained in Examples 1-3 and Comparative Examples 1-5
[0082]
[0083]
[0084] By comparing the capacity retention rates of the half-cells composed of the coated silicon negative electrode materials obtained in Examples 1-3 and Comparative Examples 1-5, it can be seen that the capacity retention rate corresponding to Example 1 is the highest, and the coating performance of boron trioxide, phosphorus pentoxide, and arsenic trioxide is significantly worse than that of vanadium pentoxide. The uniformly coated vanadium pentoxide effectively reduces the deposition of lithium on the negative electrode surface, and the cycle performance is improved.
[0085] 2.3x performance test
[0086] The half-cell composed of the coated silicon negative electrode material obtained in Example 1 was tested for rate performance, and the results are as follows: Figure 3 The coated silicon negative electrode material obtained in Example 1 exhibits excellent rate performance, and can even maintain a specific capacity of 2653 mAh / g at a rate of 1 C. This fully proves that the coated silicon negative electrode material prepared by the present invention has excellent performance and commercial potential.
Claims
1. A coated silicon negative electrode material, characterized in that: The invention comprises silicon and a coating layer covering the silicon, wherein the coating layer comprises vanadium pentoxide.
2. The coated silicon negative electrode material according to claim 1, characterized in that: The coating layer has a thickness of 5-100 nm.
3. The coated silicon negative electrode material according to claim 1, characterized in that: The mass of the silicon accounts for 80-95% of the total mass of the coated silicon negative electrode material.
4. The coated silicon negative electrode material according to claim 1, characterized in that: The particle size of the silicon is 30nm-100μm.
5. The method for preparing the coated silicon negative electrode material according to any one of claims 1 to 4, characterized in that: The following steps are involved: Mixing and dispersing silicon with water to obtain a silicon dispersion; Add ammonium vanadate to the silicon dispersion, mix, remove water, dry to obtain powder, and calcine to obtain the coated silicon negative electrode material.
6. The preparation method according to claim 5, characterized in that: The mass volume ratio of silicon to water is 1g:(80-200)mL.
7. The preparation method according to claim 5, characterized in that: The mass ratio of silicon to ammonium vanadate is 100:(1-10).
8. The preparation method according to claim 5, characterized in that: The calcination temperature is 300-800° C.; and / or the calcination time is 2-24 hours.
9. The preparation method according to claim 5, characterized in that: The calcination process is: under a protective gas atmosphere, firstly heating to 300-350° C. and keeping the temperature for 0.5-1.5 h, then heating to 550-650° C. and keeping the temperature for 4-6 h.
10. A solid-state battery, characterized in that: It comprises the coated silicon negative electrode material as described in any one of claims 1 to 4.