Interconnected device, host, host interconnect component, imaging system and acquisition method

Abstract

Embodiments of the present application provide an interconnection device, a host, a host interconnection component, an imaging system, and an acquisition method. Among them, the interconnection device includes: a first connector detachably plugged into a first interface of a first fnirs host; a second connector detachably plugged into a second interface of a second fnirs host, and the second connector has different dominant physical attributes from the first connector; a cable connection part electrically connecting the first connector and the second connector. When the first connector is plugged into the first interface of the first fnirs host and the second connector is plugged into the second interface of the second fnirs host, the first connector receives a first acquisition timing signal for synchronous acquisition from a first processing circuit part of the first fnirs host, and transmits it to a second processing circuit part of the second fnirs host via the cable connection part and the second connector. This solution can distinguish the first connector and the second connector, and specify the master host by plugging in the first connector.

Description

Technical Field

[0001] This application relates to the technical field of near-infrared spectroscopy, and particularly to an interconnected device, a host, a host interconnection component, an imaging system, and a acquisition method. Background Art

[0002] Functional near-infrared spectroscopy (fnirs) utilizes the good scattering property of the main components of blood for near-infrared light in the range of 600 - 900 nm to obtain the changes in oxyhemoglobin and deoxyhemoglobin (brain blood oxygen data) during brain activity.

[0003] This technology has begun to be applied in the research of multiple fields such as advanced cognition, developmental psychology, and abnormal psychology in natural situations. With the wider application of fnirs devices in brain research, the brain locations and the number of sites concerned for different application scenarios will also be different. Sometimes, researchers will focus on fewer SD channels, and sometimes researchers will focus on more SD channels. Many users already have several low-channel fnirs systems with a low number of SD channels, such as Figure 1 As shown, a set of fnirs system includes a headcap, an SD probe and cable, a fnirs host also called an acquisition machine, and a host computer for receiving the acquired data and presenting the acquisition and analysis software interface.

[0004] In the face of application scenarios with a high number of SD channels, rather than purchasing a new system with a high number of SD channels, it is more desirable to be able to perform simple operations on several existing low-channel fnirs systems with a low number of SD channels to achieve the acquisition of brain detection data with a high number of SD channels. Moreover, users expect this operation to be widely applicable to various existing low-channel fnirs systems with a low number of SD channels and to minimize the update and modification costs of the existing low-channel fnirs systems.

[0005] Multiple fnirs systems can be interconnected through daisy chaining. For example, 2, 3, or 4 fnirs hosts can be connected to each other in a series mode one after another to measure a larger brain area of interest, achieve a higher density configuration, and implement super-scanning fNIRS measurements, etc. The back side of the fnirs host has cascade ports (flared ports A and B) as Figure 2 shown, so that one is connected to the upstream fnirs host and one is connected to the downstream fnirs host to expand the number of SD detectors and channels.

[0006] At present, the interconnection devices for interconnecting FNIRS hosts in multiple FNIRS systems have the following defects. The interconnection device has two connectors and wires with the same appearance, that is, the two connectors connected by the interconnection device look the same, and the user simply cannot determine which FNIRS host is the master host, nor can they determine which corresponding upper computer to go to view the signal acquisition and analysis results. In addition, after a relatively large number of FNIRS hosts are connected in series in a daisy chain mode, the time delay between FNIRS hosts that are far apart will be significantly increased. Summary of the Invention

[0007] In view of this, the embodiments of the present application provide an interconnection device, a host, a host interconnection component, an imaging system and an acquisition method, so that the user can independently determine the master host among multiple interconnected FNIRS hosts by performing a plugging operation on the connectors of the interconnection device.

[0008] According to the first aspect of the present application, there is provided an interconnection device for a FNIRS host, the interconnection device including a first connector, a second connector and a cable connection portion. The first connector is disposed at the first end of the interconnection device, and the first connector is configured to be detachably plugged into the first interface of the first FNIRS host to be interconnected. The second connector is disposed at the opposite end of the first end, and the second connector has different dominant physical attributes from the first connector, and the second connector is configured to be detachably plugged into the second interface of the second FNIRS host to be interconnected. The cable connection portion is used for electrically connecting the first connector and the second connector. Wherein, when the first connector is plugged into the first interface of the first FNIRS host and the second connector is plugged into the second interface of the second FNIRS host, the first connector receives the first acquisition timing signal synchronously acquired by the first processing circuit portion of the first FNIRS host, and transmits it to the second processing circuit portion of the second FNIRS host via the cable connection portion and the second connector, and the first acquisition timing signal at least indicates the start time of a series of acquisition cycles for synchronous acquisition.

[0009] According to a second aspect of the present application, there is provided an FNIRS host. The FNIRS host includes a main processor, at least one interface, and a processing circuit unit separate from the main processor. The main processor is configured to control the acquisition of FNIRS detection signals. The at least one interface is configured to insert a first connector or a second connector of an interconnection device for the FNIRS host. The processing circuit unit is configured to identify whether the inserted connector in the at least one interface is the first connector or the second connector. When it is identified that the inserted connector is the first connector, the processing circuit unit transmits the acquisition timing signal collected synchronously to the corresponding processing circuit unit of another interconnected FNIRS host via the at least one interface. When it is identified that the inserted connector is the second connector, the processing circuit unit receives another acquisition timing signal collected synchronously from the corresponding processing circuit unit of another interconnected FNIRS host via the at least one interface.

[0010] The main processor is further configured to: when the processing circuit unit receives the another acquisition timing signal, receive the another acquisition timing signal from the processing circuit unit and use the another acquisition timing signal for synchronous acquisition of FNIRS detection signals. The main processor is further configured to: when the processing circuit unit transmits the acquisition timing signal collected synchronously outward, use the acquisition timing signal collected synchronously transmitted outward for synchronous acquisition of FNIRS detection signals, and the acquisition timing signal at least indicates the start time of a series of acquisition cycles collected synchronously.

[0011] According to a third aspect of the present application, there is provided an FNIRS host interconnection component, which includes: at least two FNIRS hosts of any one of the various embodiments of the present application; and any one of the interconnection devices of the various embodiments of the present application, and the interconnection device is configured to connect the at least two FNIRS hosts to each other.

[0012] According to a fourth aspect of the present application, there is provided an FNIRS imaging system, which includes: an FNIRS host interconnection component of any one of the various embodiments of the present application; and a probe set connected to and used in conjunction with each FNIRS host, and the probe set includes a transmitting probe and a receiving probe. Each probe set supporting each FNIRS host has a first channel number. Among them, each FNIRS host is configured to control the corresponding probe set to synchronously acquire detection data of a second channel number based on the first acquisition timing signal of the first FNIRS host connected by the first connector, and the second channel number is greater than the first channel number.

[0013] According to the fifth aspect of the present application, a method for collecting detection data with a higher number of channels by interconnecting at least two fnirs devices is provided. Each fnirs device includes a probe group and any one of the fnirs hosts in the various embodiments of the present application that is connected to and used in conjunction with the probe group. Each probe group supported by each fnirs host includes a transmitting probe and a receiving probe. The method includes the following steps.

[0014] Interconnect the at least two fnirs devices with any one of the interconnecting devices in the various embodiments of the present application. Among them, insert the first connector of the interconnecting device into the first interface of the fnirs host that serves as the master host among the at least two fnirs devices, and insert the second connector of the interconnecting device into the second interface of the fnirs host that serves as the slave host among the at least two fnirs devices.

[0015] Wear each probe group on the head of the subject via the same headgear. Note that the order of the interconnecting operation of the fnirs hosts and the headgear wearing operation is not restricted.

[0016] Using each fnirs host that serves as the master host and the slave host, based on the first acquisition timing signal synchronously acquired by the fnirs host from the master host, control the transmitting probe and the receiving probe of the corresponding probe group to synchronously collect detection data, so as to obtain detection data with a higher number of channels.

[0017] Compared with the prior art, the beneficial effects that can be achieved by the above at least one technical solution adopted in the embodiments of the present application are as follows. Through the different dominant physical attributes of the second connector and the first connector of the interconnection device, the user can distinguish which connector is the first connector and which connector is the second connector. The first connector is configured to be detachably plugged into the first interface of the first fnirs host to be interconnected. That is, which fnirs host the user plugs the first connector into makes that fnirs host serve as the master host. The second connector is configured to be detachably plugged into the second interface of the second fnirs host to be interconnected. That is, which fnirs host the user plugs the second connector into makes that fnirs host serve as the slave host. That is to say, the user can, according to the distinguished first connector and second connector and different interconnection requirements, independently plug the first connector into the fnirs host that needs to be used as the master host, so as to be able to flexibly specify or clarify the fnirs host that needs to be used as the master host by plugging the first connector, which is beneficial to knowing and clarifying the master host, and further beneficial to clarifying which fnirs host to connect to the upper computer to view the acquisition and analysis results of the signals. Through the hardware transmission between the first connector and the processing circuit part of the master host, and the hardware transmission between the second connector and the processing circuit part of the slave host, and the transmitted acquisition timing signal can at least only include the start time of a series of acquisition cycles for synchronous acquisition (the start time of the first acquisition cycle), or can include the start time of each acquisition cycle. The amount of transmitted data is very small and it is a hardware transmission, which can significantly reduce the delay between the interconnected fnirs hosts (for example, control the delay below 10 microseconds). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 is a schematic diagram of an existing fnirs system provided by an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of the back side of an existing fnirs host provided by an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of the structure of an interconnection device for a fnirs host provided by an embodiment of the present application;

[0022] Figure 4It is a structural block diagram of an fnirs host interconnected by an interconnection device provided by an embodiment of the present application;

[0023] Figure 5 It is a timing schematic diagram of the acquisition timing signal for synchronous acquisition between interconnected fnirs hosts provided by an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram of the docking structure of an interface - connector when the dominant physical property is a circuit parameter provided by an embodiment of the present application;

[0025] Figure 7 It is a schematic diagram of an interconnection device with multiple second connectors for an fnirs host provided by an embodiment of the present application;

[0026] Figure 8 It is a schematic diagram of an fnirs host interconnection component presenting a star - shaped topology provided by an embodiment of the present application;

[0027] Figure 9 It is a flowchart of a method for using at least two interconnected fnirs devices to collect detection data with a higher number of channels provided by an embodiment of the present application. Detailed implementation manners

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0029] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0030] The terms used in the implementation manners of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the", and "said" used in various embodiments of the present application are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in various embodiments of the present application refers to and includes any or all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc. may be used in various embodiments of the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "in the case of" or "when" or "determined in response to...".

[0032] In addition, the drawings are only schematic diagrams and are not necessarily drawn to scale. The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities, unless physical independence is clearly defined in the context. That is, these functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0033] In an embodiment of the present application, an interconnection device for a fnirs host is provided. As Figure 3 shown, the interconnection device for the fnirs host includes a first connector 401, a second connector 402, and a cable connection part 403 for electrically connecting the first connector 401 and the second connector 402.

[0034] The first connector 401 is disposed at the first end of the interconnection device, and the first connector 401 is configured to be detachably plugged into the first interface of the first fnirs host to be interconnected. The user can use whichever host is desired as the master host in the interconnection as the first fnirs host.

[0035] The second connector 402 is disposed at the opposite end of the first end, and the second connector 402 has different dominant physical properties from the first connector 401. The second connector 402 is configured to be detachably plugged into the second interface of the second fnirs host to be interconnected. The user can use whichever host is desired as the slave host in the interconnection as the second fnirs host.

[0036] In the case where the first connector 401 is plugged into the first interface of the first fnirs host and the second connector 402 is plugged into the second interface of the second fnirs host, the first connector 401 receives the first acquisition timing signal synchronously acquired from the first processing circuit part of the first fnirs host, and transmits it to the second processing circuit part of the second fnirs host via the cable connection part 403 and the second connector 402. The first acquisition timing signal at least indicates the start time of a series of acquisition cycles for synchronous acquisition.

[0037] In some embodiments, Figure 4 As shown, the first fnirs host 700a and the second fnirs host 700b are connected via Figure 3 The interconnection device for the FNIRS host is interconnected, the first FNIRS host 700a includes a first main processor 701a, a first processing circuit unit 702a and at least one first interface 703a, the second FNIRS host 700b includes a second main processor 701b, a second processing circuit unit 702b and at least one second interface 703b, the first connector 401 of the interconnection device is inserted into the first interface 703a, so that the first FNIRS host 700a is used as a master host, and the second connector 402 of the interconnection device is inserted into the second interface 703b, so that the second FNIRS host 700b is used as a slave host, the first connector 401 receives the first acquisition timing signal of synchronous acquisition from the first processing circuit unit 702a of the first FNIRS host 700a, and transmits it to the second processing circuit unit 702b of the second FNIRS host 700b via the cable connection unit 403 and the second connector 402, and then the second main processor 701b receives the first acquisition timing signal from the second processing circuit unit 702b, and uses the first acquisition timing signal to start acquisition according to the respective SD sub-arrangement timing configuration information, so as to start acquisition synchronously with the first FNIRS host 700a.

[0038] In some embodiments, after multiple fnirs hosts are interconnected through an interconnection device for interconnecting devices, the host computer interacts with each interconnected fnirs host so that each fnirs host knows the SD sub-arrangement timing configuration information connected to each fnirs host (i.e., which transmitting probe of all interconnected SD channels the light source of each fnirs host is connected to, the timing of lighting each light source, the lighting duration of each light source, etc.) Figure 5 As shown, Figure 5 The timing information of the thin lines in the middle is the SD sub-arrangement timing configuration information of each fnirs host, and it is known that the synchronous acquisition should be run according to this interconnection mode, that is, the acquisition timing signal transmitted by the master host in the interconnection is used as the synchronous acquisition instruction to start the respective synchronous acquisition mode. Therefore, after each slave host knows its own SD sub-arrangement timing configuration information, as long as it knows the synchronous acquisition start instruction (such as the "first acquisition timing signal" mentioned above), it can autonomously start to execute the lighting / detection of its own S / D probe. When the upper computer sends the first acquisition timing signal of synchronous acquisition to the master host, the processing circuit part of the master host transmits the first acquisition timing signal ( Figure 5The dashed line therein is a first acquisition timing signal in the form of a rising edge, and the thick-line timing signal is a periodic first acquisition timing signal including a rising edge. The moment shown by the dashed line is also the moment when the master host sends the acquisition timing signal) to the processing circuit parts of each slave host, so that each slave host can start acquisition based on the first acquisition timing signal according to its own SD sub-arrangement timing configuration information, and start acquisition simultaneously with the master host to achieve synchronous acquisition.

[0039] In some embodiments, the first connector 401 is configured to be detachably plugged into the first interface 703a of the first fnirs host 700a to be interconnected. That is, the fnirs host into which the first connector 401 is plugged is the master host among the interconnected multiple fnirs hosts. The second connector 402 is configured to be detachably plugged into the second interface 703b of the second fnirs host 700b to be interconnected. That is, the fnirs host into which the second connector 402 is plugged is the slave host among the interconnected multiple fnirs hosts. It is proposed that the way of inserting the first connector 401 or the second connector 402 can be used to flexibly and freely determine which fnirs host is the master host and which fnirs host is the slave host, without the need to pre-specify or determine which fnirs host is the master host or the slave host on the fnirs host or the upper computer. To facilitate the distinction between the first connector 401 and the second connector 402, and thus determine how to insert the first connector 401 and the second connector 402, the first connector 401 and the second connector 402 have different dominant physical attributes, so that the first connector 401 and the second connector 402 can be distinguished based on the dominant physical attributes. For example, the dominant physical attributes may include physical attributes in appearance (for example, as Figure 3 shown, different appearance shapes, different imprints on the appearance, different colors, etc.), so that users can distinguish the first connector 401 and the second connector 402 by observing the differences in appearance. The dominant physical attributes also allow the processing circuit part in the fnirs host to distinguish whether the inserted one is the first connector 401 or the second connector 402 accordingly, so as to enable the fnirs host to autonomously identify whether it is the master host or the slave host by identifying whether the inserted one is the first connector 401 or the second connector 402; in addition, through the hardware transmission between the first connector 401 and the processing circuit part of the master host, and the hardware transmission between the second connector 402 and the processing circuit part of the slave host, and the transmitted acquisition timing signal can contain at least only the start time of a series of acquisition cycles for synchronous acquisition (the start time of the first acquisition cycle), or can contain the start time of each acquisition cycle. The amount of transmitted data is very small and it is a hardware transmission, which can significantly reduce the delay between the interconnected fnirs hosts (for example, control the delay below 10 microseconds).

[0040] In some embodiments, the processing circuitry may be a hardware circuit capable of implementing information recognition and data transmission to recognize whether the inserted connector is the first connector 401 or the second connector 402 and to transmit the acquisition timing signal.

[0041] In some embodiments, the explicit physical attribute may be physical contact. The first connector 401 is configured to form a first physical contact when inserted into the first interface, such that the first processing circuitry 702a recognizes the insertion of the first connector 401. The second connector 402 is configured to form a second physical contact when inserted into the second interface, such that the first processing circuitry 702b recognizes the insertion of the second connector 402. This physical contact may be any form of physical property difference that is convenient for the processing circuitry to recognize. For example, different numbers of contact pads, different-shaped contact pads, etc. may be provided on the first connector 401 and the second connector 402, such that the processing circuitry can recognize whether the inserted connector is the first connector 401 or the second connector 402 by recognizing the difference in the number and shape of the contact pads.

[0042] In some embodiments, when the explicit physical attribute is a physical attribute for the processing circuitry in the fnirs host to distinguish between the inserted first connector 401 and the second connector 402, the explicit physical attribute may also be a circuit parameter. The first connector 401 is configured to generate a first circuit parameter when inserted into the first interface, such that the first processing circuitry 702a recognizes the insertion of the first connector 401. The second connector 402 is configured to generate a different second circuit parameter when inserted into the second interface, such that the first processing circuitry 702b recognizes the insertion of the second connector 402. This circuit parameter may be voltage, current, etc. By providing different circuit components such as resistors, cables, contact pads, etc. on the first connector 401 and the second connector 402, and then electrically connecting the pin, cable, and other circuit contact components within the processing circuitry when the first connector 401 and the second connector 402 are plugged into the interfaces of the fnirs host, different circuit parameters are formed, and the processing circuitry distinguishes between the inserted first connector 401 and the second connector 402 based on the different circuit parameters.

[0043] In some embodiments, taking voltage as an example of circuit parameters, internal sites can be set at different voltages on the first connector 401 and the second connector 402. When the first connector 401 and the second connector 402 are plugged into the interface, the internal sites within the processing circuit portion are electrically connected to form different voltages to distinguish whether the inserted one is the first connector 401 or the second connector 402. For example, the first internal site of the first connector 401 is maintained at a first voltage, and the second internal site of the second connector 402 is maintained at a second voltage, where the first voltage is different from the second voltage (it can be different single-point voltage values or different voltage ranges). When the first internal site of the first connector 401 is plugged into the first interface, it is electrically connected to the third internal site within the first processing circuit portion 702a to form a third voltage, enabling the first processing circuit portion 702a to identify whether the inserted one is the first connector 401 or the second connector 402 based on the third voltage; when the second internal site of the second connector 402 is plugged into the second interface, it is electrically connected to the fourth internal site within the first processing circuit portion 702b to form a fourth voltage, where the third voltage is different from the fourth voltage, enabling the first processing circuit portion 702b to identify whether the inserted one is the first connector 401 or the second connector 402 based on the fourth voltage.

[0044] For example, the first internal site of the first connector 401 and the second internal site of the second connector 402 can be implemented in the form of cables, contacts, etc. with different voltages. When setting cables, one or more cables can be set. In the case of setting one cable, the cables of the first internal site of the first connector 401 and the second internal site of the second connector 402 are respectively maintained at different voltage values by means of grounding or resistance. In the case of setting multiple cables, the first internal site of the first connector 401 and the second internal site of the second connector 402 can be respectively connected to cables with different serial numbers and different voltages, such as Figure 6As shown, taking the setting of three cables as an example, the first internal site of the first connector 401 is connected to the first cable, and the first cable is grounded. The second internal site of the second connector 402 is connected to the second cable 1, and the second cable 2 is grounded. There are also three cables ID1, ID2, and ID3 set in the processing circuit part of the fnirs host, and the states of the cables ID1, ID2, and ID3 are pulled up to a high level (taking 5V voltage as an example) through internal resistors respectively. When the first connector 401 is connected to the interface, the cable ID1 in the processing circuit part is connected to the first cable of the first connector 401, and the cable ID1 is pulled to a low level, that is, ID1 = low level (GND), ID2 = high level, ID3 = high level; when the second connector 402 is connected to the interface, the cable ID2 in the processing circuit part is connected to the second cable of the second connector 402, and the cable ID2 is pulled to a low level, that is, ID1 = high level, ID2 = low level (GND), ID3 = high level. Therefore, due to the different internal wiring methods (or the connection methods of the contact pieces) of the first connector 401 and the second connector 402, different changes will occur in the voltage values of ID1, ID2, and ID3 in the processing circuit part after the connector is inserted. The processing circuit part can identify whether the inserted one is the first connector 401 or the second connector 402 based on these different voltage changes.

[0045] In some embodiments, when the dominant physical attribute is the physical attribute for the processing circuit part in the fnirs host to distinguish between the inserted first connector 401 and the second connector 402, the dominant physical attribute can also be a visual feature. The first connector 401 has a first visual feature, so that the first processing circuit part 702a can identify the insertion of the first connector 401 based on a visual sensor. The second connector 402 has a second visual feature, so that the second processing circuit part 702b can identify the insertion of the second connector 402 based on a visual sensor.

[0046] In some embodiments, when the dominant physical attribute is the physical attribute for the processing circuit part in the fnirs host to distinguish between the inserted first connector 401 and the second connector 402, the dominant physical attribute can also be a magnetic identifier. The first connector 401 has a first magnetic identifier, so that the first processing circuit part 702a can identify the insertion of the first connector 401 based on a magnetic sensor. The second connector 402 has a second magnetic identifier, so that the second processing circuit part 702b can identify the insertion of the second connector 402 based on a magnetic sensor.

[0047] In some embodiments, the magnetic identifier can be a barcode, a magnetic label, etc. The magnetic sensor can include any one of a Hall effect sensor, a magnetoresistive sensor, and a coil.

[0048] In some embodiments, the first connector 401 and the second connector 402 are both detachably plugged into the same interface of the same fnirs host. That is, for the same interface of the same fnirs host, either the first connector 401 can be inserted to make the fnirs host the master host in the interconnected fnirs hosts (i.e., used as the first interface 703a), or the second connector 402 can be inserted to make the fnirs host the slave host in the interconnected fnirs hosts (i.e., used as the second interface 703b).

[0049] In some embodiments, fnirs hosts of various models generally have at least one interface, which is a basic configuration. That is to say, the interconnection device for the fnirs host of the present application can be applied to the interconnection of fnirs hosts with a basic configuration having only a single interconnection interface. Of course, it is also applicable to the interconnection of fnirs hosts with a separately provided first interface and second interface.

[0050] In some embodiments, if the interconnected fnirs hosts are connected in series one by one in a daisy chain, then from the fnirs host at the beginning of the daisy chain to the fnirs host at the end, the transmission delay of the data will be superimposed, and the deviation from the beginning will be greater as it gets closer to the end. As the number of interconnected fnirs hosts increases, the delay deviation will further increase. To avoid the problem of the superposition of the delays of multiple interconnected fnirs hosts, it is proposed that the interconnection device includes a single first connector 401 and several second connectors 402, so that multiple interconnected fnirs hosts can achieve a master host connected in parallel to multiple slave hosts. For example, as Figure 7 ( Figure 7 taking 3 second connectors 402 as an example (the number of the specific second connectors 402 is not limited and can be determined according to specific usage requirements) shows, the interconnection device includes a single first connector 401 and several second connectors 402, the cable connection part 403 includes a first cable part 4031, an expansion part 4032 and several second cable parts 4033, the expansion part 4032 is electrically connected to the first connector 401 via the first cable part 4031, and is connected to the corresponding several second connectors 402 via the several second cable parts 4033.

[0051] In some embodiments, the expansion part 4032 can be any device capable of realizing data relay. For example, it can be an expansion dock, a synchronous relay box, etc.

[0052] In some embodiments, when the first connector 401 is plugged into the first interface 703a of the first fnirs host 700a and the second connector 402 is plugged into the second interface 703b of the second fnirs host 700b, the first acquisition timing signal synchronously acquired and transmitted outward by the first connector 401 via the cable connection portion 403 and the second connector 402 indicates at least the start time of a series of acquisition cycles of synchronous acquisition. That is, the first acquisition timing signal indicates that the acquisition cycles of multiple interconnected fnirs hosts start synchronous acquisition based on the same start time. This first acquisition timing signal can indicate either the start time of the first acquisition cycle in a series of acquisition cycles of synchronous acquisition or the start time of each acquisition cycle in a series of acquisition cycles of synchronous acquisition.

[0053] In some embodiments, the first acquisition timing signal may further include identifiers for each cycle of synchronous acquisition, such that the master host and the slave host can label each acquisition cycle based on the identifiers. After the acquired detection data is transmitted to the upper computer, the upper computer can aggregate the detection data acquired by multiple groups of channels with the same acquisition cycle identifier based on the identifier, and can also determine based on the identifier which acquisition cycle has a poor acquisition status of the slave host. If there is a slave host with a poor acquisition status in a certain acquisition cycle, the upper computer can discard the detection data of other slave hosts with good acquisition status in this acquisition cycle as well and no longer aggregate and use it, so that the detection data retained for each acquisition cycle is of good quality.

[0054] In some embodiments, the identifiers for each cycle of synchronous acquisition included in the first acquisition timing signal can be any identifier that can distinguish order or difference. For example, it can be an identifier in the form of a number, a letter, a string, etc.

[0055] In some embodiments, in order to avoid the problem that individual slave hosts cannot synchronize acquisition due to the main processor being occupied, when the first connector 401 is plugged into the first interface 703a of the first FNIRS host 700a and the second connector 402 is plugged into the second interface 703b of the second FNIRS host 700b, the first connector 401 transmits the first acquisition timing signal to the second processing circuit part 702b of the second FNIRS host 700b via the cable connection part 403 and the second connector 402 only when the second main processor 701b of the second FNIRS host 700b is idle. For example, before the master host (i.e., the fnirs host plugged into the first connector 401) sends the start time of each cycle, it can pre-determine whether the main processor of the slave host is busy. If it is busy, the master processor cannot perform synchronous acquisition. At this time, the master host can temporarily not send the start time of that acquisition cycle (i.e., temporarily not send the first acquisition timing signal), because it cannot be executed even if it is sent. When it is pre-determined that the main processors of each slave host are not busy, the first acquisition timing signal including the start time of the acquisition cycle is sent to each slave host, so that the master host and each slave host can start synchronous acquisition at the same time.

[0056] In some embodiments of the present application, a fnirs host is also provided, which can be used as a master host (i.e. Figure 4 The first fnirs host 700a) can be used as a slave host (i.e. Figure 4 Note that the use of component designation x without suffixes a and b in the following text is intended to include both xa and xb. For example, when referring to the fnirs host 700 or another fnirs host 700, both can be used as the first fnirs host 700a or the second fnirs host 700b.

[0057] The fnirs host 700 may include: a main processor 701 configured to control the acquisition of fnirs detection signals; at least one interface 703 configured to insert a first connector 401 or a second connector 402 for an interconnection device of the fnirs host; a processing circuit unit 702 separate from the main processor, configured to identify whether the connector inserted into the at least one interface 703 is the first connector 401 or the second connector 402; in the case where the identified inserted connector is the first connector 401, transmit the acquisition timing signal acquired synchronously to the corresponding processing circuit unit 702 of another interconnected fnirs host 700 via the at least one interface 703, and in the case where the identified inserted connector is the second connector 402, receive another acquisition timing signal acquired synchronously from the corresponding processing circuit unit 702 of another interconnected fnirs host 700 via the at least one interface 703.

[0058] The main processor 701 is further configured to: in the case where the processing circuit unit 702 receives the another acquisition timing signal (at this time as a slave host), receive the another acquisition timing signal from the processing circuit unit 702 and use the another acquisition timing signal to perform synchronous acquisition of fnirs detection signals. When the main processor 701 transmits the acquisition timing signal acquired synchronously outward (at this time as a master host), use the acquisition timing signal acquired synchronously transmitted outward to perform synchronous acquisition of fnirs detection signals, and the acquisition timing signal at least indicates the start time of a series of acquisition cycles acquired synchronously.

[0059] In some embodiments, the main processor 701 may be any one of a CPU, an MPU, a GPU, and an SOC processor chip. The processing circuit unit may be a hardware circuit capable of realizing information recognition and data transmission. For example, it may be an ASIC circuit or an FPGA circuit.

[0060] In some embodiments, in order to achieve lower cost and greater flexibility in modifying the fnirs host, preferably, the processing circuit unit 702 may be an FPGA circuit. If an existing fnirs host needs to be modified, open the chassis, install the FPGA circuit inside, program the FPGA to perform the tasks of access recognition of the connector and mutual transmission of the acquisition timing signal, then interconnect it with the main processor, and update the application program of the main processor.

[0061] In some embodiments, in order to further reduce the latency between fnirs hosts caused by interconnection, the processing circuit unit 702 is configured to identify the insertion connector and transmit the corresponding acquisition timing signal without relying on the main processor 701. That is, the processing circuit unit 702 is configured to centrally handle the processing tasks of fnirs host interconnection (such as identifying the insertion connector, transmitting the corresponding acquisition timing signal, etc.), without relying on the main processor 701, and all are processed by the hardware circuit. In this way, the latency between fnirs hosts caused by interconnection can be minimized. For example, the latency can be controlled at a level of 10µs, 8µs, 6µs, or even 4µs and below.

[0062] In some embodiments, the processing circuit unit 702 is further configured to identify whether the inserted connector is the first connector 401 or the second connector 402 by detecting any one or any combination of the following dominant physical attributes:

[0063] Physical contact, circuit parameters generated by the insertion connector, and visual features. That is, the processing circuit unit 702, based on the dominant physical attributes of the insertion connector being any one or any combination of physical contact, circuit parameters generated by the insertion connector, and visual features, identifies whether the inserted connector is the first connector 401 or the second connector 402. This is similar to the description of the dominant physical attributes of the interconnection device for the fnirs host in the foregoing embodiments and will not be elaborated here.

[0064] In some embodiments, the at least one interface 703 can be a single interface, and the single interface can be a lemo interface or a DB square connector of the fnirs host.

[0065] In some embodiments, the acquisition timing signal further includes an identifier for each cycle of synchronous acquisition. That is, the acquisition timing signal transmitted by the processing circuit unit of the master host to the processing circuit units of each slave host through the interconnection device for the fnirs host can also include an identifier for each acquisition cycle of synchronous acquisition, so that the master host and the slave hosts can identify each acquisition cycle based on the identifier. After the detected data collected is transmitted to the upper computer, the upper computer can aggregate the detected data collected by multiple channels with the same acquisition cycle identifier based on the identifier, and can also judge based on the identifier which acquisition cycle has a poor acquisition status of the slave host, so that the detected data of other slave hosts with good acquisition status in this acquisition cycle can also be discarded and not aggregated for use, so that the detected data retained for each acquisition cycle is of good quality.

[0066] In some embodiments, the acquisition timing signal acquired synchronously transmitted by the master host to the processing circuit units of each slave host through the interconnection device for the fnirs host indicates at least the start time of a series of acquisition cycles of the synchronous acquisition, that is, the acquisition timing signal indicates that the acquisition cycles of the interconnected multiple fnirs hosts start synchronous acquisition based on the same start time. This acquisition timing signal can indicate either the start time of the first acquisition cycle in a series of acquisition cycles of the synchronous acquisition, as shown in Figure 5 ( Figure 5 the timing information of the thin lines in is the SD sub-arrangement timing configuration information of each fnirs host, Figure 5 the dotted line in is an acquisition timing signal in the form of a rising edge, and the thick-line timing signal is a periodic acquisition timing signal including a rising edge. The moment indicated by the dotted line is also the moment when the master host sends the acquisition timing signal); or it can indicate the start time of each acquisition cycle in a series of acquisition cycles of the synchronous acquisition, that is, in each acquisition cycle, the master host transmits the acquisition timing signal acquired synchronously to the processing circuit units of each slave host through the interconnection device for the fnirs host, so that each slave host can be based on this acquisition timing signal with the master host and start acquisition according to its own SD sub-arrangement timing configuration information (the SD sub-arrangement timing configuration information of each fnirs host includes the serial number of the SD probe of each fnirs host, which section of the timing signal in the total synchronous acquisition timing cycle to light / detect, etc.) to achieve synchronous acquisition. The acquisition timing signal of this synchronous acquisition can be a rising edge signal or a periodic timing signal including a rising edge. Note that in this application, the expression "total synchronous acquisition timing cycle" is intended to represent Figure 5 all the complete acquisition timing cycles (including thick lines and thin lines) in, which includes when each S / D of each serial number is lit / detected, and is distinguished from the "first acquisition timing signal" and the "acquisition timing signal".

[0067] In some embodiments, each fnirs host can be made to know the SD sub-arrangement timing configuration information of the S / D probes connected to it (that is, the timing when each S probe of each fnirs host is lit, the duration when each S probe is lit, the timing and duration when each D probe is detected, their order and the relationship of simultaneous lighting / detection, etc.) in various ways. After knowing this configuration information, as long as the synchronous acquisition start instruction (such as the "first acquisition timing signal" in the above text) is obtained, it can independently start to execute the lighting / detection of its own S / D probes, thereby achieving synchronous acquisition of high-channel detection data.

[0068] In some embodiments, each interconnected fnirs host can learn about the timing configuration information of its own SD sub-arrangement through interaction with the host computer. There are various interaction methods, and the present application does not make specific limitations. For example, it can be achieved through the following different methods.

[0069] a. Connect multiple fnirs hosts to be interconnected to the same host computer, either wirelessly or wired. The high-channel detection data collected by the subsequent interconnected fnirs hosts is also analyzed and displayed on a single host computer. The host computer can identify how many fnirs hosts are connected and their connected SD configurations (such as 8S8D); operate on the host computer to inform each fnirs host to operate in this interconnected mode of integrating low channels to form high channels, and configure the position allocation of the SD probe groups connected to each fnirs host in the target high-channel arrangement. This configuration can be automatically generated by the host computer or the host computer can provide multiple options for the user to choose.

[0070] b. Connect multiple fnirs hosts to be interconnected to the same host computer. According to the number of fnirs hosts, SD configuration, and the expected target high-channel arrangement, the user queries the position allocation of the SD probes connected to each host in the operation manual, completes the plugging of each group of SD probes accordingly, and interacts and confirms the position allocation of the SD probe groups of each host and the formed target high-channel SD arrangement on the operation interface of the same host computer. Then the host computer informs each fnirs host of the position allocation of its SD probe group.

[0071] Each fnirs host knows its own SD position allocation, that is, it knows which site (sequence number) of S (emitting probe) and which site (sequence number) of D (receiving probe) it corresponds to in the target high-channel arrangement. Thus, it also knows which time segments in the total synchronization acquisition time period indicate the lighting of its own light source and the reception of the detection probe. From this, it is determined when the total synchronization acquisition time period starts. For example, knowing the start of the period through the "(first) acquisition timing signal", it can independently complete the lighting / detection operations in the time domain responsible for in the synchronization acquisition.

[0072] In some embodiments, the processing circuit unit 702 is further configured to: when the main processor 701 of the other fnirs host 700 is occupied, temporarily refrain from transmitting the acquisition timing signal collected synchronously outward through the at least one interface 703. That is, in a plurality of interconnected fnirs hosts, if the main processor of an individual slave host is occupied, the master host temporarily refrains from transmitting the acquisition timing signal collected synchronously outward through the at least one interface to each slave host, that is, temporarily does not send the acquisition timing signal collected synchronously to each slave host. When the main processors of all slave hosts are not occupied, then transmit the acquisition timing signal collected synchronously outward through the at least one interface to each slave host, so as to ensure that each slave host can perform synchronous acquisition with the master host based on the acquisition timing signal.

[0073] In some embodiments of the present application, there is also provided a fnirs host interconnection component, including: at least two fnirs hosts of any one of the various embodiments of the present application; and

[0074] any one of the interconnection devices for fnirs hosts in the various embodiments of the present application, the interconnection device being configured to connect the at least two fnirs hosts to each other.

[0075] In some embodiments, when there are multiple fnirs hosts included, refer to Figure 7 , the interconnection device includes a single first connector 401 and several second connectors 402, the cable connection part 403 includes a first cable part 4031, an extension part 4032, and several second cable parts 4033. The extension part 4032 is electrically connected to the first connector 401 via the first cable part 4031, and is connected to the corresponding several second connectors 402 via several second cable parts 4033. Referring to Figure 4 together, the single first connector 401 is inserted into the first interface 703a of a fnirs host 700a (this fnirs host serves as the master host), and several second connectors 402 are respectively inserted into the second interfaces 703b of the remaining fnirs hosts 700b (the remaining fnirs hosts serve as slave hosts), so as to achieve parallel interconnection of one master host and multiple slave hosts, avoid the superposition of delays of interconnected fnirs hosts, and avoid delay accumulation. As Figure 8 shown, one master host 700a is interconnected in parallel with multiple slave hosts 700b ( Figure 8 taking 7 fnirs hosts 700b shown as slave hosts as an example) through the interconnection device for fnirs hosts, and forms a link in a star topology structure.

[0076] In some embodiments of the present application, a fnirs imaging system is further provided. The system includes:

[0077] Any one of the fnirs host interconnection components in various embodiments of the present application; and

[0078] A probe group including a transmitting probe (i.e., S) and a receiving probe (i.e., D) connected to and used in conjunction with each fnirs host. Each of the probe groups has a first number of channels. Among them, each fnirs host is configured to control the corresponding probe group to synchronously collect detection data of a second number of channels based on the first acquisition timing signal of the first fnirs host 700a connected by the first connector 401, and the second number of channels is greater than the first number of channels.

[0079] In some embodiments, the first number of channels is the number of channels for each of the interconnected fnirs hosts to independently implement detection data acquisition, and the second number of channels is the number of channels for all interconnected devices to achieve detection data acquisition through synchronous acquisition.

[0080] In some embodiments, the fnirs imaging system further includes:

[0081] A host computer. The host computer receives the detection data of the second number of channels synchronously collected by each fnirs host, and displays and analyzes the detection data. That is, the same host computer is used to display and analyze the detection data of the second number of channels synchronously collected by all interconnected fnirs hosts.

[0082] In some embodiments, each interconnected fnirs host can be respectively connected to a host computer. However, whichever fnirs host serves as the master host, the host computer connected to that fnirs host is used to uniformly display and analyze the detection data of the second number of channels synchronously collected by all interconnected fnirs hosts. All interconnected fnirs hosts can also be connected to a single host computer, and that single host computer is used to uniformly display and analyze the detection data of the second number of channels synchronously collected by all interconnected fnirs hosts.

[0083] In some embodiments, each fnirs host to be interconnected can be connected to the host computer through a wireless transmitter or a wired connection. At the host computer, it is determined how to form a high-channel SD total layout, and which position (or S / D serial number) in the total layout each S / D probe connected to each fnirs host serves as. Each fnirs host can learn the S / D serial numbers of the respective S / D probes it is connected to in the total layout and synchronous acquisition in various ways from the host computer.

[0084] After each interconnected fnirs host in the fnirs host interconnection component is interconnected through the interconnection device for the interconnection device, the upper computer interacts with each interconnected fnirs host so that each fnirs host knows the SD sub-arrangement timing configuration information connected to it (that is, which emission probe in all the SD channels interconnected with the light source of each fnirs host is connected, the timing of each light source being lit, the duration of each light source being lit, etc.), and knows to operate synchronous acquisition according to this interconnection mode, that is, to use the acquisition timing signal transmitted by the master host in the interconnection as a synchronous acquisition instruction to start its own synchronous acquisition mode, and the upper computer sends the acquisition timing signal of the synchronous acquisition to the master host, and then the processing circuit part of the master host transmits the acquisition timing signal to the processing circuit parts of each slave host through the interconnection device, so that each slave host can start acquisition simultaneously with the master host based on the acquisition timing signal to achieve synchronous acquisition.

[0085] In some embodiments of the present application, a method for using at least two interconnected fnirs devices to collect detection data with a higher number of channels is also provided. Each fnirs device includes a probe group and any one of the fnirs hosts in each embodiment of the present application connected to and used in conjunction with the probe group. The probe group includes an emission probe and a reception probe. As Figure 9 shown, the method includes:

[0086] Step S901: Connect the at least two fnirs devices to each other through any one of the interconnection devices for the fnirs host in each embodiment of the present application. Among them, insert the first connector 401 of the interconnection device into the first interface 703a of the fnirs host 700a that serves as the master host among the at least two fnirs devices, and insert the second connector 402 of the interconnection device into the second interface 703b of the fnirs host 700b that serves as the slave host among the at least two fnirs devices;

[0087] Step S902: Wear each probe group on the head of the subject through the same headgear;

[0088] Step S903: Use each fnirs host serving as the master host and the slave host to control the emission probe and the reception probe of the corresponding probe group to synchronously collect detection data based on the first acquisition timing signal of the synchronous acquisition from the fnirs host of the master host, so as to obtain detection data with a higher number of channels.

[0089] The embodiments of the present application achieve the following technical effects: By virtue of the different dominant physical attributes of the second connector 402 and the first connector 401, it is possible to distinguish which connector is the first connector 401 and which connector is the second connector 402. The first connector 401 is configured to be detachably plugged into the first interface 703a of the first fnirs host 700a to be interconnected. That is, which fnirs host the first connector 401 is plugged into, which fnirs host is the master host. The second connector 402 is configured to be detachably plugged into the second interface 703b of the second fnirs host 700b to be interconnected. That is, which fnirs host the second connector 402 is plugged into, which fnirs host is the slave host. In this case, the user can, according to the distinguished first connector 401 and second connector 402 and different interconnection requirements, arbitrarily and independently plug the first connector 401 into the fnirs host that needs to be used as the master host, so as to be able to flexibly and arbitrarily specify or identify the fnirs host that needs to be used as the master host by plugging the first connector 401. This is conducive to knowing and identifying the master host, and further conducive to identifying which fnirs host to connect to the upper computer to view the signal acquisition and analysis results.

[0090] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the embodiments of the present application can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order from here, or they can be separately made into individual integrated circuit modules, or multiple modules or steps among them can be made into a single integrated circuit module to implement. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0091] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the embodiments of the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A fnirs host interconnection component, characterized in that: include: At least two fnirs hosts; as well as an interconnection device for a fnirs host, the interconnection device being configured to interconnect the at least two fnirs hosts; Wherein, the interconnection device comprises: A first connector is disposed at a first end of the interconnect device, the first connector being configured to be detachably plugged into an interface of a first FNIRS host among the at least two FNIRS hosts; a second connector disposed at an end opposite to the first end, the second connector having different dominant physical properties from the first connector, the second connector being configured to be removably plugged into an interface of a second FNIRS host of the at least two FNIRS hosts; and A cable connection part, the cable connection part is used to electrically connect the first connector and the second connector, wherein, when the first connector is plugged into the interface of the first FNIRS host and the second connector is plugged into the interface of the second FNIRS host, the first connector receives the acquisition timing signal of the synchronous acquisition from the processing circuit part of the first FNIRS host, and transmits it to the processing circuit part of the second FNIRS host via the cable connection part and the second connector; Each of the at least two fnirs hosts comprises: A main processor configured to control the acquisition of the fNIRS detection signal; at least one interface configured to be plugged into a first connector or a second connector of an interconnect device for an fnirs host; A processing circuit unit separate from the main processor is configured to identify whether the connector inserted into the at least one interface is the first connector or the second connector; in the case of identifying that the inserted connector is the first connector, it is determined that it is the first FNIRS host, used as a master host, and transmits a synchronously collected acquisition timing signal to the processing circuit unit of the interconnected second FNIRS host via the at least one interface; in the case of identifying that the inserted connector is the second connector, it is determined that it is the second FNIRS host, used as a slave host, and receives another synchronously collected acquisition timing signal from the processing circuit unit of the interconnected first FNIRS host via the at least one interface; The main processor is further configured to: when used as a slave host, in the case where the processing circuit unit receives the other acquisition timing signal, receive the other acquisition timing signal from the processing circuit unit, and use the other acquisition timing signal to synchronously acquire the FNIRS detection signal; when used as a master host, in the case where the processing circuit unit transmits the acquisition timing signal for synchronous acquisition externally, use the acquisition timing signal for synchronous acquisition transmitted externally to synchronously acquire the FNIRS detection signal, and the acquisition timing signal at least indicates the start time of a series of acquisition cycles of synchronous acquisition.

2. The fnirs host interconnect component according to claim 1, characterized in that In the case where there are multiple fnirs hosts, the interconnection device includes a single first connector and several second connectors, the cable connection portion includes a first cable portion, an expansion portion and several second cable portions, the expansion portion is electrically connected to the first connector via the first cable portion, and is connected to the corresponding several second connectors via several second cable portions, the single first connector is inserted into the first interface of one fnirs host, and the several second connectors are respectively inserted into the second interfaces of the remaining fnirs hosts.

3. The fnirs host interconnection component as claimed in claim 1, characterized in that The first connector and the second connector are detachably plugged into the same interface of the same fnirs host.

4. The fnirs host interconnection component according to any one of claims 1 to 3, characterized in that The explicit physical attribute is physical contact, the first connector is configured to form a first physical contact when inserted into the interface of the first FNIRS host, so that the processing circuit unit of the first FNIRS host recognizes the insertion of the first connector, and the second connector is configured to form a second physical contact when inserted into the interface of the second FNIRS host, so that the processing circuit unit of the second FNIRS host recognizes the insertion of the second connector.

5. The fnirs host interconnection component according to any one of claims 1 to 3, characterized in that: The explicit physical attribute is a circuit parameter, the first connector is configured to generate a first circuit parameter when inserted into the interface of the first FNIRS host, so that the processing circuit unit of the first FNIRS host recognizes the insertion of the first connector, and the second connector is configured to generate a different second circuit parameter when inserted into the interface of the second FNIRS host, so that the processing circuit unit of the second FNIRS host recognizes the insertion of the second connector.

6. The fnirs host interconnection component according to any one of claims 1 to 3, characterized in that: The explicit physical attribute is a visual feature, the first connector has a first visual feature so that the processing circuit unit of the first FNIRS host recognizes the insertion of the first connector based on a visual sensor, and the second connector has a second visual feature so that the processing circuit unit of the second FNIRS host recognizes the insertion of the second connector based on the visual sensor.

7. The fnirs host interconnection component as claimed in claim 5, characterized in that The first internal site of the first connector is maintained at a first voltage, the second internal site of the second connector is maintained at a second voltage, the first internal site of the first connector is electrically connected to a third internal site in the processing circuit portion of the first FNIRS host when plugged into the interface of the first FNIRS host, and the second internal site of the second connector is electrically connected to a fourth internal site in the processing circuit portion of the second FNIRS host when plugged into the interface of the second FNIRS host.

8. The fnirs host interconnection component as claimed in claim 3, characterized in that The interconnection device includes a single first connector and several second connectors, the cable connection portion includes a first cable portion, an expansion portion and several second cable portions, the expansion portion is electrically connected to the first connector via the first cable portion, and is connected to the corresponding several second connectors via the several second cable portions.

9. The fnirs host interconnection component according to any one of claims 1 to 3, characterized in that: The acquisition timing signal also includes identification of each cycle of synchronous acquisition.

10. The fnirs host interconnection component according to any one of claims 1 to 3, characterized in that: When the first connector is plugged into the interface of the first FNIRS host and the second connector is plugged into the interface of the second FNIRS host, the first connector transmits the acquisition timing signal to the processing circuit part of the second FNIRS host via the cable connection part and the second connector only when the main processor of the second FNIRS host is idle.

11. The fnirs host interconnection component according to claim 1, characterized in that The processing circuit part is an FPGA circuit.

12. The fnirs host interconnection component according to claim 1 or 11, characterized in that: The processing circuit unit is configured to identify the inserted connector and transmit the corresponding acquisition timing signal independently of the main processor.

13. The fnirs host interconnection component according to claim 1 or 11, characterized in that: The at least one interface is a single interface, and the single interface is a Lemo interface or a DB square connector of the fnirs host.

14. The fnirs host interconnection component according to claim 11, characterized in that The acquisition timing signal also includes identification of each cycle of synchronous acquisition.

15. The fnirs host interconnection component according to claim 1 or 11, characterized in that: The processing circuit unit is further configured to temporarily not transmit the synchronously collected acquisition timing signal to the outside via the at least one interface when the main processor of the other fnirs host is occupied.

16. An fNIRS imaging system, characterized in that: include: The fnirs host interconnect assembly as claimed in any one of claims 1 to 15; and A probe group including a transmitting probe and a receiving probe connected to and used in conjunction with each fnirs host, each of the probe groups having a first number of channels, wherein each fnirs host is configured to control the corresponding probe group to synchronously acquire detection data of a second number of channels based on an acquisition timing signal of the first fnirs host connected to the first connector, wherein the second number of channels is greater than the first number of channels.

17. The fNIRS imaging system of claim 16, wherein: Also includes: The host computer receives the detection data of the second channel number synchronously collected by each fnirs host, and displays and analyzes the detection data.

18. A method for collecting detection data with a higher number of channels using the FNIRS host interconnection component according to any one of claims 1 to 15, wherein each FNIRS host and a probe group connected to and used in conjunction with the FNIRS host constitute an FNIRS device, wherein the probe group includes a transmitting probe and a receiving probe, and the method comprises: At least two FNIRS devices are interconnected through the interconnection device, wherein a first connector of the interconnection device is inserted into an interface of an FNIRS host serving as a master host in the at least two FNIRS devices, and a second connector of the interconnection device is inserted into an interface of an FNIRS host serving as a slave host in the at least two FNIRS devices; Wearing each probe set on the subject's head via the same head cap; Each fnirs host as the master host and the slave host controls the transmitting probe and the receiving probe of the corresponding probe group to synchronously collect detection data based on the first acquisition timing signal of the fnirs host of the master host, so as to obtain detection data with a higher number of channels.

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