Secondary side soft start circuit applied to isolated DC-DC power supply chip

Abstract

The invention relates to a secondary side soft start circuit applied to an isolated DC-DC power supply chip. The secondary side soft start circuit comprises a first current source, an energy storage module, a second current source, an initialization module and a source follower, the initialization module works before the output voltage exceeds the threshold voltage, the voltage value of the second end follows the voltage value of the voltage division signal input by the first end, energy is stored in the energy storage module so as to indirectly record the voltage value of the voltage division signal, and when the output voltage exceeds the threshold voltage, the second current source begins to store energy in the energy storage module so as to record the voltage value of the voltage division signal. Meanwhile, the source follower starts to work, the source follower outputs a current second following signal according to the reference current of the first current source input by the drain electrode and the current voltage value of the second end input by the grid electrode, and the voltage value of the current second following signal is the voltage value of the voltage division signal indirectly recorded by the energy storage module at present; and then the second following signal slowly rises to a preset voltage value. According to the invention, the undershoot of the output voltage can be avoided when the output voltage exceeds the threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a secondary side soft start circuit applied to an isolated DC-DC power supply chip. Background Art

[0002] There is no direct electrical connection between the input circuit and the output circuit of the isolated power supply. The input power supply and the output voltage are relatively independent, which can effectively prevent the power supply noise from being transmitted to the output end, thereby improving reliability and safety.

[0003] Early isolated power supplies did not have a soft-start circuit. After the circuit was enabled, the output voltage VISO started to climb from 0V and reached a stable state in a relatively short period of time. During this process, there were two uncontrollable factors: excessive input current and output voltage overshoot, which brought risks to the front-stage power supply and the subsequent electrical equipment.

[0004] like Figure 1 As shown in the figure, the primary power supply stores the input power energy into the primary side of the transformer according to the fixed PWM duty cycle, and then transfers the energy to the rectifier circuit through the transformer, and finally stores it in the output capacitor. If the PWM duty cycle is set too large, a large primary current will be drawn at startup, causing output voltage overshoot. If the PWM duty cycle is set too small and a large output capacitor is used, it will result in a long startup time, and there is a risk of not meeting the requirements.

[0005] Figure 2 The figure shows a schematic diagram of a closed-loop soft-start control circuit of an existing isolated DC-DC power supply chip. In the existing closed-loop soft-start control process, when the output voltage VISO does not exceed the threshold voltage UVLO, the primary soft-start circuit in the soft-start circuit of the isolated DC-DC power supply chip works, and the secondary soft-start circuit does not work. At this time, the duty cycle of the PWM1 signal of the input oscillator is determined by the primary soft-start circuit. The primary soft-start circuit generates a PWM1 signal with a gradually increasing duty cycle. There are multiple circuit structures. When the output voltage VISO exceeds the threshold voltage UVLO, the primary soft-start circuit does not work, and the secondary soft-start circuit works. At this time, the duty cycle of the PWM1 signal of the input oscillator is determined by the output voltage VISO and the secondary soft-start circuit. However, when the primary soft-start circuit finishes working and the secondary soft-start circuit starts working, the output voltage VISO will have an instantaneous undershoot, such as Figure 6 shown.

[0006] How to avoid the phenomenon that the output voltage VISO momentarily undershoots when the primary side soft start circuit stops working and the secondary side soft start circuit starts working is a technical problem that needs to be solved urgently. Summary of the invention

[0007] In order to solve the problems in the prior art, the embodiments of the present invention provide a secondary side soft start circuit applied to an isolated DC-DC power supply chip. An initialization module is added to the secondary side soft start circuit. When the primary side soft start circuit is working, the initialization module works to record the voltage division signal of the output voltage VISO. When the secondary side soft start circuit is working, the initialization module stops working and makes the follow-up signal output by the secondary side soft start circuit slowly climb from the recorded voltage division signal instead of starting from 0, so that the output voltage VISO maintains a smooth transition during the switching process between the two stages and finally rises to the target voltage.

[0008] On the one hand, an embodiment of the present specification provides a secondary side soft start circuit applied to an isolated DC-DC power supply chip, comprising: a first current source, an energy storage module, a second current source, an initialization module and a source follower;

[0009] The first end of the initialization module is used to input the voltage division signal of the output voltage VISO of the isolated DC-DC power supply chip, the second end of the initialization module is connected to the gate of the source follower and the energy storage module, and the third end of the initialization module is connected to the output end of the secondary side soft start circuit;

[0010] The drain of the source follower is connected to the first current source, and the source of the source follower is connected to the output end of the secondary side soft start circuit;

[0011] Before the output voltage VISO exceeds the threshold voltage UVLO, the initialization module works, the voltage value of the second terminal follows the voltage value of the voltage-divided signal input by the first terminal, and stores energy in the energy storage module to indirectly record the voltage value of the voltage-divided signal, and the third terminal outputs a first follow-up signal, and the voltage value of the first follow-up signal slowly rises from the initial value;

[0012] When the output voltage VISO exceeds the threshold voltage UVLO, the second current source starts to store energy in the energy storage module, and the source follower starts to work at the same time. The source follower outputs a current second follow signal according to the reference current of the first current source input at the drain and the current voltage value of the second end input at the gate. The voltage value of the current second follow signal is the voltage value of the voltage division signal currently indirectly recorded by the energy storage module. After the output voltage VISO exceeds the threshold voltage UVLO, the second follow signal slowly rises to a preset voltage value. The second follow signal is used to control the PWM duty cycle of the isolated DC-DC power supply chip, so that the output voltage VISO rises steadily from the threshold voltage UVLO to the target voltage.

[0013] Furthermore, it also includes a sampling resistor Rss;

[0014] The first end of the Rss is respectively connected to the third end, the source of the source follower and the output end of the secondary side soft start circuit;

[0015] The second end of the Rss is grounded.

[0016] Further, the initialization module includes a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, an NMOS tube N1 and an NMOS tube N4;

[0017] The input end of the input branch in the first current mirror circuit is connected to the drain of N1 through the switch S1, the gate of N1 is connected to the drain, and the source of N1 is connected to the third end;

[0018] The output branch of the first current mirror circuit is connected to the input branch of the second current mirror circuit through a switch S2;

[0019] The output branch of the second current mirror circuit is connected to the source of N4, and is used to provide a discharge current to N4;

[0020] The output branch of the third current mirror circuit is connected to the drain of N4, and is used to provide a charging current to N4;

[0021] The gate and drain of N4 are connected, the drain of N4 is connected to the second end of the initialization module through the switch S3, and the source of N4 is connected to the first end of the initialization module through the switch S4.

[0022] Further, before the output voltage VISO exceeds the threshold voltage UVLO, the S1, S2, S3 and S4 are all kept closed;

[0023] When the output voltage VISO exceeds the threshold voltage UVLO, the S1 , S2 , S3 and S4 are all disconnected. After the output voltage VISO exceeds the threshold voltage UVLO, the S1 , S2 , S3 and S4 remain disconnected.

[0024] Furthermore, it also includes a clamping module;

[0025] The input end of the clamp module is connected to the third end, and the output end of the clamp module is grounded.

[0026] Further, the clamping module includes NMOS tubes N8 and N9;

[0027] The drain and gate of N8 are both connected to the third terminal, and the source of N8 is respectively connected to the drain and gate of N9;

[0028] The source of N9 is grounded.

[0029] Furthermore, it also includes an NMOS tube N5;

[0030] The source of N5 is connected to the second end, the gate of N5 is connected to the first end, and the drain of N5 is connected to the reference voltage.

[0031] Furthermore, an input branch of the first current mirror circuit is the same as an input branch of the third current mirror circuit.

[0032] Further, the input branch of the first current mirror circuit or the input branch of the third current mirror circuit includes PMOS tubes P1 and P4, and a resistor R1, and the output branch of the first current mirror circuit includes PMOS tubes P2 and P5;

[0033] The input branch of the second current mirror circuit includes NMOS tubes N2 and N6 and a resistor R2, and the output branch of the second current mirror circuit includes NMOS tubes N3 and N7;

[0034] The output branch of the third current mirror circuit includes PMOS tubes P3 and P6;

[0035] The source of P1, the source of P2, and the source of P3 are all connected to the reference voltage;

[0036] The drain of P1 is connected to the source of P4, and the gate of P1 is connected to the gate of P2, the gate of P3 and the drain of P4 respectively;

[0037] The drain of P4 is connected to the first end of R1, and the gate of P4 is connected to the second end of R1, the gate of P5 and the gate of P6 respectively;

[0038] The second end of R1 is connected to the first end of S1, and the second end of S1 is connected to the drain and gate of N1;

[0039] The drain of P2 is connected to the source of P5, and the drain of P5 is connected to the first end of S2;

[0040] The second end of S2 is connected to the gates of N6 and N7 and the first end of R2 respectively;

[0041] The second end of R2 is connected to the drain of N6 and the gates of N2 and N3 respectively;

[0042] The source of N6 is connected to the drain of N2, and the sources of N2 and N3 are both grounded;

[0043] The drain of N3 is connected to the source of N7, and the drain of N7 is connected to the source of N4;

[0044] The drain of P3 is connected to the source of P6, and the drain of P6 is connected to the drain of N4.

[0045] Further, switches Sss1 and Sss2 are included;

[0046] The first end of the Sss1 is connected to the first current source, and the second end of the Sss1 is connected to the drain of the source follower;

[0047] The first end of the Sss2 is connected to the second current source, and the second end of the Sss2 is connected to the energy storage module;

[0048] Before the output voltage VISO exceeds the threshold voltage UVLO, the Sss1 and the Sss2 remain disconnected;

[0049] When the output voltage VISO exceeds the threshold voltage UVLO, both the Sss1 and the Sss2 are closed, and after the output voltage VISO exceeds the threshold voltage UVLO, both the Sss1 and the Sss2 remain closed. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of this article or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of this article. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 It is a schematic diagram of the structure of an isolated DC-DC power supply chip in an embodiment of this specification;

[0052] Figure 2 This is a schematic diagram of a closed-loop soft-start control circuit of an isolated DC-DC power supply chip in an embodiment of this specification;

[0053] Figure 3 This is a structural schematic diagram of a secondary side soft start circuit applied to an isolated DC-DC power supply chip in an embodiment of this specification;

[0054] Figure 4 This is a circuit diagram of an initialization module in an embodiment of this specification;

[0055] Figure 5 The output voltage VISO curve of the isolated DC-DC chip when the secondary side soft start circuit of the embodiment of this specification is applied;

[0056] Figure 6It is the output voltage VISO curve of the isolated DC-DC chip in the prior art.

[0057] [Description of Reference Numerals]

[0058] 401. A first current mirror circuit;

[0059] 4011, input branch;

[0060] 4012, output branch;

[0061] 402, a second current mirror circuit;

[0062] 4021, input branch;

[0063] 4022, output branch;

[0064] 403. a third current mirror circuit;

[0065] 4031, input branch;

[0066] 4032, output branch;

[0067] 404. Clamping module. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of this article to clearly and completely describe the technical solutions in the embodiments of this article. Obviously, the described embodiments are only part of the embodiments of this article, not all of the embodiments. Based on the embodiments of this article, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this article.

[0069] In order to solve the technical problem that in the closed-loop soft-start control circuit of the existing isolated DC-DC power supply chip, when the primary soft-start circuit ends working and the secondary soft-start circuit starts working, the output voltage VISO has an instantaneous undershoot, the embodiment of this specification provides a secondary soft-start circuit applied to the isolated DC-DC power supply chip, such as Figure 3 As shown, a first current source Iref, an energy storage module Css, a second current source Iss, an initialization module SS_initial and a source follower M1;

[0070] The first end of the initialization module SS_initial is used to input the voltage division signal of the output voltage VISO of the isolated DC-DC power supply chip, the second end of the initialization module SS_initial is connected to the gate of the source follower M1 and the energy storage module Css, and the third end of the initialization module SS_initial is connected to the output end VREF_SOFT of the secondary side soft start circuit;

[0071] The drain of the source follower M1 is connected to the first current source Iref through a switch Sss1, and the source of the source follower M1 is connected to the output terminal VREF_SOFT of the secondary side soft start circuit;

[0072] Before the output voltage VISO exceeds the threshold voltage UVLO, the initialization module SS_initial works, the voltage value VREF_SS of the second terminal follows the voltage value VISO_FB of the voltage-divided signal inputted from the first terminal, and stores energy in the energy storage module Css to indirectly record the voltage value VISO_FB of the voltage-divided signal, and the third terminal outputs a first follow-up signal VREF_SOFT, and the voltage value of the first follow-up signal VREF_SOFT rises slowly from the initial value;

[0073] When the output voltage VISO exceeds the threshold voltage UVLO, the second current source Iss starts to store energy in the energy storage module Css, and the source follower M1 starts to work at the same time. The source follower M1 outputs a current second follow signal according to the reference current of the first current source Iref input at the drain and the current voltage value of the second end input at the gate. The voltage value VREF_SOFT of the current second follow signal is the voltage value VISO_FB of the voltage-dividing signal currently indirectly recorded by the energy storage module. After the output voltage VISO exceeds the threshold voltage UVLO, the second follow signal slowly rises to a preset voltage value. The second follow signal VREF_SOFT is used to control the PWM duty cycle of the isolated DC-DC power supply chip, so that the output voltage VISO rises steadily from the threshold voltage UVLO to the target voltage.

[0074] In the embodiments of this specification, the energy storage module Css may be a capacitor or other energy storage components, and the source follower may be implemented as a MOS tube or a transistor (NPN), which is not limited in this specification.

[0075] According to one embodiment of the present specification, continue as Figure 3 As shown, the secondary side soft start circuit also includes a sampling resistor Rss;

[0076] The first end of the Rss is respectively connected to the third end, the source of the source follower M1 and the output end of the secondary side soft start circuit;

[0077] The second end of the Rss is grounded.

[0078] In the embodiment of the present specification, the sampling resistor Rss is used to convert the current of the source of the source follower M1 into a voltage, so as to output a preset value of the follow-up signal VREF_SOFT through the output terminal of the secondary soft start circuit.

[0079] like Figure 3 As shown, the preset voltage value to which the second follower signal slowly rises is calculated based on the reference current output by the first current source and the sampling resistor Rss, and the preset voltage value is Iref*Rss.

[0080] Continue as Figure 3 As shown, switches Sss1 and Sss2 are also included;

[0081] The first end of the Sss1 is connected to the first current source, and the second end of the Sss1 is connected to the drain of the source follower;

[0082] The first end of the Sss2 is connected to the second current source, and the second end of the Sss2 is connected to the energy storage module;

[0083] Before the output voltage VISO exceeds the threshold voltage UVLO, the Sss1 and the Sss2 remain disconnected;

[0084] When the output voltage VISO exceeds the threshold voltage UVLO, both the Sss1 and the Sss2 are closed, and after the output voltage VISO exceeds the threshold voltage UVLO, both the Sss1 and the Sss2 remain closed.

[0085] The detailed circuit diagram of the initialization module SS_initial is as follows Figure 4 As shown, it includes a first current mirror circuit 401, a second current mirror circuit 402, a third current mirror circuit 403, an NMOS tube N1 and an NMOS tube N4;

[0086] The input end of the input branch 4011 in the first current mirror circuit 401 is connected to the drain of the N1 through the switch S1, the gate of the N1 is connected to the drain, the source of the N1 is connected to the third end, and the output branch 4012 of the first current mirror circuit is connected to the input branch 4021 in the second current mirror circuit 402 through the switch S2;

[0087] The output branch 4022 of the second current mirror circuit 402 is connected to the source of N4, and is used to provide a discharge current to N4;

[0088] The output branch 4032 of the third current mirror circuit 403 is connected to the drain of N4, and is used to provide a charging current to N4;

[0089] The gate and drain of N4 are connected, the drain of N4 is connected to the second end of the initialization module through the switch S3, and the source of N4 is connected to the first end of the initialization module SS_initial through the switch S4.

[0090] The working process is as follows:

[0091] Before the output voltage VISO exceeds the threshold voltage UVLO, that is, the primary side soft-start circuit works, the switches Sss1 and Sss2 in the secondary side soft-start circuit are disconnected, the initialization module SS_initial works, and the switches S1, S2, S3, and S4 all remain closed. At this time, the input branch 4011 of the first current mirror circuit 401 is turned on, and the third terminal of the initialization module SS_initial starts to output a signal, which is the first following signal; as the input branch 4011 of the first current mirror circuit 401 is turned on, the output branch 4012 is also turned on, so that the input branch 4021 of the second current mirror circuit 402 is turned on, thereby enabling the output branch 4022 of the second current mirror circuit 402 to be turned on, providing a discharge current I1 for N4; the conduction of the first branch 4031 of the third current mirror circuit 403 causes the second branch 4032 to be turned on, providing a charging current I2 for N4, so N4 is turned on. The voltage difference between the gate and source of N4 is VGS4. When VREF_SS < VISO_FB + VGS4, I2 charges the drain of N4 until VREF_SS = VISO_FB + VGS4. When VREF_SS > VISO_FB + VGS, the drain of N4 discharges through I1 until VREF_SS = VISO_FB + VGS4. Therefore, under the combined action of I1, I2, and N4, it is ensured that VREF_SS = VISO_FB + VGS4, and the voltage value VREF_SS at the second terminal of the initialization module SS_initial follows the voltage value VISO_FB of the voltage-dividing signal input at the first terminal. The energy storage module Css is energized through the second terminal of the initialization module SS_initial, and the voltage value VREF_SS at the second terminal of the initialization module SS_initial is directly recorded, thereby indirectly recording the voltage value VISO_FB of the voltage-dividing signal. At the same time, the third terminal of the initialization module SS_initial outputs the first following signal, and the voltage value of the first following signal slowly rises from the initial value.

[0092] When the output voltage VISO exceeds the threshold voltage UVLO, at this moment, the primary soft start circuit stops working, and the initialization module SS_initial in the secondary soft start circuit also stops working, that is, S1, S2, S3 and S4 are all disconnected. At this time, the input branch 4011 of the first current mirror circuit 401 is disconnected, so that the third end of the initialization module SS_initial stops outputting the first follow-up signal, and the output branch 4012 of the first current mirror circuit 401 is disconnected, so that the input branch 4021 and the output branch 4022 of the second current mirror circuit 402 are both disconnected, and no discharge current is provided to N4, and the input branch 4031 and the output branch 4032 of the third current mirror circuit 403 are both disconnected, and no discharge current is provided to N4, N4 is cut off, and VREF_SS no longer follows VISO_FB. The switches Sss1 and Sss2 in the secondary soft start circuit are closed, and the source follower M1 starts to work. At this time, the voltage value of the gate of the source follower M1 is the voltage value VREF_SS of the second end of the initialization module SS_initial directly recorded by the energy storage module Css, so the source follower is turned on, and the voltage value of the source of the source follower is VREF_SOFT=VREF_SS-VGS1. VGS1 is the gate-source voltage difference of M1. In actual implementation, the gate-source voltage difference VGS4 of N4 is configured to be equal to the gate-source voltage difference VGS1 of M1, that is, VGS4=VGS1. As a result, VREF_SOFT=VISO_FB+VGS4-VGS1, that is, the voltage value of the source of the source follower M1 at this time is the voltage value VISO_FB of the voltage-dividing signal currently indirectly recorded by the energy storage module.

[0093] After the output voltage VISO exceeds the threshold voltage UVLO, the initialization module SS_initial in the secondary soft start circuit continues to stop working, that is, switches S1, S2, S3 and S4 remain disconnected. Switches Sss1 and Sss2 remain closed, the source follower M1 continues to work, and the voltage value VREF_SOFT of the source of the source follower M1 slowly rises to the preset voltage value according to VISO_FB, and the secondary soft start continues to be realized.

[0094] Therefore, after the output voltage VISO of the secondary side soft start circuit of the embodiment of this specification exceeds the under-voltage protection threshold voltage, that is, when the secondary side soft start circuit starts, the secondary side soft start circuit of this structure can enable the isolated DC-DC power supply chip to continue to soft start smoothly, and finally achieve the purpose of the output voltage VISO reaching the predetermined voltage smoothly.

[0095] In order to reduce the circuit complexity, such as Figure 4As shown, the input branch 4011 of the first current mirror circuit 401 is the same as the input branch 4031 of the third current mirror circuit 403, so that the conduction or disconnection of the input branch 4031 of the third current mirror circuit 403 is synchronized with the conduction or disconnection of the input branch 4011 of the first current mirror circuit 401.

[0096] Specifically, continue as Figure 4 As shown, the input branch 4011 of the first current mirror circuit 401 or the input branch 4031 of the third current mirror circuit 403 includes PMOS tubes P1 and P4, and a resistor R1, and the output branch 4012 of the first current mirror circuit 401 includes PMOS tubes P2 and P5;

[0097] The input branch 4021 of the second current mirror circuit 402 includes NMOS transistors N2 and N6 and a resistor R2, and the output branch 4022 of the second current mirror circuit 402 includes NMOS transistors N3 and N7;

[0098] The output branch 4032 of the third current mirror circuit 403 includes PMOS tubes P3 and P6;

[0099] The source of P1, the source of P2, and the source of P3 are all connected to the reference voltage;

[0100] The drain of P1 is connected to the source of P4, and the gate of P1 is connected to the gate of P2, the gate of P3 and the drain of P4 respectively;

[0101] The drain of P4 is connected to the first end of R1, and the gate of P4 is connected to the second end of R1, the gate of P5 and the gate of P6 respectively;

[0102] The second end of R1 is connected to the first end of S1, and the second end of S1 is connected to the third end of the initialization module through NMOS transistor N1, wherein the drain and gate of N1 are both connected to the second end of S1, and the source of N1 is connected to the third end of the initialization module;

[0103] The drain of P2 is connected to the source of P5, and the drain of P5 is connected to the first end of S2;

[0104] The second end of S2 is connected to the gates of N6 and N7 and the first end of R2 respectively;

[0105] The second end of R2 is connected to the drain of N6 and the gates of N2 and N3 respectively;

[0106] The source of N6 is connected to the drain of N2, and the sources of N2 and N3 are both grounded;

[0107] The drain of N3 is connected to the source of N7, and the drain of N7 is connected to the source of N4;

[0108] The drain of P3 is connected to the source of P6, and the drain of P6 is connected to the drain of N4.

[0109] In the embodiments of this specification, P1-P4, P2-P5, P3-P6, N2-N6, N3-N7 are cascode structures. Through the cascode structure, the drain current of P6 and the drain current of N7 are matched to the greatest extent, avoiding the inconsistency between the two due to the channel length modulation effect, which generates an inflow or outflow current to VISO_FB, thereby affecting the voltage accuracy of VISO_FB. For example, if the drain current of P6 is greater than the drain current of N7, the difference between the two will flow into the VISO_FB point, and then flow into the voltage divider resistor of the output voltage, resulting in VISO being greater than the expected voltage. If the drain current of P6 is less than the drain current of N7, the difference between the two will flow out of the VISO_FB point, resulting in VISO being less than the expected voltage.

[0110] Through the secondary side soft start circuit of the embodiment of this specification, as Figure 5 As shown in Figure 1, before and after the output voltage VISO reaches the UVLO threshold, the output voltage VISO transitions smoothly. Figure 6 As shown, when the secondary side soft start circuit of the embodiment of this specification is not used, before and after the UVLO threshold, the output voltage VISO voltage drops by different degrees ΔV according to the load current, and then climbs to a stable value. Figure 5 and Figure 6 The vertical axis V represents the voltage value, and the horizontal axis T represents the time.

[0111] According to one embodiment of the present specification, continue as Figure 4 As shown, the secondary side soft start circuit further includes a clamping module 404;

[0112] The input end of the clamp module 404 is connected to the third end, and the output end of the clamp module 404 is grounded.

[0113] The clamp module 404 is used to limit the maximum value of the first follow-up signal VREF_SOFT. After the output voltage VISO is greater than the threshold voltage UVLO, the follow-up signal VREF_SOFT can quickly pass Figure 3 The sampling resistor Rss in the circuit is used for discharge, and after discharge, it is equal to VISO_FB, thereby speeding up the circuit response speed and reducing the response time.

[0114] Specifically, Figure 4 As shown, the clamp module 404 includes NMOS tubes N8 and N9;

[0115] The drain and gate of N8 are both connected to the third terminal, and the source of N8 is respectively connected to the drain and gate of N9;

[0116] The source of N9 is grounded.

[0117] N8 and N9 are used to clamp the VREF_SOFT voltage < VGS8 + VGS9, where VGS8 and VGS9 are the voltage differences between the gate and source of N8 and N9 respectively.

[0118] Before adding N8 and N9, the higher the UVLO threshold, the larger the VREF_SOFT, and the longer the discharge time through Rss when VISO > UVLO, resulting in a longer circuit response time.

[0119] According to an embodiment of the present specification, as Figure 4 shown, the secondary side soft start circuit further includes an NMOS transistor N5;

[0120] The source of N5 is connected to the second terminal, the gate of N5 is connected to the first terminal, and the drain of N5 is connected to the reference voltage.

[0121] The function of N5 is that when VISO_FB suddenly becomes large due to an abnormality, VREF_SS can be quickly pulled up to VREF_SS = VISO_FB - VGS5 through N5. Otherwise, it still needs to be slowly adjusted through the drain current of P6 or Figure 3 the Iss current in, and the effect of voltage tracking cannot be guaranteed. Wherein, VGS5 is the voltage difference between the gate and source of N5.

[0122] Based on the same inventive concept, an embodiment of the present specification also provides a chip, on which the secondary side soft start circuit described in the embodiment of the present specification is formed.

[0123] It should be understood that in various embodiments herein, the magnitudes of the sequence numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments herein.

[0124] It should also be understood that in the embodiments herein, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0125] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this article.

[0126] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0127] In the several embodiments provided herein, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be electrical, mechanical or other forms of connection.

[0128] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this article.

[0129] In addition, each functional unit in each embodiment of this invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional unit.

[0130] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this article is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of this article. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0131] Specific embodiments are used in this article to illustrate the principles and implementation methods of this article. The description of the above embodiments is only used to help understand the methods and core ideas of this article. At the same time, for general technicians in this field, according to the ideas of this article, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this article.

Claims

1. A secondary side soft start circuit for an isolated DC-DC power supply chip, characterized in that: include: A first current source, an energy storage module, a second current source, an initialization module and a source follower; The first end of the initialization module is used to input the voltage division signal of the output voltage VISO of the isolated DC-DC power supply chip, the second end of the initialization module is connected to the gate of the source follower and the energy storage module, and the third end of the initialization module is connected to the output end of the secondary side soft start circuit; The drain of the source follower is connected to the first current source, and the source of the source follower is connected to the output end of the secondary side soft start circuit; Before the output voltage VISO exceeds the threshold voltage UVLO, the initialization module works, the voltage value of the second terminal follows the voltage value of the voltage-divided signal input by the first terminal, and stores energy in the energy storage module to indirectly record the voltage value of the voltage-divided signal, and the third terminal outputs a first follow-up signal, and the voltage value of the first follow-up signal slowly rises from the initial value; When the output voltage VISO exceeds the threshold voltage UVLO, the second current source starts to store energy in the energy storage module, and the source follower starts to work at the same time. The source follower outputs a current second follow signal according to the reference current of the first current source input at the drain and the current voltage value of the second end input at the gate. The voltage value of the current second follow signal is the voltage value of the voltage division signal currently indirectly recorded by the energy storage module. After the output voltage VISO exceeds the threshold voltage UVLO, the second follow signal slowly rises to a preset voltage value. The second follow signal is used to control the PWM duty cycle of the isolated DC-DC power supply chip, so that the output voltage VISO rises steadily from the threshold voltage UVLO to the target voltage.

2. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 1, characterized in that: It also includes a sampling resistor Rss; The first end of the Rss is respectively connected to the third end, the source of the source follower and the output end of the secondary side soft start circuit; The second end of the Rss is grounded.

3. The secondary side soft start circuit for an isolated DC-DC power supply chip according to claim 1, characterized in that: The initialization module includes a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, an NMOS tube N1 and an NMOS tube N4; The input end of the input branch in the first current mirror circuit is connected to the drain of N1 through the switch S1, the gate of N1 is connected to the drain, and the source of N1 is connected to the third end; The output branch of the first current mirror circuit is connected to the input branch of the second current mirror circuit through a switch S2; The output branch of the second current mirror circuit is connected to the source of N4, and is used to provide a discharge current to N4; The output branch of the third current mirror circuit is connected to the drain of N4, so as to provide a charging current to N4; the gate and drain of N4 are connected, the drain of N4 is connected to the second end of the initialization module through switch S3, and the source of N4 is connected to the first end of the initialization module through switch S4.

4. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 3, characterized in that: Before the output voltage VISO exceeds the threshold voltage UVLO, S1, S2, S3 and S4 are all kept closed; When the output voltage VISO exceeds the threshold voltage UVLO, the S1 , S2 , S3 , and S4 are all disconnected. After the output voltage VISO exceeds the threshold voltage UVLO, the S1 , S2 , S3 , and S4 remain disconnected.

5. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 3, characterized in that: Also included is a clamp module; The input end of the clamp module is connected to the third end, and the output end of the clamp module is grounded.

6. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 5, characterized in that: The clamp module includes NMOS tubes N8 and N9; The drain and gate of N8 are both connected to the third terminal, and the source of N8 is respectively connected to the drain and gate of N9; The source of N9 is grounded.

7. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 3, characterized in that: Also includes NMOS tube N5; The source of N5 is connected to the second end, the gate of N5 is connected to the first end, and the drain of N5 is connected to the reference voltage.

8. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 3, characterized in that: An input branch of the first current mirror circuit is the same as an input branch of the third current mirror circuit.

9. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 3, characterized in that: The input branch of the first current mirror circuit or the input branch of the third current mirror circuit includes PMOS tubes P1 and P4 and a resistor R1, and the output branch of the first current mirror circuit includes PMOS tubes P2 and P5; The input branch of the second current mirror circuit includes NMOS tubes N2 and N6 and a resistor R2, and the output branch of the second current mirror circuit includes NMOS tubes N3 and N7; The output branch of the third current mirror circuit includes PMOS tubes P3 and P6; The source of P1, the source of P2, and the source of P3 are all connected to the reference voltage; The drain of P1 is connected to the source of P4, and the gate of P1 is connected to the gate of P2, the gate of P3 and the drain of P4 respectively; The drain of P4 is connected to the first end of R1, and the gate of P4 is connected to the second end of R1, the gate of P5 and the gate of P6 respectively; The second end of R1 is connected to the first end of S1, and the second end of S1 is connected to the drain and gate of N1; The drain of P2 is connected to the source of P5, and the drain of P5 is connected to the first end of S2; The second end of S2 is connected to the gates of N6 and N7 and the first end of R2 respectively; The second end of R2 is connected to the drain of N6 and the gates of N2 and N3 respectively; The source of N6 is connected to the drain of N2, and the sources of N2 and N3 are both grounded; The drain of N3 is connected to the source of N7, and the drain of N7 is connected to the source of N4; The drain of P3 is connected to the source of P6, and the drain of P6 is connected to the drain of N4.

10. The secondary side soft start circuit applied to the isolated DC-DC power supply chip according to claim 1, characterized in that: Also includes switches Sss1 and Sss2; The first end of the Sss1 is connected to the first current source, and the second end of the Sss1 is connected to the drain of the source follower; The first end of the Sss2 is connected to the second current source, and the second end of the Sss2 is connected to the energy storage module; Before the output voltage VISO exceeds the threshold voltage UVLO, the Sss1 and the Sss2 remain disconnected; When the output voltage VISO exceeds the threshold voltage UVLO, both the Sss1 and the Sss2 are closed, and after the output voltage VISO exceeds the threshold voltage UVLO, both the Sss1 and the Sss2 remain closed.

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