Frequency jittering method, circuit and quasi-resonant flyback converter using same

Abstract

According to the frequency jittering method and circuit and the quasi-resonant flyback converter applying the same, when the quasi-resonant flyback converter works in an intermittent conduction mode, frequency jittering is carried out in the following mode that in an Mth switching period group, after the system working frequency reaches a frequency limiting line, a main switching tube is controlled to be conducted at the valley bottom after an ith zero-crossing signal is detected; in the Nth switching period group, when the working frequency of the system reaches a frequency limiting line, the main switching tube is controlled to be switched on at the valley bottom after the jth zero-crossing signal is detected; wherein M and N are two adjacent switching period groups; i is not equal to j. Through the above arrangement, when the quasi-resonant flyback converter is in an intermittent conduction mode, the two adjacent switching period groups control the conduction of the main switching tube at two different valley bottoms, the frequency spectrum of EMI can be effectively dispersed, the function of optimizing EMI is realized, and compared with a mode of jittering peak current or jittering working frequency in the prior art, the frequency spectrum of the quasi-resonant flyback converter is greatly improved. And a better EMI optimization effect is achieved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a frequency jittering method, a circuit, and a quasi-resonant flyback converter using the same. Background Art

[0002] In the prior art, in the field of power supply, in order to optimize EMI (electromagnetic interference), frequency jittering technology is usually used. As a kind of switching power supply, the quasi-resonant flyback converter can realize the opening of the main switch tube at the bottom of the valley to reduce power consumption. Therefore, in order to improve system efficiency, a quasi-resonant controller is usually used; Figure 1 The figure shows a simplified schematic diagram of a quasi-resonant flyback converter, which includes a transformer T, a main switch tube Q1 and a primary controller U1; the transformer T includes a primary winding Np, a secondary winding Ns and an auxiliary winding Naux; the primary controller U1 is used to control the on or off of the main switch tube Q1; the AC power source AC outputs Vin after passing through the rectifier unit U0, and the flyback converter converts Vin into an output voltage Vout for powering the load. Figure 2 The following is the setting curve of the operating frequency and peak current of the quasi-resonant flyback converter (from Figure 1 It can be seen that the VCS voltage can be used to represent the peak current, and the turn-off time of the main switch tube is determined based on the peak current. The solid line represents the operating frequency, and the dotted line represents the peak current). Figure 2 As shown in , the operating frequency fsw and the peak current VCS are related to the size of the error compensation signal VCOMP (the error compensation signal VCOMP is obtained according to the output voltage of the flyback converter). According to the size of the error compensation signal VCOMP, the system can operate in DCM (discontinuous conduction mode) or BCM (critical conduction mode). When VCOMP is greater than VCOMP_PFM, the set system operating frequency fsw reaches the maximum value fmax, but when VCOMP is greater than VCOMP0, that is, in the BCM mode, the actual operating frequency of the system is as follows Figure 2 As shown in , it will drop, that is, it will not work according to the set fmax. Therefore, in BCM mode, the frequency jittering is generally achieved by jittering the peak current; however, in DCM mode, especially in deep DCM mode, the impact of jittering the peak current on the actual operating frequency is very small. Figure 3As shown in , Vds is the voltage across the main switch Q1, Ip is the current on the primary winding Np, Is is the current on the secondary winding Ns, and taking the peak current jitter of 5% as an example, the switching period before jitter tsw0 = ton + tons + toff0, and the switching period after jitter tsw1 = 5% (ton + tons) + toff1. In these two switching periods, when the toff time is basically unchanged, especially when the toff time is long, the jitter amplitude of the operating frequency before and after the jitter is small, and the optimization capability for EMI is weak. In DCM mode, the design of jittering the operating frequency is helpful for EMI, but the quasi-resonant flyback converter turns on the main switch at the bottom of the valley, such as Figure 4 As shown in , after reaching the set operating frequency, that is, reaching the frequency limit line (the operating frequency jitters fsw_min-fsw_max in a certain range, so the frequency limit line also changes accordingly), the main switch tube will not be turned on. Only at t1, that is, when the resonance reaches the bottom, will the main switch tube be turned on; therefore, for the quasi-resonant flyback converter, in the DCM mode, the way of jittering the operating frequency does not achieve the effect of jittering on the actual operating frequency of the system, and cannot achieve the effect of optimizing EMI. Therefore, it is necessary to propose a new jittering solution to solve the problems existing in the prior art. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a frequency jittering method, a circuit and a quasi-resonant flyback converter using the same.

[0004] According to a first aspect of the present invention, a frequency jittering method is provided, which is applied to a quasi-resonant flyback converter, wherein the quasi-resonant flyback converter includes a main switch tube arranged on a primary side; characterized in that when the quasi-resonant flyback converter operates in a discontinuous conduction mode, the method includes:

[0005] In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the valley bottom after the i-th zero-crossing signal is detected;

[0006] In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the valley bottom after the jth zero-crossing signal is detected; M and N are two adjacent switching cycle groups, each switching cycle group contains an equal or unequal number of switching cycles; i is not equal to j;

[0007] The conduction of the main switch tube is controlled by forming a repeating unit with a continuous K switching cycle group; K is greater than or equal to 2;

[0008] In the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage; or, in the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage.

[0009] Optionally, in the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, after the i-th zero-crossing signal is detected, the main switch tube is controlled to be turned on after a first delay;

[0010] In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line and the jth zero-crossing signal is detected, the main switch tube is controlled to be turned on after a first delay.

[0011] Optionally, in the Mth switching cycle group, after the system operating frequency reaches the frequency limit line, a delay of X resonant cycles is performed, and then, after the Ath zero-crossing signal is detected, the main switch tube is controlled to be turned on after a delay of the first time; the sum of the number of zero-crossing signals contained in the X resonant cycles and A is equal to i;

[0012] In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, it is delayed by Y resonant cycles, and then, after the Bth zero-crossing signal is detected, the main switch tube is controlled to be turned on after a delay of the first time; the sum of the number of zero-crossing signals contained in the Y resonant cycles and B is equal to j.

[0013] Optionally, when the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, the first time is 1 / 4 of the resonant period;

[0014] The zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage, and the first time is 3 / 4 of the resonant cycle.

[0015] Optionally, when the quasi-resonant flyback converter operates in the discontinuous conduction mode, the system operating frequency is jittered by combining the peak current jitter method; the peak current determines the turn-off moment of the main switch tube.

[0016] Optionally, when the quasi-resonant flyback converter operates in a critical conduction mode, the jittering of the system operating frequency is achieved by jittering the peak current; and the peak current determines the turn-off moment of the main switch tube.

[0017] Optionally, the frequency limit line is a preset operating frequency, and the preset operating frequency is a fixed value or a jittered value.

[0018] The present invention also provides a frequency jittering circuit, which is applied to a quasi-resonant flyback converter, wherein the quasi-resonant flyback converter includes a main switch tube arranged on the primary side; characterized in that when the quasi-resonant flyback converter operates in a discontinuous conduction mode, the frequency jittering circuit includes:

[0019] The frequency limit line judgment circuit is used to judge whether the operating frequency of the system reaches the frequency limit line;

[0020] A switching cycle group determination circuit and a zero-crossing detection circuit, wherein when the switching cycle group determination circuit determines that the switching cycle group in the repeating unit is the Mth switching cycle group, after the system operating frequency reaches the frequency limit line, the frequency jittering circuit is used to control the main switch tube to be turned on at the bottom of the valley after the zero-crossing detection circuit detects the i-th zero-crossing signal;

[0021] When the switching cycle group determination circuit determines that the switching cycle group in the repetitive unit is the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the frequency jittering circuit is used to control the main switch tube to turn on at the valley bottom after the zero-crossing signal detection circuit detects the jth zero-crossing detection signal; M and N are two adjacent switching cycle groups, each switching cycle group contains an equal or unequal number of switching cycles; i is not equal to j;

[0022] The frequency jittering circuit controls the conduction of the main switch tube by forming the repeating unit with a group of K consecutive switch cycles; K is greater than or equal to 2;

[0023] In the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage; or, in the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage.

[0024] Optionally, the frequency jittering circuit further includes a first delay circuit, and in the Mth switching cycle group, when the system operating frequency reaches the frequency limit line and the i-th zero-crossing signal is detected, the first delay circuit controls the main switch tube to be turned on after a first delay time;

[0025] In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line and the jth zero-crossing signal is detected, the first delay circuit controls the main switch tube to be turned on after a first delay time.

[0026] Optionally, when each switching cycle group includes one switching cycle and K=2, the switching cycle group determination circuit includes a frequency divider and a state determination circuit;

[0027] The frequency divider is used to divide the driving signal for controlling the main switch tube to be turned on or off by two frequencies, and output a first control signal;

[0028] The state judgment circuit receives the first control signal and outputs a second control signal with a different state based on the high and low level states of the first control signal;

[0029] Based on the second control signal in the first state, after the zero-crossing detection circuit detects the i-th zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time; based on the second control signal in the second state, after the zero-crossing detection circuit detects the j-th zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time.

[0030] Optionally, the frequency jittering circuit further includes a second delay circuit and a first delay circuit. In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, the second delay circuit delays X resonant cycles, and then, after detecting the Ath zero-crossing signal, the first delay circuit delays for a first time to control the main switch tube to turn on; the sum of the number of zero-crossing signals contained in the X resonant cycles and A is equal to i;

[0031] In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the second delay circuit delays Y resonant cycles, and then, after detecting the Bth zero-crossing signal, the main switch tube is controlled to be turned on after delaying for a first time by the first delay circuit; the sum of the number of zero-crossing signals contained in the Y resonant cycles and B is equal to j.

[0032] Optionally, when each switching cycle group includes one switching cycle and K=2, the switching cycle group determination circuit further includes a frequency divider and a state determination circuit;

[0033] The frequency divider is used to divide the driving signal for controlling the main switch tube to be turned on or off by two frequencies, and output a first control signal;

[0034] The state judgment circuit receives the first control signal and outputs a second control signal with a different state based on the high and low level states of the first control signal;

[0035] Based on the second control signal of the first state, the second delay circuit delays X resonant cycles, and then, after the zero-crossing detection circuit detects the Ath zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time; based on the second control signal of the second state, the second delay circuit controller delays Y resonant cycles, and then, after the zero-crossing detection circuit detects the Bth zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time.

[0036] Optionally, when the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, the first time is 1 / 4 of the resonant period;

[0037] The zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage, and the first time is 3 / 4 of the resonant period.

[0038] Optionally, when the quasi-resonant flyback converter operates in a discontinuous conduction mode, the frequency jittering circuit is further provided with a jittering peak current circuit, and the jittering of the system operating frequency is achieved in combination with the jittering peak current circuit; the peak current determines the turn-off moment of the main switch tube.

[0039] The present invention further provides a quasi-resonant flyback converter, characterized in that the quasi-resonant flyback converter includes the frequency-jittering circuit described above, and electromagnetic interference is reduced based on the frequency-jittering circuit.

[0040] The beneficial effects of the present invention include at least:

[0041] The frequency jittering method, circuit and quasi-resonant flyback converter using the same provided by the present invention, when operating in the discontinuous conduction mode, perform frequency jittering in the following manner: in the Mth switching cycle group, after the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the valley after the i-th zero-crossing signal is detected; in the Nth switching cycle group, after the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the valley after the j-th zero-crossing signal is detected; wherein M and N are two adjacent switching cycle groups, each of which may include an equal or unequal number of switching cycles; i is not equal to j; and the conduction of the main switch tube is controlled by a repeating unit composed of continuous K switching cycle groups; K is greater than or equal to 2. Through the above-mentioned setting, when the quasi-resonant flyback converter is in the discontinuous conduction mode DCM, the two adjacent switching cycles control the conduction of the main switch tube at two different valleys, which can effectively disperse the spectrum of EMI and realize the function of optimizing EMI. Compared with the method of jittering the peak current or jittering the operating frequency in the prior art, it has a better effect of optimizing EMI.

[0042] Furthermore, in order to further reduce the impact of electromagnetic interference and achieve the best EMI optimization effect in DCM mode, the EMI can be further optimized by combining the method described above with the peak current jitter method.

[0043] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1A simplified schematic diagram of a quasi-resonant flyback converter is shown;

[0045] Figure 2 A setting curve diagram of the operating frequency and peak current of a quasi-resonant flyback converter is shown;

[0046] Figure 3 A schematic diagram of a working waveform of a quasi-resonant flyback converter is shown;

[0047] Figure 4 A schematic diagram of a working waveform of a jitter working frequency is shown;

[0048] Figure 5 A working waveform diagram of the frequency jittering method provided by the present invention is shown;

[0049] Figure 6 Another working waveform diagram of the frequency jittering method provided by the present invention is shown;

[0050] Figure 7 A schematic diagram of a frequency jittering circuit provided by the present invention is shown;

[0051] Figure 8 Another schematic diagram of the frequency jittering circuit provided by the present invention is shown;

[0052] Fig. 9 Another schematic diagram of the frequency jitter circuit provided by the present invention is shown

[0053] Fig.10 Shows Figure 7 A schematic diagram of a working waveform;

[0054] Fig.11 Another schematic diagram of the frequency jittering circuit provided by the present invention is shown;

[0055] Fig.12 Shows Fig.11 A schematic diagram of a working waveform. DETAILED DESCRIPTION

[0056] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0057] In view of the problems existing in the prior art, the present invention provides a frequency jittering method, which is applied to a quasi-resonant flyback converter. The quasi-resonant flyback converter can be Figure 1 The structure in is of course not limited to Figure 1The structure in, when it works in the intermittent conduction mode, performs frequency jittering in the following manner: in the Mth switching cycle group, after the system operating frequency reaches the frequency limit line, the valley after the i-th zero-crossing signal is detected controls the main switch tube to be turned on; in the Nth switching cycle group, after the system operating frequency reaches the frequency limit line, the valley after the j-th zero-crossing signal is detected controls the main switch tube to be turned on; wherein M and N are two adjacent switching cycle groups, each switching cycle group may include an equal or unequal number of switching cycles; i is not equal to j; and a repeating unit composed of K consecutive switching cycle groups controls the conduction of the main switch tube; K is greater than or equal to 2. It should be noted that the frequency limit line described in this article can be Figure 2 The working frequency set in the figure can also be the working frequency after the set working frequency is jittered accordingly, such as Figure 4 As shown in , it fluctuates between fsw_min and fsw_max; the specific form can be set according to the actual application.

[0058] Specifically, Figure 5 As shown, it is a working waveform diagram corresponding to the frequency jittering method provided in this article. The DRV signal represents the control signal for controlling the main switch tube Q1 to be turned on or off. In the time period t3-t6, it is the Mth switch cycle group, and in the time period t6-t9, it is the Nth switch cycle group. In this embodiment, the zero-crossing signal is used to represent the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, i is equal to 1, and j is equal to 2. As shown in the figure, at time t1, after the operating frequency of the system reaches the set frequency limit line, at time t2, that is, after the frequency limit line, the valley bottom (t3 moment) after the first zero-crossing signal ZCD1 is detected to control the main switch tube Q1 to be turned on, and at the Mth switch In each cycle group, the main switch Q1 can be controlled to turn on at the bottom after the first zero-crossing signal ZCD1 is detected after the frequency limit line; at time t4, after the operating frequency of the system reaches the set frequency limit line, at time t5, that is, after the frequency limit line, the main switch Q1 is controlled to turn on at the bottom (at time t6) after the second zero-crossing signal ZCD2 is detected, and in the Nth switching cycle group, the main switch Q1 can be controlled to turn on at the bottom after the second zero-crossing signal ZCD2 is detected after the frequency limit line; that is, in two adjacent switching cycle groups, the main switch Q1 can be controlled to turn on at different bottoms, which can effectively disperse the spectrum of EMI and achieve the function of optimizing EMI. Figure 5In the example, i is equal to 1 and j is equal to 2, but it is not limited to this. For example, i can also be equal to 1 and j can be equal to 3. The selection of specific values ​​can be set according to the actual application. In addition, the number of switching cycles in each switching cycle group can be set according to the actual situation. For example, the Mth and Nth switching cycle groups can each include only 1 switching cycle, or 2 switching cycles, or the Mth switching cycle group can include only 1 switching cycle, and the Nth switching cycle group can include 2 switching cycles, etc. Figure 5 It can be seen that the next switching cycle group adjacent to the Nth switching cycle group controls the main switch Q1 to be turned on at the valley bottom (at time t9) after the third zero-crossing signal ZCD3 is detected after the frequency limit line. Of course, within this switching cycle group, the main switch Q1 can also be turned on at the valley bottom after the first zero-crossing signal ZCD1 is detected after the frequency limit line. Figure 5 It is just an example. As long as it can realize that two adjacent switch cycle groups can control the conduction of the main switch tube at different valleys, other deformations can be made to achieve the same function. And two adjacent switch cycle groups (M and N) can be used as a repeating unit to control the conduction of the main switch tube, and three adjacent switch cycle groups (M, N and L) can be used as a repeating unit to control the conduction of the main switch tube. Of course, other settings can also be made. It should be noted that Figure 5 The zero-crossing signal is used as an example to illustrate the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage. Of course, the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage can also be used as the detection moment of the zero-crossing signal.

[0059] Furthermore, as one of the embodiments of this article, it can be implemented by the following method: in the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, after the i-th zero-crossing signal is detected, the main switch tube is controlled to be turned on after a first delay; in the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, after the j-th zero-crossing signal is detected, the main switch tube is controlled to be turned on after a first delay.

[0060] As another embodiment of this invention, it can also be realized by the following method: in the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, X resonant cycles are delayed, and then, after the Ath zero-crossing signal is detected, the main switch tube is controlled to be turned on after a delay of the first time; wherein, the sum of the number of zero-crossing signals contained in the X resonant cycles and A can be set to be equal to i; in the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, Y resonant cycles are delayed, and then, after the Bth zero-crossing signal is detected, the main switch tube is controlled to be turned on after a delay of the first time; the sum of the number of zero-crossing signals contained in the Y resonant cycles and B can be set to be equal to j. In this embodiment, one of X and Y can be set to zero, and of course other settings can also be made.

[0061] Among them, in the two embodiments described above, the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage can be used as the detection moment of the zero-crossing signal, and the first time is 1 / 4 of the resonant cycle. Of course, as another method of this article, the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage can also be used as the detection moment of the zero-crossing signal, and the first time can be set to 3 / 4 of the resonant cycle.

[0062] Furthermore, in order to further reduce the impact of electromagnetic interference in the DCM mode and achieve the best EMI optimization effect, the EMI can be further optimized by combining the above-mentioned method with a peak current jitter method.

[0063] To further illustrate the frequency jittering method of this article, the following example is taken as each switching cycle group includes only one switching cycle, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, i equals 1, j equals 2, and two consecutive switching cycles are used as a repeating unit for explanation. Figure 6 Another working waveform diagram corresponding to the frequency jittering method provided in this article is shown. Before time t1, the main switch tube Q1 is in the on state. During the time period t1-t3, the main switch tube Q1 is in the off state. During this period, after the main switch tube Q1 is turned off, the secondary side first performs freewheeling. After the secondary side freewheeling ends, Figure 5 It can be seen from the figure that it will enter the resonance stage. At this time, the voltage Vds across the main switch tube Q1 resonates. After the operating frequency of the system reaches the set frequency limit line, the first zero-crossing signal ZCD1 is detected at time t2. At time t3, that is, the valley moment of resonance, the main switch tube Q1 is controlled to be turned on; in the t3-t4 time period, the main switch tube Q1 is always in the on state. In the t4-t6 time period, similarly, after the main switch tube Q1 is turned off, the secondary side will first be freewheeling. After the secondary side freewheeling ends, it enters the resonance stage. At this time, after the operating frequency of the system reaches the set frequency limit line, the second zero-crossing signal ZCD2 is detected at time t5. At time t6, that is, the valley moment of resonance, the main switch tube Q1 is controlled to be turned on; the working process of the t6-t9 time period is the same as the working process of the t0-t3 time period, which will not be repeated here. Among them, zero-crossing detection can be implemented by using existing circuits in the prior art, which will not be elaborated here. For example, the function of zero-crossing detection is implemented by sampling and detecting the voltage on the auxiliary winding Naux.

[0064] Through the above-mentioned setting, when the quasi-resonant flyback converter is in the discontinuous conduction mode DCM, the conduction of the main switch tube is controlled at two different valleys in two adjacent switching cycles, which can effectively disperse the EMI spectrum and realize the function of optimizing EMI. Compared with the method of jittering the peak current or jittering the operating frequency in the prior art, it has a better effect of optimizing EMI.

[0065] Furthermore, to achieve Figure 6 The frequency jittering method in the embodiment of the present invention is as one of the embodiments of the present invention. In the previous switching cycle, when the system operating frequency reaches the frequency limit line, after the first zero-crossing signal ZCD1 is detected, the main switch tube is controlled to be turned on after a first delay; in the next switching cycle, when the system operating frequency reaches the frequency limit line, after the second zero-crossing signal ZCD2 is detected, the main switch tube is controlled to be turned on after a first delay; wherein the first time is 1 / 4 of the resonance period Tr; Figure 6 As shown in , the first time is the time period corresponding to t2-t3, t5-t6, and t8-t9.

[0066] Furthermore, to achieve Figure 6 The frequency jittering method in, as another embodiment of the present invention, after the system operating frequency reaches the frequency limit line, a delay is first performed before the zero-crossing signal is detected. In the previous switching cycle, when the system operating frequency reaches the frequency limit line, the delay time is zero, that is, no delay is performed. After that, after the zero-crossing signal (that is, ZCD1) is detected, a delay of 1 / 4 resonant cycle Tr is performed to control the main switch tube to be turned on; in the next switching cycle, a delay of one resonant cycle Tr is performed, and then, after the zero-crossing signal (the zero-crossing signal corresponds to ZCD2) is detected, a delay of 1 / 4 resonant cycle Tr is performed to control the main switch tube to be turned on.

[0067] The two embodiments described above in this article can both enable the quasi-resonant flyback converter to control the conduction of the main switch tube at two different valley bottoms in two adjacent switching cycles when in the discontinuous conduction mode DCM, which can effectively disperse the EMI spectrum and achieve the function of optimizing EMI.

[0068] Furthermore, in order to further reduce the impact of electromagnetic interference in DCM mode and achieve the best EMI optimization effect, the method described above can be combined with the peak current jitter method to further optimize EMI. Specifically, the peak current jitter method can be implemented using the circuit in the prior art, which will not be introduced in detail in this article.

[0069] Furthermore, in the BCM mode, the peak current can be jittered to optimize EMI.

[0070] This article also provides a frequency jittering circuit, which includes a frequency limit line judgment circuit for judging whether the operating frequency of the system reaches the frequency limit line; the frequency jittering circuit also includes a switch cycle group determination circuit 10 and a zero-crossing detection circuit. When the switch cycle group determination circuit determines that the switch cycle group in the repeating unit is the Mth switch cycle group, when the system operating frequency reaches the frequency limit line, the frequency jittering circuit is used to control the main switch tube to be turned on at the bottom of the valley after the zero-crossing detection circuit detects the i-th zero-crossing signal; when the switch cycle group determination circuit determines that the switch cycle group in the repeating unit is the Nth switch cycle group, when the system operating frequency reaches the frequency limit line, the frequency jittering circuit is used to control the main switch tube to be turned on at the bottom of the valley after the zero-crossing detection circuit detects the j-th zero-crossing signal; wherein M and N are two adjacent switch cycle groups, each switch cycle group contains an equal or unequal number of switch cycles; i is not equal to j. The frequency jittering circuit controls the conduction of the main switch tube by forming a repeating unit with continuous K switch cycle groups; K is greater than or equal to 2. In addition, the frequency jittering circuit can also realize other functions described in the frequency jittering method above.

[0071] As one of the embodiments of this article, Figure 5 As shown in , each switching cycle group includes a switching cycle, and three adjacent switching cycles are a repeating unit. For example, in the Mth switching cycle group, the main switch tube is turned on at the bottom of the valley control after the first zero-crossing signal is detected; in the Nth switching cycle group, the main switch tube is turned on at the bottom of the valley control after the second zero-crossing signal is detected; in the Lth switching cycle group, the main switch tube is turned on at the bottom of the valley control after the third zero-crossing signal is detected; that is, in these three switching cycles, the Nth switching cycle is adjacent to the Mth switching cycle and the Lth switching cycle, respectively, and the main switch tube is turned on at different valleys in the two adjacent switching cycles, and every three such switching cycles constitute a repeating unit. For example, in 6 consecutive switching cycles (i.e., including two repeating units), the main switch tube is turned on at the bottom of the valley control after the 1st, 2nd, 3rd, 1st, 2nd, and 3rd zero-crossing signals, respectively.

[0072] As one of the embodiments of the present invention, Figure 7 As shown, the frequency-jittering circuit also includes a first delay circuit. In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, after the i-th zero-crossing signal is detected, the first delay circuit controls the main switch tube to be turned on after a delay of a first time; in the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, after the j-th zero-crossing signal is detected, the first delay circuit controls the main switch tube to be turned on after a delay of a first time.

[0073] As another embodiment of the present invention, Figure 8As shown, the frequency-jittering circuit also includes a second delay circuit and a first delay circuit. In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, the second delay circuit delays X resonant cycles, and then, after detecting the Ath zero-crossing signal, the first delay circuit delays for a first time to control the main switch tube to be turned on; the sum of the number of zero-crossing signals contained in the X resonant cycles and A is equal to i; in the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the second delay circuit delays for Y resonant cycles, and then, after detecting the Bth zero-crossing signal, the first delay circuit delays for a first time to control the main switch tube to be turned on; the sum of the number of zero-crossing signals contained in the Y resonant cycles and B is equal to j. Figure 7 , Figure 8 Although the frequency-limiting line judgment circuit is not shown, it does not affect the understanding of the technical solution by those skilled in the art.

[0074] Furthermore, the following takes the case where each switching cycle group includes only one switching cycle, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, i is equal to 1, j is equal to 2, and the setting of the frequency jittering circuit is described with two consecutive switching cycles (i.e., K=2) as a repeating unit ( Fig. 9 and Fig.11 As one of the embodiments of this article, Fig. 9 As shown in , the switching cycle group determination circuit 10 includes a frequency divider and a state judgment circuit; the frequency divider is used to divide the driving signal DRV that controls the main switch tube to be turned on or off by two frequencies, and output a first control signal; the state judgment circuit receives the first control signal, and outputs a second control signal with different states based on the high and low level states of the first control signal. Specifically, Fig. 9In the embodiment, a D flip-flop is used as a frequency divider, the trigger end of the D flip-flop, i.e., the clock signal end CLK, is connected to the driving signal DRV that controls the main switch tube to be turned on or off, the input end D of the D flip-flop is connected to the inverting output end Q' of the D flip-flop, the output end Q of the D flip-flop (i.e., the first control signal) is connected to the input end of the state judgment circuit, and the state judgment circuit outputs a second control signal with different states based on the first control signal of different states. The output end of the state judgment circuit is connected to the input end of the zero-crossing detection circuit. When the system operating frequency reaches the frequency limit line, the zero-crossing detection circuit, based on the second control signal of the first state, detects the first zero-crossing signal, and controls the main switch tube to be turned on after the first delay circuit delays the first time; based on the second control signal of the second state, detects the second zero-crossing signal, and controls the main switch tube to be turned on after the first delay circuit delays the first time; that is, the first control signals of different states will correspond to the second control signals of different states respectively, and the second control signals of different states will affect the number of ZCDs to be detected after the frequency limit line; specifically, the setting of the number of ZCD detections can be realized by circuits such as counters. In this embodiment, i and j may also take other values ​​according to actual conditions.

[0075] Fig.10 For the corresponding Fig. 9 A schematic diagram of a working waveform, after the driving signal DRV passes through the D flip-flop, the waveform of its output terminal Q is as follows Fig. 9 As shown in FIG. , the frequency division of the driving signal DRV is realized. Figure 6As shown in, before time t1, the main switch tube Q1 is in the on state, and in the time period t1-t3, the main switch tube Q1 is in the off state. Before time t3, the first control signal, that is, the output of the D trigger is high level, and the state judgment circuit outputs a second control signal with a first state based on the high level first control signal. Based on the second control signal in the first state, it is determined that the number of ZCDs to be detected after the frequency limit line is 1. Therefore, after the system operating frequency reaches the frequency limit line, at time t2, after the zero-crossing detection circuit detects the first zero-crossing signal ZCD1, it delays 1 / 4 of the resonance period and controls the main switch tube to turn on at time t3. In the time period t3-t4, the main switch tube is in the on state, and in the time period t4-t6, the main switch tube Q1 is in the off state. Before the moment t6, the first control signal, that is, the output of the D flip-flop is low level, and the state judgment circuit outputs the second control signal with the second state based on the low level first control signal. Based on the second control signal of the second state, the number of ZCDs to be detected after the frequency limit line is determined to be 2. Therefore, after the system operating frequency reaches the frequency limit line, at the moment t5, the zero-crossing detection circuit detects the second zero-crossing signal ZCD2, and after a delay of 1 / 4 of the resonance cycle, controls the main switch tube to be turned on at the moment t6. The working process of t6-t9 is the same as the working process in the time period t0-t3, and will not be repeated here.

[0076] As another embodiment of the present invention, Fig.11 and Fig. 9 The difference is that Fig.11 In the embodiment shown, a second delay circuit is also provided. Specifically, Fig.11 A D trigger is also provided in the circuit to realize the frequency division of the driving signal DRV, and the first control signal with different states is outputted at its output terminal Q; the state judgment circuit also outputs the second control signal with different states based on the first control signal with different states. In this embodiment, the output terminal of the state judgment circuit is connected to the input terminal of the second delay circuit; the second delay circuit performs different delays based on the second control signal with different states; for example, the delay time of the second control signal based on the first state is zero, that is, no delay is performed; the delay time of the second control signal based on the second state is one resonance cycle. The output terminal of the second delay circuit is connected to the input terminal of the zero-crossing detection signal. After the corresponding delay time, when the zero-crossing detection circuit detects the zero-crossing state, the main switch tube is controlled to be turned on after the first delay circuit delays 1 / 4 of the resonance cycle.

[0077] Specifically, Fig.12 For the corresponding Fig.11 A schematic diagram of a working waveform. Similarly, after the driving signal DRV passes through the D flip-flop, the waveform of its output terminal Q is as follows Fig.12As shown in , the function of dividing the driving signal DRV is realized; before time t1, the main switch tube Q1 is in the on state, and in the time period t1-t3, the main switch tube Q1 is in the off state. Before time t3, the first control signal, that is, the output of the D flip-flop is high level, and the state judgment circuit outputs the second control signal with the first state based on the high level first control signal. Based on the second control signal in the first state, it is determined that the delay time after the frequency limit line and before the detection of ZCD is zero. Therefore, after the system operating frequency reaches the frequency limit line, at time t2, after the zero-crossing detection circuit detects the zero-crossing signal ZCD1, it delays 1 / 4 of the resonance period and controls the main switch tube to turn on at time t3. In the time period t3-t4, the main switch tube is in the on state, and in the time period t4-t6, the main switch tube Q1 is in the off state. Before the moment t6, the first control signal, that is, the output of the D flip-flop is low level, and the state judgment circuit outputs the second control signal with the second state based on the low level first control signal. Based on the second control signal in the second state, the delay time before the detection of ZCD after the frequency limit line is determined to be one resonance cycle. Therefore, after the system operating frequency reaches the frequency limit line, after a delay of one resonance cycle, at the moment t5, the zero-crossing detection circuit detects the zero-crossing signal ZCD2, and then delays 1 / 4 of the resonance cycle, and at the moment t6, the main switch tube is controlled to be turned on. The working process of t6-t9 is the same as the working process in the time period t0-t3, and will not be repeated here.

[0078] Similarly, in order to further reduce the impact of electromagnetic interference and achieve the best EMI optimization effect in DCM mode, the EMI can be further optimized by combining the peak current jitter method on the basis of the circuit described above. Specifically, the peak current jitter circuit can be implemented using the circuit in the prior art, which will not be introduced in detail in this article.

[0079] Furthermore, in the BCM mode, the peak current can be jittered to optimize EMI.

[0080] It should be noted that the circuit diagrams or waveform diagrams illustrated above are only some of the embodiments in this article, and the present invention is not limited thereto. It is also within the scope of this article to make corresponding modifications thereto to achieve the same function.

[0081] In summary, the frequency jittering method, circuit and quasi-resonant flyback converter using the same provided in this article, when it works in the discontinuous conduction mode, performs frequency jittering in the following manner: in the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the bottom after the i-th zero-crossing signal is detected; in the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the bottom after the j-th zero-crossing signal is detected; wherein M and N are two adjacent switching cycle groups, each of which may include an equal or unequal number of switching cycles; i is not equal to j; and the conduction of the main switch tube is controlled by a repeating unit composed of continuous K switching cycle groups; K is greater than or equal to 2. Through the above-mentioned setting, this article enables the quasi-resonant flyback converter to control the conduction of the main switch tube at two different valleys in the two adjacent switching cycles when it is in the discontinuous conduction mode DCM, which can effectively disperse the spectrum of EMI and realize the function of optimizing EMI. Compared with the method of jittering the peak current or jittering the operating frequency in the prior art, it has a better effect of optimizing EMI.

[0082] Furthermore, in order to further reduce the impact of electromagnetic interference and achieve the best EMI optimization effect in DCM mode, the EMI can be further optimized by combining the method described above with the peak current jitter method.

[0083] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

Claims

1. A frequency jittering method, applied to a quasi-resonant flyback converter, wherein the quasi-resonant flyback converter comprises a main switch tube arranged on the primary side; characterized in that: When the quasi-resonant flyback converter operates in a discontinuous conduction mode, the method includes: In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the valley bottom after the i-th zero-crossing signal is detected; In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the main switch tube is controlled to be turned on at the valley bottom after the jth zero-crossing signal is detected; M and N are two adjacent switching cycle groups, each switching cycle group contains an equal or unequal number of switching cycles; i is not equal to j; The conduction of the main switch tube is controlled by forming a repeating unit with a continuous K switching cycle group; K is greater than or equal to 2; In the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage; or, in the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage.

2. The frequency jittering method according to claim 1, characterized in that: In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, after the i-th zero-crossing signal is detected, the main switch tube is controlled to be turned on after a first delay; In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line and the jth zero-crossing signal is detected, the main switch tube is controlled to be turned on after a first delay.

3. The frequency jittering method according to claim 1, characterized in that: In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, a delay of X resonant cycles is performed, and then, after the Ath zero-crossing signal is detected, the main switch tube is controlled to be turned on after a delay of the first time; the sum of the number of zero-crossing signals contained in the X resonant cycles and A is equal to i; In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, it is delayed by Y resonant cycles, and then, after the Bth zero-crossing signal is detected, the main switch tube is controlled to be turned on after a delay of the first time; the sum of the number of zero-crossing signals contained in the Y resonant cycles and B is equal to j.

4. The frequency jittering method according to claim 2 or 3, characterized in that: When the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, the first time is 1 / 4 of the resonant cycle; The zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage, and the first time is 3 / 4 of the resonant cycle.

5. The frequency jittering method according to any one of claims 1 to 3, characterized in that: When the quasi-resonant flyback converter operates in the discontinuous conduction mode, the jittering of the system operating frequency is achieved by combining the jittering peak current; the peak current determines the turn-off moment of the main switch tube.

6. The frequency jittering method according to claim 1, characterized in that: When the quasi-resonant flyback converter operates in the critical conduction mode, the jittering of the system operating frequency is achieved by jittering the peak current; the peak current determines the turn-off moment of the main switch tube.

7. The frequency jittering method according to claim 1, characterized in that: The frequency limit line is a preset operating frequency, and the preset operating frequency is a fixed value or a jittered value.

8. A frequency-jittering circuit, applied to a quasi-resonant flyback converter, wherein the quasi-resonant flyback converter comprises a main switch tube arranged on the primary side; characterized in that: When the quasi-resonant flyback converter operates in a discontinuous conduction mode, the frequency jittering circuit includes: The frequency limit line judgment circuit is used to judge whether the operating frequency of the system reaches the frequency limit line; A switching cycle group determination circuit and a zero-crossing detection circuit, wherein when the switching cycle group determination circuit determines that the switching cycle group in the repeating unit is the Mth switching cycle group, after the system operating frequency reaches the frequency limit line, the frequency jittering circuit is used to control the main switch tube to be turned on at the bottom of the valley after the zero-crossing detection circuit detects the i-th zero-crossing signal; When the switching cycle group determination circuit determines that the switching cycle group in the repetitive unit is the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the frequency jittering circuit is used to control the main switch tube to turn on at the valley bottom after the zero-crossing signal detection circuit detects the jth zero-crossing detection signal; M and N are two adjacent switching cycle groups, each switching cycle group contains an equal or unequal number of switching cycles; i is not equal to j; The frequency jittering circuit controls the conduction of the main switch tube by forming the repeating unit with a group of K consecutive switch cycles; K is greater than or equal to 2; In the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage; or, in the repeating unit, the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage.

9. The frequency jittering circuit according to claim 8, characterized in that: The frequency jittering circuit further includes a first delay circuit. In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line and the i-th zero-crossing signal is detected, the first delay circuit controls the main switch tube to be turned on after a first delay time. In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line and the jth zero-crossing signal is detected, the first delay circuit controls the main switch tube to be turned on after a first delay time.

10. The frequency jittering circuit according to claim 9, characterized in that: When each switching cycle group includes one switching cycle, K=2, the switching cycle group determination circuit includes a frequency divider and a state determination circuit; The frequency divider is used to divide the driving signal for controlling the main switch tube to be turned on or off by two frequencies, and output a first control signal; The state judgment circuit receives the first control signal and outputs a second control signal with a different state based on the high and low level states of the first control signal; Based on the second control signal in the first state, after the zero-crossing detection circuit detects the i-th zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time; based on the second control signal in the second state, after the zero-crossing detection circuit detects the j-th zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time.

11. The frequency jittering circuit according to claim 8, characterized in that: The frequency jittering circuit further includes a second delay circuit and a first delay circuit. In the Mth switching cycle group, when the system operating frequency reaches the frequency limit line, the second delay circuit delays X resonant cycles, and then, after detecting the Ath zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for a first time; the sum of the number of zero-crossing signals contained in the X resonant cycles and A is equal to i; In the Nth switching cycle group, when the system operating frequency reaches the frequency limit line, the second delay circuit delays Y resonant cycles, and then, after detecting the Bth zero-crossing signal, the main switch tube is controlled to be turned on after delaying for a first time by the first delay circuit; the sum of the number of zero-crossing signals contained in the Y resonant cycles and B is equal to j.

12. The frequency jittering circuit according to claim 11, characterized in that: When each switching cycle group includes one switching cycle and K=2, the switching cycle group determination circuit further includes a frequency divider and a state determination circuit; The frequency divider is used to divide the driving signal for controlling the main switch tube to be turned on or off by two frequencies, and output a first control signal; The state judgment circuit receives the first control signal and outputs a second control signal with a different state based on the high and low level states of the first control signal; Based on the second control signal of the first state, the second delay circuit delays X resonant cycles, and then, after the zero-crossing detection circuit detects the Ath zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time; based on the second control signal of the second state, the second delay circuit controller delays Y resonant cycles, and then, after the zero-crossing detection circuit detects the Bth zero-crossing signal, the first delay circuit controls the main switch tube to be turned on after delaying for the first time.

13. The frequency jittering circuit according to any one of claims 9 to 12, characterized in that: When the zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from high to low to the input voltage, the first time is 1 / 4 of the resonant cycle; The zero-crossing signal represents the moment when the resonant voltage on the main switch tube resonates from low to high to the input voltage, and the first time is 3 / 4 of the resonant period.

14. The frequency jittering circuit according to any one of claims 8 to 12, characterized in that: When the quasi-resonant flyback converter operates in the discontinuous conduction mode, the frequency jittering circuit is further provided with a jittering peak current circuit, and the jittering of the system operating frequency is achieved in combination with the jittering peak current circuit; the peak current determines the turn-off moment of the main switch tube.

15. A quasi-resonant flyback converter, characterized in that: The quasi-resonant flyback converter comprises the frequency-jittering circuit according to any one of claims 8 to 14, and is based on the frequency-jittering circuit to reduce electromagnetic interference.

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