Flying capacitor three-level BUCK circuit based on double-voltage-sharing control and control method thereof

Abstract

The invention relates to a flying capacitor three-level BUCK circuit and a control method thereof, in particular to a flying capacitor three-level BUCK circuit based on double voltage-sharing control and a control method thereof, which are used for solving the problem of integrated optimization of voltage-sharing control and pre-charging technologies under various working conditions in the existing flying capacitor control technology. And a comprehensive solution is still lacked. The flying capacitor three-level BUCK circuit based on double-voltage-sharing control and the control method thereof comprise a direct voltage-sharing flying capacitor three-level BUCK conversion circuit and an automatic voltage-sharing control circuit which are respectively used for direct voltage sharing and indirect voltage sharing, and the voltage balance of a flying capacitor C2 can be ensured in various working states.

Description

Technical Field

[0001] The present invention relates to a flying capacitor three-level BUCK circuit and a control method thereof, and in particular to a flying capacitor three-level BUCK circuit based on dual voltage balancing control and a control method thereof. Background Art

[0002] The three-level BUCK topology with flying capacitor is an improved power management circuit, which is widely used in DC-DC buck converters. Compared with the traditional two-level BUCK circuit, the three-level topology reduces the voltage stress of the switching device by increasing the intermediate voltage level, thereby improving the conversion efficiency of the circuit. Especially in high-voltage and high-power applications, the advantages of the three-level BUCK circuit are more obvious, which can effectively reduce switching losses and current ripple.

[0003] One of the core components of this circuit is the flying capacitor, which is used to stabilize the intermediate voltage level so that the switch tube can operate under lower voltage stress. However, the voltage balance control of the flying capacitor has always been a technical difficulty, especially under light load or reverse current conditions, the traditional voltage balancing control method is often difficult to achieve effective control. The flying capacitor has a small capacity, which makes the circuit have higher requirements on the speed and accuracy of voltage balancing control. In addition, when the power is turned on for the first time, the flying capacitor needs to be pre-charged, which requires the design of a special pre-charging circuit to ensure the normal startup of the system.

[0004] Existing flying capacitor control technologies mainly focus on solving single problems, such as current direction control or light load voltage equalization control. However, there is still a lack of comprehensive solutions for the integrated optimization of voltage equalization control and pre-charging technology under various working conditions. Summary of the invention

[0005] The purpose of the present invention is to solve the problem that the existing flying capacitor control technology still lacks a comprehensive solution for the integrated optimization of voltage balancing control and pre-charging technology under various working conditions, and to provide a flying capacitor three-level BUCK circuit based on dual voltage balancing control and a control method thereof.

[0006] In order to solve the deficiencies of the above-mentioned prior art, the present invention provides the following technical solutions:

[0007] A flying capacitor three-level BUCK circuit based on dual voltage balancing control, which is special in that it includes a direct voltage balancing flying capacitor three-level BUCK conversion circuit and an automatic voltage balancing control circuit;

[0008] The direct voltage-equalizing flying capacitor three-level BUCK conversion circuit includes a first MOS tube S1, a second MOS tube S2, a third MOS tube S3, a fourth MOS tube S4, and an output capacitor C1, a flying capacitor C2, a bus capacitor C3, a filter inductor L1, an inductor L2, a current detection module, a voltage sampling module and a bidirectional isolation DCDC; the drain of the first MOS tube S1 is connected to the DC side input VIN, the source is connected to the drain of the second MOS tube S2, the source of the second MOS tube S2 is connected to the drain of the third MOS tube S3 and one end of the filter inductor L1, the source of the third MOS tube S3 is connected to the drain of the fourth MOS tube S4, and the source of the fourth MOS tube S4 is connected to the ground GND; the other end of the filter inductor L1 is connected to one end of the output capacitor C1 as a BUCK end, and the filter inductor L1 is connected to the output capacitor C1 as a BUCK end. 1 and one end of the output capacitor C1 are provided with a current detection module for collecting the load side output IL; the other end of the output capacitor C1 is connected to the ground GND; the two ends of the flying capacitor C2 are respectively connected to the drain of the second MOS tube S2 and the drain of the fourth MOS tube S4; the two ends of the bus capacitor C3 are respectively connected to the DC side input VIN and the ground GND; the positive electrode and the negative electrode of the bidirectional isolation DCDC input end are respectively connected to the DC side input VIN and the ground GND; the inductor L2 is connected in series between the positive electrode of the output end of the bidirectional isolation DCDC and the drain of the second MOS tube S2, and the negative electrode of the output end of the bidirectional isolation DCDC is connected to the drain of the fourth MOS tube S4; the voltage sampling module is used to respectively collect the DC voltage Vm at both ends of the bus capacitor C3 and the flying capacitor voltage Vcf at both ends of the flying capacitor C2;

[0009] The automatic voltage balancing control circuit is used to generate four driving signals with dead zone protection according to the difference between the DC voltage Vm, the flying capacitor voltage Vcf and the load side output IL, and respectively drive the first MOS transistor S1, the second MOS transistor S2, the third MOS transistor S3, and the fourth MOS transistor S4 to achieve indirect control of the flying capacitor voltage Vcf.

[0010] Furthermore, the automatic voltage balancing control circuit includes a flying capacitor voltage automatic unit and a PWM wave generating unit;

[0011] The flying capacitor voltage automatic unit includes a voltage regulating unit, a first comparing unit and a signal gating unit, wherein the voltage regulating unit is used to calculate the difference between the DC voltage Vm and the flying capacitor voltage Vcf and generate a corresponding control signal to output to the signal gating unit, the first comparing unit is used to receive the load side output IL and generate a signal Con to output to the signal gating unit, and the signal gating unit is used to switch different control paths according to the signal Con to output the signal Dx;

[0012] The PWM wave generating unit includes a duty cycle control unit, a triangular wave generating unit, a comparison unit and a dead zone unit; the duty cycle control unit is used to output two different signals Comp1 and Comp2 to the comparison unit according to the input duty cycle control signal Comp and the signal Dx; the triangular wave generating unit is used to generate a triangular wave signal Vramp and output it to the comparison unit; the comparison unit is used to compare the signal Comp1 with the triangular wave signal Vramp, the signal Comp2 with the triangular wave signal Vramp, and output the duty cycle modulation signal PWMA and the duty cycle modulation signal PWMB to the dead zone unit; the dead zone unit is used to generate four driving signals with dead zone protection, respectively driving the first MOS tube S1, the second MOS tube S2, the third MOS tube S3, and the fourth MOS tube S4.

[0013] Further, the voltage regulating unit includes a third proportional unit, a second proportional unit, a first summing unit, a first reverse proportional unit and a bidirectional limiting unit;

[0014] The input end of the third proportional unit is used to input the DC voltage Vm, the output end is connected to the non-inverting end of the first summing unit, the inverting end of the first summing unit is used to input the flying capacitor voltage Vcf, the output end is connected to the second proportional unit and the bidirectional limiting unit in sequence, the output end of the bidirectional limiting unit is connected to the high level input end of the selection unit, and is connected to the low level input end of the selection unit through the first reverse proportional unit.

[0015] Furthermore, the non-inverting input terminal of the first comparison unit is used to input the load side output IL, the inverting input terminal is grounded GND, and the output terminal is used to output a signal Con as a control signal of the gating unit.

[0016] Further, the duty cycle control unit includes a second summing unit and a third summing unit, and the comparison unit includes a second comparison unit and a third comparison unit;

[0017] The two input terminals of the second summing unit are respectively used to input the duty cycle control signal Comp and the signal Dx, and the output terminal is used to output the signal Comp1 to the in-phase terminal of the second comparing unit;

[0018] One input end of the third summing unit is connected to the duty cycle control signal Comp through the second reverse proportional unit, the other input end is used to input the signal Dx, and the output end is used to output the signal Comp2 to the inverting end of the third comparing unit;

[0019] The output end of the triangle wave generating unit is respectively connected to the inverting end of the second comparing unit and the non-inverting end of the third comparing unit; the output end of the second comparing unit and the output end of the third comparing unit are respectively used to output the duty cycle modulation signal PWMA and the duty cycle modulation signal PWMB to the dead zone unit.

[0020] Further, the dead zone unit includes a first dead zone unit and a second dead zone unit;

[0021] The first dead zone unit is used to receive the duty cycle modulation signal PWMA and generate a first driving signal DR1 and a fourth driving signal DR4 with complementary dead zones, the first driving signal DR1 is used to drive the first MOS transistor S1, and the fourth driving signal DR4 is used to drive the fourth MOS transistor S4;

[0022] The second dead zone unit is used to receive the duty cycle modulation signal PWMB and generate a second driving signal DR2 and a third driving signal DR3 with complementary dead zones. The second driving signal DR2 is used to drive the second MOS transistor S2, and the third driving signal DR3 is used to drive the third MOS transistor S3.

[0023] Furthermore, the voltage sampling module includes a first voltage sampling circuit and a second voltage sampling circuit; the input of the first voltage sampling circuit is connected to both ends of the bus capacitor C3 for collecting the DC voltage Vm; the input of the second voltage sampling circuit is connected to both ends of the flying capacitor C2 for collecting the flying capacitor voltage Vcf.

[0024] A control method of the flying capacitor three-level BUCK circuit based on dual voltage balancing control is special in that it includes the following steps:

[0025] Step 1: Determine whether the load side output IL is less than A. If so, proceed to step 2. Otherwise, determine whether the BUCK duty cycle is 0 or 100%. If so, proceed to step 2. Otherwise, proceed to step 3. A is 1% of the rated current.

[0026] Step 2: Perform forced voltage balancing control on the flying capacitor C2 through bidirectional isolation DCDC;

[0027] Step 3: indirectly control the flying capacitor voltage Vcf through an automatic voltage balancing control circuit.

[0028] Furthermore, the step 3 is specifically as follows:

[0029] Step 3.1, the voltage regulating unit calculates the difference between the DC voltage Vm and the flying capacitor voltage Vcf and generates a corresponding control signal to output to the signal gating unit, the first comparing unit receives the load side output IL and generates a signal Con to output to the signal gating unit, and then the signal gating unit switches different control paths according to the signal Con to output the signal Dx;

[0030] Step 3.2, the duty cycle control unit outputs two different signals Comp1 and Comp2 to the comparison unit according to the input duty cycle control signal Comp and the signal Dx obtained in step 3.1; the triangular wave generating unit generates a triangular wave signal Vramp and outputs it to the comparison unit; the comparison unit compares the signal Comp1 with the triangular wave signal Vramp, and the signal Comp2 with the triangular wave signal Vramp, and outputs the duty cycle modulation signal PWMA and the duty cycle modulation signal PWMB to the dead zone unit; the dead zone unit generates four driving signals with dead zone protection, and drives the first MOS tube S1, the second MOS tube S2, the third MOS tube S3, and the fourth MOS tube S4 respectively, so as to realize indirect control of the flying capacitor voltage Vcf.

[0031] Furthermore, the step 3.1 is specifically as follows:

[0032] The DC voltage Vm is input into the third proportional unit, and the output signal a is sent to the in-phase terminal of the first summing unit. Meanwhile, the flying capacitor voltage Vcf is input into the inverting terminal of the first summing unit. The first summing unit outputs a signal b to the second proportional unit, and the second proportional unit amplifies the signal k times and then outputs a signal c to the bidirectional limiting unit. The bidirectional limiting unit outputs a signal d to the high level input terminal of the gating unit and the first reverse proportional unit, and the first reverse proportional unit outputs a signal e to the low level input terminal of the gating unit. The value of k is 1 to 10.

[0033] The load side output IL is input to the non-inverting input terminal of the first comparison unit, the output signal Con of the first comparison unit is used as the control signal of the gating unit, and the gating unit outputs the signal Dx to one input terminal of the second summing unit and one input terminal of the third summing unit respectively;

[0034] The step 3.2 is specifically as follows:

[0035] The duty cycle control signal Comp is input into the other input end of the second summing unit and the second inverse proportional unit respectively, and the second inverse proportional unit outputs a signal -Comp to the other input end of the third summing unit;

[0036] The second summing unit outputs a signal Comp1 to the non-inverting terminal of the second comparing unit, the third summing unit outputs a signal Comp2 to the inverting terminal of the third comparing unit, and the triangular wave generating unit outputs a triangular wave signal Vramp to the inverting terminal of the second comparing unit and the non-inverting terminal of the third comparing unit respectively;

[0037] The second comparison unit outputs the duty cycle modulation signal PWMA to the first dead zone unit, and the first dead zone unit generates a first driving signal DR1 and a fourth driving signal DR4 with complementary dead zones, drives the first MOS transistor S1 through the first driving signal DR1, and drives the fourth MOS transistor S4 through the fourth driving signal DR4;

[0038] At the same time, the third comparison unit outputs the duty cycle modulation signal PWMB to the second dead zone unit, and the second dead zone unit generates a second drive signal DR2 and a third drive signal DR3 with complementary dead zones. The second MOS tube S2 is driven by the second drive signal DR2, and the third MOS tube S3 is driven by the third drive signal DR3, so as to realize indirect control of the flying capacitor voltage Vcf.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] (1) The present invention is based on a flying capacitor three-level BUCK circuit with dual voltage balancing control, including a direct voltage balancing flying capacitor three-level BUCK conversion circuit and an automatic voltage balancing control circuit, which are respectively used for direct voltage balancing and indirect voltage balancing, and can ensure voltage balance of the flying capacitor C2 in various working conditions.

[0041] (2) The present invention adopts a bidirectional isolated DC-DC with a soft load characteristic of a one-side series inductor L2 to directly equalize the DC voltage Vm corresponding to the bus capacitor C3 and the flying capacitor voltage Vcf corresponding to the flying capacitor C2, thereby ensuring natural voltage equalization under light load conditions. At the same time, the flying capacitor C2 can be pre-charged and controlled by the bidirectional isolated DC-DC, wherein the inductor L2 can prevent the ripple current of the flying capacitor C2 from triggering the overcurrent protection of the bidirectional isolated DC-DC.

[0042] (3) The present invention compensates the duty cycle of the four NMOS tubes through the voltage of the bus capacitor C3 and the flying capacitor C2 to ensure that the voltage of the flying capacitor is quickly and stably controlled during the loading process.

[0043] (4) The present invention collects the load-side output IL in real time through the current detection module to adjust the switch tube duty cycle compensation direction, thereby eliminating the flying capacitor voltage out-of-control problem caused by the change in current direction.

[0044] (5) The control method of the flying capacitor three-level BUCK circuit based on dual voltage-equalizing control of the present invention realizes indirect control of the flying capacitor voltage by dynamically adjusting the on and off states of the MOS tube by real-time detection of the flying capacitor voltage Vcf and the load-side output IL using proportional control and duty cycle modulation. The present invention can effectively adjust the discharge and charging time of the flying capacitor C2 to ensure that the flying capacitor voltage Vcf is maintained within a reasonable range, and adjust the intensity of the feedback response by adjusting the coefficient k of the proportional unit, thereby realizing efficient voltage balancing. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a circuit diagram of a direct voltage-balanced flying capacitor three-level BUCK conversion circuit in an embodiment of a flying capacitor three-level BUCK circuit based on dual voltage-balanced control of the present invention;

[0046] Figure 2 Schematic diagram of an automatic voltage-equalizing control circuit in an embodiment of the present invention;

[0047] Figure 3 It is a working timing diagram of a control process in which the current flows from the DC side to the load side and the BUCK working duty cycle is less than 50% in an embodiment of a control method of a flying capacitor three-level BUCK circuit based on dual voltage balancing control of the present invention;

[0048] Figure 4 It is a working timing diagram of the control process in which the current flows from the DC side to the load side and the BUCK duty cycle is greater than 50% in an embodiment of the present invention;

[0049] Figure 5 It is a working timing diagram of the control process in which the current is fed back from the load side to the DC side and the BUCK duty cycle is less than 50% in an embodiment of the present invention;

[0050] Figure 6 This is a working timing diagram of the control process in which the current is fed back from the load side to the DC side and the BUCK duty cycle is greater than 50% in an embodiment of the present invention.

[0051] The following are the descriptions of the reference numerals:

[0052] 10-flying capacitor voltage automatic unit, 11-voltage regulation unit; 20-PWM wave generating unit, 21-duty cycle control unit, 22-comparison unit, 23-dead zone unit;

[0053] 120-first summing unit; 121-second summing unit; 122-third summing unit; 123-first comparison unit; 124-second comparison unit; 125-third comparison unit; 126-first reverse proportional unit; 127-second reverse proportional unit; 128-triangular wave generating unit; 129-first dead zone unit; 130-second dead zone unit; 131-selection unit; 132-second proportional unit; 133-bidirectional limiting unit; 134-third proportional unit;

[0054] 100 - first voltage sampling circuit; 101 - bidirectional isolation DCDC; 102 - second voltage sampling circuit; 103 - current detection module. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the accompanying drawings and exemplary embodiments.

[0056] Reference Figure 1 and Figure 2 A flying capacitor three-level BUCK circuit based on dual voltage balancing control includes a direct voltage balancing flying capacitor three-level BUCK conversion circuit and an automatic voltage balancing control circuit.

[0057] Reference Figure 1 The direct voltage-equalizing flying capacitor three-level BUCK conversion circuit is used to step down the higher DC side input VIN into a stable load side output IL, which includes a first MOS transistor S1, a second MOS transistor S2, a third MOS transistor S3, a fourth MOS transistor S4, and an output capacitor C1, a flying capacitor C2, a bus capacitor C3, a filter inductor L1, an inductor L2, a current detection module 103, a voltage sampling module and a bidirectional isolation DCDC 101 connected in series in sequence;

[0058] The drain of the first MOS transistor S1 is connected to the DC side input VIN, and the source is connected to the drain of the second MOS transistor S2. The source of the second MOS transistor S2 is connected to the drain of the third MOS transistor S3 and one end of the filter inductor L1. The source of the third MOS transistor S3 is connected to the drain of the fourth MOS transistor S4. The source of the fourth MOS transistor S4 is connected to the ground GND.

[0059] The other end of the filter inductor L1 is connected to one end of the output capacitor C1 as a BUCK end, and a current detection module 103 is provided between the other end of the filter inductor L1 and one end of the output capacitor C1. The filter inductor L1 is used to smooth the output current, and the current detection module 103 is used to collect the load side output IL (the current flowing through the filter inductor L1); the other end of the output capacitor C1 is connected to the ground GND, so as to further reduce the voltage ripple and stabilize the output;

[0060] The two ends of the flying capacitor C2 are respectively connected to the drain of the second MOS transistor S2 and the drain of the fourth MOS transistor S4; the two ends of the bus capacitor C3 are respectively connected to the DC side input VIN and the ground GND;

[0061] The positive electrode and the negative electrode of the input end of the bidirectional isolation DCDC 101 are connected to the DC side input VIN and the ground GND respectively; the positive electrode of the output end of the bidirectional isolation DCDC 101 is connected to the drain of the second MOS tube S2 through the series inductor L2, and the negative electrode of the output end of the bidirectional isolation DCDC 101 is connected to the drain of the fourth MOS tube S4;

[0062] The voltage sampling module is used to respectively collect the DC voltage Vm corresponding to the flying capacitor C2 and the flying capacitor voltage Vcf corresponding to the bus capacitor C3, and includes a first voltage sampling circuit 100 and a second voltage sampling circuit 102; the input of the first voltage sampling circuit 100 is connected to both ends of the bus capacitor C3, and is used to collect the DC voltage Vm; the input of the second voltage sampling circuit 102 is connected to both ends of the flying capacitor C2, and is used to collect the flying capacitor voltage Vcf;

[0063] Reference Figure 2 , the automatic voltage equalization control circuit includes a PWM wave generating unit 20 and a flying capacitor voltage automatic unit 10;

[0064] The flying capacitor voltage automatic unit 10 is used to adjust the flying capacitor voltage Vcf through closed-loop control, and includes a voltage regulating unit 11, a first comparing unit 123 and a signal gating unit 131; the voltage regulating unit 11 is used to calculate the difference between the DC voltage Vm and the flying capacitor voltage Vcf and generate a corresponding control signal to output to the signal gating unit 131, and includes a third proportional unit 134, a first summing unit 120, a second proportional unit 132, a first reverse proportional unit 126 and a bidirectional limiting unit 133; the first comparing unit 123 is used to receive the load side output IL and generate a signal Con to output to the signal gating unit 131, and the signal gating unit 131 is used to switch different control paths according to the signal Con to output the signal Dx.

[0065] Specifically, the input end of the third proportional unit 134 is used to input the DC voltage Vm, the output end is connected to the non-inverting end of the first summing unit 120, the inverting end of the first summing unit 120 is used to input the flying capacitor voltage Vcf, the output end is connected to the second proportional unit 132 and the bidirectional limiting unit 133 in sequence, the output end of the bidirectional limiting unit 133 is connected to the high level input end of the gating unit 131, and is connected to the low level input end of the gating unit 131 through the first reverse proportional unit 126; the non-inverting input end of the first comparing unit 123 is used to input the load side output IL, the inverting input end is grounded GND, and the output end is used to output the signal Con as the control signal of the gating unit 131.

[0066] The PWM wave generating unit 20 is used to generate a PWM signal, and controls the switching operation of the MOS tube by adjusting the duty cycle and introducing the dead time, so as to realize the precise control of the voltage and current, and includes a duty cycle control unit 21, a triangular wave generating unit 128, a comparison unit 22 and a dead time unit 23; the duty cycle control unit 21 is used to output two different signals Comp1 and Comp2 to the comparison unit 22 according to the input duty cycle control signal Comp and the signal Dx, and the duty cycle control unit 21 includes a second summing unit 121 and a third summing unit 122; the triangular wave generating unit 128 is used to generate a triangular wave signal Vr amp, and outputs it to the comparison unit 22; the comparison unit 22 is used to compare the signal Comp1 with the triangular wave signal Vramp, the signal Comp2 with the triangular wave signal Vramp, and output the duty cycle modulation signal PWMA and the duty cycle modulation signal PWMB to the dead zone unit 23, and the comparison unit 22 includes a second comparison unit 124 and a third comparison unit 125; the dead zone unit 23 is used to generate four driving signals with dead zone protection, respectively driving the first MOS tube S1, the second MOS tube S2, the third MOS tube S3, and the fourth MOS tube S4, and the dead zone unit includes a first dead zone unit 129 and a second dead zone unit 130.

[0067] Specifically, the two input terminals of the second summing unit 121 are respectively used to input the duty cycle control signal Comp and the signal Dx, and the output terminal is used to output the signal Comp1 to the in-phase terminal of the second comparing unit 124;

[0068] One input terminal of the third summing unit 122 is used to input the duty cycle control signal Comp through the second reverse proportional unit 127, another input terminal is used to input the signal Dx, and the output terminal is used to output the signal Comp2 to the inverting terminal of the third comparing unit 125;

[0069] The output end of the triangle wave generating unit 128 is respectively connected to the inverting end of the second comparing unit 124 and the non-inverting end of the third comparing unit 125 for inputting the triangle wave signal Vramp;

[0070] The output end of the second comparison unit 124 is used to output the duty cycle modulation signal PWMA to the first dead zone unit 129. The first dead zone unit 129 is used to generate a first driving signal DR1 and a fourth driving signal DR4 with complementary dead zones. The first driving signal DR1 is used to drive the first MOS transistor S1, and the fourth driving signal DR4 is used to drive the fourth MOS transistor S4.

[0071] The output end of the third comparison unit 125 is used to output the duty cycle modulation signal PWMB to the second dead zone unit 130. The second dead zone unit 130 is used to generate a second drive signal DR2 and a third drive signal DR3 with complementary dead zones. The second drive signal DR2 is used to drive the second MOS tube S2, and the third drive signal DR3 is used to drive the third MOS tube S3.

[0072] The control method of the flying capacitor three-level BUCK circuit based on dual voltage balancing control comprises the following steps:

[0073] Step 1: Determine whether the load side output IL is less than 1% of the rated current. If so, proceed to step 2. Otherwise, determine whether the BUCK working duty cycle is 0 or 100%. If so, proceed to step 2. Otherwise, proceed to step 3.

[0074] Step 2: Perform forced voltage balancing control on the flying capacitor C2 through the bidirectional isolation DCDC 101;

[0075] Specifically, when the load-side output IL is less than 1% of the rated current, it is impossible to compensate by adjusting the BUCK working duty cycle of the four MOS tubes. At this time, the flying capacitor C2 is forced to be voltage-balanced through the bidirectional isolation DCDC 101. In order to prevent the ripple current of the flying capacitor C2 from flowing through the bidirectional isolation DCDC 101 and causing overcurrent protection, the positive electrode of the output end of the bidirectional isolation DCDC 101 is connected in series with an inductor L2. The cut-off frequency fz composed of the inductor L2 and the bus capacitor C3 should be less than 0.1 times the BUCK working switching frequency (the frequency of the MOS tube switch in the direct voltage-balanced flying capacitor three-level BUCK conversion circuit);

[0076] In addition, when the BUCK working duty cycle is 0, the first MOS tube S1 and the second MOS tube S2 are turned on, and the third MOS tube S3 and the fourth MOS tube S4 are turned off. At this time, the flying capacitor C2 has no heavy discharge process and cannot perform indirect voltage balancing control. At this time, the flying capacitor C2 is forced to be voltage-balanced through the bidirectional isolation DCDC 101;

[0077] In addition, when the BUCK working duty cycle is 100%, the first MOS tube S1 and the second MOS tube S2 are turned off, and the third MOS tube S3 and the fourth MOS tube S4 are turned on. At this time, the flying capacitor C2 has no heavy discharge process and cannot perform indirect voltage balancing control. At this time, the flying capacitor C2 is forced to be voltage-balanced through the bidirectional isolation DCDC 101.

[0078] It should be noted that if the current required for voltage balancing of the bidirectional isolation DCDC 101 exceeds its set maximum capacity at this time, the bidirectional isolation DCDC 101 will enter the current limiting working mode, and the flying capacitor C2 cannot be controlled for voltage balancing, and all MOS tubes need to be turned off;

[0079] Step 3, indirectly controlling the flying capacitor voltage Vcf through an automatic voltage balancing control circuit;

[0080] Step 3.1, the voltage regulating unit 11 calculates the difference between the DC voltage Vm and the flying capacitor voltage Vcf and generates a corresponding control signal to output to the signal gating unit 131, the first comparing unit 123 receives the load side output IL and generates a signal Con to output to the signal gating unit 131, and then the signal gating unit 131 switches different control paths according to the signal Con to output the signal Dx;

[0081] Specifically, the DC voltage Vm is input to the third proportional unit 134, and the output signal a (0.5Vm) is input to the in-phase terminal of the first summing unit 120. The flying capacitor voltage Vcf is input to the inverting terminal of the first summing unit 120. The first summing unit 120 outputs a signal b (0.5Vm-Vcf) to the second proportional unit 132, and the second proportional unit 132 amplifies the signal c (k (0.5Vm-Vcf)) by k times to the bidirectional limiting unit 133; the bidirectional limiting unit 133 outputs a signal d (when the amplitude limit value is not reached, the signal d is k (0.5Vm-Vcf)) to the high level input terminal of the gating unit 131 and the first reverse proportional unit 126, and the first reverse proportional unit 126 outputs a signal e (when the amplitude limit value is not reached, the signal e is -k (0.5Vm-Vcf)) to the low level input terminal of the gating unit 131;

[0082] The load side output IL is input to the non-inverting input terminal of the first comparison unit 123, and the first comparison unit 123 outputs a signal Con as a control signal of the selection unit 131, and then the selection unit 131 outputs a signal Dx (equal to the signal d) to an input terminal of the second summing unit 121 and an input terminal of the third summing unit 122 respectively;

[0083] When the current flows from the DC side to the load, the load side output IL is greater than 0, and the signal Con is high level;

[0084] When the current is fed back from the load side to the DC side, the load side output IL is less than 0, and the signal Con is low level;

[0085] Step 3.2, the duty cycle control unit 21 outputs two different signals Comp1 and Comp2 to the comparison unit 22 according to the input duty cycle control signal Comp and the step 3 signal Dx; the triangular wave generating unit 128 generates a triangular wave signal Vramp and outputs it to the comparison unit 22; the comparison unit 22 compares the signal Comp1 with the triangular wave signal Vramp, the signal Comp2 with the triangular wave signal Vramp, and outputs the duty cycle modulation signal PWMA and the duty cycle modulation signal PWMB to the dead zone unit 23; the dead zone unit 23 generates four driving signals with dead zone protection, which respectively drive the first MOS tube S1, the second MOS tube S2, the third MOS tube S3, and the fourth MOS tube S4 to realize indirect control of the flying capacitor voltage Vcf;

[0086] Specifically, the duty cycle control signal Comp is input to the other input terminal of the second summing unit 121 and the second inverse proportional unit 127, and the second inverse proportional unit 127 outputs a signal -Comp to the other input terminal of the third summing unit 122;

[0087] The second summing unit 121 outputs a signal Comp1 (Comp+Dx) to the non-inverting terminal of the second comparing unit 124, the third summing unit 122 outputs a signal Comp2 (-Comp+Dx) to the inverting terminal of the third comparing unit 125, and the triangular wave generating unit 128 outputs a triangular wave signal Vramp to the inverting terminal of the second comparing unit 124 and the non-inverting terminal of the third comparing unit 125;

[0088] Then the second comparison unit 124 outputs the duty cycle modulation signal PWMA to the first dead zone unit 129, and the first dead zone unit 129 generates a first driving signal DR1 and a fourth driving signal DR4 with complementary dead zones, drives the first MOS transistor S1 through the first driving signal DR1, and drives the fourth MOS transistor S4 through the fourth driving signal DR4;

[0089] At the same time, the duty cycle modulation signal PWMB is outputted from the output terminal of the third comparison unit 125 to the second dead zone unit 130, and the second dead zone unit 130 generates a second driving signal DR2 and a third driving signal DR3 with complementary dead zones, and drives the second MOS transistor S2 through the second driving signal DR2, and drives the third MOS transistor S3 through the third driving signal DR3;

[0090] Current flows from the DC side to the load;

[0091] When the flying capacitor voltage Vcf>0.5Vm, Dx=k(0.5Vm-Vcf)<0, resulting in Comp1=Comp+Dx decreasing, Comp2=-Comp+Dx decreasing, the duty cycle of the duty cycle modulation signal PWMA decreasing, the duty cycle of the duty cycle modulation signal PWMB increasing, the duty cycle of the first drive signal DR1 increasing, and the duty cycle of the second drive signal DR2 decreasing; for example Figure 3 and Figure 4 At time t1, it can be seen that the discharge time of the flying capacitor C2 increases and the charging time shortens, thereby suppressing the increase of the flying capacitor C2 voltage. The degree of negative feedback can be adjusted by the coefficient k of the proportional unit; the value of k is 1 to 10;

[0092] When the flying capacitor voltage Vcf is less than 0.5Vm, Dx=k(0.5Vm-Vcf)>0, which causes Comp1=Comp+Dx to increase, Comp2=-Comp+Dx to increase, the duty cycle of the duty cycle modulation signal PWMA to increase, the duty cycle of the duty cycle modulation signal PWMB to decrease, the duty cycle of the first drive signal DR1 to decrease, and the duty cycle of the second drive signal DR2 to increase; for example Figure 3 and Figure 4 At time t2, it can be seen that the discharge time of the flying capacitor C2 is shortened and the charging time is increased, thereby suppressing the decrease of the flying capacitor C2 voltage. The degree of negative feedback can be adjusted by the coefficient k of the proportional unit;

[0093] The current is fed back from the load side to the DC side;

[0094] When the flying capacitor voltage Vcf>0.5Vm, Dx=-k(0.5Vm-Vcf)>0, resulting in Comp1=Comp+Dx increasing, Comp2=-Comp+Dx increasing, the duty cycle of the duty cycle modulation signal PWMA increasing, the duty cycle of the duty cycle modulation signal PWMB decreasing, the duty cycle of the first drive signal DR1 decreasing, and the duty cycle of the second drive signal DR2 increasing; for example Figure 5 and Figure 6 At time t1, it can be seen that the discharge time of the flying capacitor C2 increases and the charging time shortens, thereby suppressing the increase of the flying capacitor C2 voltage. The degree of negative feedback can be adjusted by the coefficient k of the proportional unit;

[0095] When the flying capacitor voltage Vcf is less than 0.5Vm, Dx=-k(0.5Vm-Vcf)<0, which causes Comp1=Comp+Dx to decrease, Comp2=-Comp+Dx to decrease, the duty cycle of the duty cycle modulation signal PWMA to decrease, the duty cycle of the duty cycle modulation signal PWMB to increase, the duty cycle of the first drive signal DR1 to increase, and the duty cycle of the second drive signal DR2 to decrease; for example Figure 5 and Figure 6At time t2, it can be seen that the discharge time of the flying capacitor C2 is shortened and the charging time is increased, thereby suppressing the decrease in the voltage of the flying capacitor C2. The degree of negative feedback can be adjusted by the coefficient k of the proportional unit.

Claims

1. A flying capacitor three-level BUCK circuit based on dual voltage balancing control, characterized in that: It includes a direct voltage-equalizing flying capacitor three-level BUCK conversion circuit and an automatic voltage-equalizing control circuit; The direct voltage-equalizing flying capacitor three-level BUCK conversion circuit comprises a first MOS transistor S1, a second MOS transistor S2, a third MOS transistor S3, a fourth MOS transistor S4, an output capacitor C1, a flying capacitor C2, a bus capacitor C3, a filter inductor L1, an inductor L2, a current detection module (103), a voltage sampling module and a bidirectional isolation DCDC (101); the drain of the first MOS transistor S1 is connected to a DC side input VIN, the source is connected to the drain of the second MOS transistor S2, the source of the second MOS transistor S2 is connected to the drain of the third MOS transistor S3 and one end of the filter inductor L1, the source of the third MOS transistor S3 is connected to the drain of the fourth MOS transistor S4, and the source of the fourth MOS transistor S4 is connected to the ground GND; the other end of the filter inductor L1 is connected to one end of the output capacitor C1 as a BUCK end, and the other end of the filter inductor L1 is connected to the DC side input VIN. A current detection module (103) is provided between one end of the output capacitor C1, and is used for collecting the load side output IL; the other end of the output capacitor C1 is connected to the ground GND; the two ends of the flying capacitor C2 are respectively connected to the drain of the second MOS transistor S2 and the drain of the fourth MOS transistor S4; the two ends of the bus capacitor C3 are respectively connected to the DC side input VIN and the ground GND; the positive electrode and the negative electrode of the input end of the bidirectional isolation DCDC (101) are respectively connected to the DC side input VIN and the ground GND; the inductor L2 is connected in series between the positive electrode of the output end of the bidirectional isolation DCDC (101) and the drain of the second MOS transistor S2, and the negative electrode of the output end of the bidirectional isolation DCDC (101) is connected to the drain of the fourth MOS transistor S4; the voltage sampling module is used for respectively collecting the DC voltage Vm at the two ends of the bus capacitor C3 and the flying capacitor voltage Vcf at the two ends of the flying capacitor C2; The automatic voltage balancing control circuit is used to generate four driving signals with dead zone protection according to the difference between the DC voltage Vm, the flying capacitor voltage Vcf and the load side output IL, and respectively drive the first MOS transistor S1, the second MOS transistor S2, the third MOS transistor S3, and the fourth MOS transistor S4 to achieve indirect control of the flying capacitor voltage Vcf.

2. The flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 1, characterized in that: The automatic voltage-equalizing control circuit comprises a flying capacitor voltage automatic unit (10) and a PWM wave generating unit (20); The flying capacitor voltage automatic unit (10) comprises a voltage regulating unit (11), a first comparing unit (123) and a signal gating unit (131), wherein the voltage regulating unit (11) is used to calculate the difference between the DC voltage Vm and the flying capacitor voltage Vcf and generate a corresponding control signal to output to the signal gating unit (131), the first comparing unit (123) is used to receive the load side output IL and generate a signal Con to output to the signal gating unit (131), and the signal gating unit (131) is used to switch different control paths according to the signal Con to output the signal Dx; The PWM wave generating unit (20) comprises a duty cycle control unit (21), a triangular wave generating unit (128), a comparison unit (22) and a dead zone unit (23); the duty cycle control unit (21) is used to output two different signals Comp1 and Comp2 to the comparison unit (22) according to the input duty cycle control signal Comp and the signal Dx; the triangular wave generating unit (128) is used to generate a triangular wave signal Vramp and output it to the comparison unit (22); the comparison unit (22) is used to compare the signal Comp1 with the triangular wave signal Vramp, the signal Comp2 with the triangular wave signal Vramp, and output a duty cycle modulation signal PWMA and a duty cycle modulation signal PWMB to the dead zone unit (23); the dead zone unit (23) is used to generate four driving signals with dead zone protection, and respectively drive a first MOS tube S1, a second MOS tube S2, a third MOS tube S3 and a fourth MOS tube S4.

3. The flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 2, characterized in that: The voltage regulating unit (11) comprises a third proportional unit (134), a second proportional unit (132), a first summing unit (120), a first reverse proportional unit (126) and a bidirectional limiting unit (133); The input end of the third proportional unit (134) is used to input a DC voltage Vm, the output end is connected to the non-inverting end of the first summing unit (120), the inverting end of the first summing unit (120) is used to input the flying capacitor voltage Vcf, the output end is sequentially connected to the second proportional unit (132) and the bidirectional limiting unit (133), the output end of the bidirectional limiting unit (133) is connected to the high level input end of the gating unit (131), and is connected to the low level input end of the gating unit (131) through the first reverse proportional unit (126).

4. The flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 2, characterized in that: The first comparison unit (123) has a non-inverting input terminal for inputting the load-side output IL, an inverting input terminal connected to the ground GND, and an output terminal for outputting a signal Con as a control signal of the gating unit (131).

5. The flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 2, characterized in that: The duty cycle control unit (21) comprises a second summing unit (121) and a third summing unit (122); the comparison unit (22) comprises a second comparison unit (124) and a third comparison unit (125); The two input terminals of the second summing unit (121) are respectively used to input the duty cycle control signal Comp and the signal Dx, and the output terminal is used to output the signal Comp1 to the in-phase terminal of the second comparing unit (124); One input end of the third summing unit (122) is connected to the duty cycle control signal Comp via a second reverse proportional unit (127), the other input end is used to input the signal Dx, and the output end is used to output the signal Comp2 to the inverting end of the third comparing unit (125); The output end of the triangle wave generating unit (128) is respectively connected to the inverting end of the second comparing unit (124) and the non-inverting end of the third comparing unit (125); the output end of the second comparing unit (124) and the output end of the third comparing unit (125) are respectively used to output the duty cycle modulation signal PWMA and the duty cycle modulation signal PWMB to the dead zone unit (23).

6. The flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 5, characterized in that: The dead zone unit (23) comprises a first dead zone unit (129) and a second dead zone unit (130); The first dead zone unit (129) is used to receive the duty cycle modulation signal PWMA and generate a first drive signal DR1 and a fourth drive signal DR4 with complementary dead zones, the first drive signal DR1 is used to drive the first MOS transistor S1, and the fourth drive signal DR4 is used to drive the fourth MOS transistor S4; The second dead zone unit (130) is used to receive the duty cycle modulation signal PWMB and generate a second drive signal DR2 and a third drive signal DR3 with complementary dead zones, the second drive signal DR2 is used to drive the second MOS transistor S2, and the third drive signal DR3 is used to drive the third MOS transistor S3.

7. The flying capacitor three-level BUCK circuit based on dual voltage balancing control according to any one of claims 1 to 6, characterized in that: The voltage sampling module comprises a first voltage sampling circuit (100) and a second voltage sampling circuit (102); the input of the first voltage sampling circuit (100) is connected to both ends of a bus capacitor C3, and is used to collect a DC voltage Vm; the input of the second voltage sampling circuit (102) is connected to both ends of a flying capacitor C2, and is used to collect a flying capacitor voltage Vcf.

8. A control method for a flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 1, characterized in that: The steps include: Step 1: Determine whether the load side output IL is less than A. If so, proceed to step 2. Otherwise, determine whether the BUCK duty cycle is 0 or 100%. If so, proceed to step 2. Otherwise, proceed to step 3. A is 1% of the rated current. Step 2: Performing forced voltage balancing control on the flying capacitor C2 through a bidirectional isolation DCDC (101); Step 3: indirectly control the flying capacitor voltage Vcf through an automatic voltage equalization control circuit.

9. The control method of the flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 8, characterized in that: The step 3 is specifically as follows: Step 3.1, the voltage regulating unit (11) calculates the difference between the DC voltage Vm and the flying capacitor voltage Vcf and generates a corresponding control signal to output to the signal gating unit (131), the first comparing unit (123) receives the load side output IL and generates a signal Con to output to the signal gating unit (131), and then the signal gating unit (131) switches different control paths according to the signal Con to output the signal Dx; Step 3.2, the duty cycle control unit (21) outputs two different signals Comp1 and Comp2 to the comparison unit (22) according to the input duty cycle control signal Comp and the signal Dx obtained in step 3.1; the triangular wave generating unit (128) generates a triangular wave signal Vramp and outputs it to the comparison unit (22); the comparison unit (22) compares the signal Comp1 with the triangular wave signal Vramp, and the signal Comp2 with the triangular wave signal Vramp, and outputs a duty cycle modulation signal PWMA and a duty cycle modulation signal PWMB to the dead zone unit (23); the dead zone unit (23) generates four driving signals with dead zone protection, and drives the first MOS tube S1, the second MOS tube S2, the third MOS tube S3, and the fourth MOS tube S4 respectively, so as to realize indirect control of the flying capacitor voltage Vcf.

10. The control method of the flying capacitor three-level BUCK circuit based on dual voltage balancing control according to claim 9, characterized in that: The step 3.1 is specifically as follows: The DC voltage Vm is input into the third proportional unit (134) to output a signal a to the in-phase terminal of the first summing unit (120), and the flying capacitor voltage Vcf is input into the inverting terminal of the first summing unit (120); the first summing unit (120) outputs a signal b to the second proportional unit (132); the second proportional unit (132) amplifies the signal k times and outputs a signal c to the bidirectional amplitude limiting unit (133); the bidirectional amplitude limiting unit (133) outputs a signal d to the high level input terminal of the gating unit (131) and the first reverse proportional unit (126); and the first reverse proportional unit (126) outputs a signal e to the low level input terminal of the gating unit (131); the value of k is 1 to 10; The load side output IL is input to the non-inverting input terminal of the first comparison unit (123), the first comparison unit (123) outputs a signal Con as a control signal of the selection unit (131), and the selection unit (131) outputs a signal Dx to an input terminal of the second summing unit (121) and an input terminal of the third summing unit (122); The step 3.2 is specifically as follows: The duty cycle control signal Comp is input into the other input end of the second summing unit (121) and the second reverse proportional unit (127), and the second reverse proportional unit (127) outputs a signal -Comp to the other input end of the third summing unit (122); The second summing unit (121) outputs a signal Comp1 to the in-phase terminal of the second comparing unit (124), the third summing unit (122) outputs a signal Comp2 to the inverting terminal of the third comparing unit (125), and the triangular wave generating unit (128) outputs a triangular wave signal Vramp to the inverting terminal of the second comparing unit (124) and the in-phase terminal of the third comparing unit (125); The second comparison unit (124) outputs a duty cycle modulation signal PWMA to the first dead zone unit (129), and the first dead zone unit (129) generates a first drive signal DR1 and a fourth drive signal DR4 with complementary dead zones, and drives the first MOS transistor S1 through the first drive signal DR1, and drives the fourth MOS transistor S4 through the fourth drive signal DR4; At the same time, the third comparison unit (125) outputs a duty cycle modulation signal PWMB to the second dead zone unit (130), and the second dead zone unit (130) generates a second drive signal DR2 and a third drive signal DR3 with complementary dead zones, drives the second MOS transistor S2 through the second drive signal DR2, and drives the third MOS transistor S3 through the third drive signal DR3, thereby realizing indirect control of the flying capacitor voltage Vcf.

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