Sliding Mode Optimization Control Method and System for Three-Phase Inverter Parallel System Considering Inter-Phase and Phase-Inside Circulating Currents

Abstract

A sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and intra-phase circulating currents of the present invention includes the following steps: Step 1, design a robust droop sliding mode control controller, which includes a bus voltage following sliding mode control, a Q-U loop voltage response sliding mode control, a P-f loop frequency response sliding mode control, and an adaptive virtual reactance regulator; Step 2, design a zero-sequence voltage sliding mode control suppressor, and introduce a regulation factor k m to control the action time of vector synthesis. The present invention solves the problem of poor performance caused by the PI control method in the inter-phase circulating current model and improves the performance of the intra-phase circulating current model. Compared with the PI control, the sliding mode control has stronger robustness, can maintain stability under system parameter changes and external disturbances, and at the same time has a faster dynamic response and can effectively cope with rapid disturbances.

Description

Technical Field

[0001] The present invention relates to the technical field of sliding mode control systems for three-phase inverters, and specifically to a sliding mode optimization control method and system for a three-phase inverter parallel system considering inter-phase and phase-internal circulating currents. Background Art

[0002] A three-phase inverter parallel system is a topological structure in which multiple three-phase inverters operate in parallel to work together. It can significantly increase the total output power of the system and enhance the reliability of the system. However, due to the fact that the parameters and operating states of each parallel inverter cannot be exactly the same, under high-power input conditions, inter-phase and phase-internal circulating currents will inevitably occur in the system. Such circulating currents will not only reduce the conversion efficiency of the system, but also have a negative impact on the stability of the system. When the amplitude of the circulating current exceeds the critical value, it may even cause large-scale oscillations in the power grid and even lead to serious problems such as power grid collapse. At present, the solutions to the phase circulating current still need to be improved. In the existing analysis of three-phase inverter parallel systems, from the perspective of modeling, there is no clear distinction between the modeling of inter-phase and phase-internal circulating currents. From the perspective of control, the traditional virtual impedance droop control (VIDC) only uses simple PI control to suppress inter-phase circulating currents, only considering active-power-frequency (P-f) and reactive-power-voltage (Q-U) regulation. This method has poor suppression performance for inter-phase circulating currents. In addition, the traditional SVPWM cannot solve the zero-sequence voltage problem, and the phase-internal circulating current is serious. The present invention mainly solves the following problems:

[0003] 1. Solve the problem of poor model performance caused by using PI control during the suppression of inter-phase circulating currents.

[0004] PI control is a common control method. Its algorithm is simple and can be applied to various different controlled systems. However, the PI controller has a slow response and is difficult to cope with rapid disturbances and high-frequency oscillations. In addition, its tuning is complex, and its robustness to system parameter changes and external disturbances is also poor. It is difficult to handle the nonlinear and time-varying characteristics of the system, and the suppression effect on inter-phase circulating currents is not ideal. Therefore, other strategies need to be adopted to improve the suppression effect.

[0005] 2. Solve the problem of inter-phase circulating currents caused by poor system power distribution accuracy of the traditional VIDC method.

[0006] Typical traditional virtual impedance droop control methods use PI control and only consider the characteristic relationships between active power - frequency (P - f) and reactive power - voltage (Q - U). When this method is in the steady state of a parallel system, a unified modulation means can be used to distribute the active power of the load. However, due to the differences in the output impedance of each phase inverter itself and the line transmission impedance, although the virtual impedance is "connected in series" with the inverter output impedance, reducing the resistive influence of the transmission line, the reactive power of the load still cannot be accurately distributed. This method has unstable output voltage, slow output voltage response speed, low output frequency accuracy, fixed virtual impedance, and poor suppression performance for phase - inner circulating current. Therefore, there is an urgent need to develop more advanced control strategies.

[0007] 3. Solve the problem of phase - inner circulating current caused by asynchronous inverter switching and inconsistent control.

[0008] In a parallel inverter system, traditional SVPWM evenly distributes zero - voltage vectors into each voltage vector synthesis. However, due to the asynchronous duty cycles of the switching signals of each phase inverter bridge arm or control errors, zero - sequence voltage will be generated, and this deviation will form a circulating current path within the phase. This phase - inner circulating current will not only increase the losses of inverter components but also cause the temperature rise and heating of the equipment, thereby shortening the service life of the equipment. In addition, it will also affect the power quality and conversion efficiency of the microgrid output side. The traditional SVPWM method cannot solve this problem and needs to be improved. Summary of the Invention

[0009] In view of the above - mentioned technical problems, the present invention provides a sliding - mode optimization control method and system for a three - phase inverter parallel system considering inter - phase and phase - inner circulating currents.

[0010] A sliding - mode optimization control method for a three - phase inverter parallel system considering inter - phase and phase - inner circulating currents according to the present invention includes the following steps:

[0011] Step 1: Design a robust droop sliding - mode control controller, which includes a bus - voltage - following sliding - mode control, a Q - U loop voltage - response sliding - mode control, a P - f loop frequency - response sliding - mode control, and an adaptive virtual reactance regulator;

[0012] Step 2: Design a zero - sequence voltage sliding - mode control suppressor and introduce a regulation factor k m to control the action time of the control vector synthesis.

[0013] Further, in Step 1, the specific method for establishing the bus - voltage - following sliding - mode control model is as follows:

[0014] Design the sliding - mode strategy as follows:

[0015]

[0016] where: x U is the system state variable; Us is the bus voltage; U N is the rated voltage; S U is the sliding mode surface; c U1 > 0 is the proportional regulation parameter; c U2 > 0 is the integral regulation parameter; u U is the control law; ε U > 0, k U > 0 are the exponential reaching law design parameters.

[0017] The time t required for the system to reach the sliding mode surface S U = 0 is: U as follows:

[0018]

[0019] where: S U (0) is the initial state of S U .

[0020] Construct the Lyapunov equation V U = 0.5S U 2 , and its first derivative is expressed as:

[0021]

[0022] Furthermore, in step one, the method for establishing the Q-U loop voltage response sliding mode control model is:

[0023] Design the sliding mode strategy as follows:

[0024]

[0025] where: x E is the state variable; U s ' is the bus voltage adjustment output value; U Qm is the Q-U loop output voltage value; S E is the sliding mode surface; c E1 > 0 is the proportional term coefficient; c E2 > 0 is the integral term coefficient; u E is the control law; ε E > 0, k E > 0 are the improved reaching law design parameters.

[0026] Construct the Lyapunov equation V E = 0.5S E 2 , and its first derivative is expressed as:

[0027]

[0028] The improved Q-U loop control equation is as follows:

[0029]

[0030] Where: U N and Q Nm represent the voltage and reactive power of each phase shunt inverter respectively; U m and Q m represent the actual output of the m-th phase inverter; N m is the voltage droop coefficient of the m-th phase inverter.

[0031] Furthermore, in step one, the method for establishing the P-f loop frequency response sliding mode control model is as follows:

[0032] Design the sliding mode strategy as follows:

[0033]

[0034] Where x f is the state variable; f s is the output frequency of the parallel system; f N is the rated frequency; S f is the sliding mode surface; c f1 > 0 is the proportional term coefficient; c f2 > 0 is the integral term coefficient; u f is the control law; ε f > 0, k f > 0 are the reaching law design parameters.

[0035] Construct the Lyapunov equation V f = 0.5S f 2 , and its first derivative is expressed as:

[0036]

[0037] The improved P-f loop control equation is as follows:

[0038]

[0039] Where: f N and P Nm represent the rated output frequency and active power of each phase shunt inverter respectively; f m and P m represent the actual output of the m-th phase inverter; M m is the frequency droop coefficient of the m-th phase inverter.

[0040] Furthermore, in step one, the improved Q-U loop and P-f loop control equations adjust the distribution of the system output power as follows:

[0041] When the system operates in a steady state, it can be obtained that:

[0042]

[0043] In the formula: ΔP m = P m - P Nm , ΔQ m = Q m - Q Nm , Δf s = f s - f N , ΔU s = U s - U N .

[0044] Set the parameters of each-phase inverter c f1 , c f2 , c E1 , c E2 to be the same, and it can be obtained that:

[0045]

[0046] Define the measurement error of the RMS value of the output voltage of the m-phase inverter as ΔU sm ', and the resulting reactive power error ΔQ m ' is:

[0047]

[0048] Furthermore, the RMS measurement error of the voltage value ΔU s ' = ΔU s1 '- ΔU s2 '(N1 = N2) causes the reactive power error e Q :

[0049]

[0050] Furthermore, in step one, the method for establishing the adaptive virtual reactance regulator model is:

[0051] Design the sliding mode strategy as follows:

[0052]

[0053] In the formula, x c is the state variable; i okm is the system output current; i sk is the grid-side current; S c is the sliding mode surface; c c1 > 0 is the proportional term coefficient; X virm is the fixed reactance; c c2>0 is the integral term coefficient, and the initial value is X virm (0); u c is the control law; ε c >0, k c >0 are the reaching law design parameters.

[0054] Construct the Lyapunov equation V c = 0.5S c 2 , and its first derivative is expressed as:

[0055]

[0056] X virm The change of causes the reactive power Q m of the system output to change:

[0057]

[0058] In the formula: U virm is the voltage drop generated on X virm ; U Qm represents the output voltage value of the Q-U loop; U virm along U Qm direction can be decomposed into ΔU virm and sinψ·U refm ', U refm ' is the droop loop given voltage after introducing X virm . Since ψ is small, it is considered that U virm ≈ΔU virm .

[0059] Furthermore, in step one, the method for establishing the adaptive virtual reactance regulator model further includes:

[0060] When the parallel system is in steady-state operation, it is considered that U Qm is the actual output voltage value U m of the inverter. After introducing X virm , the Q-U loop control equation is:

[0061]

[0062] In the formula: N virm = X virm / U Qm represents the droop voltage coefficient of X virm . The above control loop has a droop limit. Therefore, according to the output characteristics of the inverter, the maximum output voltage distortion rate γ% and the maximum output reactive power Q max can be set. From this, we can get:

[0063]

[0064] It can be sorted out to get X virm The adjustment upper limit is:

[0065]

[0066] Furthermore, in step two, the method for establishing the zero-sequence voltage sliding mode control suppressor model is as follows:

[0067] Introduce the zero-sequence voltage k m After modulation, the duty cycle of the control signal on each bridge arm of the inverter is:

[0068]

[0069] In the formula: d km represents the duty cycle of the control signal on each bridge arm of the inverter; T c represents the control period; d 0m represents the zero-vector duty cycle; d 1m , d 2m represent the duty cycles of the non-zero vectors 100 and 110, and satisfy d 0m +d 1m +d 2m =1; Denote d 0m T c =t 0m , d 1m T c =t 1m , d 2m T c =t 2m . The expression of the zero-sequence duty cycle d zm can be obtained:

[0070]

[0071] The switching time of the synthesized vector of the three-phase bridge arm after adjustment is:

[0072]

[0073] In the formula: T Skm represents the switching time of each bridge arm vector; T Skm ' is the vector action time after adjustment; k m takes values in the range of [-d 0m / 4, d 0m / 4].

[0074] The formula for the in-phase loop current of the parallel system after adjustment is:

[0075]

[0076] In the formula: i z is the in-phase loop current; U dcis a DC voltage; L fkm 、L lkm 、R lkm respectively represent the filter inductance of each phase of the inverter, the transmission line inductance and the transmission line resistance; L eqkm =L fkm1 +L fkm2 +L lkm represents the equivalent inductance of the k-phase transmission line in the m-phase inverter.

[0077] Furthermore, in step two, the method for establishing the zero-sequence voltage sliding mode control suppressor model further includes:

[0078] Design the sliding mode strategy as follows:

[0079]

[0080] where: x z is the state variable; S z is the sliding mode surface; c z1 >0, c z2 >0 are the sliding mode surface design parameters; u z is the control law; ε z >0, k z >0 are the reaching law design parameters.

[0081] Construct the Lyapunov equation V z =0.5S z 2 , and its first derivative is expressed as:

[0082]

[0083] The present invention also relates to a sliding mode optimization control system for a three-phase inverter parallel system considering inter-phase and intra-phase circulating currents, including a computer module, and the computer module uses the sliding mode optimization control method for the three-phase inverter parallel system considering inter-phase and intra-phase circulating currents.

[0084] Beneficial effects

[0085] (1) The sliding mode optimization control method for the three-phase inverter parallel system considering inter-phase and intra-phase circulating currents of the present invention solves the problem of poor performance caused by the PI control method in the inter-phase circulating current model and improves the performance of the intra-phase circulating current model. Compared with the PI control, the sliding mode control has stronger robustness, can maintain stability under system parameter changes and external disturbances, and at the same time has a faster dynamic response and can effectively cope with rapid disturbances. In addition, the sliding mode control is good at dealing with nonlinear and time-varying characteristics, is suitable for complex systems, and has the ability to suppress high-frequency oscillations, which can greatly improve the system performance.

[0086] (2) The sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and intra-phase circulating currents of the present invention designs a robust droop sliding mode control controller to effectively suppress the inter-phase circulating current. Compared with the traditional VIDC method, the robust droop sliding mode control controller is designed from four aspects: bus voltage following sliding mode control, Q-U loop voltage response sliding mode control, P-f loop frequency response sliding mode control, and adaptive virtual reactance regulator. Specifically, the bus voltage following sliding mode control can provide a stable reference voltage for the Q-U loop voltage response sliding mode control; the Q-U loop voltage response sliding mode control can improve the accuracy and response speed of the output voltage; the P-f loop frequency response sliding mode control can improve the accuracy and response speed of the output frequency; and the adaptive virtual reactance regulator provides the required inductive impedance condition for the Q-U loop voltage response sliding mode control. Compared with the traditional VIDC controller, the improved droop sliding mode control controller has stronger robustness, effectively suppressing the generation of inter-phase circulating current while improving the system power distribution accuracy.

[0087] (3) The sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and intra-phase circulating currents of the present invention designs a zero-sequence voltage sliding mode control suppressor to effectively suppress the intra-phase circulating current. The regulation factor k m is introduced to control the action time of each vector synthesis, making the switching actions of the corresponding phase bridge arms consistent, eliminating the zero-sequence voltage, indirectly suppressing the intra-phase circulating current, and improving the stability of the system. Brief Description of the Drawings

[0088] Figure 1 It is a schematic diagram of the parallel three-phase inverter system in the present invention.

[0089] Figure 2 It is a frame diagram of the improved control scheme for the phase circulating current composite suppression strategy in the present invention.

[0090] Figure 3 It is a structural diagram of the robust droop sliding mode control controller in the present invention.

[0091] Figure 4 It is a schematic diagram of the virtual impedance voltage drop vector in the present invention.

[0092] Figure 5 It is a schematic diagram of the SVPWM voltage vector sector division in the present invention.

[0093] Figure 6 It is a schematic diagram of the modulation signal of the traditional SVPWM in the first sector in the present invention.

[0094] Figure 7 It is for the present invention to introduce k m The schematic diagram of the modulation signal of the SVPWM in the first sector after that.

[0095] Figure 8This is the model diagram of the zero-sequence voltage sliding mode control suppressor in the present invention.

[0096] Figure 9 This is the control block diagram of the composite suppression strategy for the phase circulating current in the parallel inverter system of the present invention.

[0097] Figure 10(a) is the output performance diagram of the parallel system with the same capacity and line parameters in the present invention (the active power P output by each-phase inverter m ).

[0098] Figure 10(b) is the output performance diagram of the parallel system with the same capacity and line parameters in the present invention (the output frequency f of the P-f loop of each-phase inverter m ).

[0099] Figure 10(c) is the output performance diagram of the parallel system with the same capacity and line parameters in the present invention (the reactive power Q output by each-phase inverter m ).

[0100] Figure 10(d) is the output performance diagram of the parallel system with the same capacity and line parameters in the present invention (the output voltage amplitude U of the Q-U loop of each-phase inverter m ).

[0101] Figure 10(e) is the output performance diagram of the parallel system with the same capacity and line parameters in the present invention (the inter-phase circulating current i of the parallel system c ).

[0102] Figure 10(f) is the output performance diagram of the parallel system with the same capacity and line parameters in the present invention (the intra-phase circulating current i of the parallel system zm ).

[0103] Figure 11(a) is the output performance diagram of the parallel system with the same capacity and perturbed line parameters in the present invention (the active power P output by each-phase inverter m ).

[0104] Figure 11(b) is the output performance diagram of the parallel system with the same capacity and perturbed line parameters in the present invention (the reactive power Q output by each-phase inverter m ).

[0105] Figure 11(c) is the output performance diagram of the parallel system with the same capacity and perturbed line parameters in the present invention (the inter-phase circulating current i of the parallel system c ).

[0106] Figure 11(d) is the output performance diagram of the parallel system with the same capacity and perturbed line parameters in the present invention (the intra-phase circulating current i of the parallel system zm ).

[0107] Figure 11(e) is the output performance diagram of the parallel system with the same capacity and disturbed line parameters in the present invention (virtual inductive reactance X virm ).

[0108] Figure 11(f) is the output performance diagram of the parallel system with the same capacity and disturbed line parameters in the present invention (regulation factor k1). Detailed implementation manners

[0109] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0110] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other. The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but it is not limited to the present invention.

[0111] A sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and phase-internal circulating currents in the present invention includes a robust droop sliding mode control controller and a zero-sequence voltage sliding mode control suppressor. The structure of the studied parallel three-phase inverter is as Figure 1 shown.

[0112] Step 1: Design a robust droop sliding mode control controller, which includes a bus voltage following sliding mode control, a Q-U loop voltage response sliding mode control, a P-f loop frequency response sliding mode control, and an adaptive virtual inductive reactance regulator;

[0113] From Figure 2 The designed robust droop sliding mode control structure is as Figure 3 shown, and the specific design of the robust droop sliding mode control in Figure 3 is carried out. In the figure: f N , U N , P Nm , Q Nm respectively represent the rated output frequency, voltage, active power, and reactive power of each phase of the parallel inverter; f m , U m , P m , Q m represent the actual output quantities of the m-th phase inverter; f s , f N represent the output frequency and the rated frequency; i sa , i oam represent the grid-side current and the system output current; U s , U s ', UQm respectively represent the bus voltage, the adjusted output value of the bus voltage, and the output voltage of the Q-U loop; M m , N m are the frequency and voltage droop coefficients of the m-phase inverter. U refm , U refm ' are the output voltage and the given voltage of the droop loop after introducing X virm ; X virm , u virm are the fixed inductive reactance and the fixed voltage drop.

[0114] Step 1: The design of the bus voltage following sliding mode control model is as follows:

[0115] First, design the sliding mode strategy as follows:

[0116]

[0117] In the formula: x U is the system state variable; S U is the sliding mode surface; c U1 > 0 is the proportional adjustment parameter; c U2 > 0 is the integral adjustment parameter; u U is the control law; ε U > 0, k U > 0 are the design parameters of the exponential reaching law.

[0118] According to the sliding mode surface derivative formula, the time t U required for the linear sliding mode system to reach the sliding mode surface S U = 0 from the initial voltage state is:

[0119]

[0120] In the formula: S U (0) is the initial state of S U ; construct the Lyapunov equation V U = 0.5S U 2 , and its first derivative is expressed as:

[0121]

[0122] Step 2: The design of the Q-U loop voltage response sliding mode control model is as follows:

[0123] Design the sliding mode strategy as follows:

[0124]

[0125] In the formula: x E is the state variable; S E is the sliding mode surface; cE1 > 0 is the proportional term coefficient; c E2 > 0 is the integral term coefficient; u E is the control law; ε E > 0, k E > 0 are the design parameters of the improved reaching law.

[0126] Construct the Lyapunov equation V E = 0.5S E 2 Its first derivative is expressed as:

[0127]

[0128] The improved Q-U loop control equation is:

[0129]

[0130] In the formula: N m is the voltage droop coefficient of the m-th phase inverter.

[0131] Steps One and Three. The P-f loop frequency response sliding mode control model design and the improved Q-U loop and P-f loop control equations adjust the distribution of the system output power as follows:

[0132] Design the sliding mode strategy as follows:

[0133]

[0134] In the formula, x f is the state variable; S f is the sliding mode surface; c f1 > 0 is the proportional term coefficient; c f2 > 0 is the integral term coefficient; u f is the control law; ε f > 0, k f > 0 are the reaching law design parameters;

[0135] Construct the Lyapunov equation V f = 0.5S f 2 Its first derivative is expressed as:

[0136]

[0137] Referring to Equation (6), the improved P-f loop control equation is:

[0138]

[0139] In the formula: M m is the frequency droop coefficient of the m-th phase inverter.

[0140] When the system operates in a steady state, it can be obtained that:

[0141]

[0142] Where: ΔP m = P m - P Nm 、ΔQ m = Q m - Q Nm 、Δf s = f s - f N 、ΔU s = U s - U N .

[0143] It can be seen from Equation (10) that for the parallel system in operation, setting the parameters c f1 、c f2 、c E1 、c E2 of each phase inverter to be the same, it can be obtained that:

[0144]

[0145] Define the measurement error of the RMS value of the output voltage of the m-th phase inverter as ΔU sm ', and the reactive power error ΔQ m ' caused by it is:

[0146]

[0147] From Equation (13), the RMS measurement error ΔU s ' = ΔU s1 '-ΔU s2 ' (N1 = N2) can be further obtained to cause the reactive power error e Q . When measuring the RMS value of the voltage at the same point on the AC bus, the error voltage ΔU s ' = 0.

[0148]

[0149] Step 14. The design of the adaptive virtual reactance regulator model is as follows:

[0150] Design the sliding mode strategy as follows:

[0151]

[0152] Where, x c is the state variable; S c is the sliding mode surface; c c1 > 0 is the proportional term coefficient; c c2> 0 is the integral term coefficient, and its initial value is X virm (0); u c is the control law; ε c > 0, k c > 0 are the reaching law design parameters;

[0153] Figure 4 is X virm is the voltage drop vector diagram generated on X. In the figure: ψ represents the phase difference between U virm after adding X refm ' and U Qm ; U virm along the direction of U Qm can be decomposed into ΔU virm and sinψ·U refm ', U refm ' is the droop loop given voltage after introducing X virm . Since ψ is small, it can be considered that U virm ≈ΔU virm .

[0154] Construct the Lyapunov equation V c = 0.5S c 2 , and its first derivative is expressed as:

[0155]

[0156] X virm 's change causes the change of the system output reactive power Q m :

[0157]

[0158] When the parallel system operates in a steady state, it is considered that U Qm is the actual output voltage value U m of the inverter. Combining Equation (16) with the Q-U loop control equation (6), the Q-U loop control equation after introducing X virm can be obtained as:

[0159]

[0160] In the formula: N virm = X virm / U Qm represents the droop voltage coefficient of X virm ;

[0161] The control loop of Equation (17) has a droop limit. Therefore, according to the output characteristics of the inverter, the maximum output voltage distortion rate γ% and the maximum output reactive power Q max can be set, and thus:

[0162]

[0163] X can be obtained virm The adjustment upper limit is:

[0164]

[0165] Step 2: Design a zero-sequence voltage sliding-mode control suppressor and introduce an adjustment factor k m The action time of the control vector synthesis

[0166] The method for establishing the zero-sequence voltage sliding-mode control suppressor model is as follows:

[0167] The parallel inverter adopts Figure 5 the SVPWM shown to generate the control signal. Compared with Figure 6 Figure 7 After introducing the zero-sequence voltage k m in modulation, the duty cycle of the control signal on each bridge arm of the inverter is:

[0168]

[0169] In the formula: d km represents the duty cycle of the control signal on each bridge arm of the inverter; T c represents the control period; d 0m represents the zero-vector duty cycle; d 1m 、d 2m represent Figure 5 the duty cycles of the non-zero vectors u s4 and u s6 in 0m +d 1m +d 2m =1; Denote d 0m T c =t 0m 、d 1m T c =t 1m 、d 2m T c =t 2m .

[0170] The expression of the zero-sequence duty cycle d zm can be obtained:

[0171]

[0172] The switching time of the synthesized vector of the three-phase bridge arm after adjustment is:

[0173]

[0174] In the formula: T Skm represents the switching time of each bridge arm vector; T Skm ​' is the adjusted vector action time; k m The value range of 0m is [-d 0m / 4, d Figure 8 . It is controlled by

[0175] The formula for the in-phase internal loop current of the adjusted parallel system is:

[0176]

[0177] In the formula: i z is the in-phase internal loop current; U dc is the DC voltage; L fkm , L lkm , R lkm respectively represent the filter inductance of each phase of the inverter, the transmission line inductance, and the transmission line resistance; L eqkm = L fkm1 +L fkm2 +L lkm represents the equivalent inductance of the k-phase transmission line in the m-phase inverter.

[0178] Design the sliding mode strategy as follows:

[0179]

[0180] In the formula: x z is the state variable; S z is the sliding mode surface; c z1 >0, c z2 >0 are the design parameters of the sliding mode surface; u z is the control law; ε z >0, k z >0 are the design parameters of the reaching law;

[0181] Construct the Lyapunov equation V z = 0.5S z 2 , and its first derivative is expressed as:

[0182]

[0183] Effect verification:

[0184] Next, the suppression effect of the present invention on the in-phase internal loop current will be verified by simulation. Taking the two-phase parallel three-phase inverter system as an example, simulation experiments with 2 working conditions are designed, and the superior performance of the in-phase internal loop current composite suppression strategy when applied to parallel inverters is compared and analyzed. The system circuit parameters are shown in Table 1 below. The control system structure of the in-phase internal loop current composite suppression strategy is as Figure 9As shown (here, a zero-sequence voltage sliding mode control suppressor is added to the first-phase inverter of the parallel system). To ensure the reliability of the verification results, the same voltage-current double closed-loop control structure is adopted for both strategies. The controller parameters of the phase circulating current composite suppression strategy are shown in Table 2.

[0185] 1. Condition 1: The parallel system has the same capacity and line parameters

[0186] Set the capacities and line parameters of the two-phase parallel inverters to be the same, and verify the system power and circulating current performance when the load power changes. Simulation process: At t = 0, set the load power to be the same as the rated power; at t = 0.15 s, P L = 8 kW, Q L = 800 var; at t = 0.3 s, P L = 4 kW, Q L = 400 var. The simulation results are shown in Figure 10 and Table 3.

[0187] Figure 10(a) shows the active power P m output by the parallel system. In terms of dynamic performance, the initial convergence time of the P mCS curve is reduced by 66.7% compared to P mVI , and the maximum overshoot of P mCS is controlled within 6.6%, which is reduced by 21.7% compared to P mVI , ensuring the smoothness of the active power output; when the load power changes, the response time of P mCS is reduced by 58.8% compared to P mVI , which benefits from the fast switching response characteristic of the sliding mode control controller designed in the present invention.

[0188] Table 1 Circuit parameters of the parallel inverter system

[0189]

[0190] Table 2 Controller parameters of the phase circulating current composite suppression strategy

[0191]

[0192] In terms of static performance, the average steady-state error of P mCS is only 19.7 W, which is reduced by 84.8% compared to P mVI , improving the accuracy of the active power distribution output. In Figure 10(b), the output frequency f m of the P-f loop corresponds to the change of P m , where the response time and steady-state error of f mCS are reduced by 54.6% and 9.1% compared to f mCS , which benefits from the fast following performance of the sliding mode control in Equation (7).

[0193] Figure 10(c) shows the reactive power Q output by the parallel system m curve. The Q mCS curve quickly stabilizes within 0.015 s with a maximum overshoot of 39.4%, and is reduced by 72.2% and 49.5% respectively compared to Q mVI ; when following the load power, the average steady-state error of Q mCS is only 25.362 var, which is reduced by 37.3% compared to Q mVI . This is due to the stable regulation of the output voltage amplitude U m in the Q-U loop in Figure 10(d). As can be seen from Figure 10(d), at t = 0.15 s, U mVI suddenly increases with the increase of Q L , and Q mVI produces large fluctuations and the equalization effect deteriorates. However, U mCS remains stable under the robust action of Equation (1), slowing down the fluctuations of Q mCS ; at t = 0.3 s, U mVI suddenly drops due to the decrease of Q L , Q mVI fluctuates greatly, while U mCS ensures the smoothness of Q mCS under the action of Equation (1). Thanks to the designed voltage response sliding mode control in Equation (4), the average response time of U mCS is reduced by 33.3%. This shows that the phase circulating current composite suppression strategy can overcome the limitations of the traditional VIDC and achieve precise distribution of the reactive power output by the parallel system.

[0194] Table 3 Comparison of control performances of VIDC and phase circulating current composite suppression strategy under Condition 1

[0195]

[0196] Due to the excellent performance of the power curves in Figures 10(a) and 10(c), the inter-phase circulating current i cCS in the parallel system in Figure 10(e) is only 0.191 A, which is reduced by 80.6% compared to i cVI ; similarly, under the action of the zero-sequence voltage sliding mode control suppressor in Equation (24), the in-phase circulating current i zmCS in the parallel system in Figure 10(f) is only 0.093 A, which is reduced by 88.1% compared to i zmVI . This proves that the proposed phase circulating current composite suppression strategy can effectively suppress the phase circulating current of the parallel system under the condition of load power change.

[0197] 2. Condition 2: The parallel system has the same capacity and the line parameters are disturbed

[0198] To highlight the differences in the transmission line parameters of the parallel system before and after being disturbed, a disturbance is only added to the transmission line of the first-phase inverter here. Simulation process: At t = 0, Z l1 is the same as that in Table 1; at t = 0.15 s, Z l1 = 0.051 + j0.116 Ω / km; at t = 0.3 s, Z l1 = 0.202 + j0.462 Ω / km, and the output changes of the system are observed from this. The simulation results are shown in Figure 11 and Table 4.

[0199] As can be seen from the active power P m shown in Figure 11(a), after the two parameter disturbances, due to the imbalance of the parallel system line parameters, P mVI and P mCS fluctuate significantly. Combining Table 3 and Table 4, it can be known that the maximum disturbance error of P mVI is 225.324 W, and its steady-state error increases by 13.7% compared with that before the line parameter change; while the maximum disturbance error of P mCS is only 1 / 5 of P mVI , its steady-state error only increases by 11.9%, and the disturbance recovery time is reduced by 66.7% compared with P mVI .

[0200] In Figure 11(b), the maximum error and steady-state error of the reactive power Q m after being disturbed are reduced by 51.7% and 41.7% respectively compared with Q mVI , and the disturbance recovery time is reduced by 68.6%. Figure 11(a) And 11(b) the output power in is accurately distributed, further ensuring the efficient suppression of the inter-phase circulating current under the disturbance condition.

[0201] In Figure 11(c), i cCS is more stable after the line parameters are disturbed. Combining Table 4, it can be known that its steady-state error is 0.491 A, which is reduced by 54.7% compared with i cVI . This not only depends on the strong robustness of the sliding mode control, but also benefits from the adaptive regulation of X virmCS in Figure 11(e). Before the Z l1 disturbance, X virmCS is slightly adjusted under the control of Equation (14); when Z l1 is disturbed, the adjustment amplitude of X virmCS increases significantly, ensuring the stable change of i cCS in Figure 11(c), and the adjustment amplitude of X virmCS during the whole process is within the limit of X virmMAX , meeting the design requirements in Table 1.

[0202] Figure 11(d) shows the phase inner loop circulating current i zm . It can be seen that izmCS At Z l1 After being disturbed, it is more stable than i zmVI This depends on the adjustment factor k1 in Fig. 11(f), which has an increased amplitude change at Z l1 After being disturbed, rapidly eliminates the zero-sequence voltage, and enhances the suppression of i zmCS .

[0203] This proves that the designed phase circulating current composite suppression strategy can ensure the strong robustness of the parallel system under the condition of transmission line disturbance, reduce the output power error of the parallel system, and effectively suppress the phase circulating current while doing so.

[0204] Table 4 Comparison of control performance between VIDC and phase circulating current composite suppression strategy under Condition 2

[0205]

[0206] Although the present invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed, as long as they do not depart from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the features described in the different dependent claims and in the present document can be combined in ways different from those described in the original claims. It should also be understood that the features described in connection with a single embodiment can be used in other described embodiments.

Claims

1. A sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and phase-internal circulating currents, characterized in that It includes the following steps: Step 1: Design a robust droop sliding mode control controller, which includes bus voltage following sliding mode control, Q-U loop voltage response sliding mode control, P-f loop frequency response sliding mode control, and an adaptive virtual reactance regulator; Step 2: Design a zero-sequence voltage sliding-mode controller and introduce an adjustment factor k m Control the action time of vector synthesis In Step 1, the specific method for establishing the bus voltage following sliding mode control model is as follows: Design the sliding mode strategy as follows: where: x U is the system state variable; U s is the bus voltage; U N is the rated voltage; S U is the sliding mode surface; c U1 > 0 is the proportional regulation parameter; c U2 > 0 is the integral regulation parameter; u U is the control law; ε U > 0, k U > 0 are the exponential reaching law design parameters; The time t required for the system to reach the sliding mode surface S from the initial voltage state U = 0 U is as follows: Where: S U (0) is the initial state of S U Construct the Lyapunov equation V U = 0.5S U 2 , and its first derivative is expressed as: The method for establishing the Q-U loop voltage response sliding mode control model is: Design the sliding mode strategy as follows: where: x E is the state variable; U s ' is the output value of the bus voltage adjustment; U Qm is the output voltage value of the Q-U loop; S E is the sliding mode surface; c E1 > 0 is the proportional term coefficient; c E2 > 0 is the integral term coefficient; u E is the control law; ε E > 0, k E > 0 are the design parameters of the improved reaching law; Construct the Lyapunov equation V E = 0.5S E 2 , and its first derivative is expressed as: The improved Q-U loop control equation is: Where: U N , Q Nm respectively represent the voltage and reactive power of each phase parallel inverter; U m , Q m represent the actual output of the m-th phase inverter; N m is the voltage droop coefficient of the m-th phase inverter; The method for establishing the P-f loop frequency response sliding mode control model is: Design the sliding mode strategy as follows: where x f is the state variable; f s is the output frequency of the parallel system; f N is the rated frequency; S f is the sliding mode surface; c f1 > 0 is the proportional term coefficient; c f2 > 0 is the integral term coefficient; u f is the control law; ε f > 0, k f > 0 are the reaching law design parameters; Construct the Lyapunov equation V f = 0.5S f 2 , and its first derivative is expressed as: The improved P-f loop control equation is: where: s represents the Laplace complex frequency variable; f N , P Nm respectively represent the rated output frequency and active power of each phase parallel inverter; f m , P m represent the actual output of the m-th phase inverter; M m is the frequency droop coefficient of the m-th phase inverter; The method for establishing the adaptive virtual reactance regulator model is: Design the sliding mode strategy as follows: where x c is the state variable; i okm is the system output current; i sk is the grid-side current; S c is the sliding mode surface; c c1 > 0 is the proportional term coefficient; X virm is the fixed inductive reactance; c c2 > 0 is the integral term coefficient, and the initial value is X virm (0); u c is the control law; ε c > 0, k c > 0 are the reaching law design parameters; Construct the Lyapunov equation V c = 0.5S c 2 , and its first derivative is expressed as: X virm The change in m causes a change in the reactive power Q output by the system, and we can obtain: Where: U virm is the voltage drop generated on X virm ; U Qm represents the Q-U loop output voltage value; U virm Along U Qm the direction can be decomposed into ΔU virm and sinψ·U refm ', U refm ' is the given voltage of the droop loop after introducing X virm Since ψ is extremely small, it can be considered that U virm ≈ΔU virm .

2. The sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and in-phase circulating currents according to claim 1, wherein In Step 1, the improved Q-U loop and P-f loop control equations adjust the distribution of the system output power as follows: When the system operates in a steady state, it can be obtained that: where: ΔP m = P m - P Nm , ΔQ m = Q m - Q Nm , Δf s = f s - f N , ΔU s = U s - U N ; Set the parameters c of each phase inverter f1 , c f2 , c E1 , c E2 to be the same, we can obtain: Define the measurement error of the RMS value of the output voltage of the m - phase inverter as ΔU sm ', and the reactive power error ΔQ m ' generated is as follows: Further obtain the RMS measurement error ΔU of the voltage value s ' = ΔU s1 '- ΔU s2 ' (N1 = N2) caused reactive power error e Q is:

3. The sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and in-phase circulating currents according to claim 1, wherein, In Step 1, the method for establishing the adaptive virtual reactance regulator model further includes: When the parallel system operates in a steady state, it is considered that U Qm is the actual output voltage value U m of the inverter. After introducing X virm , the Q-U loop control equation is as follows: Where: N virm = X virm / U Qm represents the sag voltage coefficient of X virm ; there is a sag limit in the above control loop, so the maximum output voltage distortion rate γ% and the maximum output reactive power Q max can be set according to the inverter output characteristics. From this, we can obtain: It can be sorted out to get X virm The adjustment upper limit is:

4. The sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and in-phase circulating currents according to claim 1, characterized in that, In Step 2, the method for establishing the zero-sequence voltage sliding mode control suppressor model is: Introduce zero-sequence voltage k m After modulation, the duty cycle of the control signals on each bridge arm of the inverter is as follows: Where: d km (k = a, b, c) represents the duty cycle of the control signals on each bridge arm of the inverter; T c represents the control period; d 0m represents the zero-vector duty cycle; d 1m , d 2m represent the duty cycles of non-zero vectors 100 and 110, and satisfy d 0m + d 1m + d 2m = 1; t 0m = d 0m T c 、t 1m = d 1m T c 、t 2m = d 2m T c ; The zero-sequence duty cycle d zm can be obtained as follows: The switching time of the synthesized vector of the three-phase bridge arm after adjustment is: Where: T Skm represents the switching time of each bridge arm vector; T Skm ' is the action time of the adjusted vector; k m ranges from [-d 0m / 4, d 0m / 4]; The formula for the in-phase circulating current in the parallel system after adjustment is: where: i z is the internal phase circulation; U dc is the DC voltage; L fkm , L lkm , R lkm respectively represent the filter inductance of each phase of the inverter, the transmission line inductance, and the transmission line resistance; L eqkm = L fkm1 + L fkm2 + L lkm represents the equivalent inductance of the k-phase transmission line in the m-phase inverter.

5. The sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and in-phase circulating currents according to claim 4, characterized in that, In Step 2, the method for establishing the zero-sequence voltage sliding mode control suppressor model further includes: Design the sliding mode strategy as follows: where: x z is the state variable; S z is the sliding surface; c z1 > 0, c z2 > 0 are the sliding surface design parameters; u z is the control law; ε z > 0, k z > 0 are the reaching law design parameters; Construct the Lyapunov equation V z = 0.5S z 2 , and its first derivative is expressed as:

6. A sliding mode optimization control system for a three-phase inverter parallel system considering inter-phase and intra-phase circulating currents, characterized in that, It includes a computer module, and the computer module uses the sliding mode optimization control method for a three-phase inverter parallel system considering inter-phase and in-phase circulating currents according to any one of claims 1 to 5 above.

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