Radio frequency mixer with shared bias current

Abstract

The invention relates to a radio frequency mixer with shared bias current. An electronic device may include wireless circuitry having a mixer. The mixer may include a transconductor having a first input transistor and a second input transistor; a switching four-channel having a first pair of mixer transistors and a second pair of mixer transistors; and a transformer coupled between the transconductor and the switching four-channel. The transformer may have a primary winding and a secondary winding. The transformer may have a conductive path that couples a center tap contact of the primary winding to a center tap contact of the secondary winding. The conductive path may configure the transformer to share a DC bias current between the transconductor and the switching four-channel. This may eliminate the need to use different supply voltages to bias the transconductor and the switching four-channel, thereby minimizing power consumption without sacrificing performance.

Description

[0001] This application claims priority to U.S. patent application No. 18 / 361,302, filed on July 28, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to electronic devices, including electronic devices having wireless communications circuitry. Background Art

[0003] An electronic device may have wireless communication capabilities. An electronic device with wireless communication capabilities has wireless communication circuitry that has one or more antennas. The wireless communication circuitry uses the antennas to receive and transmit radio frequency signals.

[0004] Wireless communication circuits may include a transceiver having one or more mixers. A mixer may be used to modulate a signal from a first frequency to a second frequency. It may be challenging to design a mixer that exhibits adequate performance levels while minimizing power consumption of the wireless communication circuit. Summary of the invention

[0005] An electronic device may include wireless circuitry. The wireless circuitry may include one or more mixers that receive an oscillating signal. The mixer may be a radio frequency transmit mixer or a radio frequency receive mixer. A local oscillator may generate the oscillating signal. The mixer may be a transformer-based mixer that exhibits improved linearity.

[0006] The mixer may include: a transconductor including a first input transistor and a second input transistor; a switching quad including a first pair of mixer transistors and a second pair of mixer transistors; and a transformer coupled between the transconductor and the switching quad. The transformer may have a primary winding and a secondary winding. The transformer may have a conductive path that couples a center tap contact of the primary winding to a center tap contact of the secondary winding. The conductive path may configure the transformer to share a DC bias current between the transconductor and the switching quad. This may eliminate the need to use different supply voltages to bias the transconductor and the switching quad, thereby minimizing power consumption without sacrificing performance.

[0007] One aspect of the present disclosure provides a mixer circuit. The mixer circuit may include a transformer having a first winding and a second winding. The mixer circuit may include a first input transistor, the first input transistor coupled to a first terminal of the first winding and configured to receive an input signal. The mixer circuit may include a second input transistor, the second input transistor coupled to a second terminal of the first winding and configured to receive an input signal. The mixer circuit may include a first pair of mixer transistors, the first pair of mixer transistors coupled to a first terminal of the second winding and configured to receive an oscillation signal. The mixer circuit may include a second pair of mixer transistors, the second pair of mixer transistors coupled to a second terminal of the second winding and configured to receive an oscillation signal. The mixer circuit may include a conductive path, the conductive path coupling a center tap contact of the first winding to a center tap contact of the second winding.

[0008] One aspect of the present disclosure provides a mixer circuit. The mixer circuit may include a transconductor. The mixer circuit may include a mixer transistor. The mixer circuit may include a transformer that couples an output of the transconductor to an input of the mixer transistor. The transformer may include a first coil having a first center tap contact. The transformer may include a second coil that is magnetically coupled to the first coil, the second coil having a second center tap contact that is coupled to the first center tap contact via a conductive path.

[0009] One aspect of the present disclosure provides an electronic device. The electronic device may include an antenna. The electronic device may include a transceiver configured to transmit a radio frequency signal using an antenna. The transceiver may include a first pair of transistors having a first gate terminal configured to receive an input signal and having a first source-drain terminal. The transceiver may include a second pair of transistors having a second gate terminal configured to receive a local oscillator (LO) signal and having a second source-drain terminal. The transceiver may include a third pair of transistors having a third gate terminal configured to receive an LO signal and having a third source-drain terminal. The transceiver may include a transformer having a first inductor and a second inductor, wherein the first inductor is coupled between the first source-drain terminal, the second inductor is coupled between the second source-drain terminal and the third source-drain terminal, and the center tap of the first inductor is coupled to the center tap of the second conductor through a conductive path. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram of an illustrative electronic device with wireless circuitry according to some embodiments.

[0011] Figure 2is a diagram of an illustrative wireless circuit having a transceiver with mixer circuitry, according to some implementations.

[0012] Figure 3 is a block diagram of an illustrative mixer circuit according to some implementations.

[0013] Figure 4 is a circuit diagram of an illustrative mixer circuit having a transconductor, a switching quad, and a transformer that shares bias current between the transconductor and the switching quad, according to some implementations. DETAILED DESCRIPTION

[0014] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch device, a hanging device, a headset or earpiece device, a device embedded in glasses; or other equipment worn on the user's head; or other wearable or miniature devices, televisions, computer displays that do not contain embedded computers, gaming devices, navigation devices, embedded systems (such as systems in which electronic equipment with displays is installed in kiosks or cars), voice-controlled speakers connected to wireless Internet, home entertainment equipment, remote control devices, game controllers, peripheral user input devices, wireless base stations or access points, equipment that implements the functions of two or more of these devices; or other electronic equipment.

[0015] like Figure 1 As shown in the schematic diagram in , device 10 may include components located on or within an electronic device housing such as housing 12. Housing 12 (which may sometimes be referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloy, etc.), other suitable materials, or combinations of these materials. In some cases, part or all of housing 12 may be formed of a dielectric or other low conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12 or at least some of the structures that make up housing 12 may be formed of metal elements.

[0016] Device 10 may include control circuitry 14. Control circuitry 14 may include storage, such as storage circuitry 16. Storage circuitry 16 may include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 may include storage integrated within device 10 and / or removable storage media.

[0017] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more processors, such as a microprocessor, a microcontroller, a digital signal processor, a host processor, a baseband processor integrated circuit, an application-specific integrated circuit, a central processing unit (CPU), a graphics processing unit (GPU), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). The software code may sometimes be referred to as program instructions, software, data, instructions, or code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0018] Control circuitry 14 may be used to run software on device 10, such as satellite navigation applications, Internet browsing applications, Voice over Internet Protocol (VOIP) phone call applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 may be used to implement communication protocols. Communication protocols that may be implemented using control circuitry 14 include Internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as ), such as Protocols for other short-range wireless communication links such as the IEEE 802.11ad protocol or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth generation (5G) new radio (NR) protocols, sixth generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies a physical connection method for implementing the protocol.

[0019] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays, light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touch pads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice, and joysticks, and other input-output devices may be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 22 may be peripheral devices coupled to a main processing unit or other portion of device 10 via a wired or wireless link).

[0020] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communications. Wireless circuitry 24 (sometimes referred to herein as wireless communications circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmission lines, radio frequency front end circuitry, and / or any other circuitry for transmitting and / or receiving radio frequency signals using an antenna.

[0021] Wireless circuitry 24 may transmit and / or receive wireless signals within a corresponding frequency band of the electromagnetic spectrum (sometimes referred to herein as a communication band or simply a “band”). The frequency band processed by wireless circuitry 24 may include a wireless local area network (WLAN) frequency band (e.g., (IEEE 802.11) or other WLAN communication bands) such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925 MHz to 7125 MHz) and / or other frequency bands (e.g., 1875 MHz to 5160 MHz); wireless personal area network (WPAN) bands such as 2.4 GHz frequency band or other WPAN communication frequency band; cellular telephone frequency band (e.g., frequency band from about 600 MHz to about 5 GHz, 3G frequency band, 4G LTE frequency band, 5G new radio frequency range 1 (FR1) frequency band below 10 GHz, 5G new radio frequency range 2 (FR2) frequency band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave frequency bands between 10 GHz and 100 GHz; sub-THz frequency band between about 100 GHz and 1000 GHz (e.g., 6G frequency band); near field communication (NFC) frequency band (e.g., 13.56 MHz); satellite navigation frequency band (e.g., GPS frequency band from 1565 MHz to 1610 MHz, global navigation satellite system (GLONASS) frequency band, BeiDou navigation satellite system (BDS) frequency band, etc.); ultra-wideband (UWB) frequency band operating under IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; communication frequency band under 3GPP wireless communication standard family; under IEEE communications bands under the 802.XX family of standards; and / or any other desired frequency bands of interest.

[0022] Figure 2 2 is a diagram showing illustrative components within wireless circuitry 24. Figure 2 As shown, wireless circuit 24 may include one or more processors such as processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processor 26 may be a baseband processor (e.g., may include baseband processing circuitry), an application processor, a digital signal processor, a microcontroller, a microprocessor, a central processing unit (CPU), a programmable device, a combination of these circuits, and / or Figure 1 1. The processor 26 may be configured to generate digital (transmit or baseband) signals. The processor 26 may be coupled to the transceiver 28 via a path 34 (sometimes referred to as a baseband path). The transceiver 28 may be coupled to the antenna 42 via an RF transmission line path 36. If desired, one or more RF front-end modules (such as the RF front-end module 40) may be disposed between the transceiver 28 and the antenna 42 along the RF transmission line path 36.

[0023] Wireless circuitry 24 may include one or more antennas, such as antenna 42. Antenna 42 may be formed using any desired antenna structure. For example, antenna 42 may be an antenna having a resonant element formed by a loop antenna structure, a patch antenna structure, an inverted F antenna (IFA) structure, a slot antenna structure, a planar inverted F antenna (PIFA) structure, a helical antenna structure, a monopole antenna, a dipole, a dielectric resonator antenna (DRA) structure, a waveguide antenna structure, a bowtie antenna structure, a mixture of these designs, and the like. If desired, two or more antennas 42 may be arranged into one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). If desired, parasitic elements may be included in antenna 42 to adjust antenna performance. If desired, antenna 42 may be provided with a conductive cavity that supports an antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0024] exist Figure 2 In the example of FIG. 1 , for clarity, the wireless circuit 24 is shown as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. In general, the wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include a transmitter circuit configured to output an uplink signal to the antenna 42, may include a receiver circuit configured to receive a downlink signal from the antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmission line path 36. If desired, one or more of the RF transmission line paths 36 in the wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0025] The front end module (FEM) 40 may include RF front end circuitry that operates on RF signals transmitted (transmitted and / or received) via the RF transmission line path 36. The front end module may, for example, include front end module (FEM) components such as RF filter circuitry 44 (e.g., a low pass filter, a high pass filter, a notch filter, a band pass filter, a multiplexing circuit, a duplexer circuit, a diplexer circuit, a triplexer circuit, etc.), a switching circuitry 46 (e.g., one or more RF switches), an RF amplifier circuitry 48 (e.g., one or more power amplifiers and one or more low noise amplifiers), an impedance matching circuitry (e.g., a circuitry that helps match the impedance of the antenna 42 to the impedance of the RF transmission line 36), an antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of the antenna 42), an RF coupler circuitry, a charge pump circuitry, a power management circuitry, a digital control and interface circuitry, and / or any other desired circuitry that operates on RF signals transmitted and / or received by the antenna 42. Each of the front end module components may be mounted to a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit substrate. If desired, the various front-end module components may also be integrated into a single integrated circuit chip.

[0026] Filter circuits 44, switching circuits 46, amplifier circuits 48, and other circuits may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0027] The RF transmission line path 36 may be coupled to an antenna feed on the antenna 42. The antenna feed may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmission line path 36 may have a positive transmission line signal path that is coupled to the positive antenna feed terminal on the antenna 42. The RF transmission line path 36 may have a ground transmission line signal path that is coupled to the ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feeds coupled to one or more RF transmission line paths 36.

[0028] The RF transmission line path 36 may include a Figure 1) for routing RF antenna signals within the device 10. The transmission lines in the device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed by combinations of these types of transmission lines, and the like. The transmission lines in the device 10, such as the transmission lines in the RF transmission line path 36, may be integrated into a rigid and / or flexible printed circuit board. In a suitable specific implementation, the RF transmission line path (such as the RF transmission line path 36) may also include transmission line conductors that are integrated into a multilayer laminate structure (e.g., layers of conductive material (such as copper) and dielectric material (such as resin) laminated together without an intervening adhesive). If desired, the multilayer laminate structure may be folded or bent in multiple dimensions (e.g., two or three dimensions) and may maintain a bent or folded shape after bending (e.g., the multilayer laminate structure may be folded into a specific three-dimensional structural shape to route around other device components and may be rigid enough to maintain its shape after folding without reinforcements or other structures to hold it in place). All of the multiple layers of the laminated structure may be laminated together in batches (eg, in a single pressing process) without an adhesive (eg, as opposed to performing multiple pressing processes to laminate the multiple layers together with an adhesive).

[0029] Transceiver circuitry 28 may include processors that handle WLAN communication bands (e.g., (IEEE 802.11) or other WLAN communication bands) such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925 MHz to 7125 MHz) and / or other Wireless LAN transceiver circuits for frequency bands (e.g., 1875MHz to 5160MHz); handles 2.4GHz Wireless personal area network transceiver circuits for the WPAN frequency band or other WPAN communication frequency bands; cellular telephone transceiver circuits for processing cellular telephone frequency bands (e.g., frequency bands from about 600 MHz to about 5 GHz, 3G frequency bands, 4G LTE frequency bands, 5G new radio frequency range 1 (FR1) frequency bands below 10 GHz, 5G new radio frequency range 2 (FR2) frequency bands between 20 GHz and 60 GHz, 6G frequency bands above 100 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS frequency bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) frequency bands, BeiDou Navigation Satellite System (BDS) frequency bands, etc.); using IEEE Ultra-wideband (UWB) transceiver circuitry for handling communications in accordance with the 802.15.4 protocol and / or other ultra-wideband communications protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communications band of interest.

[0030] As used herein, the term "transmitting radio frequency signals" means the transmission and / or reception of radio frequency signals (e.g., for performing unidirectional and / or bidirectional wireless communication with external wireless communication equipment). When performing wireless transmission, the processor 26 may provide a digital signal to the transceiver 28 via a path 34. The transceiver 28 may also include a circuit for converting a baseband signal received from the processor 26 into a corresponding intermediate frequency or radio frequency signal. For example, the transceiver circuit 28 may include a mixer circuit 50 that up-converts (or modulates) a baseband signal to an intermediate frequency (e.g., as an intermediate frequency (IF) signal), up-converts a baseband signal to a radio frequency higher than the intermediate frequency (e.g., as a radio frequency (RF) signal), and / or up-converts an IF signal to a radio frequency before transmitting via the antenna 42. The transceiver circuit 28 may also include a digital-to-analog converter (DAC) circuit and / or an analog-to-digital converter (ADC) circuit that converts signals between the digital domain and the analog domain. Transceiver 28 may include a transmitter that transmits RF signals through antenna 42 via RF transmission line path 36 and front end module 40. Antenna 42 may transmit RF signals to external wireless equipment by radiating the RF signals into free space (or radiating into free space through a dielectric cover on device 10).

[0031] When performing wireless reception, the antenna 42 can receive radio frequency signals from external wireless equipment (e.g., from free space). The received radio frequency signals can be transmitted to the transceiver 28 via the radio frequency transmission line path 36 and the front end module 40. The transceiver 28 may include circuits for converting the received radio frequency signals to corresponding intermediate frequencies or baseband signals. For example, the transceiver 28 may use a mixer circuit 50 to down-convert (or demodulate) the received radio frequency signals to an intermediate frequency, down-convert the received radio frequency signals to a baseband frequency (e.g., as a baseband signal or baseband data), and / or down-convert the IF signal to a baseband frequency, and then transmit the received signal to the processor 26 via the path 34. The mixer circuit 50 may include a local oscillator circuit, such as a local oscillator (LO) circuit 52. The local oscillator circuit 52 may generate an oscillator signal, which the mixer circuit 50 may use to modulate the transmit signal from the baseband frequency to the radio frequency and / or demodulate the received signal from the radio frequency to the baseband frequency.

[0032] Figure 3 is a block diagram of an exemplary mixer circuit 50. Figure 3 As shown, mixer circuit 50 (sometimes referred to herein simply as mixer 50) may include an input stage such as transconductance (Gm) circuit 60 (sometimes referred to herein as transconductor 60), a transformer such as transformer 62, and an output stage including associated mixer subcircuits 51-1 and 51-2. The pair of mixer subcircuits 51-1 and 51-2 may each include two LO input transistors, and are therefore sometimes collectively referred to as switching quad 51.

[0033] The transformer 62 may include a first coil, winding or inductor, such as a primary coil Lp. The transformer 62 may also include a second coil, winding or inductor, such as a secondary coil Ls. The primary coil Lp may also be referred to herein as the primary winding Lp or primary inductor Lp of the transformer 62 at times. The secondary coil Ls may also be referred to herein as the secondary winding Ls or secondary inductor Ls of the transformer 62 at times. The terminals of the primary coil Lp may be coupled to the transconductor 60, and the terminals of the secondary coil Ls may be coupled to the switching quad 51.

[0034] The transconductor 60 may be a differential circuit having a differential input port and a differential output port. The differential input port of the transconductor 60 may be coupled to a differential input signal path (eg, Figure 2 The transconductor 60 can receive an input voltage V from the differential input signal path at its differential input port. 输入The differential output port of the transconductor 60 may be coupled to terminals of the primary winding Lp of the transformer 62. In other words, the differential output port of the transconductor 60 may include a first output terminal and a second output terminal, and the primary winding Lp may be coupled across or between the first output terminal and the second output terminal.

[0035] Input voltage V 输入 represents the input signal to be upconverted or downconverted by the mixer circuit 50. The mixer circuit 50 can generate an output signal at its differential output port as an output voltage V 输出 (For example, the mixer circuit 50 may be configured to receive an input signal (such as an input voltage V 输入 ) is up-converted or down-converted to generate an output signal (such as an output voltage V 输出 )). The mixer circuit 50 can convert an input signal (eg, an input voltage V 输入 ) is converted from a first frequency to a second frequency different from the first frequency, thereby generating an output signal at the second frequency (e.g., an output voltage V 输出 may be at a second frequency).

[0036] For example, when the mixer circuit 50 is provided in the transmitter or the transceiver circuit 28 ( Figure 2 ), the mixer circuit 50 may up-convert the input signal from the baseband frequency to the intermediate frequency, may up-convert the input signal from the intermediate frequency to the radio frequency, or may up-convert the input signal from the baseband frequency to the radio frequency. As another example, when the mixer circuit 50 is disposed in the receiver or the transceiver circuit 28 ( Figure 2 ), the mixer circuit 50 may down-convert the input signal from the RF to an IF, may down-convert the input signal from the RF to a baseband frequency, or may down-convert the input signal from the IF to a baseband frequency.

[0037] The transconductor 60 can receive an input voltage V 输入 , into corresponding output currents at its differential output ports. The use of a transconductance circuit (sometimes referred to as a Gm cell) as the input stage of mixer circuit 50 is exemplary. Other types of amplifiers, buffers, drivers, or input stages may be employed if desired.

[0038] The primary coil Lp of the transformer 62 may have a first terminal coupled to the first output terminal of the transconductor 60, a second terminal coupled to the second output terminal of the transconductor 60, and a corresponding center tap terminal (for clarity, Figure 3). The first output terminal and the second output terminal of the transconductor 60 may together form a differential output port of the transconductor 60. The secondary coil Ls may have a first terminal coupled to the first mixer subcircuit 51-1 of the switching quad channel 51; a second terminal coupled to the second mixer subcircuit 51-2 of the switching quad channel 51; and a corresponding center tap terminal (for clarity, Figure 3 not shown).

[0039] The first mixer sub-circuit 51-1 of the switching quad channel 51 has a first input terminal coupled to a first terminal of the secondary coil Ls; a second input terminal configured to receive a local oscillator (eg, Figure 2 The switching quad channel 51 includes a first input terminal coupled to the second terminal of the secondary coil Ls, a second input terminal also configured to receive the local oscillator signal LO, and an output terminal coupled to the differential output port of the mixer circuit 50. The switching quad channel 51 includes a first input terminal coupled to the second terminal of the secondary coil Ls, a second input terminal also configured to receive the local oscillator signal LO, and an output terminal coupled to the differential output port of the mixer circuit 50. The switching quad channel 51 may receive an input signal from the transconductor 60 via the transformer 62, and may up-convert the input signal to a second frequency (e.g., by modulating the local oscillator signal LO with the input signal).

[0040] Figure 4 is a circuit diagram illustrating one specific implementation of mixer circuit 50. Mixer circuit 50 may represent a transmit mixer (eg, a mixer in a transmit path) or a receive mixer (eg, a mixer in a receive path).

[0041] like Figure 4 As shown, the mixer circuit 50 may include an input transformer, such as input transformer 64. Input transformer 64 may have a primary coil 66 and a secondary coil 67. The terminals of primary coil 66 may be coupled to input terminals 68 (e.g., a pair of input terminals 68 that together form a differential input port of the mixer circuit 50). The terminals of secondary coil 67 may be coupled to the differential input port of transconductor 60. The mixer circuit 50 may receive an input voltage V across input terminals 68. 输入 . Input voltage V 输入 is the first voltage V at the first input terminal 68 输入 + and the second voltage V at the second input terminal 68 输入 -The RF differential voltage is defined by the difference between them.

[0042] The transconductor 60 may include a set of one or more input transistors 70, such as a first input transistor 70-1 and a second input transistor 70-2. The gate terminals of the input transistors 70-1 and 70-2 may collectively form a differential input port of the transconductor 60. The gate terminal of the input transistor 70-1 may be coupled to a first terminal of a secondary winding 67 in the input transformer 64. The gate terminal of the input transistor 70-2 may be coupled to a second terminal of the secondary winding 67 in the input transformer 64. Alternatively, the input transformer 64 may be omitted (e.g., the input terminal 68 may be directly connected to the gate terminals of the input transistors 70-1 and 70-2, so that the input terminal 68 forms a differential input port of the transconductor 60 and so that the gate terminals of the transinput transistors receive the input voltage V 输入 ).

[0043] As an example, input transistors 70-1 and 70-2 may be n-channel devices such as n-type metal oxide semiconductor (NMOS) transistors. Input transistor 70-1 may have a drain terminal coupled to a first terminal of primary coil Lp in transformer 62; a source terminal coupled to ground line 72 (e.g., a ground power line, path or plane on which a ground voltage or other reference voltage is provided); and a gate terminal configured to receive a voltage V (e.g., via input transformer 64). 输入 +. The input transistor 70-2 may have a drain terminal coupled to the second terminal of the primary coil Lp in the transformer 62; a source terminal coupled to the ground line 72; and a gate terminal configured to receive a voltage V 输入 -. The terms "source" and "drain" terminals used to refer to current-carrying terminals in a transistor are used interchangeably and are sometimes referred to as "source-drain" terminals. Thus, the drain terminal of transistor 70-1 may sometimes be referred to as a first source-drain terminal, and the source terminal of transistor 70-1 may be referred to as a second source-drain terminal (or vice versa), etc.

[0044] The mixer circuit 50 may include an output transformer 82. The output transformer 82 may have a primary coil 80 and a secondary coil 78. The terminals of the secondary coil 78 may be coupled to the corresponding output terminals 76 of the mixer circuit 50 (e.g., the secondary coil 78 may be coupled across the output terminals 76 or coupled between the output terminals 76). The terminals of the primary coil 80 may be coupled to the output of the switching quad 51. The primary coil 80 may have a center tap contact (e.g., a center tap conductor) coupled to the voltage line 74. The voltage line 74 may receive a positive power supply voltage, a ground power supply voltage, a negative power supply voltage, an intermediate voltage between the positive power supply voltage and the ground power supply voltage, or other static (direct current or DC) voltage. The specific implementation of the voltage line 74 providing a positive power supply voltage to the center tap of the primary coil 80 is described as an example herein.

[0045] The transformer 62 can couple the output of the transconductor 60 to the input of the switching quad 51. For example, the mixer sub-circuit 51-1 ( Figure 3 ) may include a first pair of mixer transistors 104-1A and 104-1B (e.g., a first transistor pair). Mixer transistor 104-1A may have a source terminal coupled to a first terminal of secondary coil Ls in transformer 62; a gate terminal configured to receive signal LO+; and a drain terminal coupled to a first terminal of primary coil 80 in output transformer 82. Mixer transistor 104-1B may have a source terminal also coupled to a first terminal of secondary coil Ls in transformer 62; a gate terminal configured to receive signal LO-; and a drain terminal coupled to a second terminal of primary coil 80 in output transformer 82. Source terminals of mixer transistors 104-1A and 104-1B may both be coupled to a first tail node Tp of switching quad 51. Tail node Tp may be coupled to a first terminal of secondary coil Ls in transformer 62.

[0046] The mixer subcircuit 51-2 may include a second pair of mixer transistors 104-2A and 104-2B (e.g., a second transistor pair). The mixer transistor 104-2A may have a source terminal coupled to the second terminal of the secondary coil Ls in the transformer 62; a gate terminal configured to receive the signal LO+; and a drain terminal coupled to the second terminal of the primary coil 80 in the output transformer 82. The mixer transistor 104-2B may have a source terminal also coupled to the second terminal of the secondary coil Ls in the transformer 62; a gate terminal configured to receive the signal LO-; and a drain terminal coupled to the first terminal of the primary coil 80 in the output transformer 82. The source terminals of the mixer transistors 104-2A and 104-2B may both be coupled to the second tail node Tm of the switching quad 51. The tail node Tm may be coupled to a second terminal of the secondary coil Ls in the transformer 62 (eg, the secondary coil Ls of the transformer 62 may be coupled between the tail nodes Tp and Tm). The tail nodes Tm and Tp may form a differential input port of the switching quad 51 .

[0047] The signals LO+ and LO- represent the positive and negative polarities of the differential signal and may be collectively referred to as local oscillator (LO) signals or oscillation signals. The gate terminals of the mixer transistors 104-1A and 104-1B collectively form a differential input port for receiving the oscillation signal. The gate terminals of the mixer transistors 104-2A and 104-2B also collectively form a differential input port for receiving the oscillation signal. The drain terminals of the mixer transistors 104-1B and 104-2A and the drain terminals of the mixer transistors 104-1A and 104-2B (e.g., the first terminal and the second terminal of the primary coil 80 in the output transformer 82) collectively form a differential output port of the switching quad 51. The output terminals 76 collectively form a differential output port of the mixer circuit 50. Alternatively, transformer 82 may be omitted and the differential output ports of the switched quad channel 51 may form differential output ports of the mixer circuit 50 (e.g., drain terminals of mixer transistors 104-1B and 104-2A may be coupled to a first output terminal 76, and drain terminals of mixer transistors 104-1A and 104-2B may be coupled to a second output terminal 76, with an inductor coupled between the output terminals 76 and having a center tap terminal coupled to voltage line 74).

[0048] During operation (eg, during signal transmission or reception using mixer circuit 50), input transformer 64 may use an input signal (eg, input voltage V 输入 ) to drive the gate terminals of input transistors 70-1 and 70-2. This allows the input voltage V 输入The corresponding current flows through the source-drain terminals of the input transistor 70. The transformer 62 can transmit the corresponding signal to the switching quad 51 via the near-field electromagnetic coupling 108 between the primary coil Lp and the secondary coil Ls (e.g., the primary coil Lp is magnetically coupled to the secondary coil Ls). The gate terminal of the mixer transistor 104 in the switching quad 51 is driven using the LO signal to modulate the LO signal using the signal from the transformer 62, thereby effectively up-converting or down-converting the signal to produce an output signal. The output transformer 82 can pass the output signal to the output terminal 76 (e.g., as an output voltage V 输出 , which is a first voltage V at the first output terminal 76 输出 + and the second voltage V at the second output terminal 76 输出 - differential signal defined by the difference between them).

[0049] In a high frequency transceiver (such as transceiver circuit 28 ( Figure 2 )) have stringent requirements for gain, noise, linearity, transmission, and filtering. Depending on the application, higher mixer gain can help relax the gain and / or linearity requirements of other circuit blocks coupled to the input and / or output of the mixer. Since gain is related to power consumption, a Gilbert cell-based mixer (e.g., a mixer with two inputs (such as an input voltage V 输入 A mixer that outputs a frequency signal proportional to the product of the LO signal (i.e., the frequency of the mixer outputting the frequency signal proportional to the product of the LO signal) can trade off between these two metrics and can affect the overall power efficiency of the transceiver. Coupling transformer 62 between switching quad 51 and transconductor 60 can help improve mixer gain (e.g., by imparting a voltage / current gain to the signal via near-field electromagnetic coupling 108).

[0050] In some implementations, two separate power supply voltages are used to bias the switching quad 51 and the transconductor 60. In these implementations, the center tap contact of the primary coil Lp in the transformer 62 is coupled to a power supply line that receives a first positive power supply voltage, and the center tap contact of the secondary coil Ls in the transformer 62 is coupled to a ground line 72. At the same time, the center tap contact of the primary coil 80 in the output transformer 82 receives a second positive power supply voltage that is separate (independent) from the first positive power supply voltage. The switching quad 51 is thus biased by the second positive power supply voltage provided to the center tap of the primary coil 80 in the output transformer 82 and the ground voltage provided to the center tap of the secondary coil Ls in the transformer 62, so that a first bias current flows through the switching quad 51. On the other hand, the transconductor 60 is biased by the first positive power supply voltage provided to the center tap of the primary coil Lp in the transformer 62 and the ground voltage provided to the source terminals of the input transistors 70-1 and 70-2, so that a second bias current different from (independent of) the first bias current flows through the transconductor 60. In other words, the bias current flowing through switching quad 51 is different from and decoupled from the bias current flowing through transconductor 60. Since the supply current of switching quad 51 can be higher than the bias current flowing through switching quad 51 when mixer transistor 104 is being turned on and off by the LO signal (sometimes referred to herein as the switching operation of switching quad 51), independently biasing switching quad 51 can result in excessive power consumption in mixer circuit 50 relative to quiescent conditions.

[0051] In order to minimize the power consumption of the mixer circuit 50 without sacrificing linearity or performance, the transformer 62 may be a "current recycling" transformer that shares or recycles the bias current between the primary coil Lp and the secondary coil Ls. Figure 4 As shown, the primary coil Lp may have a center tap contact CTA (sometimes referred to herein as a center tap conductor CTA or simply referred to as a center tap CTA). The secondary coil Ls may have a center tap contact CTB (sometimes referred to herein as a center tap conductor CTB or simply referred to as a center tap CTB). The transformer 62 (sometimes referred to herein as a current recycling transformer 62) may include a conductive path (line) 84 extending between the primary coil Lp and the secondary coil Ls. The center tap contact CTA of the primary coil Lp may be coupled to a first end of the conductive path 84, and the center tap contact CTB of the secondary coil Ls may be coupled to a second (opposite) end of the conductive path 84 (e.g., the conductive path 84 may couple, galvanically connect, or short the center tap contact CTA of the primary coil Lp to the center tap contact CTB of the secondary coil Ls).

[0052] As an example, the conductive path 84 may be implemented using conductive traces, conductive vias, and / or conductive wires. In a specific implementation where the conductive path 84 is implemented as a conductive trace, the conductive trace may be patterned onto an underlying substrate (such as a printed circuit board or a semiconductor substrate). If desired, the primary coil Lp and / or the secondary coil Ls may be implemented as an on-chip inductor formed by windings of conductive traces on one or more layers of a substrate (e.g., the same layer as the conductive path 84 and / or an additional layer). In a specific implementation where the primary coil Lp and the secondary coil Ls include conductive traces on different layers of the substrate, the conductive path 84 may include conductive vias (e.g., in addition to or in lieu of conductive traces used to form the conductive path 84) that couple the conductive traces from the coils Lp and Ls together (e.g., through one or more layers of the substrate). In a specific implementation where the conductive path 84 includes a conductive wire, the conductive wire may be soldered or fused to the center tap contacts CTA and / or CTB, if desired.

[0053] Conductive path 84 (sometimes referred to herein as center tap path 84 or conductive line 84) can configure transformer 62 to share or reuse bias current between switching quad 51 and transconductor 60. For example, during operation, the positive supply voltage received by the center tap conductor of primary coil 80 in output transformer 82 (from voltage line 74) and the ground voltage received by the source terminals of input transistors 70-1 and 70-2 from ground line 72 can generate a bias current I flowing through both switching quad 51 and transconductor 60 via, through, or through conductive path 84. DC (e.g., DC bias current).

[0054] As shown by arrow 92, the bias current I DC The first half of the bias current I flows from the drain terminal of the input transistor 70-1 into the first terminal of the primary winding Lp in the transformer 62. As shown by arrow 94, the bias current I DC The second half of the current flows from the drain terminal of the input transistor 70-2 to the second terminal of the primary coil Lp in the transformer 62. When the transformer transfers the input signal from the transconductor 60 to the switching quad 51 via the near-field electromagnetic coupling 108, the transformer 62 transmits the input signal (e.g., carrying wireless data and corresponding to the input voltage V 输入 The signal) gives a passive voltage / current gain. At the same time, the bias current I DC The bias current I flows from the center tap contact CTA of the primary coil Lp to the center tap contact CTB of the secondary coil Ls through, via or across the conductive path 84 (as indicated by arrow 90). DC The first half of the bias current I flows from the center tap contact CTB of the secondary coil Ls to the tail node Tp of the switching quad 51 (as shown by arrow 98). DCThe second half of the bias current flows from the center tap contact CTB to the tail node Tm of the switching quad 51 (as shown by arrow 96). DC The current can thereby bias the operation of the switching quad 51 .

[0055] In this way, the switching contact 51 does not require a separate / dedicated power supply, but instead uses the bias current I received from the transconductor 60 via the conductive path 84 in the transformer 62. DC In other words, the conductive path 84 in the transformer 62 configures the transformer 62 to share the same bias current I between the transconductor 60 and the switching quad 51. DC , which can be used to minimize power consumption of the mixer circuit 50 while utilizing the passive voltage / current gain from the transformer 62, thereby allowing the mixer circuit 50 to meet the gain, linearity, noise, and / or filtering requirements of other circuits coupled to the input and / or output of the mixer circuit. Assuming a quality factor of Q=12 for the transformer coil and a quality factor of Q=8 for the capacitor, the bias current shared by the transformer 62 can reduce power consumption in the mixer circuit 50 by 8 mW or more, can produce a gain improvement of 4 dB or more, can produce comparable linearity, can reduce the LO swing by up to 50% (thereby further saving LO power), and / or can reduce the physical size of the switch quad 51 by up to 60% (e.g., relative to an implementation in which the switch quad 51 and the transconductor 60 are biased by separate bias currents (e.g., different positive supply voltages) and the transformer 62 does not include the conductive path 84).

[0056] In some implementations, the conductive path 84 includes a single conductive line that directly connects the center tap contacts CTA and CTB (e.g., no other components are disposed on the conductive path 84). If desired, a node on the conductive path 84 can be coupled to the ground line 72 (e.g., through an additional conductive path). If desired, a common mode impedance termination can be disposed on the conductive path 84. The common mode impedance termination can include a first common mode impedance termination 88 (e.g., having an impedance Z ) disposed on the conductive path 84 and coupled in series between the center tap contacts CTA and CTB. S1 ), and / or may include a second common mode impedance termination 106 (eg, having an impedance Z) disposed on the conductive path between the conductive path 84 and the ground line 72. SH ) (e.g., second common-mode impedance termination 106 may form a shunt impedance from conductive path 84). Common-mode impedance terminations 88 and 106 may perform impedance termination and / or filtering for common-mode signals transmitted via conductive path 84 (e.g., where two differential lines driven with a common-mode excitation exhibit an even mode corresponding to driving each line with the same amplitude and polarity, and exhibit an odd mode corresponding to driving each line with the same amplitude but opposite polarity).

[0057] Additionally or alternatively, a differential mode impedance termination may be coupled between the terminals of the secondary coil Ls and the tail nodes Tp and Tm. Figure 4 As shown, the first differential mode impedance terminal 102 may be coupled in series between the first terminal of the secondary coil Ls and the tail node Tp, and / or the second differential mode impedance terminal 100 may be coupled in series between the second terminal of the secondary coil Ls and the tail node Tm. The differential mode impedance terminals 102 and 100 may perform impedance termination and / or filtering on the differential mode signal transmitted through the conductive path 84.

[0058] The impedance terminations 100, 102, 88, and 106 may each include any desired number of resistive, inductive, and / or capacitive components arranged in any desired manner. If desired, one or more of the impedance terminations 100, 102, 88, and 106 may include a switching circuit. The switching circuit may be adjusted to actively adjust the impedance of one or more of the impedance terminations. If desired, the switching circuit may have at least one switch state in which the impedance termination is bypassed (e.g., the impedance terminations 100, 102, 88, and / or 106 may be switched to be used or not used as desired). The mixer circuit 50 may include all of the impedance terminations 100, 102, 88, and 106, only differential mode impedance terminations 100 and / or 102, only common mode impedance terminations 88 and / or 106, or impedance terminations 100, 102, 88, and 106 may be omitted. For example, impedance terminations 100 , 102 , 88 , and 106 may help further increase linearity, reduce emissions, and / or improve filtering of mixer circuit 50 .

[0059] As used herein, the term "simultaneous" refers to overlapping at least partially in time. In other words, if at least some of the first event occurs simultaneously with at least some of the second event (e.g., if at least some of the first event occurs during at least some of the second event, occurs at the same time as at least some of the second event, or occurs when at least some of the second event occurs), the first event and the second event are referred to as "simultaneous" with each other in this article. If the first event and the second event are synchronized (e.g., if the entire duration of the first event overlaps with the entire duration of the second event in time), the first event and the second event can be simultaneous, but if the first event and the second event are asynchronous (e.g., if the first event starts before or after the second event starts, if the first event ends before or after the second event ends, or if the first event and the second event do not partially overlap in time), the first event and the second event can also be simultaneous. As used herein, the term "while" is synonymous with "concurrent".

[0060] Device 10 may collect and / or use personally identifiable information. As is well known, use of personally identifiable information should be subject to privacy policies and practices that are generally recognized to meet or exceed industry or government requirements for maintaining user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly stated to the user.

[0061] Combination of the above Figures 1 to 4 The described methods and operations may be performed by the components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuits or hardware). The software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more of the components of device 10 (e.g., a computer-readable storage medium). Figure 1 The software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include a drive, non-volatile memory such as non-volatile random access memory (NVRAM), a removable flash drive or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be executed by processing circuitry (e.g., Figure 1 The processing circuit may include a microprocessor, a central processing unit (CPU), a dedicated integrated circuit with a processing circuit, or other processing circuits.

[0062] According to one embodiment, a mixer circuit is provided, which includes a transformer having a first winding and a second winding; a first input transistor, which is coupled to the first terminal of the first winding and is configured to receive an input signal; a second input transistor, which is coupled to the second terminal of the first winding and is configured to receive an input signal; a first pair of mixer transistors, which are coupled to the first terminal of the second winding and are configured to receive an oscillation signal; a second pair of mixer transistors, which are coupled to the second terminal of the second winding and are configured to receive an oscillation signal; and a conductive path, which couples a center tap contact of the first winding to a center tap contact of the second winding.

[0063] According to another embodiment, a mixer circuit includes an output transformer having a third winding and a fourth winding, the first pair of mixer transistors coupled between first terminals of the output transformer and the second winding, and the second pair of mixer transistors coupled between second terminals of the output transformer and the second winding; and a positive power supply line coupled to a center tap contact of the third winding.

[0064] According to another embodiment, the first input transistor has a first source-drain terminal coupled to the first terminal of the first winding, a second source-drain terminal coupled to the ground line, and a first gate terminal configured to receive an input signal.

[0065] According to another embodiment, the second input transistor has a third source-drain terminal coupled to the second terminal of the first winding; a fourth source-drain terminal coupled to the ground line; and a second gate terminal configured to receive an input signal.

[0066] According to another embodiment, the positive power line and the ground line are configured to generate a DC bias current that flows through a conductive path between a center tap contact of the first winding and a center tap contact of the second winding.

[0067] According to another embodiment, a mixer circuit includes a first impedance termination disposed on the conductive path.

[0068] According to another embodiment, the mixer circuit includes a second impedance termination coupling the conductive path to the ground line.

[0069] According to another embodiment, the first pair of mixer transistors has a first source-drain terminal, which is coupled to the first terminal of the second winding, and the first pair of mixer transistors has a first gate terminal, which is configured to receive the oscillating signal, and the second pair of mixer transistors has a second source-drain terminal, which is coupled to the second terminal of the second winding, and the second pair of mixer transistors has a second gate terminal, which is configured to receive the oscillating signal.

[0070] According to another embodiment, the mixer circuit includes a first impedance terminal coupled between the first source-drain terminal and the first terminal of the second winding, and a second impedance terminal coupled between the second source-drain terminal and the second terminal of the second winding.

[0071] According to another embodiment, the mixer circuit includes a third impedance termination disposed on the conductive path.

[0072] According to another embodiment, the first impedance termination includes a first differential mode impedance termination, the second impedance termination includes a second differential mode impedance termination, and the third impedance termination includes a common mode impedance termination.

[0073] According to another embodiment, the mixer circuit includes an additional conductive path coupling a node on the conductive path to a ground line.

[0074] According to another embodiment, the first pair of mixer transistors and the second pair of mixer transistors are configured to generate an output signal based on an oscillation signal and an input signal, the output signal having a frequency different from the input signal, and the conductive path is configured to share a DC bias current between the first pair of mixer transistors, the second pair of mixer transistors, the first input transistor, and the second input transistor.

[0075] According to one embodiment, a mixer circuit is provided, which includes a transconductor, a mixer transistor and a transformer, which couples the output of the transconductor to the input of the mixer transistor, and the transformer includes a first coil having a first center tap contact; and a second coil, which is magnetically coupled to the first coil, the second coil having a second center tap contact, and the second center tap contact is coupled to the first center tap contact through a conductive path.

[0076] According to another embodiment, a mixer transistor has a first source-drain terminal coupled to the first terminal and the second terminal of the second coil, and has a gate terminal configured to receive an oscillating signal.

[0077] According to another embodiment, the transconductor includes a transistor having a second source-drain terminal coupled to the first terminal and the second terminal of the first coil.

[0078] According to another embodiment, the transistor in the transconductor has a third source-drain terminal coupled to a ground line.

[0079] According to another embodiment, the mixer transistor has a fourth source-drain terminal, the mixer circuit includes a third coil, the fourth source-drain terminal is coupled to the first terminal and the second terminal of the third coil, and the third coil has a third center tap contact coupled to the power line.

[0080] According to one embodiment, an electronic device is provided, which includes an antenna and a transceiver, which is configured to transmit a radio frequency signal using the antenna, the transceiver including a first pair of transistors, the first pair of transistors having a first gate terminal configured to receive an input signal and having a first source-drain terminal; a second pair of transistors, the second pair of transistors having a second gate terminal configured to receive a local oscillator (LO) signal and having a second source-drain terminal; a third pair of transistors, the third pair of transistors having a third gate terminal configured to receive the LO signal and having a third source-drain terminal; and a transformer, the transformer having a first inductor and a second inductor, the first inductor coupled between the first source-drain terminals, the second inductor coupled between the second source-drain terminals and the third source-drain terminals, and a center tap of the first inductor coupled to the center tap of the second inductor through a conductive path.

[0081] According to another embodiment, the first pair of transistors has a fourth source-drain terminal, the second pair of transistors has a fifth source-drain terminal, the third pair of transistors has a sixth source-drain terminal, the second pair of transistors is configured to generate an output signal at the fifth source-drain terminal based on an input signal, the third pair of transistors is configured to generate an output signal at the sixth source-drain terminal based on the input signal, the output signal is at a frequency different from the input signal, and the electronic device includes a ground power line coupled to the fourth source-drain terminal; a third inductor coupled between the fifth source-drain terminal and the sixth source-drain terminal; and a positive power line coupled to the center tap of the third inductor.

[0082] The foregoing is exemplary and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented independently or in any combination.

Claims

1. A mixer circuit, comprising: a transformer having a first winding and a second winding; a first input transistor coupled to a first terminal of the first winding and configured to receive an input signal; a second input transistor coupled to a second terminal of the first winding and configured to receive the input signal; a first pair of mixer transistors coupled to a first terminal of the second winding and configured to receive an oscillating signal; a second pair of mixer transistors coupled to a second terminal of the second winding and configured to receive the oscillating signal; as well as A conductive path couples the center tap contact of the first winding to the center tap contact of the second winding.

2. The mixer circuit according to claim 1, further comprising: an output transformer having a third winding and a fourth winding, the first pair of mixer transistors coupled between the output transformer and the first terminal of the second winding, and the second pair of mixer transistors coupled between the output transformer and the second terminal of the second winding; as well as A positive power supply line is coupled to a center tap contact of the third winding.

3. The mixer circuit of claim 2 , wherein the first input transistor has a first source-drain terminal coupled to the first terminal of the first winding; a second source-drain terminal coupled to a ground line; and a first gate terminal configured to receive the input signal.

4. The mixer circuit of claim 3 , wherein the second input transistor has a third source-drain terminal coupled to the second terminal of the first winding; a fourth source-drain terminal coupled to the ground line; and a second gate terminal configured to receive the input signal.

5. The mixer circuit of claim 3, wherein the positive power supply line and the ground line are configured to generate a DC bias current that flows through the conductive path between the center tap contact of the first winding and the center tap contact of the second winding.

6. The mixer circuit according to claim 1, further comprising: A first impedance terminal is disposed on the conductive path.

7. The mixer circuit according to claim 6, further comprising: A second impedance termination couples the conductive path to a ground line.

8. The mixer circuit of claim 1 , wherein the first pair of mixer transistors have a first source-drain terminal coupled to the first terminal of the second winding, the first pair of mixer transistors have a first gate terminal configured to receive the oscillating signal, the second pair of mixer transistors have a second source-drain terminal coupled to the second terminal of the second winding, and the second pair of mixer transistors have a second gate terminal configured to receive the oscillating signal.

9. The mixer circuit according to claim 8, further comprising: a first impedance terminal coupled between the first source-drain terminal and the first terminal of the second winding; as well as A second impedance terminal is coupled between the second source-drain terminal and the second terminal of the second winding.

10. The mixer circuit according to claim 9, further comprising: A third impedance terminal is disposed on the conductive path.

11. The mixer circuit of claim 10, wherein the first impedance termination comprises a first differential mode impedance termination, the second impedance termination comprises a second differential mode impedance termination, and the third impedance termination comprises a common mode impedance termination.

12. The mixer circuit according to claim 1, further comprising: An additional conductive path couples a node on the conductive path to a ground line.

13. The mixer circuit of claim 1 , wherein the first pair of mixer transistors and the second pair of mixer transistors are configured to generate an output signal based on the oscillation signal and the input signal, the output signal having a frequency different from that of the input signal, and the conductive path is configured to share a DC bias current between the first pair of mixer transistors, the second pair of mixer transistors, the first input transistor, and the second input transistor.

14. A mixer circuit comprising: transconductor; mixer transistors; as well as a transformer coupling the output of the transconductor to the input of the mixer transistor, wherein the transformer comprises a first coil having a first center tap contact, and A second coil is magnetically coupled to the first coil, the second coil having a second center tap contact coupled to the first center tap contact through a conductive path. 15 . The mixer circuit of claim 14 , wherein the mixer transistor has a first source-drain terminal coupled to the first terminal and the second terminal of the second coil, and has a gate terminal configured to receive an oscillating signal. 16 . The mixer circuit of claim 15 , wherein the transconductor comprises a transistor having a second source-drain terminal coupled to the first terminal and the second terminal of the first coil.

17. The mixer circuit of claim 16, wherein the transistor in the transconductor has a third source-drain terminal coupled to a ground line.

18. The mixer circuit of claim 17, wherein the mixer transistor has a fourth source-drain terminal, the mixer circuit further comprising: A third coil, wherein the fourth source-drain terminal is coupled to the first terminal and the second terminal of the third coil, the third coil having a third center tap contact coupled to a power line.

19. An electronic device comprising: antenna; as well as A transceiver configured to transmit a radio frequency signal using the antenna, the transceiver comprising a first pair of transistors having first gate terminals configured to receive an input signal and having first source-drain terminals, a second pair of transistors having second gate terminals configured to receive a local oscillator (LO) signal and having second source-drain terminals, a third pair of transistors having a third gate terminal configured to receive the LO signal and having a third source-drain terminal, and A transformer having a first inductor and a second inductor, wherein the first inductor is coupled between the first source-drain terminals, the second inductor is coupled between the second source-drain terminals and the third source-drain terminals, and a center tap of the first inductor is coupled to a center tap of the second inductor through a conductive path.

20. The electronic device of claim 19, the first pair of transistors having a fourth source-drain terminal, the second pair of transistors having a fifth source-drain terminal, the third pair of transistors having a sixth source-drain terminal, the second pair of transistors being configured to generate an output signal at the fifth source-drain terminal based on the input signal, the third pair of transistors being configured to generate the output signal at the sixth source-drain terminal based on the input signal, the output signal being at a different frequency than the input signal, and the electronic device further comprising: a ground power line coupled to the fourth source-drain terminal; a third inductor coupled between the fifth source-drain terminal and the sixth source-drain terminal; as well as A positive power supply line is coupled to a center tap of the third inductor.

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