Power amplifier

Abstract

The invention provides a power amplification device which realizes miniaturization of the power amplification device. The present invention is provided with: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier and provided on the surface; a balance-unbalance converter is used for carrier waves; a balance-unbalance converter is used for a peak value; and a surface mount component. The substrate has a plurality of insulating layers arranged in the stacking direction. An electrode for welding a surface-mounted component is provided on the surface. When viewed from the stacking direction, a carrier balun, an electrode, and a peak balun are arranged side by side in the second planar direction on one side of the integrated circuit in the first planar direction. One of the carrier balun and the peak balun is provided on the insulating layer disposed closer to the first lamination direction than the insulating layer constituting the surface, and at least partially overlaps the electrode when viewed from the lamination direction.

Description

Technical Field

[0001] The present disclosure relates to a power amplification device. Background Art

[0002] As one of the power amplifier devices, there is a differential amplifier device having a differential Doherty circuit. In the differential Doherty circuit, a carrier amplifier is connected in parallel with a peak amplifier. The carrier amplifier operates regardless of the power level of the input signal. The peak amplifier is disconnected when the power level of the input signal is small, and is connected when the power level of the input signal is large. In addition, the differential Doherty circuit has a carrier balun connected to the carrier amplifier, a peak balun connected to the peak amplifier, and an adjustment circuit (adjustment circuit component). In addition, regarding the layout on the substrate, the carrier balun and the peak balun are configured to be adjacent to one side of the integrated circuit having the carrier amplifier and the peak amplifier. That is, the carrier balun and the peak balun are configured to be adjacent to each other. In addition, surface mounted components such as adjustment circuit components are mounted on the surface of the substrate.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-170224 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] In addition, when the distance between the carrier balun and the peak balun is small, electromagnetic interference occurs between the carrier balun and the peak balun. As a result, the characteristics may be degraded. For this reason, the carrier balun and the peak balun are separated by a predetermined distance or more. As a result, a dead space is formed between the carrier balun and the peak balun, resulting in a large-scale power amplifier. Therefore, it is expected to use this dead space to achieve a small-scale power amplifier.

[0008] The present disclosure is made in view of the above-mentioned problems, and an object of the present disclosure is to provide a miniaturized power amplifier device.

[0009] Solutions for solving problems

[0010] A power amplifier device according to one aspect of the present disclosure includes: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being arranged on the surface; a carrier balun connected to the carrier amplifier; a peak balun connected to the peak amplifier; and a surface mount component arranged on the surface. The carrier amplifier and the peak amplifier are each a pair of differential amplifiers. A direction in which the integrated circuit and the substrate are arranged is defined as a stacking direction. A direction in which the substrate is arranged when viewed from the integrated circuit in the stacking direction is defined as a first stacking direction. A direction parallel to the surface is defined as a first plane direction. A direction parallel to the surface and intersecting the first plane direction is defined as a second plane direction. The substrate has a plurality of insulating layers arranged in the stacking direction. An electrode for soldering the surface mount component is provided on the surface. When viewed from the stacking direction, the carrier balun, the electrode, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction. One of the carrier balun and the peak balun is disposed on the insulating layer configured to be closer to the first stacking direction than the insulating layer constituting the surface, and at least a portion of the one of the carrier balun and the peak balun overlaps with the electrode when viewed from the stacking direction.

[0011] A power amplifier device according to one aspect of the present disclosure includes: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being arranged on the surface; a carrier balun connected to the carrier amplifier; a peak balun connected to the peak amplifier; and an inductor being a surface mounted component arranged on the surface. The carrier amplifier and the peak amplifier are each a pair of differential amplifiers. A direction in which the integrated circuit and the substrate are arranged is defined as a stacking direction. A direction in which the substrate is arranged when viewed from the integrated circuit in the stacking direction is defined as a first stacking direction. A direction parallel to the surface is defined as a first plane direction. A direction parallel to the surface and intersecting the first plane direction is defined as a second plane direction. The substrate has a plurality of insulating layers arranged in the stacking direction. The carrier balun has a primary-side carrier balun and a secondary-side carrier balun, and the center lines of the windings of the primary-side carrier balun and the secondary-side carrier balun extend along the stacking direction. One of the primary-side carrier balun and the secondary-side carrier balun is provided on the surface, and the other is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface. The peak balun has a primary-side peak balun and a secondary-side peak balun, and the center lines of the windings of the primary-side peak balun and the secondary-side peak balun extend along the stacking direction. One of the primary-side peak balun and the secondary-side peak balun is provided on the surface, and the other is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface. When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction. A center line of the winding of the inductor extends along the second planar direction.

[0012] A power amplifier device according to one aspect of the present disclosure includes: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being arranged on the surface; a carrier balun connected to the carrier amplifier; a peak balun connected to the peak amplifier; and an inductor which is a surface mounted component arranged on the surface. The carrier amplifier and the peak amplifier are each a pair of differential amplifiers. A direction in which the integrated circuit and the substrate are arranged is defined as a stacking direction. A direction in which the substrate is arranged when viewed from the integrated circuit in the stacking direction is defined as a first stacking direction. A direction parallel to the surface is defined as a first plane direction. A direction parallel to the surface and intersecting the first plane direction is defined as a second plane direction. The substrate has a plurality of insulating layers arranged in the stacking direction. When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction. The carrier balun has a primary-side carrier balun and a secondary-side carrier balun, the center lines of the windings of the primary-side carrier balun and the secondary-side carrier balun extend in the stacking direction, and the primary-side carrier balun and the secondary-side carrier balun are arranged in different insulating layers. The peak balun has a primary-side peak balun and a secondary-side peak balun, the center lines of the windings of the primary-side peak and the secondary-side peak extend in the stacking direction, and the primary-side peak balun and the secondary-side peak balun are arranged in different insulating layers. One of the carrier balun and the peak balun is provided on the insulating layer disposed closer to the first stacking direction than the insulating layer constituting the surface. A center line of the winding of the inductor extends along the second planar direction.

[0013] Effects of the Invention

[0014] According to the present disclosure, the power amplifying device is miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a diagram showing the overall circuit configuration of the power amplifier device according to the first embodiment.

[0016] Figure 2This is a schematic diagram showing an example of the relationship between the power of the high-frequency signal of the power amplifier circuit and the signal output by the detection circuit according to the first embodiment.

[0017] Figure 3 It is a diagram showing a specific example of the detector circuit and the drive level detection circuit of the power amplifier circuit according to the first embodiment.

[0018] Figure 4 It is a diagram showing an equivalent circuit of a specific example of a detector circuit and a drive level detection circuit of the power amplifier circuit according to the fifth embodiment.

[0019] Figure 5 This is a diagram showing an example of the relationship between the power of a high-frequency signal and the bias voltage applied to the peak amplifier in the power amplifier circuit according to the first embodiment.

[0020] Figure 6 1 is a diagram showing a circuit configuration of a Doherty circuit in the power amplifier device according to the first embodiment.

[0021] Figure 7 This is a diagram showing a plan view of the surface of the substrate in the power amplifier device according to the first embodiment.

[0022] Figure 8 It is a diagram for explaining the layout of the second insulating layer in the power amplifier device according to the first embodiment.

[0023] Fig. 9 It is a diagram for explaining the layout of the third insulating layer in the power amplifier device according to the first embodiment.

[0024] Fig.10 Is magnification Figure 7 A magnified image of a portion of the image.

[0025] Fig.11 1 is a plan view showing the surface of a substrate of the power amplifier device according to the first modification.

[0026] Fig.12 FIG. 1 is a diagram showing a circuit configuration of a Doherty circuit in a power amplifier device according to a second modification.

[0027] Fig.13 This is a diagram showing a plan view of the surface of a substrate in a power amplifier device according to a second modification.

[0028] Fig.14 It is a diagram for explaining the layout of the second insulating layer in the power amplifier device according to the second modification.

[0029] Fig.15 It is a diagram for explaining the layout of the third insulating layer in the power amplifier device according to the second modification.

[0030] Fig.16 So Fig.13 Schematic diagram of a cross section taken along line XVI-XVI. DETAILED DESCRIPTION

[0031] Below, the implementation of the power amplifier device of the present disclosure is described in detail based on the accompanying drawings. In addition, the present disclosure is not limited to the implementation. Each implementation is an example, and it is self-evident that partial replacement or combination of the structures shown in different implementations can be performed. After the third variant, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects of the same structure will not be mentioned one by one in each implementation.

[0032] First, the overall structure of the power amplifier device 100 is described, and then the differential Doherty circuit is described in detail. In addition, the carrier amplifier of the power amplifier device 100 of the present disclosure is composed of a pair of differential amplifiers 13a and 13b, and the peak amplifier is composed of a pair of differential amplifiers 17a and 17b (see Figure 6 ), but in order to simplify the description of the overall structure of the power amplifier device 100, an example of using a carrier amplifier 13 and a peak amplifier 17 that are single-ended rather than a pair of differential amplifiers is cited for description.

[0033] (First Embodiment)

[0034] Figure 1 1 is a diagram showing the overall circuit structure of the power amplifier device of the first embodiment. The power amplifier device 100 includes a power amplifier circuit 1. The power amplifier circuit 1 includes an amplifier 2, a bias circuit 3, and a Doherty amplifier circuit 10. The Doherty amplifier circuit 10 includes a splitter 11, a carrier amplifier 12 of a primary stage (driver stage), a carrier amplifier 13 of a final stage (power stage), a bias circuit 14, a bias circuit 15, a peak amplifier 16 of a primary stage (driver stage), a peak amplifier 17 of a final stage (power stage), a bias circuit 18, a bias circuit 19, a coupler 40, a control circuit 21, and an adjustment circuit 60.

[0035] The control circuit 21 includes a detection circuit 22 and a drive level detection circuit 26. The number of stages of the Doherty amplifier circuit 10 is set to two, but the present disclosure is not limited thereto. The number of stages of the Doherty amplifier circuit 10 may be one, or three or more.

[0036] The bias circuit 3 applies a bias to the amplifier 2. A high-frequency signal RF (Radio-Frequency) is input to the amplifier 2. The frequency of the high-frequency signal RFin is, for example, about several GHz. The amplifier 2 amplifies the input high-frequency signal RFin. Then, the amplifier 2 outputs the amplified high-frequency signal RF1 to the splitter 11. In addition, the high-frequency signal RF is sometimes referred to as the signal RF below.

[0037] The splitter 11 is a 90° hybrid circuit. The 90° hybrid circuit divides the high-frequency signal RF1 into a high-frequency signal RF2 and a high-frequency signal RF5, which have phases that differ from each other by approximately 90°, and outputs the high-frequency signal RF2 to the carrier amplifier 12, and outputs the high-frequency signal RF5 to the peak amplifier 16. In addition, "approximately 90°" includes not only a phase of 90°, but also a phase of more than 45° and less than 135°. In addition, the phase of the high-frequency signal RF2 lags the phase of the high-frequency signal RF5 by 90°. The power of the high-frequency signal RF2 is the same as the power of the high-frequency signal RF5.

[0038] The bias circuit 14 applies a bias to the carrier amplifier 12. The bias circuit 15 applies a bias to the carrier amplifier 13. The carrier amplifier 12 outputs a high-frequency signal RF3 obtained by amplifying the high-frequency signal RF2 to the carrier amplifier 13. The carrier amplifier 13 outputs a high-frequency signal RF4 obtained by amplifying the high-frequency signal RF3 to the coupler 40.

[0039] The bias circuit 18 applies a bias to the peak amplifier 16. The bias circuit 19 applies a bias to the peak amplifier 17. The peak amplifier 16 outputs a high-frequency signal RF6 obtained by amplifying the high-frequency signal RF5 to the peak amplifier 17. The peak amplifier 17 outputs a high-frequency signal RF7 obtained by amplifying the high-frequency signal RF6 to the coupler 40.

[0040] The coupler 40 couples the high frequency signal RF4 with the high frequency signal RF7. In addition, the coupler 40 couples the high frequency signal RF7 with the high frequency signal RF4 by delaying its phase by 90°. In addition, the adjustment circuit 60 is a circuit for matching the impedance between the output terminals of the carrier amplifier 13 and the peak amplifier 17 and the output terminal of the power amplifier circuit 1. The details of the coupler 40 and the adjustment circuit 60 will be described later.

[0041] The drive level detection circuit 26 outputs a signal S1 indicating the drive level (operation level) of the carrier amplifier 13 to the detection circuit 22 based on the high frequency signal RF4 outputted from the carrier amplifier 13 .

[0042] A high-frequency signal RFin and a signal S1 are input to a detection circuit 22. In the present disclosure, it is also possible that a high-frequency signal RF1 is input to the detection circuit 22 instead of the high-frequency signal RFin, or a high-frequency signal RF2 is input to the detection circuit 22 instead of the high-frequency signal RFin.

[0043] Based on the high-frequency signal RFin and the signal S1, the detection circuit 22 outputs a signal S2 for controlling the bias circuit 18 and the bias circuit 19 to the bias circuit 18 and the bias circuit 19. Moreover, the bias circuit 18 applies a bias to the peak amplifier 16 based on the signal S2. The bias circuit 19 applies a bias to the peak amplifier 17 based on the signal S2. That is, the detection circuit 22 controls the biases of the peak amplifier 16 and the peak amplifier 17 based on the high-frequency signal RFin and the signal S1.

[0044] Figure 2 is a schematic diagram showing an example of the relationship between the power of the high-frequency signal of the power amplifier circuit according to the first embodiment and the signal output from the detection circuit. In Figure 2 it, the horizontal axis represents the power of the high-frequency signal RFin, and the vertical axis represents the signal S2 output from the detection circuit 22.

[0045] The detection circuit 22 makes the rising point of the signal S2 different according to the signal S1. In addition, the rising point of the signal S2 is sometimes referred to as a threshold value. The waveform 31 represents the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively low. The waveform 32 represents the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively medium. The waveform 33 represents the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively high.

[0046] As shown in the waveform 31, when the drive level of the carrier amplifier 13 is relatively low, when the power of the high-frequency signal RFin becomes the value A, the detection circuit 22 raises the signal S2. In the range where the power of the high-frequency signal RFin is above the value A, the greater the power of the high-frequency signal RFin, the greater the signal S2 made by the detection circuit 22.

[0047] As shown in the waveform 32, when the drive level of the carrier amplifier 13 is relatively medium, when the power of the high-frequency signal RFin becomes the value B (B < A), the detection circuit 22 raises the signal S2. In the range where the power of the high-frequency signal RFin is above the value B, the greater the power of the high-frequency signal RFin, the greater the signal S2 made by the detection circuit 22.

[0048] As shown in waveform 33, when the driving level of carrier amplifiers 13 is relatively high and the power of high-frequency signal RFin becomes value C (C < B), detection circuit 22 causes signal S2 to rise. In the range where the power of high-frequency signal RFin is above value C, the larger the high-frequency signal RFin, the larger signal S2 becomes in detection circuit 22.

[0049] When a high-power high-frequency signal RFin, which is the main cause of saturation of carrier amplifiers 12 and 13, is input, detection circuit 22 causes bias circuits 18 and 19 to activate peak amplifiers 16 and 17 by outputting signal S2 to bias circuits 18 and 19. As a result, carrier amplifiers 12 and 13 are basically not saturated.

[0050] Here, the response speed of detection circuit 22 is important. Since detection circuit 22 detects high-frequency signal RFin, it can respond extremely quickly compared to the case of detecting saturation of carrier amplifiers in the prior art. Thus, even when the power of high-frequency signal RFin rises for a short time, detection circuit 22 immediately responds to cause bias circuits 18 and 19 to activate peak amplifiers 16 and 17, so that carrier amplifiers 12 and 13 are not saturated, even instantaneously.

[0051] On the other hand, in the case where the temperature or other surrounding environment changes (for example, when the gain of carrier amplifiers 12 and 13 increases at extremely low temperatures, etc.), even if the power of high-frequency signal RFin is small, carrier amplifiers 12 and 13 may saturate. To be able to handle such a situation as well, detection circuit 22 detects signal S1 indicating the driving level of carrier amplifiers 12 and 13, and immediately activates peak amplifiers 16 and 17 even when the power of high-frequency signal RFin is small when carrier amplifiers 12 and 13 are approaching saturation.

[0052] Detection circuit 22 detects high-frequency signal RFin. Therefore, even if it takes time to detect the driving level of carrier amplifiers 12 and 13, it can cause bias circuits 18 and 19 to activate peak amplifiers 16 and 17 without saturating carrier amplifiers 12 and 13. As a result, Doherty amplifier circuit 10 can suppress the degradation of the quality of high-frequency signal RFout.

[0053] It is also possible to consider that detection circuit 22 operates feedforwardly based on high-frequency signal RFin and feedbackly based on signal S1. In addition, in the present embodiment, signal S2 for controlling bias circuit 18 and bias circuit 19 is output to each of bias circuit 18 and bias circuit 19, but the present disclosure may also be to output signal S2 only to one of bias circuit 18 and bias circuit 19.

[0054] (A Specific Example of a Detection Circuit and a Drive Level Detection Circuit)

[0055] Figure 3 FIG. 1 is a diagram showing a specific example of a detection circuit and a drive level detection circuit of the power amplifier circuit according to the first embodiment. Figure 3 In FIG. 1 , circuit elements for applying a bias to the detection circuit 22 are also shown. Figure 3 The low-pass filter 25A and the bias circuits 18 and 19 are shown. The low-pass filter 25A can be omitted when a good differential signal can be obtained. The bias circuits 18 and 19 can be omitted when the bias-providing transistor (amplifying transistor) is small.

[0056] The detection circuit 22 includes a transistor Q DE1 and Q DE2 , and resistor R DEE1 and R DEE2 .

[0057] In the present disclosure, each transistor is set as a bipolar transistor, but the present disclosure is not limited to this. Regarding the bipolar transistor, a heterojunction bipolar transistor (HBT) is exemplified, but the present disclosure is not limited to this. The transistor may also be a field effect transistor (FET), for example. The transistor may also be a multi-finger transistor (multi-finger transistor) formed by electrically connecting a plurality of unit transistors in parallel. The unit transistor refers to the minimum structure that can constitute a transistor.

[0058] Transistor Q DE1 The collector of transistor Q is electrically connected to the power supply potential Vcc. DE1 The emitter and resistor R DEE1 That is, transistor Q DE1 With resistor R DEE1 Connected in emitter follower mode. Transistor Q DE1 and resistor R DEE1 A first emitter follower circuit 22a is constructed.

[0059] The detection circuit 22 may include a source follower circuit instead of the first emitter follower circuit 22a.

[0060] Transistor Q DE2 The collector of transistor Q is electrically connected to the power supply potential Vcc. DE2 The emitter and resistor R DEE2 That is, transistor Q DE2 With resistor RDEE2 Connected in emitter follower mode. Transistor Q DE2 and resistor R DEE2 A second emitter follower circuit 22b is constructed.

[0061] The detection circuit 22 may include a source follower circuit instead of the second emitter follower circuit 22b.

[0062] Resistor R DEE1 The other end of the resistor R DEE2 The output current I1 of the detection circuit 22 is the sum of the output current of the first emitter follower circuit 22a and the output current of the second emitter follower circuit 22b.

[0063] Resistor R DEBB , R DEB1 and R DEB2 and transistor Q DE5 , Q DE6 and Q DE7 For transistor Q DE1 and Q DE2 A bias voltage is applied to the base.

[0064] Resistor R DEBB One end of the resistor R DEB1 One end and the resistor R DEB2 One end is electrically connected.

[0065] Resistor R DEBB The other end of the transistor Q DE7 The collector and base of transistor Q are electrically connected. DE7 Connected in diode form. Transistor Q DE7 The emitter of transistor Q DE6 The collector and base of transistor Q are electrically connected. DE6 Connected in diode form. Transistor Q DE6 The emitter of transistor Q DE5 The collector and base of transistor Q are electrically connected. DE5 Connected in diode form. Transistor Q DE5 The emitter of is electrically connected to the reference potential GND. As for the reference potential GND, a ground potential is exemplified, but the present disclosure is not limited to this.

[0066] To resistor R DEBB One end of the resistor R DEB1 One end and the resistor R DEB2 One end of the input bias current BIAS1. Resistor R DEBB , transistor Q DE7 , transistor Q DE6 and transistor QDE5 This voltage is passed through the resistor R DEB1 is input to transistor Q DE1 The base of the DEB2 is input to transistor Q DE2 The base of.

[0067] Transistor Q DE3 and Q DE4 Each transistor in the transistor Q DE5 Connected in current mirror mode. Transistor Q DE3 The collector of transistor Q DE1 The base of transistor Q is electrically connected. DE3 Ability to adjust transistor Q DE1 The base current of transistor Q DE4 The collector of transistor Q DE2 The base of transistor Q is electrically connected. DE4 Ability to adjust transistor Q DE2 of the base current.

[0068] The high-frequency signal RFin is converted into a differential signal, and the high-frequency signals IN1 and IN2 are input to transistors Q DE1 The base of transistor Q DE2 For example, high-frequency signals IN1 and IN2 can be obtained by inputting high-frequency signal RFin to a balanced-unbalanced transformer.

[0069] Resistor R DEE1 The other end and resistor R DEE2 The other end of is electrically connected to the constant current circuit 24. The constant current circuit 24 includes a transistor Q DE11 The constant current circuit 24 is a current bias circuit for the detection circuit 22 .

[0070] The driving level detection circuit 26 includes a resistor R MO1 , R MO2 , R MO3 , R MO4 and R MO5 , transistor Q MO1 , Q MO2 , Q MO4 , Q MO5 , Q MO6 and Q MO7 , and capacitor C MO1 .

[0071] In addition, in this description, it is assumed that the carrier amplifier 13 (refer to Figure 1 ) is a pair of differential amplifiers (differential amplifiers), and is set as a carrier amplifier 13 to output high-frequency signals RF71 and RF72 that constitute a pair of differential signals.

[0072] To transistor Q MO1 The emitter of the transistor Q is used to input the high frequency signal RF71. MO1 The emitter of is electrically connected to the output terminal of an amplifier in the carrier amplifier 13 (the collector or drain of the output transistor).

[0073] To transistor Q MO2 The emitter of the transistor Q is used to input the high frequency signal RF72. MO2 The emitter of is electrically connected to the output terminal of another amplifier in the carrier amplifier 13 (the collector or drain of the output transistor).

[0074] Transistor Q MO1 The base of transistor Q MO2 The base of transistor Q is electrically connected to node N3. MO1 The collector of transistor Q MO2 The collector of is electrically connected to the node N4.

[0075] Resistor R MO1 , R MO2 and R MO3 and transistor Q MO4 A voltage is applied to the node N3. That is, the resistor R MO1 , R MO2 and R MO3 and transistor Q MO4 For transistor Q MO1 The base of transistor Q MO2 The base is biased.

[0076] Resistor R MO3 One end of the resistor R is electrically connected to the power supply potential Vcc. MO3 The other end is connected to the node N3 and the transistor Q MO4 The collector and resistor R MO1 One end of the resistor R MO1 The other end of the transistor Q MO4 The base and resistor R MO2 One end of transistor Q is electrically connected. MO4 The emitter and resistor R MO2 The other end of the resistor R is electrically connected to the reference potential GND. MO1 and R MO2 and transistor Q MO4 A constant voltage is generated, and this voltage becomes the voltage of the node N3.

[0077] Resistor R MO4 and R MO5 and transistor Q MO6 and Q MO7A voltage is applied to node N4. That is, the resistor R MO4 and R MO5 and transistor Q MO6 and Q MO7 For transistor Q MO1 The collector of transistor Q MO2 The collector bias is applied.

[0078] Resistor R MO5 One end of the resistor R is electrically connected to the power supply potential Vcc. MO5 The other end of the transistor Q MO6 The collector and base of transistor Q are electrically connected. MO6 Connected in diode form. Transistor Q MO6 The emitter of transistor Q MO7 The collector and base of transistor Q are electrically connected. MO7 Connected in diode form. Transistor Q MO7 The emitter of is electrically connected to the reference potential GND. MO4 One end of the resistor R MO5 The other end of the transistor Q MO6 The collector and base are electrically connected. MO4 The other end of transistor Q is electrically connected to node N4. MO6 and Q MO7 This voltage is passed through the resistor R MO4 This becomes the voltage of the node N4.

[0079] Transistor Q MO5 The collector and base of transistor Q are electrically connected to node N4. MO5 Connected in diode form. Transistor Q MO5 The emitter of the capacitor C MO1 One end of the capacitor is electrically connected. MO1 The other end is electrically connected to the reference potential GND.

[0080] Transistor Q MO5 The signal S1 is output from the emitter. That is, in this embodiment, the transistor Q MO5 The emitter voltage of capacitor C is equivalent to signal S1. MO1 The high frequency components of signal S1 are branched and smoothed.

[0081] Resistor R MO1 , R MO2 and R MO3 and transistor Q MO4 As long as it can output a roughly constant voltage, it can be replaced with a constant voltage source. MO5 and transistor QMO6 and Q MO7 As long as it can output a roughly constant voltage, it can be replaced by a constant voltage source. MO5 As long as a substantially constant voltage drop is generated, it is possible to consider replacing it with a constant voltage source.

[0082] The low-pass filter 25B includes a resistor R LPF and capacitor C LPF .

[0083] Resistor R LPF One end of the transistor Q MO5 The emitter is electrically connected to the resistor R LPF The other end of the capacitor C LPF One end of the capacitor is electrically connected. LPF The other end is electrically connected to the reference potential GND.

[0084] Resistor R LPF The other end of the capacitor C LPF One end of the transistor Q DE11 The low-pass filter 25B allows the low-frequency band of the signal S1 to pass through and output to the transistor Q DE11 The base of.

[0085] The low pass filter 25A includes a capacitor C env . Capacitor C env One end of the resistor R DEE1 The other end of the resistor R DEE2 The other end of the transistor Q DE11 The collector of capacitor C is electrically connected to env The other end is electrically connected to the reference potential GND.

[0086] Capacitor C env The output current I1 of the detection circuit 22 and the transistor Q DE11 The difference between the collector current I2 and the capacitor C is used to charge or discharge. env The voltage of capacitor C is signal S2. env The high-frequency component (for example, carrier frequency signal component) of the signal S2 is terminated at the reference potential GND to remove it, and only the low-frequency component is passed. env It is possible to appropriately apply a bias to the bias circuits 18 and 19 at the subsequent stage and the bias-applying target transistor (amplifier transistor).

[0087] Bias circuit 18 includes transistor Q DE8 , Q DE9 and Q DE10 In addition, the bias circuit 19 (refer to Figure 1) is the same as the circuit structure of the bias circuit 18, so the description is omitted.

[0088] Transistor Q DE9 Connected in diode form. Transistor Q DE9 The collector and base of the capacitor C env One end of transistor Q is electrically connected. DE9 The emitter of transistor Q DE8 The collector and base of transistor Q are electrically connected. DE8 Connected in diode form. Transistor Q DE8 The emitter of transistor Q is electrically connected to the reference potential GND. DE9 and Q DE8 Flow through capacitor C env The voltage corresponds to the current.

[0089] Transistor Q DE10 The collector of transistor Q is electrically connected to the power supply potential Vcc. DE10 The base of transistor Q DE9 The collector and base of transistor Q are electrically connected. DE10 The emitter voltage is used as the bias voltage BIAS 16 (BIAS 17 ) is output to the peak amplifier 16 (17).

[0090] Figure 4 It is a diagram showing an equivalent circuit of a specific example of a detector circuit and a drive level detection circuit of the power amplifier circuit according to the fifth embodiment. Figure 4 The constant voltage source V MO1 Equivalent to Figure 3 The resistance R MO1 , R MO2 and R MO3 and transistor Q MO4 . Figure 4 The constant voltage source V MO2 Equivalent to Figure 3 The resistance R MO5 and transistor Q MO6 and Q MO7 . Figure 4 The constant voltage source V MO3 Equivalent to Figure 3 The transistor Q MO5 .

[0091] (Operation of the drive level detection circuit)

[0092] Reference Figure 4 The operation of the drive level detection circuit 26 is described with reference to an equivalent circuit of FIG.

[0093] Generally speaking, the output terminal voltage of the final-stage carrier amplifier 13 oscillates with the voltage amplitude of the high-frequency signal around the bias voltage. When the final-stage carrier amplifier 13 is saturated, the voltage amplitude of the high-frequency signal becomes large and is roughly equal to the bias voltage. In this case, during the oscillation cycle of the high-frequency signal, there will be a moment when the output terminal voltage approaches 0V. This moment is a moment when no amplification effect is obtained, resulting in a phenomenon such as amplifier saturation.

[0094] The circuit of this embodiment detects the drive level of the carrier amplifier 13 using the principle of saturation.

[0095] Specifically, within the period of the high-frequency signals RF71 and RF72, only when the voltage of the high-frequency signals RF71 and RF72 becomes higher than that of the constant voltage source V MO1 The voltage minus the voltage of transistor Q MO1 and Q MO2 The threshold voltage corresponding to the voltage drop obtained during the low voltage period, transistor Q MO1 and Q MO2 Become connected.

[0096] When the carrier amplifier 13 operates with a sufficient margin for saturation, the transistor Q MO1 and Q MO2 There is no period of on-state, so no collector current flows. Therefore, the resistor R MO4 No current flows, so no voltage drop occurs. Therefore, signal S1 becomes the constant voltage source V MO2 The voltage minus the constant voltage source V MO3 The voltage obtained by the voltage.

[0097] On the other hand, when the amplitudes of high-frequency signals RF71 and RF72 increase, transistor Q MO1 and Q MO2 The period of on-state occurs, so the collector current flows. Therefore, the resistor R MO4 Current flows, thus creating a voltage drop.

[0098] When the amplitudes of high frequency signals RF71 and RF72 further increase, transistor Q MO1 and Q MO2 The period of being in the on state becomes longer, so more collector current flows. Therefore, the resistor R MO4 More current flows, so a greater voltage drop occurs.

[0099] Therefore, as the driving level of the carrier amplifier 13 increases, the signal S1 becomes a voltage which is lower than the voltage when the high-frequency signals RF71 and RF72 are small signals by the amount of the resistor R. MO4 The voltage drop at the point is equivalent to the voltage of the voltage.

[0100] Next, the operation of the detection circuit 22 will be described.

[0101] Transistor Q DE1 The high frequency signal IN1 is transistor Q DE1 When the threshold voltage is above , it becomes on and outputs emitter current. DE2 The high frequency signal IN2 is transistor Q DE2 When the threshold voltage is above , it becomes the on state and outputs the emitter current.

[0102] That is, the larger the amplitude of the high-frequency signals IN1 and IN2 (the larger the power of the high-frequency signal RFin), the larger the output current of the detection circuit 22. On the other hand, the smaller the amplitude of the high-frequency signals IN1 and IN2 (the smaller the power of the high-frequency signal RFin), the smaller the output current of the detection circuit 22.

[0103] On the other hand, as described above, when the drive level of the carrier amplifier 13 is relatively high (close to saturation), the signal S1 becomes a relatively low voltage, and when the drive level of the carrier amplifier 13 is relatively low (when the amplification factor is reduced), the signal S1 becomes a relatively high voltage.

[0104] That is, the higher the driving level of the carrier amplifier 13 is (the closer to saturation), the higher the transistor Q DE11 In addition, the lower the driving level of the carrier amplifier 13 is (the lower the amplification factor is), the smaller the collector current I2 is. DE11 The larger the collector current I2.

[0105] In summary, the higher the driving level of the carrier amplifier 13 is (the closer to saturation), the larger the capacitor C env In addition, the lower the driving level of the carrier amplifier 13 is (the lower the amplification factor is), the capacitor C env In addition, the greater the power of the high-frequency signal RFin, the greater the capacitor C env In addition, the lower the power of the high-frequency signal RFin, the lower the capacitor C env The voltage is more difficult to become higher.

[0106] Figure 5 FIG. 1 is a diagram showing an example of the relationship between the power of a high frequency signal and the bias voltage applied to the peak amplifier in the power amplifier circuit of the first embodiment. Figure 5 In FIG. 1 , the horizontal axis represents the power of the high-frequency signal RFin, and the vertical axis represents the bias voltage BIAS applied from the bias circuit 18 (19) to the peak amplifier 16 (17). 16 (BIAS17 ).

[0107] Waveform 34 shows the bias voltage BIAS when the drive level of the carrier amplifier 13 is relatively low. 16 (BIAS 17 Waveform 35 shows the bias voltage BIAS when the drive level of the carrier amplifier 13 is relatively medium. 16 (BIAS 17 Waveform 36 shows the bias voltage BIAS when the drive level of the carrier amplifier 13 is relatively high. 16 (BIAS 17 ) changes.

[0108] As shown in waveform 36, when the driving level of the carrier amplifier 13 is relatively high, even if the power of the high-frequency signal RFin is low, the detection circuit 22 can activate the peak amplifiers 16 and 17. Conversely, as shown in waveform 34, when the driving level of the carrier amplifier 13 is relatively low, the detection circuit 22 can delay the activation of the peak amplifiers 16 and 17 until the power of the high-frequency signal RFin becomes high.

[0109] Therefore, when the driving level of the carrier amplifier 13 is in a relatively high state (close to saturation), it is sufficient to reduce the current of the constant current circuit 24 so that the peak amplifiers 16 and 17 can be started even if the power of the high-frequency signal RFin is low. On the contrary, when the driving level of the carrier amplifier 13 is relatively low, it is not necessary to start the peak amplifiers 16 and 17 before the power of the high-frequency signal RFin increases, so it is sufficient to increase the current of the constant current circuit 24. That is, if the voltage BIAS2 input to the constant current circuit 24 is set to a voltage that changes complementarily with the driving level of the carrier amplifier 13, the target operation can be achieved in the circuit as a whole.

[0110] The response of the detection circuit 22 becomes faster due to the following reason.

[0111] First, the first emitter follower circuit 22a and the second emitter follower circuit 22b perform differential operation. Therefore, compared with the case where the emitter follower circuit performs single-ended operation, the capacitor C env The capacity of capacitor C is small. env The delay at 2 is small, so the change of signal S2 becomes faster. In other words, the response of detection circuit 22 becomes faster.

[0112] Second, the emitter follower circuit is a circuit that can output a large current. Therefore, the first emitter follower circuit 22a and the second emitter follower circuit 22b can each output a large current. In other words, the detector circuit 22 can output a large output current I1. Thus, the detector circuit 22 can quickly detect the capacitor C env That is, the rising response of the detection circuit 22 becomes faster.

[0113] Third, transistor Q DE11 Capacitor C can be made to env discharge. Therefore, transistor Q DE11 Capacitor C can be quickly env That is, the falling response of the detection circuit 22 becomes faster.

[0114] Figure 6 1 is a diagram showing a circuit structure of a Doherty circuit of a power amplifier device according to the first embodiment. Next, the details of the Doherty amplifier circuit 10 according to the first embodiment will be described. Figure 6 As shown, the Doherty amplifier circuit 10 of the power amplifier device 100 has two splitters 30A, 30B, a pair of differential amplifiers 13a, 13b, a pair of differential amplifiers 17a, 17b, a coupler 40 (balanced-unbalanced transformer 41 for carrier, balanced-unbalanced transformer 51 for peak), an adjustment circuit 60 and a load (antenna) 70.

[0115] The splitter 30A will be used to divide the carrier amplifier 12 (also refer to Figure 1 ) output high frequency signal RF3 (refer to Figure 1 ) is split and output to a pair of differential amplifiers 13a and 13b. The splitter 30B outputs the peak amplifier 16 (see also Figure 1 ) output high frequency signal R6 (refer to Figure 1 ) are separated and output to a pair of differential amplifiers 17a and 17b.

[0116] A pair of differential amplifiers 13a and 13b constitute a carrier amplifier 13 (see Figure 1 A pair of differential amplifiers 17a and 17b constitutes the peak amplifier 17 (see Figure 1 In the present disclosure, the type of the differential amplifier is not particularly limited, and may be, for example, a bipolar transistor such as a heterojunction bipolar transistor (HBT) or a field effect transistor such as a MOSFET (Metal-oxide-semiconductor Field Effect Transistor).

[0117] The coupler 40 includes a carrier balun 41 and a peak balun 51. The carrier balun 41 includes a primary carrier balun 42 and a secondary carrier balun 43 magnetically coupled to the primary carrier balun 42. Both ends of the primary carrier balun 42 are connected to a pair of differential amplifiers 13a and 13b. A power supply potential Vcc is supplied to a midpoint 42a of the primary carrier balun 42.

[0118] The peak balun 51 includes a primary-side peak balun 52 and a secondary-side peak balun 53 magnetically coupled to the primary-side peak balun 52. Both ends of the primary-side peak balun 52 are connected to a pair of differential amplifiers 17a and 17b. A power supply potential Vcc is supplied to a midpoint 52a of the primary-side peak balun 52.

[0119] One end of the secondary side peak balun 53 is connected to the reference potential GND. The other end of the secondary side peak balun 53 is connected to one end of the secondary side carrier balun 43. Thus, the secondary side carrier balun 43 and the secondary side peak balun 53 are connected in series.

[0120] The adjustment circuit 60 of the first embodiment has a capacitor 62. The capacitor 62 is a component for the adjustment circuit of this embodiment and corresponds to a surface mount component. The other end of the secondary side carrier balun 43 is connected to a load (antenna) 70. In addition, one end of the capacitor 62 is connected to one end of the secondary side carrier balun 43, and the other end of the capacitor 62 is connected to the reference potential GND, and the capacitor 62 is connected in parallel with the secondary side peak balun 53.

[0121] According to the present embodiment, the high frequency signal RF7 (see FIG. 1 ) input from the primary side peak balun 52 to the secondary side peak balun 53 is Figure 1 ) is delayed by 90° by capacitor 62. Then, the high-frequency signal RF7 is combined with the high-frequency signal RF4 (refer to Figure 1 ) coupling. In addition, the high-frequency signal RFout obtained by coupling (refer to Figure 1 ) is output as electromagnetic waves from the load (antenna) 70. Next, the layout of the power amplifier device 100 according to the first embodiment will be described.

[0122] Figure 7This is a diagram showing a plan view of the surface of the substrate in the power amplifier device according to the first embodiment. Figure 8 It is a diagram for explaining the layout of the second insulating layer in the power amplifier device according to the first embodiment. Fig. 9 It is a diagram for explaining the layout of the third insulating layer in the power amplifier device according to the first embodiment.

[0123] like Figure 7 As shown, the power amplifier device 100 has a substrate 101. When the substrate 101 is viewed from above, the substrate 101 is in a rectangular shape. That is, the surface 102 of the substrate 101 is in a rectangular shape. In addition, the surface 102 has a pair of short sides 102a and a pair of long sides 102b.

[0124] Hereinafter, the direction parallel to the short side 102a in the plane direction parallel to the surface 102 is referred to as the first plane direction X. The direction parallel to the first plane direction X and parallel to the long side 102b (the direction intersecting the first plane direction X) is referred to as the second plane direction Y. In addition, the present disclosure is not limited to the example in which the first plane direction X and the second plane direction Y are orthogonal, and the first plane direction X and the second plane direction Y may also intersect.

[0125] An integrated circuit 90 is mounted on a surface 102 of a substrate 101. The integrated circuit 90 is an HBT (Heterojunction Bipolar Transistor). The integrated circuit 90 includes splitters 30A and 30B and a pair of differential amplifiers 13a, 13b, 17a, and 17b (see Figure 6 ) functions.

[0126] Hereinafter, the direction in which the integrated circuit 90 and the substrate 101 are arranged is referred to as a stacking direction. In the stacking direction, the direction in which the substrate 101 is arranged when viewed from the integrated circuit 90 is referred to as a first stacking direction, and the direction opposite to the first stacking direction is referred to as a second stacking direction.

[0127] like Figures 7 to 9 As shown, the substrate 101 is a multi-layer substrate having a plurality of insulating layers arranged in the stacking direction. Hereinafter, three insulating layers arranged in sequence from the second stacking direction among the plurality of insulating layers are referred to as first insulating layers 110 (see Figure 7 )、the second insulating layer 120 (refer to Figure 8 ) and the third insulating layer 130 (refer to Fig. 9 ). In addition, the surface of the first insulating layer 110 in the second stacking direction constitutes the surface 102.

[0128] Conductive layers formed by patterning are provided on each insulating layer of the substrate 101. The electrodes, wirings, and baluns (carrier baluns 41, peak baluns 51) described below are composed of conductive layers. In addition, in the drawings, hatching is indicated on the conductive layers to facilitate understanding of the range of the conductive layers.

[0129] like Figure 7 As shown in FIG. 1 , a primary side peak balanced-unbalanced transformer 52 is provided on the surface 102 (first insulating layer 110). Figure 8 As shown in FIG. 1 , a primary-side carrier balun 42 and a secondary-side peak balun 53 are provided on the second insulating layer 120. Fig. 9 As shown in FIG. 1 , the secondary-side carrier balun 43 is provided on the third insulating layer 130. Each balun is formed in a C-shape when viewed from the stacking direction.

[0130] like Figure 7 As shown in FIG. 1 , electrodes 111, 112, 113, and 114 are provided as conductive layers on the surface 102 (first insulating layer 110). The electrodes 111, 112, 113, and 114 are arranged at intervals in the second plane direction Y. In addition, the electrodes 111, 112, 113, and 114 are arranged in a range overlapping with the integrated circuit 90 and connected to the output terminal (not shown) of the integrated circuit 90. Thus, the input from the differential amplifier 13a (see FIG. 1 ) to the electrode 111 is Figure 6 ) output signal. The electrode 112 is input from the differential amplifier 13b (refer to Figure 6 ) output signal. The electrode 113 is input from the differential amplifier 17a (refer to Figure 6 ) output signal. The electrode 114 is input from the differential amplifier 17b (refer to Figure 6 ) output signal.

[0131] The electrodes 113 and 114 are connected to both ends of the primary side peak balanced-unbalanced transformer 52. In addition, the electrodes 111 and 112 are connected to one ends of wirings 117 and 118 extending in the first plane direction X. Interlayer connection conductors 111a and 112a are provided at the other ends of the wirings 117 and 118. Figure 8 As shown, the interlayer connection conductors 111a and 112a extend to the second insulating layer 120 and are connected to both ends of the primary carrier balun 42. In each figure, the interlayer connection conductors are blank (without hatching) to make them easier to see.

[0132] In addition, wiring 115 is provided on the surface 102 (first insulating layer 110). In addition, a power supply potential Vcc ( Figure 7 Not shown in the figure. Figure 6 ). In addition, the power supply potential Vcc applied to the wiring 115 can be an external voltage generated outside the substrate 101, and the present disclosure is not particularly limited. The primary side peak balanced-unbalanced transformer 52 is connected to the wiring 115 via the junction point (midpoint 52a). The primary side carrier balanced-unbalanced transformer 42 is connected to the wiring 115 via the junction point (midpoint 42a) and the interlayer connection conductor 116a. Thus, the power supply potential Vcc is provided to the primary side peak balanced-unbalanced transformer 52 and the primary side carrier balanced-unbalanced transformer 42.

[0133] like Figure 8 As shown in FIG. 1 , an interlayer connection conductor 127 is provided at one end 53a of the secondary side peak balanced-unbalanced transformer 53. The interlayer connection conductor 127 extends to the insulating layer (not shown) below the fourth layer and is connected to the reference potential GND. An interlayer connection conductor 131 is provided at the other end 53b of the secondary side peak balanced-unbalanced transformer 53. Fig. 9 As shown, the interlayer connection conductor 131 extends to the third insulating layer 130 and is connected to one end 43a of the secondary side carrier balun 43. Based on the above, the secondary side peak balun 53 is connected in series with the secondary side carrier balun 43. In addition, although not particularly shown, the other end 43b of the secondary side carrier balun 43 is connected to the load (antenna 70).

[0134] like Figure 7 As shown, electrodes 160 and 161 are provided on the surface 102 (first insulating layer 110) and are arranged at intervals in the first plane direction X. The capacitor 62 (see Figure 6 ) are welded to the electrodes 160 and 161 in a manner overlapping the electrodes 160 and 161. In addition, interlayer connection conductors 160a and 161a are provided on the electrodes 160 and 161. Fig. 9 As shown, the interlayer connection conductor 160a extends to the second insulating layer 120 and is connected to the reference potential GND. In addition, the interlayer connection conductor 161a extends to the second insulating layer 120 and is connected to the other end 53b of the secondary side peak balanced-unbalanced transformer 53. Thus, the capacitor 62 is connected in parallel with the secondary side peak balanced-unbalanced transformer 53.

[0135] As described above, according to the first embodiment, Figures 7 to 9As shown in FIG. 1 , when viewed from the stacking direction, each balun (carrier balun 41, peak balun 51) is arranged on one side in the first plane direction X1 relative to the integrated circuit 90. In addition, each balun (carrier balun 41, peak balun 51) is arranged to be separated from each other in the second plane direction Y so as not to generate electromagnetic interference.

[0136] Fig.10 Is magnification Figure 7 In addition, Fig.10 As shown in FIG. 1 , when viewed from the stacking direction, the capacitor 62, which is one of the adjustment circuit components, is arranged between the carrier balun 41 and the peak balun 51. That is, in this embodiment, the region that has been an ineffective region is used as a space for arranging the capacitor 62. Therefore, there is no need to separately provide a space for arranging the capacitor 62 on the surface 102 of the substrate 101, and the power amplifier device 100 is miniaturized.

[0137] The primary-side peak balun 52 is separated from the electrodes 160 and 161 by a distance L1 . This is to prevent the solder joining the capacitor 62 to the electrodes 160 and 161 from being connected to the primary-side peak balun 52 .

[0138] Furthermore, assuming that the primary-side carrier balun 42 is disposed on the surface 102 of the substrate 101, for the same reason, the primary-side carrier balun 42 needs to be disposed in a direction farther from the electrodes 160 and 161 than the imaginary line L2 (the imaginary line at a distance L1 from the electrodes 160 and 161). That is, when the primary-side carrier balun 42 and the primary-side peak balun 52 are disposed on the surface 102 of the substrate 101, the interval between the primary-side carrier balun 42 and the primary-side peak balun 52 is at least L3.

[0139] On the other hand, in the present embodiment, the primary-side carrier balun 42 is not provided on the surface 102 (first insulating layer 110) of the substrate 101. That is, the solder joining the capacitor 62 to the electrodes 160 and 161 cannot be connected to the primary-side carrier balun 42. Therefore, the primary-side carrier balun 42 can be arranged closer to the primary-side peak balun 52 beyond the imaginary line L2.

[0140] In addition, when viewed from the stacking direction, the carrier balun 41 overlaps the electrode 161. That is, the interval between the carrier balun 41 and the peak balun 51 of the present embodiment is smaller by the distance L4 than the interval L3 when both the primary-side carrier balun 42 and the primary-side peak balun 52 are arranged on the substrate 101. Therefore, the power amplifier device 100 is miniaturized.

[0141] The first embodiment has been described above. Next, a modification example obtained by partially modifying the first embodiment will be described. In the following description, the differences from the first embodiment will be focused on.

[0142] (First Modification)

[0143] Fig.11 FIG. 1 is a top view showing the surface of the substrate of the power amplifier device of the first modification. The difference from the first embodiment is that Fig.11 As shown, the power amplifier device 100A of the first modified example not only arranges the carrier balun 41 on the insulating layer closer to the first stacking direction than the surface 102, but also arranges the peak balun 51 on the insulating layer closer to the first stacking direction than the surface 102. That is, in the first modified example, the primary-side peak balun 52 is arranged on the second insulating layer 120, and the secondary-side peak balun 53 is arranged on the third insulating layer 130.

[0144] As described above, even in the first modification, the power amplifier device 100A can be miniaturized in the same manner as in the first embodiment. In the first modification, the peak balun 51 does not overlap the electrode 161 when viewed from the stacking direction, but in the present disclosure, the peak balun 51 can overlap the electrode 161 in the same manner as the carrier balun 41, thereby further miniaturizing the device. This is preferred.

[0145] The first embodiment and the first modified example are described above, but the present disclosure is not limited thereto. For example, in the first embodiment, an example is described in which one of the two baluns is disposed on the surface 102, but the balun disposed on the surface 102 is not limited to the peak balun 51 shown in the first embodiment, and may be the carrier balun 41.

[0146] In addition, the present disclosure may include a λ / 4 converter that delays the phase of the high-frequency signal output from the differential amplifiers 17 a and 17 b by 90°, instead of the adjustment circuit 60 (capacitor 62 ).

[0147] In addition, in the first embodiment, the adjustment circuit component (capacitor 62) is arranged in the invalid area, but the present disclosure may also be arranged in the invalid area for components other than the adjustment circuit component. In other words, as long as it is a surface mounted component mounted on the surface 102, there is no particular limitation. The following describes an example in which a surface mounted component is arranged in the invalid area.

[0148] (Second Modification)

[0149] Fig.12 FIG. 1 is a diagram showing a circuit structure of a Doherty circuit of a power amplifier device according to a second variant. The difference from the first embodiment is that Fig.12 As shown, the Doherty amplifier circuit 10 of the power amplifier device 100B of the second modified example includes an inductor 54. The inductor 54 is interposed between the power supply potential Vcc and the midpoint 52a of the primary side peak balun 52. In addition, the inductor 54 is a surface mount component mounted on the surface 102 of the substrate 101. The following describes the details of the layout.

[0150] Fig.13 This is a diagram showing a plan view of the surface of a substrate in a power amplifier device according to a second modification. Fig.14 It is a diagram for explaining the layout of the second insulating layer in the power amplifier device according to the second modification. Fig.15 It is a diagram for explaining the layout of the third insulating layer in the power amplifier device according to the second modification.

[0151] The difference from the first embodiment is that Fig.13 As shown in FIG. 1 , the primary-side carrier balun 42 of the power amplifier device 100B of the second modified example is provided on the surface 102 (first insulating layer 110) of the substrate 101. The difference from the first embodiment is that Fig.14 As shown, the secondary-side carrier balun 43 of the power amplifier device 100B according to the second modification is provided on the second insulating layer 120 .

[0152] In addition, when viewed from the stacking direction, an inductor 54 is arranged between the primary-side carrier balun 42 and the primary-side peak balun 52. The inductor 54 is welded to the electrodes 171 and 172. In addition, the difference from the first embodiment is that each of the primary-side carrier balun 42 and the primary-side peak balun 52 does not overlap with the electrodes 171 and 172 to which the inductor 54 is joined.

[0153] The capacitor 62 is disposed on one side of the inductor 54 in the first planar direction X. The capacitor 62 is soldered to the electrodes 163 and 164 .

[0154] like Fig.14 As shown, one end 53a of the secondary side peak balun 53 is connected to the reference potential GND via an interlayer connection conductor 140. The other end 53b of the secondary side peak balun 53 is connected to one end 43a of the secondary side carrier balun 43 via a wiring 141 extending in the second plane direction Y. In addition, although not particularly shown, the other end 43b of the secondary side carrier balun 43 is connected to a load (antenna) 70.

[0155] like Fig.12 As shown, an electrode 142 is provided on the second insulating layer 120 and is arranged between the secondary side carrier balanced-unbalanced transformer 43 and the secondary side peak balanced-unbalanced transformer 53. The electrode 142 is connected to the power supply potential Vcc. An interlayer connection conductor 143 extending to the third insulating layer 130 and the first insulating layer is provided on the electrode 142. Fig.15 As shown, the interlayer connection conductor 143 is connected to one end of a wiring 144 provided in the third insulating layer 130. The other end of the wiring 144 is connected to an interlayer connection conductor 145 extending to the first insulating layer 110. Fig.13 As shown, the interlayer connection conductor 145 is connected to an electrode 146 connected to the midpoint 42a of the primary-side carrier balun 42. Thus, the midpoint 42a of the primary-side carrier balun 42 is supplied with a power supply potential Vcc.

[0156] like Fig.13 As shown, the interlayer connection conductor 143 is connected to the electrode 171 of the first insulating layer 110. The electrode 172 is provided with an interlayer connection conductor 172a. Fig.15 As shown in FIG. 1 , the interlayer connection conductor 172a extends to the third insulating layer 130 and is connected to one end of the wiring 147. The other end of the wiring 147 is connected to the interlayer connection conductor 148. Fig.13 As shown, the interlayer connection conductor 148 extends to the first insulating layer 110 and is connected to an electrode 149 connected to the midpoint 52a of the primary side peak balun 52. Thus, the midpoint 52a of the primary side peak balun 52 is supplied with a power supply potential Vcc.

[0157] like Fig.15 As shown in FIG. 1 , an electrode 165 connected to the reference potential GND is provided on the third insulating layer 130. An interlayer connection conductor 166 is provided on the electrode 165. Fig.13As shown, the interlayer connection conductor 166 extends to the first insulating layer 110 and is connected to the electrode 164 connected to the capacitor 62. The interlayer connection conductor 167 is provided on the electrode 163. Fig.14 As shown, the interlayer connection conductor 167 extends to the second insulating layer 120 and is connected to the wiring 141. Therefore, the capacitor 62 is connected in parallel with the secondary side peak balun 53.

[0158] Fig.16 So Fig.15 Schematic diagram of the cross section taken along the XVI-XVI line. Fig.16 As shown, the inductor 54 is a winding centered on a center line (not shown) extending along the second plane direction Y. Therefore, the direction of the magnetic field passing through the inside of the inductor 54 (refer to Fig.16 The arrow M1) is the second plane direction Y. On the other hand, Fig.16 As shown in FIG. 1 , the directions of the magnetic fields passing through the carrier balun 41 and the peak balun 51 are shown in FIG. 1 (see FIG. 1 ). Fig.16 The arrow M2) is the stacking direction.

[0159] As described above, according to the third modification, the inductor 54 is arranged in the region which has been the ineffective region in the past, and the power amplifier device 100B is miniaturized. Fig.16 As shown in FIG. 1 , the magnetic fields of carrier balun 41 and peak balun 51 are orthogonal to the magnetic field of inductor 54. Therefore, each of carrier balun 41 and peak balun 51 is unlikely to be magnetically coupled with inductor 54. In addition, the magnetic field of inductor 54 exerts a shielding effect, and the magnetic fields of carrier balun 41 and peak balun 51 are unlikely to interfere with each other.

[0160] Furthermore, in the third modified example, the carrier balun 41 (primary-side carrier balun 42) and the peak balun 51 (primary-side peak balun 52) are respectively provided on the surface 102 of the substrate 101, but the present disclosure may be such that one of the carrier balun 41 (primary-side carrier balun 42) and the peak balun 51 (primary-side peak balun 52) is provided on the surface 102 of the substrate 101. In other words, one of the carrier balun 41 and the peak balun 51 may be provided on the insulating layer arranged closer to the first stacking direction than the first insulating layer 110 constituting the surface 102. Furthermore, the other of the carrier balun 41 and the peak balun 52 may also be provided on an insulating layer disposed closer to the first stacking direction than the first insulating layer 110 constituting the surface 102. In other words, both the carrier balun 41 and the peak balun 51 may be provided not on the first insulating layer 110 but on an insulating layer below the second insulating layer 120.

[0161] Furthermore, the present disclosure may be a combination of the following structures.

[0162] (1) A power amplifier device comprising:

[0163] a substrate having a surface;

[0164] an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being disposed on the surface;

[0165] A carrier balanced-unbalanced transformer connected to the carrier amplifier;

[0166] a peak-use balun connected to the peak amplifier; and

[0167] a surface mounted component disposed on said surface,

[0168] Wherein, the carrier amplifier and the peak amplifier are each a pair of differential amplifiers,

[0169] The direction in which the integrated circuit and the substrate are arranged is set as a stacking direction,

[0170] The direction in which the substrate is arranged when viewed from the integrated circuit among the stacking directions is defined as a first stacking direction,

[0171] A direction parallel to the surface is set as a first plane direction,

[0172] A direction parallel to the surface and intersecting the first plane direction is set as a second plane direction,

[0173] The substrate has a plurality of insulating layers arranged in the stacking direction,

[0174] An electrode for soldering the surface-mounted component is provided on the surface.

[0175] When viewed from the stacking direction, on one side of the integrated circuit in the first plane direction, the carrier balun, the electrode, and the peak balun are arranged in sequence along the second plane direction.

[0176] One of the carrier balun and the peak balun is disposed on the insulating layer configured to be closer to the first stacking direction than the insulating layer constituting the surface, and at least a portion of the one of the carrier balun and the peak balun overlaps with the electrode when viewed from the stacking direction.

[0177] (2) A power amplifier device comprising:

[0178] a substrate having a surface;

[0179] an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being disposed on the surface;

[0180] A carrier balanced-unbalanced transformer connected to the carrier amplifier;

[0181] a peak-use balun connected to the peak amplifier; and

[0182] an inductor which is a surface mount component provided on the surface,

[0183] Wherein, the carrier amplifier and the peak amplifier are each a pair of differential amplifiers,

[0184] The direction in which the integrated circuit and the substrate are arranged is set as a stacking direction,

[0185] The direction in which the substrate is arranged when viewed from the integrated circuit among the stacking directions is defined as a first stacking direction,

[0186] A direction parallel to the surface is set as a first plane direction,

[0187] A direction parallel to the surface and intersecting the first plane direction is set as a second plane direction,

[0188] The substrate has a plurality of insulating layers arranged in the stacking direction,

[0189] The carrier balun has a primary-side carrier balun and a secondary-side carrier balun, wherein the center lines of the windings of the primary-side carrier balun and the secondary-side carrier balun extend in the stacking direction.

[0190] One of the primary-side carrier balun and the secondary-side carrier balun is provided on the surface, and the other is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface.

[0191] The peak balun has a primary-side peak balun and a secondary-side peak balun, wherein the center lines of the windings of the primary-side peak balun and the secondary-side peak balun extend in the stacking direction.

[0192] One of the primary-side peak balanced-unbalanced transformer and the secondary-side peak balanced-unbalanced transformer is provided on the surface, and the other is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface.

[0193] When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction.

[0194] A center line of the winding of the inductor extends along the second planar direction.

[0195] (3) A power amplifier device comprising:

[0196] a substrate having a surface;

[0197] an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being disposed on the surface;

[0198] A carrier balanced-unbalanced transformer connected to the carrier amplifier;

[0199] a peak-use balun connected to the peak amplifier; and

[0200] an inductor which is a surface mount component provided on the surface,

[0201] Wherein, the carrier amplifier and the peak amplifier are each a pair of differential amplifiers,

[0202] The direction in which the integrated circuit and the substrate are arranged is set as a stacking direction,

[0203] The direction in which the substrate is arranged when viewed from the integrated circuit among the stacking directions is defined as a first stacking direction,

[0204] A direction parallel to the surface is set as a first plane direction,

[0205] A direction parallel to the surface and intersecting the first plane direction is set as a second plane direction,

[0206] The substrate has a plurality of insulating layers arranged in the stacking direction,

[0207] When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction.

[0208] The carrier balun has a primary-side carrier balun and a secondary-side carrier balun, the center lines of the windings of the primary-side carrier balun and the secondary-side carrier balun extend along the stacking direction, and the primary-side carrier balun and the secondary-side carrier balun are arranged in different insulating layers.

[0209] The peak balun has a primary-side peak balun and a secondary-side peak balun, the center lines of the windings of the primary-side peak balun and the secondary-side peak balun extend along the stacking direction, and the primary-side peak balun and the secondary-side peak balun are arranged in different insulating layers.

[0210] One of the carrier balun and the peak balun is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface.

[0211] A center line of the winding of the inductor extends along the second planar direction.

[0212] (4) The power amplifier device according to (1), wherein:

[0213] The other of the carrier balun and the peak balun is provided on the insulating layer disposed closer to the first stacking direction than the insulating layer constituting the surface.

[0214] (5) The power amplifier device according to (1) or (4), characterized in that:

[0215] The surface mount component is a component for adjusting the circuit.

[0216] (6) The power amplifier device according to (5), characterized in that:

[0217] The adjusting circuit component is a capacitor.

[0218] (7) The power amplifier device according to (3), wherein:

[0219] The other of the carrier balun and the peak balun is provided on the insulating layer disposed closer to the first stacking direction than the insulating layer constituting the surface.

[0220] Description of Reference Numerals

[0221] 1: power amplifier circuit; 10: Doherty amplifier circuit; 12, 13: carrier amplifier; 13a, 13b, 17a, 17b: differential amplifier; 16, 17: peak amplifier; 21: control circuit; 22: detection circuit; 26: drive level detection circuit; 40: coupler; 41: carrier balanced-unbalanced transformer; 42: primary side carrier balanced-unbalanced transformer; 43: secondary side carrier balanced-unbalanced transformer; 51: peak balanced-unbalanced transformer; 52: primary side peak balanced-unbalanced transformer; 53: secondary side peak balanced-unbalanced transformer; 54: inductor; 60: adjustment circuit; 62: capacitor; 100, 100A, 100B: power amplifier device; 101: substrate; 102: surface; 110: first insulating layer; 120: second insulating layer; 130: third insulating layer; 160, 161: electrodes.

Claims

1. A power amplifier device, comprising: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being disposed on the surface; A carrier balanced-unbalanced transformer connected to the carrier amplifier; a peak-use balun connected to the peak amplifier; and a surface mounted component disposed on said surface, in, The carrier amplifier and the peak amplifier are each a pair of differential amplifiers, The direction in which the integrated circuit and the substrate are arranged is set as a stacking direction, The direction in which the substrate is arranged when viewed from the integrated circuit among the stacking directions is defined as a first stacking direction, A direction parallel to the surface is set as a first plane direction, A direction parallel to the surface and intersecting the first plane direction is set as a second plane direction, The substrate has a plurality of insulating layers arranged in the stacking direction, An electrode for soldering the surface-mounted component is provided on the surface. When viewed from the stacking direction, on one side of the integrated circuit in the first plane direction, the carrier balun, the electrode, and the peak balun are arranged in sequence along the second plane direction. One of the carrier balun and the peak balun is disposed on the insulating layer configured to be closer to the first stacking direction than the insulating layer constituting the surface, and at least a portion of the one of the carrier balun and the peak balun overlaps with the electrode when viewed from the stacking direction.

2. The power amplification device according to claim 1, wherein: The other of the carrier balun and the peak balun is provided on the insulating layer disposed closer to the first stacking direction than the insulating layer constituting the surface.

3. The power amplifier device according to claim 1 or 2, wherein: The surface mount component is a component for adjusting the circuit.

4. The power amplifying device according to claim 3, wherein: The adjusting circuit component is a capacitor.

5. A power amplifier device, comprising: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being disposed on the surface; A carrier balanced-unbalanced transformer connected to the carrier amplifier; a peak-use balun connected to the peak amplifier; and an inductor which is a surface mount component provided on the surface, in, The carrier amplifier and the peak amplifier are each a pair of differential amplifiers, The direction in which the integrated circuit and the substrate are arranged is set as a stacking direction, The direction in which the substrate is arranged when viewed from the integrated circuit among the stacking directions is defined as a first stacking direction, A direction parallel to the surface is set as a first plane direction, A direction parallel to the surface and intersecting the first plane direction is set as a second plane direction, The substrate has a plurality of insulating layers arranged in the stacking direction, The carrier balun has a primary-side carrier balun and a secondary-side carrier balun, wherein the center lines of the windings of the primary-side carrier balun and the secondary-side carrier balun extend in the stacking direction. One of the primary-side carrier balun and the secondary-side carrier balun is provided on the surface, and the other is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface. The peak balun has a primary-side peak balun and a secondary-side peak balun, wherein the center lines of the windings of the primary-side peak balun and the secondary-side peak balun extend in the stacking direction. One of the primary-side peak balanced-unbalanced transformer and the secondary-side peak balanced-unbalanced transformer is provided on the surface, and the other is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface. When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction. A center line of the winding of the inductor extends along the second planar direction.

6. A power amplifier device, comprising: a substrate having a surface; an integrated circuit having a carrier amplifier and a peak amplifier, the integrated circuit being disposed on the surface; A carrier balanced-unbalanced transformer connected to the carrier amplifier; a peak-use balun connected to the peak amplifier; and an inductor which is a surface mount component provided on the surface, in, The carrier amplifier and the peak amplifier are each a pair of differential amplifiers, The direction in which the integrated circuit and the substrate are arranged is set as a stacking direction, The direction in which the substrate is arranged when viewed from the integrated circuit among the stacking directions is defined as a first stacking direction, A direction parallel to the surface is set as a first plane direction, A direction parallel to the surface and intersecting the first plane direction is set as a second plane direction, The substrate has a plurality of insulating layers arranged in the stacking direction, When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in sequence along the second plane direction on one side of the integrated circuit in the first plane direction. The carrier balun has a primary-side carrier balun and a secondary-side carrier balun, the center lines of the windings of the primary-side carrier balun and the secondary-side carrier balun extend along the stacking direction, and the primary-side carrier balun and the secondary-side carrier balun are arranged in different insulating layers. The peak balun has a primary-side peak balun and a secondary-side peak balun, the center lines of the windings of the primary-side peak balun and the secondary-side peak balun extend along the stacking direction, and the primary-side peak balun and the secondary-side peak balun are arranged in different insulating layers. One of the carrier balun and the peak balun is provided on the insulating layer arranged closer to the first stacking direction than the insulating layer constituting the surface. A center line of the winding of the inductor extends along the second planar direction.

7. The power amplifying device according to claim 6, wherein: The other of the carrier balun and the peak balun is provided on the insulating layer disposed closer to the first stacking direction than the insulating layer constituting the surface.

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