A stress-reducing filtering device and a manufacturing method thereof

Abstract

The present application discloses a stress-reducing filtering device and a manufacturing method thereof. It relates to the field of filtering technology. Among them, the acoustic resonator in the filtering device is formed on the first side of a substrate serving as a carrier, and the capacitive structure is formed on the second side of the substrate. Thus, perforations can be made starting from the substrate serving as a carrier, which not only penetrate the bonding layer, but also sequentially penetrate solid material layers such as the cutoff boundary layer, the sacrificial layer, the dielectric layer, and the piezoelectric layer, to form through-holes for realizing electrical connection between the capacitor and the acoustic resonator electrode. Since these layers are mainly composed of solid materials with high mechanical strength and toughness, the risk of fracture caused by weak connection of materials can be significantly reduced during perforation, the local stress concentration that may be introduced by the perforation operation is reduced, and the fracture situation of the filtering device caused by perforation during manufacturing and use is reduced. Furthermore, the technical problem in the prior art that the filtering device integrating the acoustic resonator and the capacitive filter is prone to fracture is solved.

Description

Technical Field

[0001] This application relates to the field of filtering technology, and in particular to a stress-reducing filtering device and a manufacturing method thereof. Background Art

[0002] With the increasingly wide application of filters, there are more and more ways to implement filters. Among them, the integrated passive device (IPD, Integrated Passive Device) technology uses thin-film inductors and capacitors to form filters, which can meet the performance requirements of high frequency and large bandwidth. Acoustic resonators can be divided into surface acoustic wave (SAW) filters and bulk acoustic wave (BAW) filters according to different structures, and have the advantage of a high Q value, which can achieve a rapid roll-off of the filter.

[0003] In order to achieve the purpose of having a high Q value while meeting the large bandwidth requirement, the existing solution fabricates an acoustic resonator and a capacitor on a single wafer and integrates them into a filtering device. For example, the invention patent application with the publication number CN116846358A discloses a filtering device, which includes a substrate B as a carrier and a substrate C as a cap. The acoustic resonator is formed between the two substrates, and the capacitor is arranged on the side of the substrate C as the cap away from the acoustic resonator. In order to realize the electrical connection between the capacitor and the electrode of the acoustic resonator, it is necessary to perforate starting from the substrate C as the cap, and a through hole for realizing the electrical connection between the capacitor and the acoustic resonator electrode is formed after only penetrating a bonding layer B. However, since the bonding layer is an organic material such as BSiO2 or SiNx, its viscosity and strength are poor, so it is easy to break when opening the through hole.

[0004] Aiming at the problem that the existing filtering device integrating an acoustic resonator and a capacitor filter is prone to breakage, no effective solution has been proposed yet. Summary of the Invention

[0005] Embodiments of the present disclosure provide a stress-reducing filtering device and a manufacturing method thereof. At least solve the technical problem that the existing filtering device integrating an acoustic resonator and a capacitor filter is prone to breakage.

[0006] According to one aspect of the embodiments of the present disclosure, a stress-reducing filtering device is provided, including: a substrate as a carrier, an acoustic resonator, and at least one capacitor structure, wherein the acoustic resonator is formed on a first side of the substrate; and the capacitor structure is formed on a second side of the substrate and is electrically connected to at least one electrode of the acoustic resonator through a through hole.

[0007] Optionally, the acoustic resonator includes: a piezoelectric layer, a first electrode, a second electrode, and a resonance cavity; wherein, the first electrode is located on a side of the piezoelectric layer away from the substrate; the second electrode is located on a side of the piezoelectric layer close to the substrate; the resonance cavity is formed between the piezoelectric layer and the substrate; and, the capacitive structure includes a first capacitor and / or a second capacitor; the first capacitor is electrically connected to the first electrode through a first via hole; the second capacitor is electrically connected to the second electrode through a second via hole.

[0008] Optionally, the capacitive structure includes the first capacitor; the first via hole penetrates through the substrate, the piezoelectric layer and contacts the first electrode; and, the first capacitor includes: a first signal lead, a part of the first signal lead is electrically connected to the first electrode through the first via hole; another part of the first signal lead overlaps with the substrate at least partially in a first direction; a first dielectric layer located on a second side of the substrate and covering the first signal lead; and a third electrode located on a side of the first dielectric layer away from the substrate.

[0009] Optionally, the capacitive structure includes the second capacitor; the second via hole penetrates through the substrate and contacts the second electrode; and, the second capacitor includes: a second signal lead, a part of the second signal lead is electrically connected to the second electrode through the second via hole; another part of the second signal lead overlaps with the substrate at least partially in a first direction; a first dielectric layer located on a second side of the substrate and covering the second signal lead; and a fourth electrode located on a side of the first dielectric layer away from the substrate.

[0010] Optionally, the filtering device further includes: a second dielectric layer located on a surface of the second electrode away from the piezoelectric layer; a sacrificial layer located on a surface of the second dielectric layer away from the piezoelectric layer; a cut-off boundary layer located on a surface of the sacrificial layer away from the second dielectric layer; a bonding layer located on a side of the cut-off boundary layer away from the second dielectric layer; and, the first via hole sequentially penetrates through the substrate, the bonding layer, the cut-off boundary layer, the sacrificial layer, the piezoelectric layer and contacts the first electrode; the second via hole sequentially penetrates through the substrate, the bonding layer, the cut-off boundary layer, the sacrificial layer, the second dielectric layer and contacts the second electrode.

[0011] Optionally, the number of capacitors included in the filtering device is greater than or equal to three.

[0012] Optionally, the filtering device further includes: a third dielectric layer located on a side of the first dielectric layer away from the substrate and covering the third electrode and the fourth electrode; and a first inductor and / or a second inductor located on a side of the third dielectric layer away from the substrate; wherein the first inductor is electrically connected to the fourth electrode, and the second inductor is electrically connected to the first signal lead.

[0013] Optionally, the filtering device further includes: a fourth dielectric layer located on a side of the third dielectric layer away from the substrate and covering the first inductor and the second inductor; and a third inductor and / or a fourth inductor located on a side of the fourth dielectric layer away from the substrate; wherein the third inductor is electrically connected to the first inductor, and the fourth inductor is electrically connected to the second inductor.

[0014] According to another aspect of the embodiments of the present disclosure, there is also provided a method for manufacturing a filtering device for stress mitigation, including: manufacturing a substrate, an acoustic resonator, and at least one capacitive structure as carriers, wherein the acoustic resonator is formed on a first side of the substrate; and the capacitive structure is formed on a second side of the substrate and is electrically connected to at least one electrode of the acoustic resonator through a via hole.

[0015] Optionally, the step of manufacturing the acoustic resonator includes: manufacturing a piezoelectric layer, a first electrode, a second electrode, and a resonant cavity; wherein the first electrode is located on a side of the piezoelectric layer away from the substrate; the second electrode is located on a side of the piezoelectric layer close to the substrate; the resonant cavity is formed between the piezoelectric layer and the substrate; and the step of manufacturing the capacitive structure includes: manufacturing a first capacitor and / or a second capacitor; the first capacitor is electrically connected to the first electrode through a first via hole; the second capacitor is electrically connected to the second electrode through a second via hole.

[0016] Optionally, the capacitive structure includes the first capacitor; the operation of manufacturing the first via hole includes: starting the first via hole from the substrate, penetrating the piezoelectric layer until the first via hole contacts the first electrode; and the step of manufacturing the first capacitor includes: manufacturing a first signal lead, a part of the first signal lead is electrically connected to the first electrode through the first via hole; another part of the first signal lead overlaps with the substrate at least partially in a first direction; manufacturing a first dielectric layer located on the second side of the substrate and covering the first signal lead; manufacturing a third electrode located on a side of the first dielectric layer away from the substrate.

[0017] Optionally, the capacitive structure includes the second capacitor; the operation of fabricating the second via includes: forming a second via from the substrate until the second via contacts the second electrode; and the step of fabricating the second capacitor includes: fabricating a second signal lead, a part of the second signal lead is electrically connected to the second electrode through the second via; another part of the second signal lead overlaps with the substrate at least partially in a first direction; fabricating a first dielectric layer located on the second side of the substrate and covering the second signal lead; fabricating a fourth electrode located on a side of the first dielectric layer away from the substrate.

[0018] Optionally, the manufacturing method further includes: fabricating a second dielectric layer on a surface of the second electrode away from the piezoelectric layer; fabricating a sacrificial layer on a surface of the second dielectric layer away from the piezoelectric layer; fabricating a cut-off boundary layer on a surface of the sacrificial layer away from the second dielectric layer; fabricating a bonding layer on a side of the cut-off boundary layer away from the second dielectric layer;

[0019] And, the operation of fabricating the first via includes: forming a first via from the substrate, successively penetrating the bonding layer, the cut-off boundary layer, the sacrificial layer, the piezoelectric layer until the first via contacts the first electrode; the operation of fabricating the second via includes: forming a second via from the substrate, successively penetrating the bonding layer, the cut-off boundary layer, the sacrificial layer, the second dielectric layer until the second via contacts the second electrode.

[0020] In the stress mitigation filter device proposed in this application, an acoustic resonator is formed on a first side of a substrate serving as a carrier, and a capacitive structure is formed on a second side of the substrate, so that perforation can start from the substrate serving as a carrier, not only penetrating the bonding layer, but also successively penetrating solid material layers such as the cut-off boundary layer, the sacrificial layer, the dielectric layer, and the piezoelectric layer to form vias for realizing electrical connection between the capacitor and the acoustic resonator electrodes. Since these layers are mainly composed of solid materials with high mechanical strength and toughness, the risk of fracture caused by weak material connections (such as the bonding layer) can be significantly reduced during perforation, the local stress concentration that may be introduced by the perforation operation is reduced, and the fracture situation of the filter device caused by perforation during manufacturing and use is greatly reduced, improving the reliability and stability of the filter device. Furthermore, the technical problem in the prior art that a filter device integrating an acoustic resonator and a capacitive filter is prone to fracture is solved. Description of the Drawings

[0021] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of this application. The schematic embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure. In the drawings:

[0022] Figures 1-36 Schematic diagrams of each structure during the manufacturing process of the filtering device provided by an embodiment of the present application. Detailed implementation manners

[0023] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0025] Secondly, the present application will be described in detail with reference to the schematic diagrams. When detailing the embodiments of the present application, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present application here. In addition, in actual manufacturing, three-dimensional spatial dimensions including length, width, and depth should be included.

[0026] As described in the background art section, in the layout where the capacitor is disposed on the side of the substrate C serving as a cap away from the acoustic resonator, only one bonding layer B is penetrated when opening the through hole. Since the bonding layer is an organic material such as BSiO2 or SiNx, the viscosity and strength are poor, so the through hole is likely to break when being opened.

[0027] In view of this, the embodiments of the present application provide a stress-reducing filtering device and a manufacturing method thereof to reduce the fracture situation caused by perforation during the manufacturing and use of the filtering device, and improve the reliability and stability of the filtering device.

[0028] The following will describe the stress-reducing filtering device provided by the embodiments of the present application and the manufacturing method thereof with reference to specific embodiments. For the convenience of understanding, the present application will first describe the manufacturing method of the stress-reducing filtering device.

[0029] The manufacturing method of the stress - reducing filter device provided by the embodiment of the present application includes: manufacturing a substrate as a carrier, an acoustic resonator, and at least one capacitive structure, wherein the acoustic resonator is formed on the first side of the substrate; and the capacitive structure is formed on the second side of the substrate and is electrically connected to at least one electrode of the acoustic resonator through a via hole. Thus, perforation can start from the substrate as a carrier, not only penetrating through the bonding layer, but also successively penetrating through solid material layers such as the cutoff boundary layer, sacrificial layer, dielectric layer, and piezoelectric layer, to form a via hole for realizing the electrical connection between the capacitor and the acoustic resonator electrode. Since these layers are mainly composed of solid materials with high mechanical strength and toughness, the risk of fracture caused by weak material connection (such as the bonding layer) can be significantly reduced during perforation, the local stress concentration that may be introduced by the perforation operation can be reduced, and the fracture situation of the filter device caused by perforation during manufacturing and use can be greatly reduced, improving the reliability and stability of the filter device.

[0030] It should be noted that, in this embodiment, the stress - reducing filter device includes: a substrate as a carrier, an acoustic resonator, and at least one capacitive structure, wherein the acoustic resonator is formed on the first side of the substrate; and the capacitive structure is formed on the second side of the substrate and is electrically connected to at least one electrode of the acoustic resonator through a via hole.

[0031] Specifically, the manufacturing method of the stress - reducing filter device provided by the embodiment of the present application includes:

[0032] As Figure 1 shown, a transition layer 110, a seed layer 120, a first electrode layer 130, a piezoelectric layer 140, and a second electrode layer 150 are successively manufactured on a substrate A100 used as a temporary substrate. Among them, the first electrode layer is used to manufacture the first electrode, and the second electrode layer is used to manufacture the second electrode.

[0033] Optionally, in an embodiment of the present application, the substrate A100 is a silicon substrate, a silicon - on - insulator substrate, a glass substrate, a silicon carbide substrate, or a gallium arsenide (GaAs) substrate, etc.;

[0034] The transition layer 110 can be a silicon oxide (SiO2) layer or a silicon nitride (SiNx) layer, etc., and the forming method can be a thermal oxidation process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process, etc.;

[0035] The seed layer 120 can be an aluminum nitride (AlN) layer, and the forming method is a physical vapor deposition (PVD) process, specifically a magnetron sputtering process;

[0036] The first electrode layer 130 can be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and the forming method can be a physical vapor deposition (PVD) process; similarly, the second electrode layer 150 can be an Al layer, a Cu layer, a Mo layer, an Au layer or a Pt layer, and the forming method can be a physical vapor deposition (PVD) process;

[0037] The piezoelectric layer 140 can be an AlN layer, a scandium-doped aluminum nitride (AlxSc1-xN) layer, a lithium niobate (LiNbO3) layer, a lithium tantalate (LiTaO3) layer or a quartz layer, etc. It can be a polycrystalline layer or a single crystal layer, and the forming method is PVD or metal-organic chemical vapor deposition (MOCVD), etc.

[0038] Such as Figure 2 As shown, the first region of the second electrode layer 150 is etched to form a step structure 151 in the second electrode layer 150 to improve the performance of the acoustic resonator. It should be noted that in this embodiment, the distance between the boundary of the first region and the boundary of the second electrode layer is greater than zero.

[0039] Specifically, in an embodiment of the present application, the process of etching the second electrode layer can be a dry etching process or a wet etching process, but the present application does not limit this, and it depends on the specific situation.

[0040] Such as Figure 3 As shown, a dielectric layer A160 (corresponding to the second dielectric layer) is formed on the side of the second electrode layer 150 away from the substrate A100. Optionally, the forming process of the dielectric layer A160 is a deposition process, specifically PVD or CVD, etc. The material of the dielectric layer A160 can be SiO2, SiNx or AlN, etc. The present application does not limit this, and it depends on the specific situation.

[0041] It should be noted that in the embodiment of the present application, the dielectric layer A160 is a protective layer for the second electrode layer 150 to prevent the second electrode layer 150 from being oxidized. Optionally, the dielectric layer A also serves as the dielectric layer of the capacitor formed subsequently.

[0042] Such as Figure 4As shown, the second region of the second electrode layer 150 and the portion of the dielectric layer A 160 located on the surface of the second region of the second electrode layer are etched to obtain a lower electrode pattern structure. The lower electrode pattern structure includes the remaining portion of the second electrode layer (i.e., the second electrode 152) and the portion of the dielectric layer A located on the surface of the second electrode 152. In a plane parallel to the plane of the substrate A, the second region is located on the first side of the stepped structure. Optionally, the process of etching the dielectric layer A and the second electrode layer can be a wet etching process or a dry etching process.

[0043] A fifth electrode is fabricated on the surface of the dielectric layer A on the side away from the piezoelectric layer. The fifth electrode is located on one side of the first resonant cavity and forms a capacitor A with the dielectric layer A and the second electrode. Specifically, fabricating a fifth electrode on the surface of the dielectric layer A on the side away from the piezoelectric layer includes:

[0044] As Figure 5 shown, a fifth electrode 170 is formed in the third region on the surface of the lower electrode pattern structure, that is, a fifth electrode 170 is formed in the third region on the surface of the dielectric layer A 160 on the side away from the piezoelectric layer 140. In a plane parallel to the plane of the substrate A 100, the third region is located on the second side of the stepped structure 151, and the second side is opposite to the first side. It should be noted that in this embodiment, the fifth electrode 170 forms a capacitor A with the dielectric layer A 160 and the second electrode 152. Optionally, the material of the fifth electrode can be Al, Cu, Mo, Au, Pt, etc., and the present application does not limit this, which depends on the specific situation.

[0045] Specifically, in an embodiment of the present application, forming a fifth electrode in the third region on the surface of the lower electrode pattern structure includes:

[0046] A third electrode layer is formed on the surface of the lower electrode pattern structure and the exposed surface of the piezoelectric layer. The forming process of the third electrode layer can be PVD, electroplating, electroless plating, etc.;

[0047] The third electrode layer is etched to remove the portion of the third electrode layer located on the surface of the piezoelectric layer and a part of the third electrode layer located on the surface of the lower electrode pattern structure, and the portion of the third electrode layer located on the surface of the lower electrode pattern structure (i.e., the portion of the third electrode layer located in the third region on the surface of the lower electrode pattern structure) is retained to form a fifth electrode. Optionally, the etching process of the third electrode layer can be wet etching or dry etching.

[0048] As Figure 6As shown, a sacrificial layer 180 is formed on the side of the lower electrode pattern structure away from the piezoelectric layer 140. The sacrificial layer 180 also covers the exposed portion of the piezoelectric layer 140 and the fifth electrode 170, that is, a sacrificial layer is formed on the side of the fifth electrode 170 away from the dielectric layer A160. The projection of the sacrificial layer on the substrate A coincides with the substrate A. Optionally, the material of the sacrificial layer 180 can be SiO2, PSG, USG, a-Si, photoresist, etc.; the formation process of the sacrificial layer 180 can be PVD, CVD, spin coating, etc.

[0049] As Figure 7 As shown, the sacrificial layer 180 is etched to form a via hole A181 and a via hole B182 in the sacrificial layer 180. Among them, the via hole A181 exposes a part of the surface of the piezoelectric layer 140, and the via hole B182 exposes a part of the surface of the dielectric layer A160. Specifically, the etching process of the sacrificial layer 180 can be dry etching or wet etching.

[0050] As Figure 8 As shown, a cut-off boundary layer 190 is formed on the side of the sacrificial layer 180 away from the dielectric layer A160. The cut-off boundary layer 190 also fills the via hole A181 and the via hole B182, that is, the cut-off boundary layer 190 covers the sacrificial layer 180 and the side walls of the via hole A181, the bottom of the via hole A181, the side walls of the via hole B182, and the bottom of the via hole B182. It should be noted that in this embodiment, the cut-off boundary layer 190 has a first protrusion and a second protrusion facing the piezoelectric layer 140. The first protrusion corresponds to the via hole A181 and contacts the exposed area of the piezoelectric layer, and the second protrusion corresponds to the via hole B182 and contacts the dielectric layer A.

[0051] It should also be noted that in this embodiment, the cut-off boundary layer 190 and the sacrificial layer 180 are made of different materials so that the chemical substances during the etching of the sacrificial layer 180 will not damage the cut-off boundary layer 190. Optionally, the material of the cut-off boundary layer 190 can be SiO2 or polycrystalline silicon (poly-Si), and the formation process can be PVD, CVD, etc.

[0052] As Figure 9 As shown, a bonding layer A200 is formed on the side of the cut-off boundary layer 190 away from the piezoelectric layer 140. The bonding layer A200 covers the surface of the cut-off boundary layer 190 and also fills the via hole A and the via hole B. Optionally, the material of the bonding layer A can be SiO2, and the formation process can be PVD or CVD, etc. This application does not limit this, and it depends on the specific situation.

[0053] As Figure 10As shown, a substrate B210 serving as a carrier is bonded to the side of the bonding layer A200 away from the cut-off boundary layer 190.

[0054] As Figure 11 shown, the wafer composed of the above-prepared structures is flipped, and the substrate A100 and the transition layer 110 are removed from the side of the substrate A100 away from the substrate B210. Optionally, the removal process of the substrate A100 and the transition layer 110 can be in the form of grinding or chemical mechanical polishing (CMP). This application does not make any limitations in this regard and depends on specific circumstances.

[0055] As Figure 12 shown, the parts of the seed layer 120 and the first electrode layer 130 located in the fourth region are etched to expose a part of the surface of the piezoelectric layer 140, forming an upper electrode pattern structure. The upper electrode pattern includes the first electrode 131 and the part of the seed layer located on the surface of the first electrode 131. Among them, the first electrode 131 is located in the fifth region on the first side of the piezoelectric layer 140.

[0056] Optionally, the etching process of the seed layer 120 and the first electrode layer 130 can be wet etching or dry etching.

[0057] As Figure 13 shown, a via C1401 is formed in the exposed part of the piezoelectric layer 140. The via C1401 penetrates through the piezoelectric layer 140 to expose a part of the surface of the second electrode 152, facilitating the extraction of the second electrode 152. The second electrode 152 is located in the sixth region on the second side of the piezoelectric layer 140. In the first direction, the fifth region and the sixth region partially overlap and partially do not overlap.

[0058] Optionally, the formation process of the via C1401 can be a wet etching process or a dry etching process.

[0059] As Figure 14 shown, a via D1201 is formed in the seed layer 120. The via D1201 exposes a part of the surface of the first electrode 131, facilitating the extraction of the first electrode 131. Specifically, the formation process of the via D1201 can be a wet etching process or a dry etching process.

[0060] As Figure 15As shown, a first conductive layer 230 is formed in the through hole D. The first conductive layer 230 covers the sidewall and the bottom of the through hole D, and also extends to cover a part of the surface of the seed layer 120. A second conductive layer 220 is formed in the through hole C. The second conductive layer 220 covers the sidewall and the bottom of the through hole C, and also extends to cover a part of the surface of the piezoelectric layer 140. It should be noted that, in this embodiment, the first conductive layer is electrically connected to the first electrode, and compared with the first electrode, the first conductive layer has a higher conductivity. The second conductive layer is electrically connected to the second electrode, and compared with the second electrode, the second conductive layer has a higher conductivity.

[0061] Optionally, in an embodiment of the present application, the material of the first conductive layer may be Au, Cu, Al, etc., and the forming method may be PVD, electroplating, etc. Similarly, the material of the second conductive layer may be Au, Cu, Al, etc., and the forming method may be PVD, electroplating, etc.

[0062] Optionally, the second conductive layer and the first conductive layer are formed simultaneously to simplify the forming process of the filtering device. Specifically, in an embodiment of the present application, the forming methods of the first conductive layer and the second conductive layer include:

[0063] A conductive layer is formed on the side of the seed layer away from the piezoelectric layer. The conductive layer covers the surface of the seed layer, the surface of the through hole D, the exposed surface of the piezoelectric layer, and the surface of the through hole C.

[0064] The conductive layer is etched to form a first conductive layer and a second conductive layer. Among them, the first conductive layer covers the sidewall and the bottom of the through hole D, and also extends to cover a part of the surface of the seed layer. The second conductive layer covers the sidewall and the bottom of the through hole C, and also extends to cover a part of the surface of the piezoelectric layer.

[0065] It should be noted that, in this embodiment, the etching process of the conductive layer may be a wet etching process or a dry etching process.

[0066] Such as Figure 16As shown, a preset region of the sacrificial layer 180 is released to form a first resonant cavity 1801 under the acoustic resonator. Among them, the preset region is located between the first protrusion and the second protrusion, that is, the part of the sacrificial layer 180 located between the first protrusion and the second protrusion is released, the part of the sacrificial layer located on the side of the first protrusion away from the second protrusion is reserved to form a first sacrificial layer, and the part of the sacrificial layer located on the side of the second protrusion away from the first protrusion is formed into a second sacrificial layer. The first resonant cavity 1801 is a region defined by the piezoelectric layer 140, the dielectric layer A 160, the first protrusion, the second protrusion, and the cutoff boundary layer 190. At least a part of the first resonant cavity 1801 is in contact with the piezoelectric layer 140.

[0067] Optionally, in an embodiment of the present application, releasing a preset region of the sacrificial layer to form a first resonant cavity under the acoustic resonator includes: using a liquid-phase etching or gas-phase etching method to release the preset region of the sacrificial layer and form a first resonant cavity under the acoustic resonator.

[0068] Specifically, in an embodiment of the present application, using a liquid-phase etching or gas-phase etching method to release a preset region of the sacrificial layer and form a first resonant cavity under the acoustic resonator includes:

[0069] Using a liquid-phase etching solution such as hydrofluoric acid solution (HF) or buffered oxide etchant (BOE) to etch the preset region of the sacrificial layer and form a first resonant cavity under the acoustic resonator;

[0070] Or, using a gas such as gaseous hydrogen fluoride (HF) or xenon difluoride (XeF2) to etch the preset region of the sacrificial layer and form a first resonant cavity under the acoustic resonator.

[0071] As Figure 17 shown, a bonding layer B 240 is formed. The bonding layer B 240 is located on the side of the first electrode 131 away from the piezoelectric layer 140, that is, the bonding layer B 240 is located on the side of the seed layer 120 away from the piezoelectric layer 140, and the bonding layer B 240 also covers the exposed surface of the piezoelectric layer 140.

[0072] Optionally, in an embodiment of the present application, the material of the bonding layer B is SiO2 or SiNx, etc., and the formation process can be PVD or CVD, etc.; in another embodiment of the present application, the bonding layer B is a dry film substance similar to a photoresist and is formed by processes such as spin coating and lithography. The present application does not limit this and specifically depends on the situation.

[0073] As Figure 18As shown, a second resonance cavity 2400 is formed above the acoustic resonator, and at least a partial area of the second resonance cavity 2400 is in contact with the piezoelectric layer 140. As Figure 19 shown, a substrate C250 serving as a cap is bonded to a side of the bonding layer B240 away from the seed layer 120. A region defined by the substrate C250, the bonding layer B240, the first electrode 131, and the piezoelectric layer 140 is the second resonance cavity 2400. Optionally, the material of the substrate C may be silicon, glass, SiC, GaAs, etc., and the present application does not limit this, which depends on specific circumstances.

[0074] As Figure 20 shown, the substrate C250 is thinned.

[0075] As Figure 21 shown, the wafer formed by the above-made various structures is flipped.

[0076] As Figure 22 shown, holes are formed in the substrate B210 to form a through hole E2101 (corresponding to the first through hole) and a through hole F2102 (corresponding to the second through hole). Among them, the through hole E2101 penetrates through the substrate B210, the bonding layer A200, the cutoff boundary layer 190, the sacrificial layer 180, and the piezoelectric layer 140, exposing a partial surface of the first electrode 131 to facilitate the extraction of the first electrode 131. The through hole F2102 penetrates through the substrate B210, the bonding layer A200, the cutoff boundary layer 190, the sacrificial layer 180, and the dielectric layer A160, exposing a partial surface of the second electrode 152 to facilitate the extraction of the second electrode 152.

[0077] Optionally, in an embodiment of the present application, the forming process of the through hole E2101 and the through hole F2102 is a dry etching process. Specifically, using a deep reactive ion etching (DRIE) device and process, the substrate B210, the bonding layer A200, the cutoff boundary layer 190, the sacrificial layer 180, and the piezoelectric layer 140 are dry-etched to form the through hole E2101. Using a deep reactive ion etching (DRIE) device and process, the substrate B210, the bonding layer A200, the cutoff boundary layer 190, the sacrificial layer 180, and the dielectric layer A160 are dry-etched to form the through hole F2102.

[0078] As Figure 23As shown, a third conductive layer 260 is formed on the surface of the through hole E2101. The third conductive layer 260 covers the side wall and the bottom of the through hole E2101, and also extends to cover a part of the surface of the substrate B210. A fourth conductive layer 270 is formed on the surface of the through hole F2102. The fourth conductive layer 270 covers the side wall and the bottom of the through hole F2102, and also extends to cover a part of the surface of the substrate B210.

[0079] It should be noted that, in this embodiment, the third conductive layer 260 is electrically connected to the first electrode 131, and compared with the first electrode 131, the third conductive layer 260 has a higher conductivity. The fourth conductive layer 270 is electrically connected to the second electrode 152, and compared with the second electrode 152, the fourth conductive layer 270 has a higher conductivity.

[0080] Optionally, in an embodiment of the present application, the material of the third conductive layer 260 may be Au, Cu, Al, etc., and the forming method may be PVD, electroplating, etc. Similarly, the material of the fourth conductive layer 270 may be Au, Cu, Al, etc., and the forming method may be PVD, electroplating, etc.

[0081] Optionally, the third conductive layer 260 and the fourth conductive layer 270 are formed simultaneously to simplify the forming process of the filtering device. Specifically, in an embodiment of the present application, the forming methods of the third conductive layer 260 and the fourth conductive layer 270 include:

[0082] A conductive layer is formed on the side of the substrate B210 away from the piezoelectric layer 140. The conductive layer covers the surface of the substrate B210, the surface of the through hole E2101, the exposed surface of the piezoelectric layer 140, and the surface of the through hole F2102.

[0083] The conductive layer is etched to form the third conductive layer 260 and the fourth conductive layer 270. Among them, the third conductive layer 260 covers the side wall and the bottom of the through hole E2101 and the exposed surface of the piezoelectric layer 140, and also extends to cover a part of the surface of the substrate B210. The fourth conductive layer 270 covers the side wall and the bottom of the through hole F2102 and the exposed surface of the piezoelectric layer 140, and also extends to cover a part of the surface of the substrate B210.

[0084] It should be noted that, in this embodiment, the etching process of the conductive layer may be a wet etching process or a dry etching process.

[0085] As Figure 24As shown, a first signal lead 280 and a second signal lead 290 are fabricated on the side of the substrate B210 away from the piezoelectric layer 140. The first signal lead 280 is electrically connected to the first electrode 131, and the second signal lead 290 is electrically connected to the second electrode 152. Specifically, the first signal lead 280 is formed on the surface of the third conductive layer 260, and the first signal lead 280 is electrically connected to the first electrode 131 through the third conductive layer 260. The second signal lead 290 is formed on the surface of the fourth conductive layer 270, and the second signal lead 290 is electrically connected to the second electrode 152 through the fourth conductive layer 270. It should be noted that in the embodiments of the present application, the first signal lead and the second signal lead are signal leads of the acoustic resonator. Optionally, the first signal lead and the second signal lead can also be used as the capacitor bottom electrodes for subsequent fabrication.

[0086] Optionally, in an embodiment of the present application, the material of the first signal lead can be Cu, Al, Au, Ag, etc. Similarly, the material of the second signal lead can also be Cu, Al, Au, Ag, etc. Optionally, the second signal lead and the first signal lead are of the same material, so that the second signal lead and the first signal lead can be fabricated simultaneously, but the present application does not limit this, and it depends on the specific situation.

[0087] Specifically, in an embodiment of the present application, forming the second signal lead on the surface of the fourth conductive layer and forming the first signal lead on the surface of the third conductive layer includes:

[0088] Form a metal layer on the surface of the fourth conductive layer, the surface of the third conductive layer, and the surface of the substrate B;

[0089] Etch the metal layer to remove the part of the metal layer on the surface of the substrate B, and retain the part of the metal layer on the surface of the third conductive layer and the part of the metal layer on the surface of the fourth conductive layer, so as to obtain the first signal lead on the surface of the third conductive layer and the second signal lead on the surface of the fourth conductive layer.

[0090] Optionally, in an embodiment of the present application, the forming process of the metal layer can be PVD, including evaporation plating, sputtering, or electroplating, etc.; the etching process of the metal layer can be a wet etching process or a dry etching process, and the present application does not limit this, and it depends on the specific situation.

[0091] Such as Figure 25As shown, a dielectric layer B300 (corresponding to the first dielectric layer) is formed on the side of the first signal lead 280 and the second signal lead 290 away from the substrate B, and the dielectric layer B300 covers the first signal lead 280, the second signal lead 290, and the exposed surface of the substrate B. It should be noted that in this embodiment, the dielectric layer B is the capacitor dielectric layer of the subsequently formed capacitor B (corresponding to the first capacitor) and capacitor C (corresponding to the second capacitor). Optionally, the material of the dielectric layer B can be SiO2 or SiNx, etc., and the forming process can be CVD, etc. This application does not limit this, and it depends on the specific situation.

[0092] Continue as Figure 25 As shown, a fourth electrode layer 310 is formed on the side of the dielectric layer B300 away from the substrate B.

[0093] As Figure 26 As shown, the fourth electrode layer 310 is etched to form a third electrode 3102 and a fourth electrode 3101. In the first direction, the third electrode 3102 at least partially overlaps with the first signal lead 280, and the third electrode 3102, the first signal lead 280, and the dielectric layer B300 form a capacitor B (corresponding to the first capacitor);

[0094] In the first direction, the fourth electrode 3101 at least partially overlaps with the second signal lead 290, and the fourth electrode 3101, the second signal lead 290, and the dielectric layer B300 form a capacitor C (corresponding to the second capacitor).

[0095] It should be noted that in this embodiment, the projection of the fourth electrode in the plane of the dielectric layer B is located within the projection range of the second signal lead in the plane of the dielectric layer B, and the projection area of the fourth electrode is smaller than the projection area of the second signal lead; similarly, the projection of the third electrode in the plane of the dielectric layer B is located within the projection range of the first signal lead in the plane of the dielectric layer B, and the projection area of the third electrode is smaller than the projection area of the first signal lead.

[0096] It should also be noted that Figure 26 The shown filtering device includes both a first capacitor and a second capacitor, but this application does not limit this. In other embodiments of this application, the filtering device may also only include a first capacitor or only include a second capacitor, depending on the specific situation.

[0097] Optionally, the etching process of the fourth electrode layer can be a dry etching process or a wet etching process.

[0098] As Figures 27-36As shown, a first electrode lead-out structure and a second electrode lead-out structure are fabricated. Among them, the first electrode lead-out structure is used to achieve the electrical connection between the first electrode and the outside world, and the second electrode lead-out structure is used to achieve the electrical connection between the second electrode and the outside world. Among them, the second electrode lead-out structure can be electrically connected to the second signal lead to achieve the lead-out of the second electrode, or can be electrically connected to the fourth electrode to achieve the lead-out of the second electrode; similarly, the first electrode lead-out structure can be electrically connected to the first signal lead to achieve the lead-out of the first electrode, or can be electrically connected to the fifth electrode to achieve the lead-out of the first electrode.

[0099] Specifically, as Figure 27 shown, the dielectric layer B300 is etched to form a through hole P3001 in the dielectric layer B300. The through hole P exposes a partial area of the first signal lead 280, so as to facilitate the lead-out of the lower electrode of the third capacitor filter, that is, the lead-out of the first signal lead 280, thereby facilitating the subsequent electrical connection between the first electrode and the outside world. Specifically, the etching process of the dielectric layer B300 can be a dry etching process or a wet etching process. This application does not limit this, and it depends on the specific situation.

[0100] As Figure 28 shown, a dielectric layer C320 (corresponding to the third dielectric layer) is formed on the side of the dielectric layer B300 away from the substrate B. The dielectric layer C320 covers the dielectric layer B300, the fourth electrode 3101, and the third electrode 3102. Optionally, the material of the dielectric layer C can be a photosensitive organic material, such as polyimide (abbreviated as PI), benzocyclobutene (BCB), etc., and is formed by spin coating.

[0101] As Figure 29 shown, the dielectric layer C320 is etched to form a through hole Q3201 and a through hole R3202 in the dielectric layer C320. Among them, the through hole Q3201 communicates with the through hole P3001 to form a through hole S. The through hole S exposes a partial area of the first signal lead 280. The through hole R3202 penetrates the dielectric layer C and exposes a partial area of the fourth electrode 3101. Specifically, in an embodiment of the present application, the through holes Q3201 and R3202 are obtained by exposing and developing the dielectric layer C.

[0102] It should be noted that although Figure 29The through-hole S is shown to expose a partial area of the first signal lead 280 to achieve electrical connection between the first electrode and the outside world. However, the present application does not limit this. In other embodiments of the present application, instead of choosing the through-hole S to expose a partial area of the first signal lead 280, the through-hole Q can be selected to expose a partial area of the third electrode 3102 to achieve electrical connection between the first electrode and the outside world. The present application does not limit this and depends on specific circumstances.

[0103] Similarly, although Figure 29 the through-hole R3202 in the dielectric layer C320 is shown to expose a partial area of the fourth electrode 3101 to achieve electrical connection between the second electrode 152 and the outside world. However, the present application does not limit this. In other embodiments of the present application, the through-hole R3202 in the dielectric layer C320 may not choose to expose a partial area of the fourth electrode 3101 to achieve electrical connection between the second electrode and the outside world, but instead choose to expose a partial area of the second signal lead 290 to achieve electrical connection between the second electrode and the outside world. The present application does not limit this and depends on specific circumstances.

[0104] As Figure 30 shown, a first inductor layer 330 is formed on the side of the dielectric layer C320 away from the dielectric layer B300. The first inductor layer 330 covers the dielectric layer C320 and also fills the through-hole S and the through-hole R. Optionally, the material of the first inductor layer can be nickel-zinc ferrite material, manganese-zinc ferrite material or metal soft magnetic material, preferably manganese-zinc ferrite material. The forming process can be winding method, lamination method, powder metallurgy method, laser direct forming method or thin film technology. The present application does not limit this and depends on specific circumstances.

[0105] As Figure 31 shown, the first inductor layer 330 is patterned to form a first inductor 3301 and a second inductor 3302. Among them, the first inductor 3301 is electrically connected to the fourth electrode 3101, and the second inductor 3302 is electrically connected to the first signal lead 280. Specifically, the patterning method of the first inductor layer 330 can be wet etching or dry etching.

[0106] It should also be noted that Figure 31 the shown filtering device includes both a first inductor and a second inductor. However, the present application does not limit this. In other embodiments of the present application, the filtering device may also only include the first inductor or only include the second inductor, depending on specific circumstances.

[0107] As Figure 32As shown in the figure, a dielectric layer D340 (corresponding to the fourth dielectric layer) is formed on the side of the first inductor 3301 and the second inductor 3302 away from the dielectric layer C320. The dielectric layer D340 has a via hole T3401 and a via hole U3402. The via hole T exposes a partial area of the first inductor 3301, and the via hole U3402 exposes a partial area of the second inductor 3302. Optionally, the material of the dielectric layer D can be a photosensitive organic material, such as polyimide (abbreviated as PI), benzocyclobutene (BCB), etc., and is formed by spin coating; the via holes T3401 and U3402 can be obtained through exposure and development.

[0108] As Figure 33 As shown in the figure, a second inductor layer 350 is formed on the side of the dielectric layer D340 away from the dielectric layer C320, and the second inductor layer 350 also fills the via holes T3401 and U3402;

[0109] As Figure 34 As shown in the figure, the second inductor layer 350 is patterned to obtain a third inductor 3501 and a fourth inductor 3502. Among them, the third inductor 3501 is electrically connected to the first inductor 3301 through the via hole T3401, and the fourth inductor 3502 is electrically connected to the second inductor 3302 through the via hole U3402.

[0110] Optionally, the material of the second inductor layer can be a nickel-zinc ferrite material, a manganese-zinc ferrite material, or a metal soft magnetic material, and the forming process can be a winding method, a lamination method, a powder metallurgy method, a laser direct forming method, or a thin film technology; the patterning process of the second inductor layer can be a dry etching process or a wet etching process, and the present application does not limit this, and it depends on the specific situation.

[0111] It should be noted that in this embodiment, Figure 34 the shown filtering device not only includes the first inductor and the second inductor, but also includes the third inductor and the fourth inductor, but the present application does not limit this. In other embodiments of the present application, the filtering device may further include more inductors, depending on the specific situation.

[0112] As Figure 35As shown, a dielectric layer E360 is formed on a side of the third inductor 3501 and the fourth inductor 3502 away from the dielectric layer D340. The dielectric layer E360 has a via V3601 and a via W3602. Among them, the via V3601 exposes a partial area of the surface of the third inductor 3501, and the via W3602 exposes a partial area of the surface of the fourth inductor 3502. Optionally, the material of the dielectric layer E can be a photosensitive organic material, such as polyimide (abbreviated as PI), benzocyclobutene (BCB), etc., and can be formed by spin coating during formation; the via V3601 and the via W3602 are obtained through exposure and development.

[0113] It should be noted that, in this embodiment, the via V3601 and the via W3602 are used for electrical connection with the outside.

[0114] Specifically, in an embodiment of the present application, the third inductor 3501 and the fourth inductor 3502 are respectively electrically connected to the outside through the via V3601 and the via W3602 by wire bonding.

[0115] In another embodiment of the present application, as Figure 36 shown, a pad 370 and a solder ball 380 are sequentially formed in the via V3601 and the via W3602, and then electrically connected to the outside by bumping.

[0116] As can be seen from the above, the filtering device manufactured by using the manufacturing method of the stress mitigation filtering device provided by the embodiment of the present application includes: a substrate as a carrier, an acoustic resonator, and at least one capacitive structure, wherein the acoustic resonator is formed on a first side of the substrate; and the capacitive structure is formed on a second side of the substrate and is electrically connected to at least one electrode of the acoustic resonator through a via. Thus, perforation can start from the substrate as a carrier, not only penetrating the bonding layer, but also sequentially penetrating solid material layers such as the cutoff boundary layer, the sacrificial layer, the dielectric layer, and the piezoelectric layer, forming a via for realizing electrical connection between the capacitor and the acoustic resonator electrode. Since these layers are mainly composed of solid materials with high mechanical strength and toughness, the risk of fracture caused by weak connection of materials (such as the bonding layer) can be significantly reduced during perforation, the local stress concentration that may be introduced by the perforation operation is reduced, and the fracture situation of the filtering device caused by perforation during manufacturing and use is greatly reduced, improving the reliability and stability of the filtering device. Furthermore, the technical problem that the filtering device integrating the acoustic resonator and the capacitive filter in the prior art is prone to fracture is solved.

[0117] In addition, the embodiment of the present application also provides a stress mitigation filtering device manufactured by using the manufacturing method provided in any of the above embodiments.

[0118] As Figure 36 shown, the stress - reducing filter device provided by the embodiment of the present application includes: a substrate B210 as a carrier, an acoustic resonator, and at least one capacitive structure, wherein the acoustic resonator is formed on the first side of the substrate; and the capacitive structure is formed on the second side of the substrate B210 and is electrically connected to at least one electrode of the acoustic resonator through a via hole.

[0119] Optionally, the acoustic resonator includes: a piezoelectric layer 140, a first electrode 131, and a second electrode 152; wherein, the first electrode 131 is located on the side of the piezoelectric layer 140 away from the substrate B210; the second electrode 152 is located on the side of the piezoelectric layer 140 close to the substrate B210; and, the capacitive structure includes a first capacitor and / or a second capacitor; the first capacitor is electrically connected to the first electrode through a first via hole; the second capacitor is electrically connected to the second electrode through a second via hole.

[0120] Optionally, the capacitive structure includes the first capacitor; the first via hole penetrates through the substrate B210, the piezoelectric layer 140 and is in contact with the first electrode 131; and, the first capacitor includes: a first signal lead 280 located in the first via hole and electrically connected to the first electrode 131; a dielectric layer B300 located on the second side of the substrate B210 and covering the first signal lead 280; and a third electrode 3102 located on the side of the dielectric layer B300 away from the substrate B210.

[0121] Optionally, the capacitive structure includes the second capacitor; the second via hole penetrates through the substrate B210 and is in contact with the second electrode 152; and, the second capacitor includes: a second signal lead 290 located in the second via hole and electrically connected to the second electrode 152; a dielectric layer B300 located on the second side of the substrate B210 and covering the second signal lead 290; and a fourth electrode 3101 located on the side of the dielectric layer B300 away from the substrate B210.

[0122] Optionally, the filtering device further includes: a dielectric layer A160 located on a surface of the second electrode 152 away from the piezoelectric layer 140; a sacrificial layer 180 located on a surface of the dielectric layer A160 away from the piezoelectric layer 140; a cut-off boundary layer 190 located on a surface of the sacrificial layer 180 away from the dielectric layer A160; a bonding layer A200 located on a side of the cut-off boundary layer 190 away from the dielectric layer A160; and, the first through hole sequentially penetrates through the substrate B210, the bonding layer A200, the cut-off boundary layer 190, the sacrificial layer 180, the piezoelectric layer 140 and contacts the first electrode 131; the second through hole sequentially penetrates through the substrate B210, the bonding layer A200, the cut-off boundary layer 190, the sacrificial layer 180, the dielectric layer A160 and contacts the second electrode 152.

[0123] Based on the above embodiments, in an embodiment of the present application, the filtering device includes a fourth electrode 3101 and a third electrode 3102, and the filtering device further includes: a first electrode lead-out structure and a second electrode lead-out structure; wherein, the first electrode lead-out structure is electrically connected to the first signal lead 280 or electrically connected to the third electrode 3102, and is used to lead out the electrical connection end of the first electrode 131 for facilitating external electrical connection; the second electrode lead-out structure is electrically connected to the second signal lead 290 or electrically connected to the fourth electrode 3101, and is used to lead out the electrical connection end of the second electrode 152 for facilitating external electrical connection.

[0124] Optionally, in an embodiment of the present application, the filtering device further includes: a pad and a solder ball electrically connected to the second electrode lead-out structure and the first electrode lead-out structure. Specifically, the filtering device includes:

[0125] a first pad and a first solder ball, the first pad is electrically connected to the first electrode lead-out structure, and the first solder ball is electrically connected to the first pad, and is used for electrically connecting the first electrode lead-out structure and the outside;

[0126] a second pad and a second solder ball, the second pad is electrically connected to the second electrode lead-out structure, and the second solder ball is electrically connected to the second pad, and is used for electrically connecting the second electrode lead-out structure and the outside.

[0127] It should be noted that since the detailed structure of the filtering device has been described in detail in the manufacturing method of the filtering device, it will not be elaborated here.

[0128] It should also be noted that although the stress-reducing filter device and its manufacturing method provided in the embodiments of the present application are described by taking the filter device including three capacitors as an example, the present application is not limited thereto. In other embodiments of the present application, the filter device may further include other numbers of capacitors, which depends on the specific situation.

[0129] Although the stress-reducing filter device and its manufacturing method provided in the embodiments of the present application are described by taking the filter device including four inductors as an example, the present application is not limited thereto. In other embodiments of the present application, the filter device may further include other numbers of inductors, which depends on the specific situation.

[0130] In summary, in the stress-reducing filter device and its manufacturing method provided in the embodiments of the present application, the acoustic resonator is formed on the first side of the substrate as a carrier, and the capacitive structure is formed on the second side of the substrate. Thus, it is possible to perforate starting from the substrate as a carrier, which not only penetrates the bonding layer, but also sequentially penetrates solid material layers such as the cutoff boundary layer, the sacrificial layer, the dielectric layer, and the piezoelectric layer, to form a through hole for realizing the electrical connection between the capacitor and the acoustic resonator electrode. Since these layers are mainly composed of solid materials with high mechanical strength and toughness, the risk of fracture caused by weak material connections (such as the bonding layer) can be significantly reduced during perforation, the local stress concentration that may be introduced by the perforation operation is reduced, and the fracture situation of the filter device caused by perforation during the manufacturing and use processes is greatly reduced, thereby improving the reliability and stability of the filter device. Furthermore, the technical problem in the prior art that the filter device integrating the acoustic resonator and the capacitive filter is prone to fracture is solved.

[0131] Each part in this specification is described in a progressive manner. The key point of each part is to illustrate the differences from other parts. For the same or similar parts among each part, reference can be made to each other.

[0132] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A stress-reducing filtering device, characterized in that, Comprising: a first substrate as a carrier, a first bonding layer, a second substrate as a cap, an acoustic resonator, and at least one capacitive structure, wherein the acoustic resonator is formed on a first side of the first substrate; the second substrate is located on a side of the acoustic resonator away from the first substrate and is bonded to the acoustic resonator through the first bonding layer; and the capacitive structure is formed on a second side of the first substrate and is electrically connected to at least one electrode of the acoustic resonator through a via hole; a lateral position of the via hole corresponds to the first bonding layer.

2. The filtering device according to claim 1, wherein The acoustic resonator includes: a piezoelectric layer, a first electrode, a second electrode, and a resonant cavity; wherein, the first electrode is located on a side of the piezoelectric layer away from the first substrate; the second electrode is located on a side of the piezoelectric layer close to the first substrate; the resonant cavity is formed between the piezoelectric layer and the first substrate; and, the capacitive structure includes a first capacitor and / or a second capacitor; the first capacitor is electrically connected to the first electrode through a first via hole; the second capacitor is electrically connected to the second electrode through a second via hole.

3. The filtering device according to claim 2, characterized in that, The capacitive structure includes the first capacitor; the first via hole penetrates through the first substrate, the piezoelectric layer and contacts the first electrode; and, the first capacitor includes: a first signal lead, a part of the first signal lead is electrically connected to the first electrode through the first via hole; another part of the first signal lead overlaps with the first substrate at least partially in a first direction; a first dielectric layer located on the second side of the first substrate and covering the first signal lead; and a third electrode located on a side of the first dielectric layer away from the first substrate.

4. The filtering device according to claim 3, characterized in that, The capacitive structure includes the second capacitor; the second via hole penetrates through the first substrate and contacts the second electrode; and, the second capacitor includes: a second signal lead, a part of the second signal lead is electrically connected to the second electrode through the second via hole; another part of the second signal lead overlaps with the first substrate at least partially in a first direction; a first dielectric layer located on the second side of the first substrate and covering the second signal lead; and a fourth electrode located on a side of the first dielectric layer away from the first substrate.

5. The filtering device according to claim 2, characterized in that, The filtering device further includes: a second dielectric layer located on a surface of the second electrode away from the piezoelectric layer; a sacrificial layer located on a surface of the second dielectric layer away from the piezoelectric layer; a cut-off boundary layer located on a surface of the sacrificial layer away from the second dielectric layer; a second bonding layer located on a side of the cut-off boundary layer away from the second dielectric layer; and, the first via hole sequentially penetrates through the first substrate, the second bonding layer, the cut-off boundary layer, the sacrificial layer, the piezoelectric layer and contacts the first electrode; the second via hole sequentially penetrates through the first substrate, the second bonding layer, the cut-off boundary layer, the sacrificial layer, the second dielectric layer and contacts the second electrode.

6. The filtering device according to claim 1, wherein, The number of capacitors included in the filtering device is greater than or equal to three.

7. The filtering device according to claim 4, wherein The filtering device further includes: A third dielectric layer located on a side of the first dielectric layer away from the first substrate and covering the third electrode and the fourth electrode; and A first inductor and / or a second inductor located on a side of the third dielectric layer away from the first substrate; wherein the first inductor is electrically connected to the fourth electrode, and the second inductor is electrically connected to the first signal lead.

8. The filtering device according to claim 7, wherein, The filtering device further includes: A fourth dielectric layer located on a side of the third dielectric layer away from the first substrate and covering the first inductor and the second inductor; and A third inductor and / or a fourth inductor located on a side of the fourth dielectric layer away from the first substrate; wherein the third inductor is electrically connected to the first inductor, and the fourth inductor is electrically connected to the second inductor.

9. A method for manufacturing a stress-reducing filtering device, characterized in that, Comprising: Fabricating a first substrate as a carrier, a first bonding layer, a second substrate as a cap, an acoustic resonator, and at least one capacitive structure, wherein the acoustic resonator is formed on a first side of the first substrate; The second substrate is located on a side of the acoustic resonator away from the first substrate and is bonded to the acoustic resonator through the first bonding layer; and the capacitive structure is formed on a second side of the first substrate and is electrically connected to at least one electrode of the acoustic resonator through a via hole; a lateral position of the via hole corresponds to the first bonding layer.

10. The manufacturing method according to claim 9, wherein, The step of fabricating the acoustic resonator includes: fabricating a piezoelectric layer, a first electrode, a second electrode, and a resonant cavity; wherein the first electrode is located on a side of the piezoelectric layer away from the first substrate; the second electrode is located on a side of the piezoelectric layer close to the first substrate; the resonant cavity is formed between the piezoelectric layer and the first substrate; And, the step of fabricating the capacitive structure includes: fabricating a first capacitor and / or a second capacitor; the first capacitor is electrically connected to the first electrode through a first via hole; the second capacitor is electrically connected to the second electrode through a second via hole.

11. The manufacturing method according to claim 10, characterized in that, The capacitive structure includes the first capacitor; the operation of fabricating the first via hole includes: starting the first via hole from the first substrate, penetrating through the piezoelectric layer until the first via hole contacts the first electrode; and, the step of fabricating the first capacitor includes: fabricating a first signal lead, a part of the first signal lead is electrically connected to the first electrode through the first via hole; another part of the first signal lead overlaps with the first substrate at least partially in a first direction; fabricating a first dielectric layer located on the second side of the first substrate and covering the first signal lead; and fabricating a third electrode located on a side of the first dielectric layer away from the first substrate; and / or The capacitive structure includes the second capacitor; the operation of fabricating the second through-hole includes: forming a second through-hole from the first substrate until the second through-hole contacts the second electrode; and the step of fabricating the second capacitor includes: fabricating a second signal lead, a part of the second signal lead is electrically connected to the second electrode through the second through-hole; another part of the second signal lead overlaps with the first substrate at least partially in a first direction; fabricating a first dielectric layer located on the second side of the first substrate and covering the second signal lead; and fabricating a fourth electrode located on a side of the first dielectric layer away from the first substrate.

12. The manufacturing method according to claim 10, characterized in that, Further included are: fabricating a second dielectric layer on a surface of the second electrode away from the piezoelectric layer; fabricating a sacrificial layer on a surface of the second dielectric layer away from the piezoelectric layer; fabricating a cut-off boundary layer on a surface of the sacrificial layer away from the second dielectric layer; fabricating a second bonding layer on a side of the cut-off boundary layer away from the second dielectric layer; and the operation of fabricating the first through-hole includes: forming a first through-hole from the first substrate, sequentially penetrating through the bonding layer, the cut-off boundary layer, the sacrificial layer, the piezoelectric layer until the first through-hole contacts the first electrode; the operation of fabricating the second through-hole includes: forming a second through-hole from the first substrate, sequentially penetrating through the second bonding layer, the cut-off boundary layer, the sacrificial layer, the second dielectric layer until the second through-hole contacts the second electrode.

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