Correction circuit

Abstract

A correction circuit for correcting one or more errors in a digitized current signal, the digitized current signal being a digital representation of an analog current signal of a current flowing through an energy storage element, wherein the correction circuit is configured to correct one or more errors in the digitized current signal by comparing the digitized current signal with the analog current signal, and correcting the digitized current signal based on a result of the comparison.

Description

[0001] The present disclosure relates to a correction circuit for correcting one or more errors in a digitized current signal. In particular, the present disclosure relates to a correction circuit applicable to a switching converter.

[0002] background

[0003] Figure 1 is a schematic diagram of a digital buck converter 100 including a power stage 101, analog-to-digital converters (ADCs) 102, 104, 106, and a controller 108. The power stage 101 includes switches 110, 112, an inductor 114, and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0004] When the power stage 101 and passive components (inductor 114 and capacitor 116) remain the same as for the analog buck converter, ADC 102 converts the output voltage VOUT into a digital value. Optionally, the inductor current IL of the inductor 114 and the input voltage VIN can also be converted from analog to digital according to a digital control method.

[0005] We distinguish:

[0006] The switching frequency (FSW) of the buck converter 100, for example 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage.

[0007] The processing frequency (FS) of the digital controller 108 , for example, about 100 MHz. FS is equal to 1 / TS, where TS is the processing period of the controller 108 . Optionally, FS may also be the sampling frequency of the ADC 102 .

[0008] A digital system, such as the digital buck converter 100, may use a digital signal representing the current flowing through the energy storage element during operation. For example, a controller may require a digitized current signal to control the switching operation of a digital switching converter.

[0009] In this example, the digitized current signal is a digitized inductor current DIL as provided by an ADC 104 that converts an analog current signal indicative of the inductor current IL into a digital format. It is to be understood that components and methods other than the ADC 104 may be used to generate the digitized inductor current DIL. The digitized inductor current DIL may be generated using sensor-based or sensorless techniques. The digitized inductor current DIL is provided to a controller 108, which uses information about the inductor current IL to control the switching operation of the power switches 110, 112. The dependence of the control scheme on the inductor current means that such a system may be referred to as a current mode converter using current mode control.

[0010] For efficient operation of a buck converter, or any other digital system that uses a digitized current signal during operation, it is desirable that the digitized current signal DIL accurately represents the analog current signal IL. With reference to the buck converter 100, it is desirable that the digitized inductor current DIL accurately represents the inductor current IL. It should be noted that both the analog current signal and the inductor current may be represented by the variable "IL" to represent the analog current signal representing the current flowing through the inductor. It is to be understood that the analog current signal IL may not be the current signal itself, but may be, for example, a voltage signal representing the current signal.

[0011] Overview

[0012] It would be desirable to provide a system for improving the accuracy of a digitized current signal compared to existing methods.

[0013] According to a first aspect of the present disclosure, there is provided a correction circuit for correcting one or more errors in a digitized current signal, the digitized current signal being a digital representation of an analog current signal of a current flowing through an energy storage element, wherein the correction circuit is configured to correct one or more errors in the digitized current signal by comparing the digitized current signal with the analog current signal and correcting the digitized current signal based on a result of the comparison.

[0014] Optionally, the digitized current signal is provided by a current synthesizer.

[0015] Optionally, the correction circuit is configured to generate a correction signal depending on the result of the comparison and provide the correction signal to the current synthesizer, the correction signal being suitable for correcting one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on the result of the comparison.

[0016] Optionally, the correction circuit is configured to correct an offset error between the digitized current signal and the analog current signal.

[0017] Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine an offset error, and to correct the digitized current signal using the determined offset error.

[0018] Optionally, the correction circuit is configured to determine the offset error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses a first analog threshold, calculating a first duration between the first time step and the second time step, determining a first slope of at least one of the digitized current signal and the analog current signal, and multiplying the first duration by the first slope to determine the offset error.

[0019] Optionally, the first digital threshold is approximately equal to the digitized first analog threshold.

[0020] Optionally, the correction circuit comprises a comparator configured to provide an output indicative of the analog current signal crossing a first analog threshold, the output being used to determine the second time step.

[0021] Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal.

[0022] Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine a relative slope error, and to correct the digitized current signal using the determined relative slope error.

[0023] Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses the first analog threshold, detecting a third time step when the digitized current signal crosses the second digital threshold, detecting a fourth time step when the analog current signal crosses the second analog threshold, calculating a first digital slope delay between the first time step and the third time step, calculating a first analog slope delay between the second time step and the fourth time step, dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, and then subtracting 1 from the first delay parameter to determine the relative slope error.

[0024] Optionally, the correction circuit is configured to correct a relative slope error between the digitized current signal and the analog current signal.

[0025] Optionally, the correction circuit is configured to correct the relative slope error before correcting the offset error.

[0026] Optionally, the correction circuit is configured to compare the digitized current signal with the analog current signal to determine a relative slope error and an offset error, and to correct the digitized current signal using the determined relative slope error and offset error.

[0027] Optionally, the correction circuit is configured to determine the relative slope error by detecting a first time step when the digitized current signal crosses a first digital threshold, detecting a second time step when the analog current signal crosses the first analog threshold, detecting a third time step when the digitized current signal crosses the second digital threshold, detecting a fourth time step when the analog current signal crosses the second analog threshold, calculating a first digital slope delay between the first time step and the third time step, calculating a first analog slope delay between the second time step and the fourth time step, dividing the first analog slope delay by the first digital slope delay to calculate a first delay parameter, and then subtracting 1 from the first delay parameter to determine the relative slope error.

[0028] Optionally, the correction circuit is configured to determine the offset error by calculating a first duration between a first time step and a second time step, determining a first slope of the analog current signal by subtracting the second analog threshold from the first analog threshold to calculate an analog threshold difference, dividing the analog threshold difference by the first analog slope delay, and multiplying the first slope of the analog current signal by the first duration to determine the offset error.

[0029] Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal during operation of the switching converter including the energy storage element.

[0030] Optionally, the switching converter is one of a buck converter, a boost converter and a buck-boost converter.

[0031] Optionally, the energy storage element comprises an inductor.

[0032] Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal two or more times during operation of the switching converter, either in response to an external signal, or in response to one of the one or more errors exceeding a threshold, or in response to a mode change of the switching converter, or in response to a transient.

[0033] Optionally, the correction circuit is configured to correct one or more errors in the digitized current signal periodically or aperiodically during operation of the switching converter.

[0034] According to a second aspect of the present disclosure, there is provided a method for correcting one or more errors in a digitized current signal using a correction circuit, wherein the digitized current signal is a digital representation of an analog current signal of current flowing through an energy storage element, the method comprising comparing the digitized current signal with the analog current signal, and correcting the digitized current signal based on a result of the comparison.

[0035] It is to be understood that the method of the second aspect may include the features set out in the first aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0038] Figure 1 is a schematic diagram of a digital buck converter;

[0039] Figure 2 yes Figure 1 A graph of inductor current variation with time during operation of a buck converter;

[0040] Figure 3 is a timing diagram illustrating an example of how parameters associated with the operation of a buck converter vary over time during operation;

[0041] Figure 4 shows a timing diagram illustrating an example of how parameters related to the operation of a buck converter vary over time during operation and for different inductor current values;

[0042] Figure 5 is a timing diagram showing representative waveforms of a digital inductor current and an inductor current IL due to a load transient during operation of a buck converter;

[0043] FIG. 6( a ) is a schematic diagram of a correction circuit according to a first embodiment of the present disclosure, and FIG. 6( b ) is a schematic diagram of a correction circuit and an energy storage element according to a second embodiment of the present disclosure;

[0044] Figure 7 is a timing diagram showing a digitized current signal and an analog current signal during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a );

[0045] Figure 8 is a timing diagram showing a digitized current signal and an analog current signal during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a );

[0046] FIG. 9( a ) is a timing diagram of a digitized inductor current during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a ); FIG. 9( b ) is a timing diagram of a digitized inductor current during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a );

[0047] Fig.10 is a timing diagram showing a digitized current signal and an analog current signal during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a );

[0048] Fig.11 is a schematic diagram of a specific embodiment of a correction circuit and a switching converter according to a third embodiment of the present disclosure;

[0049] Fig.12 is an example of an exemplary embodiment of the present disclosure, for example Fig.11 The timing of the digitized current signal and the analog current signal during operation of the device shown in;

[0050] Fig.13 is a timing diagram showing simulation results of a practical implementation of a known system using a low bandwidth correction mechanism;

[0051] FIG. 14( a ) shows Fig.11 FIG. 14( b ) is a timing diagram of simulation results of an actual implementation of the system shown in FIG. 14( a ) on a shorter time scale; and

[0052] Fig.15 is a schematic diagram of a comparator unit, which can be used to Fig.11 One or both of the two comparator units.

[0053] Detailed Description

[0054] Figure 2 yes Figure 1 FIG. 1 is a graph of inductor current IL versus time during operation of buck converter 100. During operation, inductor 114 switches between coupling to input voltage VIN via switch 110 (magnetization phase, labeled with numeral 202) and coupling to ground PGND via switch 112 (demagnetization phase, labeled with numeral 204).

[0055] The graph shows a first trace 206 showing an ideal inductor current. The inductor current IL may have an ideal shape consisting of a straight line, as used in US9419627B2 and US9667260B2. The graph also shows a second trace 208 showing a more realistic current profile, where the slope of each stage has a non-linear shape (exponential decay for the falling slope).

[0056] Note that the timing diagrams are continuous in time and continuous in data to aid in clarity of interpretation.

[0057] For some switching converters, a straight-line approximation of the inductor current IL may be sufficient for an effective control scheme. However, it is desirable to have a more accurate, nonlinear, digitized inductor current DIL waveform, as this may ensure more accurate current control. Furthermore, the digitized inductor current DIL with improved accuracy may be used for additional applications besides regulation, for example, for overcurrent protection.

[0058] As known to the skilled person, there are several suitable methods for generating the digitized inductor current DIL. For example, the digitized inductor current DIL can be generated using Figure 1 The described ADC 104 generates, or may generate using, a current synthesizer. The following description relates to generating the digitized inductor current DIL using a current synthesizer.

[0059] In the discrete time domain (timed as TS, which is the processing cycle of the controller 108), the digitized inductor current DIL during the magnetization phase can be expressed as follows:

[0060]

[0061] The digitized inductor current DIL during the demagnetization phase can be expressed as follows:

[0062]

[0063] Variable R MAG and R DEMAG Therefore, the nonlinear corrections to the ideal slope are made in the magnetization phase and the demagnetization phase, respectively. L is the inductance of the inductor 114, DIN is the digital input voltage signal, DOUT is the digital output voltage signal, and n is an integer.

[0064] R MAG =DCR+RHS (3)

[0065] R DEMAG =DCR+RLS (4)

[0066] Wherein, RHS is the on-resistance of transistor 110 , RLS is the on-resistance of transistor 112 , and DCR is the series resistance of inductor 114 .

[0067] It is to be appreciated that the digitized inductor current DIL may have a profile as shown by trace 206 by setting R MAG =R DEMAG = 0 This distribution is obtained using a straight line approximation.

[0068] A current synthesizer may be used to generate the digitized inductor current DIL using equations (1) to (4).

[0069] As an example, referring to equations (1)-(4), it is clear that achieving accurate digitization of the inductor current DIL depends on the precise values ​​of the parameters used in the equations (e.g., L, RHS, RLS, DCR, DIN, DOUT). Other sources of error may include, but are not limited to:

[0070] Drive speed

[0071] Dead-time between LS and HS switch conduction

[0072] Temperature change of resistance

[0073] Inductor aging.

[0074] Errors due to temperature tend to vary slowly. The error in the digitized inductor current DIL is related to the change in driver speed with a time constant of L / R, where R is given by:

[0075] R=D.(RHS+DCR)+(1-D).(RLS+DCR) (5)

[0076] Where D is the duty cycle of the buck converter 100. Errors associated with the dead time may occur within one clock cycle. The accumulation of these errors can introduce a large difference between the digitized inductor currents DIL and IL (up to 1.3A observed in simulations).

[0077] Figure 3 3 is a timing diagram showing an example of how parameters related to the operation of buck converter 100 vary over time during operation. Trace 300 shows the inductor current IL varying over time; trace 302 shows the pulse width modulation (PWM) signal varying over time; and trace 304 shows the voltage at the switch node SW. The PWM signal is used to control the switching operation of buck converter 100, and the use of PWM in this context is well known to the skilled person.

[0078] Figure 3The timing diagram of FIG. 1 shows a simplified and enlarged view of the driver delay (Tdly1 , Tdly2 ) and dead zone (Tdz1 , Tdz2 ) for a specific inductor current IL.

[0079] In this case, there is a delay (Tdly1) between the rising edge of the PWM signal and the power switch responding to that change. There is a similar (but not equal) delay (Tdly2) on the falling edge of the PWM signal.

[0080] From a simulation point of view, we consider MAG (for magnetizing phase) to be the portion of time when the inductor current IL is rising and the inductor current IL is close to zero.

[0081] From equations (1) and (2), it can be seen that the expression during the magnetization phase is different from the expression during the demagnetization phase, so it is desirable to know the timing of the transitions between these phases accurately. If the PWM signal is used to identify the time of the transition, it is obvious that this will introduce errors due to Tdly1 and Tdly2.

[0082] Furthermore, the different slope of the inductor current IL during the dead time Tdz1 and Tdz2 compared to the slope during the rest of the magnetizing phase (where SW=VIN) is not taken into account in equations (1) and (2). The above errors are highly dependent on IL, VIN, VOUT and temperature.

[0083] Figure 4 A timing diagram is shown which illustrates an example of how parameters related to the operation of the buck converter 100 vary over time during operation and for different values ​​of the inductor current IL.

[0084] Figure 4 1 shows how the effective MAG duration varies with the inductor current IL (for a fixed desired PWM duration). More precisely, the effective MAG duration varies according to the valley current (IL_valley) and peak current (IL_peak) of the inductor current IL at the end of the MAG phase and at the end of the DEMAG phase. This is due to the current conduction through the freewheeling diode that depends on the polarity of the inductor current IL. The change in the switch node SW voltage depends on the polarity of the inductor current IL at the end of the DEMAG and at the end of the MAG.

[0085] These errors (and more) can be corrected in a feed-forward fashion, which can reduce the magnitude of the (DIL-IL) error. However, even small residuals can be integrated and eventually result in differences that increase over time.

[0086] Figure 55 is a timing diagram showing representative waveforms of the digital inductor current DIL (trace 500 ) and the inductor current IL (trace 502 ) due to a load transient during operation of the buck converter 100 .

[0087] After a transient, there is a mismatch between the waveforms. For a single-phase converter, the error between DIL and IL may still allow the system to function, but is still undesirable due to performance degradation under transient loads and the fact that the digitized inductor current DIL is not suitable for applications such as overcurrent protection. For multi-phase converters, mismatches between the phase currents are highly undesirable as they degrade transient performance and efficiency. When the errors in DIL relative to IL are independent of each other, the effective mismatch between the inductor current IL of two different converter stages can be doubled relative to the DIL relative to IL mismatch of a single-phase converter.

[0088] It is desired that the digitized inductor current DIL has the following characteristics:

[0089] Compared to the exact average value of IL

[0090] · Exact ripple amplitude compared to IL

[0091] Rapid correction of any introduced errors

[0092] No time-dependent differences relative to IL

[0093] Nonlinear shape similar to IL.

[0094] 6( a ) is a schematic diagram of a correction circuit 600 for correcting one or more errors in a digitized current signal DIL according to a first embodiment of the present disclosure. The digitized current signal DIL is a digital representation of an analog current signal IL of a current flowing through an energy storage element 602 .

[0095] It should be noted that the variables "IL" and "DIL" are used to be consistent with the previous description, in which the energy storage element includes an inductor as part of a buck converter. In this embodiment, energy storage element 602 is generally considered. In specific embodiments, energy storage element 602 can include an inductor or a different circuit component, as understood by a skilled person.

[0096] During operation, the correction circuit 600 corrects one or more errors in the digitized current signal DIL by comparing the digitized current signal DIL with the analog current signal IL and then correcting the digitized current signal DIL based on a result of the comparison.

[0097] The digitized current signal DIL may be provided by a current synthesizer 612 . The correction circuit 600 may be configured to generate a correction signal 601 depending on a result of the comparison, and to provide the correction signal 601 to the current synthesizer 612 .

[0098] The correction signal 601 is a signal suitable for correcting one or more errors in the digitized current signal DIL when received by the current synthesizer 612. Thus, during operation, the current synthesizer 612 uses the correction signal 601 to correct the digitized current signal DIL based on the result of the comparison.

[0099] The correction signal 601 may include information related to a mismatch between the two signals IL, DIL, such as occurs when the digitized current signal DIL is not an accurate digital representation of the analog current signal IL. The current synthesizer 612 may then use the information provided by the comparison signal 601 to adjust or otherwise correct the digitized current signal DIL to reduce the mismatch and ensure that it more accurately digitally represents the analog current signal IL.

[0100] If the digitized current signal DIL is already a sufficiently accurate representation of the analog current signal IL, as may be defined by a threshold, then the mismatch indicated by the correction signal 601 may be suitably small such that no correction needs to be applied by the current synthesizer 612 .

[0101] 6( b ) is a schematic diagram of a correction circuit 600 and an energy storage element 602 according to a second embodiment of the present disclosure. In this embodiment, the energy storage element 602 is a component of a switching converter 604 , which includes at least one power switch 606 .

[0102] In this embodiment, the correction circuit 600 corrects one or more errors in the digitized current signal DIL during operation of the switching converter 604. The switching converter 604 may be a buck converter, a boost converter, or a buck-boost converter.

[0103] The correction circuit 600 can correct one or more errors in the digitized current signal DIL on one or more occasions. In a particular embodiment, the correction can be performed periodically or aperiodically. In another embodiment, the correction can be performed in response to an external signal; in response to at least one of the errors exceeding a threshold; in response to a transient; or in response to a mode change of the switching converter. In another embodiment, the correction can be applied based on one or more of the above situations.

[0104] It is to be understood that the correction process may be applied more than once during operation of the overall system including the energy storage element 602. This may be necessary if an event occurs that causes an increase in the mismatch between the digitized current signal DIL and the analog current signal IL, such as a transient.

[0105] In certain embodiments, the correction circuit 600 may be configured to correct an offset error between the digitized current signal DIL and the analog current signal IL.

[0106] Figure 7 6( a) during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a). In this example, there is an offset error (represented by ΔI) between the digitized current signal DIL (trace 700) and the analog current signal IL (trace 702).

[0107] As previously mentioned, a continuous time and value representation of the digitized current signal DIL is used to aid clarity of explanation. However, in reality, the digitized current signal DIL comprises values ​​that vary with discrete time steps.

[0108] The following description assumes that the energy storage element 602 is an inductor used as part of a buck converter. However, it is to be understood that the concept is applicable to other switching converter topologies, including but not limited to boost converters, buck-boost converters, and multi-switch converters, according to the understanding of the skilled person.

[0109] Reference Figure 7 , the waveforms IL, DIL are phase aligned because the digitized inductor current DIL is a digital representation of the analog inductor current IL. In addition, the slew rates of the digitized inductor current DIL and the analog inductor current IL are equal during the demagnetization phase (denoted by "DEMAG"), which is also assumed to be true during the magnetization phase (denoted by "MAG"). The slew rate is denoted by "SR" and has units of amperes per unit time (e.g., A / s, where "A" means amperes and "s" means seconds). Slew rates may also be referred to as "slopes".

[0110] The offset error ΔI indicates the mismatch between the average levels of the digitized current signal DIL and the analog current signal IL (which may be referred to as their direct current (DC) levels). In order to accurately represent the analog current signal IL with the digitized current signal DIL, the offset error ΔI should be approximately equal to zero.

[0111] With regard to certain embodiments of the present disclosure, to correct the offset error ΔI, the correction circuit 600 compares the digitized current signal DIL with the analog current signal IL to determine the offset error ΔI. Using this information, the correction circuit 600 then corrects the digitized current signal DIL to reduce the offset error ΔI to approximately zero, thereby correcting the digitized current signal DIL.

[0112] In this example, the digital threshold DISET1 has its analog representation ISET1, which is obtained via DAC 704, which receives the threshold DISET1 to generate Figure 7 The digital threshold DISET1 is approximately equal to the analog threshold ISET1 because the two signals represent the same quantity in different domains. Therefore, the thresholds DISET1 and ISET1 are Figure 7 Center alignment.

[0113] The digital threshold DISET1 may be any threshold between the peak value of the digitized inductor current DIL and the valley value of the digitized inductor current DIL, and the analog threshold ISET1 is similarly defined with respect to the analog inductor current IL.

[0114] Point P1 is obtained from the digitized inductor current DIL (digital signal) crossing a digital threshold DISET1. It is to be understood that this is a digital comparison.

[0115] Point P2 is obtained from the simulated inductor current IL (real analog signal) crossing the real threshold ISET1. This simulated comparison will result in a real event (eg, comparator output).

[0116] In certain embodiments, the correction circuit 600 may include a comparator (not shown) configured to provide an output indicating that the analog current signal IL has crossed the threshold value ISET1 , wherein the output is used to determine the time step t2 .

[0117] Using the two comparison points P1, P2, the offset ΔI between the DIL and IL waveforms can be determined.

[0118] In a specific embodiment, the offset error ΔI is determined by the correction circuit 600 in the following manner: first, when the digitized current signal DIL crosses the digital threshold DISET1, the time step t1 is detected at the point P1; when the analog current signal IL crosses the analog threshold ISET1, the time step t2 is detected at the point P2; and then the duration ΔT between the two time steps is calculated. ΔT can be calculated by subtracting the time step t2 from the time step t1.

[0119] Furthermore, the correction circuit 600 is configured to determine a slope SR of one of the signals IL, DIL. In the present embodiment, the slopes are equal and thus the slope SR may be determined from either of the signals DIL, IL.

[0120] During operation, the correction circuit 600 then determines the offset error ΔI using the following relationship between the slope SR and the duration ΔT.

[0121] ΔI = SR. ΔT (6)

[0122] If SR and ΔT can be measured (or otherwise known), the offset between the waveforms can be corrected.If ΔI=0, the two waveforms DIL and IL are aligned, which means that the DIL representation of IL is accurate.

[0123] If the waveforms IL, DIL are spaced apart so that the simulated inductor current IL does not cross the threshold ISET1, the exact value of the offset can be determined by first applying a coarse correction to try to make the two waveforms DIL, IL close enough for measurement.

[0124] In another specific embodiment, the correction circuit 600 may be configured to correct a relative slope error between the digitized current signal DIL and the analog current signal IL.

[0125] Figure 8 6( a) during operation of the device shown in FIG. 6( a). In this example, there is a relative slope error between the digitized current signal DIL (trace 800) and the analog current signal IL (trace 802).

[0126] like Figure 7 , Figure 8 A digitized current signal DIL having a continuous time representation is shown, and the following examples will be described with respect to a buck converter.

[0127] In this example, the slopes are not equal. The slope of the digitized inductor current DIL is labeled "SR_DIL" and the slope of the simulated inductor current IL is labeled "SR_IL".

[0128] With respect to certain embodiments of the present disclosure, in order to correct the relative slope error, the correction circuit compares the signals IL and DIL to determine the relative slope error SR_ERR. Using this information, the correction circuit 600 then corrects the digitized current signal DIL to reduce the relative slope error SR_ERR to approximately zero, thereby correcting the digitized current signal DIL.

[0129] In this example, the thresholds ISET1 and DISET1 are as follows: Figure 7 In this example, the digital threshold ISET2 has its analog representation ISET2 obtained via DAC 804, which receives the threshold DISET2 to generate Figure 8 The digital threshold DISET2 is approximately equal to the analog threshold ISET2 because the two signals represent the same quantity in different domains. Therefore, the thresholds DISET2 and ISET2 are Figure 8 Center alignment.

[0130] Point P3 is obtained from the digitized inductor current DIL (digital signal) crossing the digital threshold DISET2. It is to be understood that this is a digital comparison.

[0131] Point P4 is obtained from the simulated inductor current IL (real analog signal) crossing the real threshold ISET2. This simulated comparison will result in a real event (eg, comparator output).

[0132] In a specific embodiment, the relative slope error SR_ERR is determined by the correction circuit 600 in the following manner: Figure 7 As described, time steps t1 and t2 are detected; when the digitized current signal DIL crosses the digital threshold DISET2, time step t3 is detected at point P3; when the analog current signal IL crosses the analog threshold ISET2, time step t4 is detected at point P4; the digital slope delay ΔT_DIL between time steps t1 and t3 is calculated; the analog slope delay ΔT_IL between time steps t2 and t4 is calculated; and the slope delays ΔT_DIL and ΔT_IL are divided, that is, To calculate the relative slope error SR_ERR.

[0133] We can define the following equation related to the threshold:

[0134] ΔISET = ISET1 - ISET2 (7)

[0135] ΔDISET=DISET1-DISET2(8)

[0136] As previously described, the three delay measurements ΔT, ΔT_DIL, ΔT_DIL may be derived from the results of a digital comparison of the digitized inductor current DIL with the digital thresholds DISET1, DISET and an analog comparison of the analog inductor current IL with the analog thresholds ISET1, ISET2.

[0137] The relative slope error SR_ERR can be calculated as follows:

[0138]

[0139] Where SR_DIL is the slope of the digitized inductor current DIL, and SR_IL is the slope of the analog inductor current IL.

[0140] The value of the relative slew rate of the analog inductor current IL and the digitized inductor current DIL is provided by the relative slope error SR_ERR and can be used to correct the digitized inductor current DIL signal to align its slope SR_DIL with the slope of the analog inductor current SR_IL.

[0141] There are several methods for adjusting the slope SR_DIL, which will be clear to the skilled person. For example, referring to equations (1) and (2), one option is to change the value of the L parameter used in the expression for calculating DIL[n]. L represents the inductance of the inductor of the energy storage element 602.

[0142] In another embodiment, the correction circuit 600 may be configured to correct for relative slope error and offset error. For example, the correction circuit 600 may be configured to compare the digitized current signal DIL with the analog current signal IL to determine the offset and relative slope errors, and then correct the digitized current signal DIL based on the determined errors.

[0143] In certain embodiments, expressions (1) and (2) may be modified as follows to allow for corrections to errors and slopes to be taken into account when generating the digitized inductor current DIL[n]:

[0144]

[0145]

[0146] Since the expressions provided by equations (10) and (11) are recursive (depending on the previous value), the offset correction only needs to be done once after the calculation (to avoid integrating the correction).

[0147] Once the offset error is corrected, all future DIL[n] will be corrected. The relative slope error term SR_ERR can (and should) be used in each subsequent DIL[n] value calculation.

[0148] Can be about Figure 7 or Figure 8 The relative slope error can be determined as described with respect to Figure 8 Definitely as described.

[0149] It is desirable that the slopes of the waveforms DIL, IL are equal during the demagnetization phase (DEMAG) and the magnetization phase (MAG) and before correcting the offset error. Therefore, in certain embodiments, the relative slope error may be corrected before correcting the offset error.

[0150] Reference Figure 8 The following equation can be used to determine the offset error:

[0151] ΔI = SR_IL. ΔT (12)

[0152] in:

[0153]

[0154] Equations (12) and (13) can be used to correct the offset error ΔI after the relative slope error is corrected.

[0155] If a relative slope error exists, then it is preferred to apply the relative slope error correction before correcting the offset error. However, embodiments of the present disclosure may apply the offset error correction before the relative slope error correction. Other embodiments may only apply the offset error correction.

[0156] FIG9(a) is a timing diagram of the digitized inductor current DIL during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG6(a). In this example, the offset error is corrected by aligning the digitized inductor current DIL (trace 900) with the simulated inductor current IL (trace 902). In this example, the digitized inductor current DIL is aligned with the simulated inductor current IL at thresholds DISET1, ISET1.

[0157] FIG9( b) is a timing diagram of the digitized inductor current DIL during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG6( a). In this example, the offset error is corrected by aligning the digitized inductor current DIL (trace 904) with the simulated inductor current IL (trace 906). In this example, the digitized inductor current DIL is aligned with the simulated inductor current IL at thresholds DISET2, ISET2.

[0158] If the slope of DIL (SR_DIL) and the slope of IL (SR_IL) are not the same and the offset is corrected, the two waveforms may be aligned at the ISET1, DISET1 thresholds (as shown in Figure 9(a)) or may be aligned at the ISET2, DISET2 thresholds (as shown in Figure 9(b)). However, the average digitized inductor current (which can be expressed as <dil>) and the average simulated inductor current (which can be expressed as <il>) will not be equal.

[0159] Fig.10 6( a) is a timing diagram showing a digitized current signal DIL and an analog current signal IL during operation of an example embodiment of the present disclosure, for example, involving the apparatus shown in FIG. 6( a), where the energy storage element 602 is an inductor as part of a buck converter. This example may be used as described in reference to Figure 8 Describes the offset error correction and relative slope error correction methods.

[0160] In this example, during operation, the relative slope error and then the offset error are corrected by the correction circuit 600. A trace 1000 of the digitized inductor current DIL and a trace 1002 of the simulated inductor current are shown. In this example, the correction circuit 600 applies the relative slope error correction and the offset error correction at the end of two consecutive demagnetization phases at time 1006 and time 1008. After time 1008, it can be seen that the signals DIL, IL are aligned and therefore the correction circuit 600 has corrected the digitized current signal DIL. It is to be understood that in another embodiment, the correction can be applied at the end of the magnetization phase instead of being applied at the end of the demagnetization phase. It is to be understood that in another embodiment, the correction can be applied at any point in time during the switching cycle.

[0161] In further embodiments, the correction process provided by the correction circuit 600 may be applied based on one or more of the following conditions:

[0162] Each switching cycle

[0163] Every N switching cycles, where N is an integer

[0164] Aperiodic

[0165] On demand, such as determined by measurement error or by an external source

[0166] When the calculated error exceeds a predefined threshold

[0167] When the mode changes (for example, when changing from single-stage operation to multi-stage operation)

[0168] When a transient is detected (such as a load transient, power transient, or temperature change).

[0169] These corrections thus prevent any residual error from accumulating. Although these corrections themselves may still have some residual error, they are implemented as long as necessary to limit the (DIL-IL) error.

[0170] Fig.11 6 is a schematic diagram of a specific embodiment of a correction circuit 600 and a switching converter 604 according to the third embodiment of the present disclosure, wherein the switching converter 604 is a buck converter. In this embodiment, the buck converter 604 includes a capacitor 1100, a power switch 606 as a high-side switch, and a low-side switch 1101; the correction circuit 600 includes a logic block 1102 and two comparator units 1104; an analog-to-digital converter (which can be used as a current synthesizer 612 as described above and generates a DIL based on equations (1) and (2)); the comparison circuit 608 includes a timing extraction unit 1106, a timing extraction unit 1108, an offset and relative slope error extraction unit 1110, and an optional filter unit 1112. The timing extraction unit 1108 includes a time to digital converter 1108a, 1108b.

[0171] It is to be understood that ADC 612 represents one method of generating the digitized inductor current DIL and that further embodiments may use alternative methods of digitized inductor current DIL generation as understood by the skilled person. The method of digitizing the inductor current DIL may be, for example, sensor-based or sensorless.

[0172] In the present embodiment, each comparator unit 1104 comprises a comparator. It is to be understood that in further embodiments, alternative implementations are possible according to the understanding of the skilled person.

[0173] In this example, the current IL is sensed by measuring the voltage drop across the low-side switch LS1101, and is described in more detail below. In another embodiment, the current IL can be sensed using the HS switch 606, and then the alignment of IL and DIL can occur during MAG rather than during DEMAG. As previously described, both the analog current signal IL (for comparison with the digitized current signal DIL) and the current flowing through the inductor 602 are represented by the variable "IL" to represent the analog current signal IL representing the current flowing through the inductor. Logic block 1102 is used to generate DISET1 and DISET2 so that they are between the peak value of DIL and the valley value of DIL.

[0174] In this embodiment, the offset error signal (denoted by I_ERR) and the relative slope error (denoted by SR_ERR) are examples of the previously described correction signal 601. Using the information provided by these signals, the current synthesizer 612 corrects the offset error and relative slope error in the generation of the digitized inductor current DIL.

[0175] Fig.12 is an example of an exemplary embodiment of the present disclosure, for example Fig.11 1200 and the timing of the digitized current signal DIL (trace 1200) and the analog current signal IL (1202) during the operation of the device shown in FIG. Also shown are a first comparator output signal COMP1 (trace 1204) as an output of a comparator from one of the comparator units 1104; a second comparator output signal COMP2 (trace 1206) as an output of a comparator from another comparator unit 1104, and a clock signal CLKS (trace 1208).

[0176] In the previous timing diagrams, the digitized inductor current DIL is shown as continuous time. As discussed, in practice, the digitized inductor current DIL will be a discrete time, discrete value digital signal. The analog current signal IL represents the real inductor current and is therefore continuous in time and value.

[0177] It is to be understood that there are a number of possible methods for determining the timing of the points discussed previously. The following discussion involves reference to Fig.11 and Fig.12 One such example method is described.

[0178] Fig.12 Points C and D on the graph refer to the real current IL(t) flowing through the inductor 602. In this example, the comparator unit 1104 is used to detect the simulated inductor current IL and compare the simulated inductor current IL with the threshold values ​​ISET1 and ISET2. Each of the two comparator units 1104 is configured to compare the simulated inductor current IL with one of the threshold values ​​ISET1 and ISET2.

[0179] In this embodiment, the comparator will detect the digitized inductor current IL as a voltage drop across the device resistance of the low side switch 1101. The thresholds ISET1, ISET2 are voltage references 1114 obtained from the digital thresholds DISET1, DISET2 via a DAC.

[0180] Assuming zero offset and zero delay of the comparators of the comparator unit 1104, outputs COMP1 and COMP2 will be generated. The rising edge of COMP1 represents point C, and the rising edge of COMP2 represents point D. The delay between these signals can then be measured and converted into digital values ​​via a timing extraction unit 1108 including time to digital converters 1108a, 1108b. It is to be understood that in further embodiments, alternative methods may be used to extract the timing delays, as understood by the skilled person.

[0181] Points A and B refer to the digitized inductor current DIL[n], which is a discrete-time, discrete-value signal. A simple way to calculate the T_AB delay is to monitor the digitized inductor current DIL value at each clock cycle and determine if the DISET1 (or DISET2) level has been crossed.

[0182] By knowing the values ​​of the digitized inductor current DIL before and after the crossing, an interpolation (e.g., linear interpolation) can be performed to determine the time when the digitized inductor current DIL crosses DISET1 or DISET2. By knowing the integer number of clock cycles between A and B and the fractional part of the processing period TS, the time step T_A, and the time step T_B, the total T_AB can be calculated. T_AB can correspond to ΔT_DIL, as described with respect to Figure 8 described.

[0183] The determination of the delay T_AC uses two points referenced to two different signals DIL, IL located in different domains (digital and analog). A potential solution is to measure the time T_C instead of directly measuring T_CD. This allows T_AC to be calculated as:

[0184] T_AC = T_A+ N.TS - T_C (14)

[0185] where N is the integer number of clock cycles that elapse between the end of the T_A measurement and the end of the T_C measurement, Fig.12 Where N=2.

[0186] It is to be understood that the method used to determine T_AC can also be applied to the determination of T_BC or T_BD.

[0187] It is important to understand that Fig.12 The digitized inductor current DIL and the simulated inductor current IL shown in both include linear slopes when their values ​​increase or decrease.

[0188] It is important to understand that Fig.12 The described method of extracting the time delays T_AB, T_CD, T_AC, T_BD can also be applied to non-linear slopes, such as exponential decay waveform portions including both IL and DIL. However, the accuracy may be reduced compared to the linear example because the method described above uses a linear slope approximation. It is to be understood that for non-linear slopes, different methods of determining the delays may be performed according to the understanding of the skilled person.

[0189] Fig.13 1 is a timing diagram showing simulation results of an actual implementation of a known system using a low bandwidth correction mechanism. The output voltage of the buck converter (trace 1300); the simulated inductor current IL (trace 1302); the digitized inductor current DIL (trace 1303); and the current error I_ERR (trace 1304) which is equal to DIL-IL after filtering. Traces 1302, 1303 appear to overlap in the figure.

[0190] Due to the long settling time (greater than 500 μs), the error I_ERR before the transient (such as that occurring at time TA) is small. After the load transient, the large error I_ERR accumulates quickly. The error I_ERR decreases at a very slow rate over time to a minimum value of -740 mA.

[0191] FIG. 14( a ) is a timing diagram showing Fig.11 The simulation results show the same Fig.13 The same load transient shown in Figure 2 and in this example, the system Fig.13 The example shown in reaches steady state faster. The output voltage of the buck converter (trace 1400); simulated inductor current IL (trace 1402); digitized inductor current DIL (trace 1403); current error I_ERR which is equal to DIL-IL after filtering (trace 1404); digitized inductor current slope SR_DIL (trace 1406); and simulated inductor current slope SR_IL (trace 1408) are shown.

[0192] The error I_ERR starts at a similar value (45mA) and reaches -290mA due to the error caused by the load transient. The error I_ERR is then quickly corrected. SR_IL and SR_DIL before and after the load transient are also shown. Despite the filtering applied to the slope correction, SR_IL and SR_DIL can still converge quickly. In another embodiment, the relative slope error can be fully corrected within one cycle.

[0193] Figure 14(b) is a timing diagram of Figure 14(a) on a shorter time scale. The offset correction is applied at the end of MAG (t=251 μs).

[0194] Fig.15 is a schematic diagram of a comparator unit 1500, which can be used to Fig.11 The comparator unit 1500 includes switches 1502, 1504, 1506, 1508, 1510, 1512; capacitors 1514, 1516, 1518; an operational amplifier (op amp) 1520 and a comparator 1522.

[0195] The example above mentions the desire for zero-delay, zero-offset comparators to determine points C and D. For the present disclosure, some approximations can be made to allow for effective simulation of zero-delay, zero-offset comparators. By illustrating that the properties of a buck converter (or other switching converter) allow for some assumptions to be made about the inputs to these comparators, this example can achieve zero offset and zero delay when used in the embodiments disclosed herein.

[0196] The absolute comparator delay is not important when determining T_CD, as long as the delay between the two comparators is matched. However, the absolute delay of the comparator is important for offset correction (based on point C or point D).

[0197] Considering Fig.15 When IL=ISET1 or IL=ISET2, one of the inputs to comparator 1522 will be a constant (VN) and the other will have a relatively predictable slope defined by SR_IL. Current source 1114 is sized in a way that comparator 1522 toggles when IL=ISET1 or IL=ISET2.

[0198] The system 1500 can achieve near zero offset and near zero delay considering the IL slope constant. The system 1500 samples the residual voltage VOFFS when the comparator 1522 switches and based on this, adjusts the additional offset (VOFFS_COMP) of the input of the comparator 1522 so that VP = (VSW_SNS + VOFFS_COMP).

[0199] Steady state is achieved when comparator 1522COMP switches exactly when the residual offset VOFFS is zero. This results in an effectively zero delay and zero offset comparator.

[0200] This is valid if the slope of the inductor current SR_IL does not change. When the slope changes (due to VIN / VOUT, load transients, or temperature effects), the system will introduce errors until it settles to the new steady state again.

[0201] In summary, embodiments of the present disclosure may be used to correct DIL-IL errors in terms of offset and ripple (via slope adjustment). The specific embodiments described herein perform correction of offset errors in the digitized inductor current DIL in a switch-mode power converter by aligning the digitized inductor current DIL with one or more measurement points of the real inductor current (or a signal derived from the real inductor current) labeled "IL". Embodiments of the present disclosure perform correction of slope (slew rate) errors of the digitized inductor current DIL in a switch-mode power converter by aligning the digitized inductor current DIL with two or more measurement points of the real inductor current (or a signal derived from the real inductor current) labeled "IL". Embodiments of the present disclosure perform correction of offset and slope (slew rate) errors of the digitized inductor current DIL in a switch-mode power converter by aligning the digitized inductor current DIL with two or more measurement points of the real inductor current (or a signal derived from the real inductor current) labeled "IL". Embodiments of the present disclosure use delay measurements (in the analog domain) and direct delay calculations (in the digital domain) in the calculation of offset and slope (slew rate) corrections.

[0202] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.< / il> < / dil>

Claims

1. A correction circuit for correcting one or more errors in a digitized current signal, the digitized current signal being a digital representation of an analog current signal of a current flowing through an energy storage element, wherein: The correction circuit is configured to correct the one or more errors in the digitized current signal by: comparing the digitized current signal to the analog current signal; and Based on a result of the comparison, the digitized current signal is corrected.

2. The correction circuit according to claim 1, wherein: The digitized current signal is provided by a current synthesizer.

3. The correction circuit according to claim 2, wherein: The correction circuit is configured to: generating a correction signal dependent on a result of said comparing; and The correction signal is provided to the current synthesizer, the correction signal being adapted to correct the one or more errors in the digitized current signal when received by the current synthesizer, thereby correcting the digitized current signal based on a result of the comparison.

4. A correction circuit according to any preceding claim, configured to: Correcting an offset error between the digitized current signal and the analog current signal; and / or A relative slope error between the digitized current signal and the analog current signal is corrected.

5. The correction circuit according to claim 4, wherein the correction circuit is configured to: comparing the digitized current signal to the analog current signal to determine the offset error; and The digitized current signal is corrected using the determined offset error.

6. The correction circuit according to claim 5, wherein the correction circuit is configured to: The offset error is determined by: detecting a first time step when the digitized current signal crosses a first digital threshold; When the analog current signal crosses a first analog threshold, detecting a second time step; calculating a first duration between the first time step and the second time step; determining a first slope of at least one of the digitized current signal and the analog current signal; The first duration is multiplied by the first slope to determine the offset error.

7. The correction circuit according to claim 4, wherein the correction circuit is configured to: comparing the digitized current signal to the analog current signal to determine the relative slope error; and The digitized current signal is corrected using the determined relative slope error.

8. The correction circuit according to claim 7, wherein the correction circuit is configured to: The relative slope error is determined by the following method: detecting a first time step when the digitized current signal crosses a first digital threshold; When the analog current signal crosses a first analog threshold, detecting a second time step; detecting a third time step when the digitized current signal crosses a second digital threshold; When the analog current signal crosses a second analog threshold, detecting a fourth time step; calculating a first digital slope delay between the first time step and the third time step; calculating a first simulated slope delay between the second time step and the fourth time step; The first analog slope delay is divided by the first digital slope delay to calculate a first delay parameter, and then 1 is subtracted from the first delay parameter to determine the relative slope error. 9 . The correction circuit of claim 4 , the correction circuit being configured to correct the relative slope error before correcting the offset error.

10. The correction circuit according to claim 9, wherein the correction circuit is configured to: comparing the digitized current signal to the analog current signal to determine the relative slope error and the offset error; and The digitized current signal is corrected using the determined relative slope error and offset error.

11. The correction circuit according to claim 10, wherein the correction circuit is configured to: The relative slope error is determined by the following method: detecting a first time step when the digitized current signal crosses a first digital threshold; When the analog current signal crosses a first analog threshold, detecting a second time step; detecting a third time step when the digitized current signal crosses a second digital threshold; When the analog current signal crosses a second analog threshold, detecting a fourth time step; calculating a first digital slope delay between the first time step and the third time step; calculating a first simulated slope delay between the second time step and the fourth time step; The first analog slope delay is divided by the first digital slope delay to calculate a first delay parameter, and then 1 is subtracted from the first delay parameter to determine the relative slope error.

12. The correction circuit according to claim 11, wherein the correction circuit is configured to: The offset error is determined by: calculating a first duration between the first time step and the second time step; The first slope of the analog current signal is determined by: calculating an analog threshold difference by subtracting the second analog threshold from the first analog threshold; and dividing the analog threshold difference by the first analog slope delay; and The offset error is determined by multiplying the first slope of the analog current signal by the first duration.

13. A method of correcting one or more errors in a digitized current signal using a correction circuit, the digitized current signal being a digital representation of an analog current signal of current flowing through an energy storage element, the method comprising: comparing the digitized current signal with the analog current signal; and Based on a result of the comparison, the digitized current signal is corrected.

Images