System and method for analog-to-digital conversion using calibration

Abstract

The invention relates to a system and method for analog-to-digital conversion using calibration. An apparatus may include an analog-to-digital converter including a loop circuit and a comparator circuit. The apparatus may also include a first circuit configured to provide comparator offset calibration for the comparator circuit and a second circuit configured to provide loop calibration for the loop circuit.

Description

Technical Field

[0001] The present disclosure generally relates to systems and methods of compensation or calibration in analog-to-digital conversion operations or analog-to-digital converters (ADCs), including but not limited to ADCs used in transceivers. Background Art

[0002] Over the past few decades, the market for integrated circuit (IC) devices has grown by several orders of magnitude, driven by the need for portable devices and increased connectivity and data transfer between various devices. Analog / digital conversion operations are widely used in integrated circuit (IC) devices. ADCs are typically provided in communication circuits and other types of circuits that use both analog and digital signals. In some applications, radio frequency transmitters used in wireless base stations include ADCs. ADCs convert electrical analog signals into digital signals for wireless and wired communication or processing. For example, wireless communication systems may operate according to one or more standards including, but not limited to, IEEE 802.11, Bluetooth, LTE, 6G, and the like. The accuracy with which analog signals are converted into digital signals may affect the speed, accuracy, and robustness of communications. Summary of the invention

[0003] In one aspect, the present disclosure provides an apparatus comprising: an analog-to-digital converter comprising a loop circuit and a comparator circuit; a first circuit configured to provide comparator offset calibration of the comparator circuit; and a second circuit configured to provide loop calibration of the loop circuit.

[0004] In another aspect, the present disclosure provides an analog-to-digital converter, comprising: a loop circuit having a first stage and a second stage; and a first circuit configured to provide loop calibration of the first stage and loop calibration of the second stage.

[0005] On the other hand, the present disclosure provides a method, which includes: using an on-chip circuit system to provide a comparator offset calibration of a comparator circuit of an analog / digital converter; and using the on-chip circuit system to provide a loop calibration of a loop circuit of the analog / digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, wherein the same reference characters identify all corresponding elements. In the drawings, the same reference numerals generally indicate the same, functionally similar and / or structurally similar elements.

[0007] Figure 1 is a general schematic block diagram of an analog-to-digital conversion system according to some embodiments;

[0008] Figure 2is used for comparator offset calibration operation according to some embodiments Figure 1 A more detailed schematic block diagram of a portion of the analog / digital conversion system described in;

[0009] Figure 3 According to some embodiments Figure 1 A schematic block diagram of a frequency estimator of the analog / digital conversion system described in;

[0010] Figure 4 is configured for a first stage loop calibration operation according to some embodiments Figure 1 A more detailed schematic block diagram of a portion of the analog to digital conversion system described in; and

[0011] Figure 5 is configured for second stage loop calibration operation according to some embodiments Figure 1 A more detailed schematic block diagram of a portion of the analog-to-digital conversion system illustrated in FIG.

[0012] Figure 6 is to show that according to some embodiments Figure 1 Flowchart of the comparator offset calibration operation of the analog-to-digital conversion system described in . DETAILED DESCRIPTION

[0013] Analog-to-digital converters (ADCs) are used in a variety of wireless and wired communication devices and other mixed-signal systems. ADCs are also used in processors, microcontrollers, sensors, and other circuits that receive or process analog signals and transmit or process digital signals. In some embodiments, integrated circuits (ICs) for WiFi and Bluetooth wireless devices (including but not limited to cellular phones, tablets, watches, headphones, computers, sensors, etc.) use one or more ADCs. The ICs may include ICs used in combined 7nm WiFi and Bluetooth applications.

[0014] Calibration hardware and associated algorithms for wideband Σ-Δ ADCs can ensure accuracy of robust analog-to-digital conversion. In some embodiments, the ADC can be used in a high-performance WiFi and Bluetooth combination device. In some embodiments, the ADC is a flash Σ-Δ ADC, which in some embodiments is robust against process-voltage-temperature (PVT) variations. In some embodiments, a precise on-chip calibration scheme can be used to fine-tune all or most of the major components in a complex wideband ADC design.

[0015] In some embodiments, systems and methods for ADC calibration provide reliable calibration while keeping chip area consumption small. In some embodiments, systems and methods perform on-chip robust calibration algorithms that balance calibration time, chip performance, and yield. In some embodiments, calibration operations do not require external devices such as signal generators or stable signal inputs and spectrum analyzers. In some embodiments, the calibration engine and any related software are fully embedded on the chip or within the package of the ADC (e.g., within a system-on-chip (SoC) solution) and provide fast and robust calibration operations. In some embodiments, a fully on-chip calibration engine uses a small chip area and optimizes calibration time and yield. In some embodiments, on-chip may refer to operations or circuits included within an integrated circuit package (e.g., a single package or a multi-chip module).

[0016] In some embodiments, the systems and methods employ a two-step calibration scheme. In some embodiments, the calibration scheme includes a comparator offset calibration and a loop calibration (e.g., filter resistor capacitor (RC) calibration). In some embodiments, the comparator offset calibration uses an on-chip digital / analog converter (DAC), whose test can extend the DC signal to complete the comparator offset calibration. In some embodiments, the loop calibration configures the on-chip operational amplifier and loop filter for resonance or oscillation. In some embodiments, a digital module is used to calculate the oscillation period.

[0017] In some embodiments, the operation flow of the ADC automatically performs comparator offset calibration and loop calibration. In some embodiments, the system and method sweep the ADC to find the best offset value in the comparator offset calibration. In some embodiments, the loop calibration obtains the best capacitor value for tuning the oscillation signal to the pole frequency. In some embodiments, a full on-chip calibration engine for a wideband ADC is provided, which includes a stable and scalable input source and a high-resolution amplitude and frequency analyzer. In some embodiments, the system and method reuse key analog components in the calibration mode using a reconfigurable architecture. The switch between the calibration mode and the operating mode is controlled by software settings.

[0018] Some embodiments relate to an apparatus. The apparatus includes an analog-to-digital converter including a loop circuit and a comparator circuit. The apparatus also includes a first circuit configured to provide comparator offset calibration of the comparator circuit and a second circuit configured to provide loop calibration of the loop circuit.

[0019] In some embodiments, the second circuit includes a frequency estimator and an analyzer. The analyzer receives a frequency measurement for the loop circuit from the frequency estimator and adjusts a resistance or capacitance in the loop circuit. In some embodiments, the apparatus is part of a transceiver provided in a single IC package. In some embodiments, the analyzer receives a first frequency measurement for a first stage of the loop circuit from the frequency estimator, adjusts a resistance or capacitance of the first stage, receives a second frequency measurement for a second stage of the loop circuit from the frequency estimator, and adjusts a resistance or capacitance of the second stage in the loop circuit. In some embodiments, the second circuit adjusts a capacitance of the loop circuit or a stage of the loop circuit.

[0020] In some embodiments, the first circuit is configured to detect a switching of a comparator output. In some embodiments, the comparator circuit comprises 7 1-bit comparators.

[0021] Some embodiments relate to an analog-to-digital converter. The analog-to-digital converter includes a loop circuit and a first circuit. The loop circuit has a first stage and a second stage. The first circuit is configured to provide loop calibration of the first stage and loop calibration of the second stage.

[0022] In some embodiments, the first circuit includes a frequency estimator and an analyzer. The analyzer receives a first frequency measurement from the frequency estimator for the first stage and adjusts a resistance or capacitance in the first stage. In some embodiments, the analyzer receives a second frequency measurement from the frequency estimator for the second stage and adjusts a resistance or capacitance in the second stage.

[0023] In some embodiments, the analog-to-digital converter further comprises an IC package containing the first circuit and the loop circuit. In some embodiments, the analog-to-digital converter further comprises a comparator circuit coupled to the second stage. In some embodiments, the analog-to-digital converter further comprises a second circuit configured to provide a comparator offset calibration of the comparator circuit.

[0024] In some embodiments, the second circuit is configured to detect switching of a comparator output. In some embodiments, the first circuit adjusts a capacitance of the first stage.

[0025] Some embodiments are directed to a method. The method includes providing comparator offset calibration of a comparator circuit of an analog-to-digital converter using on-chip circuitry. The method also includes providing loop calibration of a loop circuit of the analog-to-digital converter using the on-chip circuitry.

[0026] In some embodiments, the loop calibration of the loop circuit uses a frequency estimator and an analyzer.The analyzer receives a first frequency measurement from the frequency estimator for a first stage of the loop circuit and adjusts a resistance or capacitance in the first stage.

[0027] In some embodiments, the comparator circuit and the loop circuit are in an in-phase path. In some embodiments, the comparator circuit and the loop circuit are in a quadrature path. In some embodiments, the comparator offset calibration includes detecting a switching of a comparator output.

[0028] refer to Figure 1 , ADC system 100 is provided on a physical (PHY) chip or integrated circuit (IC) in package 110. Package 110 may be part of a communication system or device, a computing device, a sensing device, etc. In some embodiments, ADC system 100 is a single chip design and may be used in transceivers for cellular, WiFi, and Bluetooth applications. ADC system 100 may be a radio frequency ADC device. The systems and methods described herein with respect to ADC system 100 may be used for a variety of different ADC architectures in a variety of devices, including, but not limited to, devices used in high speed and high resolution applications.

[0029] ADC system 100 includes calibration circuit 104, calibration circuit 106, and ADC 108. ADC system 100 receives an analog signal at input 102 and provides a digital signal at output 112. The analog input signal may be an in-phase or quadrature phase signal of an RF modulated signal. The digital signal may be a 3-bit signal. In some embodiments, ADC system 100 may be part of a larger device and no external hardware is required. In some embodiments, device and package 110 may include more than one ADC system 100 (e.g., one per channel).

[0030] In some embodiments, ADC 108 is a flash ADC. ADC 108 may be a current mode or voltage mode conversion circuit. In some embodiments, ADC 108 is a Σ-Δ ADC (e.g., a flash Σ-Δ ADC). In some embodiments, ADC 108 may be a first order, second order, or other order ADC. ADC 108 may also include decimators, filters, switches, oscillators, and other circuit components. In some embodiments, ADC 108 is a voltage mode ADC and includes loop circuit 122 and comparator circuit 124. Loop circuit 122 is configured to perform Δ-Σ processing on the analog signal at input 102, and comparator circuit 124 is configured to compare the output of loop circuit 122 with a threshold value to provide a digital bit as an output signal at digital output 108.

[0031] In some embodiments, loop circuit 122 is an operational amplifier circuit with a feedback loop. In some embodiments, loop circuit 122 may include a digital / analog converter, a differentiator, a filter, a summer, an integrator, resistive and / or capacitive components, switches, and other components. Loop circuit 122 may be in various configurations, including one or more feedback networks having passive and active components coupled to an operational amplifier.

[0032] In some embodiments, the comparator circuit 124 is an operational amplifier based comparator circuit. In some embodiments, the comparator circuit 124 includes a set of comparators, each of which is configured to compare an input signal with a corresponding threshold value. In some embodiments, the comparator circuit 124 may include a filter (e.g., digital), a threshold circuit, a resistor and / or capacitor component, a switch, and other components. The comparator circuit 124 may include a logic circuit for converting the output of the comparator into a digital word. The comparator circuit 124 may be in various configurations, including one or more comparators coupled to receive a corresponding threshold voltage associated with an analog / digital conversion operation.

[0033] The calibration circuit 104 is configured to calibrate the comparator circuit 124. In some embodiments, the calibration circuit 104 is configured to compensate for a comparator offset associated with the comparator circuit 124. In some embodiments, the comparator offset may refer to an error associated with a mismatch between a threshold voltage and a voltage that causes the comparator to change its output. The comparator offset may be caused by comparator design, temperature changes, process variations, power supply variations, and the like. The calibration circuit 104 is configured to provide adjustments to accommodate the comparator offset (e.g., to reduce mismatch errors). In some embodiments, the calibration circuit 104 is a digital engine that calculates the average of the ADC output over a configurable time interval and searches for an optimal offset value that centers the ADC output within a desired range.

[0034] In some embodiments, the calibration circuit 104 is configured for use with high speed comparators that have large direct current (DC) offsets that can degrade quantizer linearity and cause non-monotonicity. In some embodiments, the calibration circuit 104 can accommodate approximately 25mV / Σ comparator offsets. In some embodiments, the calibration circuit 104 uses a feedback DAC to sweep the flash quantizer input voltage at threshold levels and adjust individual comparator offsets to cause the flash comparators to switch at these threshold levels. In some embodiments, the first stage of the loop circuit 122 is powered off and the second stage of the loop circuit 122 is set to bypass mode to set the predefined DC gain of the feedback DAC. In some embodiments, the digital input of the feedback DAC is varied (Din changes) to change the input of the quantizer. In some embodiments, the additional loop delay (ELD) is also varied to match the data input changes (e.g., in an override mode).

[0035] The calibration circuit 106 is configured to calibrate the loop circuit 122. In some embodiments, the calibration circuit 106 is configured to adjust the resonant condition of the loop circuit 122. For example, using an ideal operational amplifier, the resonant condition is defined by C1 / C2=(R1-R2) / R1 and the resonant frequency w=1 / SQR(C1C2R1R2). C1 and C2 represent the capacitance values ​​in the loop and may reflect the series or parallel capacitors and the inherent capacitance in the loop. R1 and R2 represent the resistance values ​​in the loop and may reflect the series or parallel resistors and the inherent resistance in the loop.

[0036] Due to the limited gain bandwidth (LGBW) and direct current (DC) gain of the operational amplifier, the above equations may deviate from the ideal calculation. Applying off-chip RC calibration can be used to achieve the correct resonant frequency w. Matching can be relied upon to ensure or obtain improved resonant conditions. However, due to the high-speed nature of wideband ADCs, parasitic effects can become significant and process-dependent, degrading the improved resonant conditions.

[0037] In some embodiments, calibration circuit 106 is configured to perform in-circuit or on-chip calibration to reduce degradation. In some embodiments, calibration circuit 106 is configured to program the values ​​of C1 and C2, R1 and R2, or both to detect oscillation and measure the oscillation frequency. In some embodiments, when a 3-bit quantizer is used, both oscillation detection and frequency measurement are performed in the digital domain, thereby reducing the analog complexity (and thus reducing parasitic effects) of improving high-speed, lower resolution ADCs.

[0038] refer to Figure 2 , the comparator offset calibration operation is explained below with reference to the circuit 300 including a portion of the ADC 108. The comparator offset calibration operation may be performed by the calibration circuit 104. In some embodiments, the comparator offset calibration may refer to any adjustment of the comparator circuit that is desired to reduce an error. The error may be an offset error or a mismatch error associated with the comparator circuit 124. In some embodiments, the calibration may set the comparator offset control signal to reduce the mismatch error.

[0039] In some embodiments, circuit 300 includes a set of comparators 402a to 402g (eg, 1-bit comparators), level shift circuit 404, switch 410, switch 412, comparator reference circuit 418, analyzer 442, and amplifier 414. Amplifier 414 is Figure 1 In some embodiments, comparator group 402a to 402g is used for the in-phase (I) path or the quadrature (Q) path. In some embodiments, comparators 402a to 402g, level shift circuit 404, and comparator reference circuit 418 are Figure 1402a-402g are part of the comparator circuit 124 in FIG. In some embodiments, comparators 402a-402g are operational amplifiers without a feedback loop, having a non-inverting input coupled to receive a signal from amplifier 414 and an inverting input coupled to receive a specific threshold voltage. Logic is used to convert the output signal at outputs 408a-408g of comparators 402a-402g into a 3-bit signal (representing 8 levels).

[0040] The level shift circuit 404 provides the corresponding level of each comparator 402a to 402g to the non-inverting input in the calibration mode. The level shift circuit 404 is configured to provide a corresponding voltage level to match the threshold voltage of each of the comparators 402a to 402g during calibration. The level shift circuit 404 is used to provide a signal of a specific voltage level from the comparator reference circuit 418 in response to a control signal at the input 422. In some embodiments, the level shift circuit 404 can be a multiplexer or switch matrix that selects a specific threshold voltage from the amplifier 414 and the comparator reference circuit 418.

[0041] The comparator reference circuit 418 provides accurate voltage levels. The comparator reference circuit 418 can provide a reference voltage using any of several technologies. In some embodiments, the comparator reference circuit 418 includes a DAC and provides an analog voltage level in response to a bit value. For example, a 4-bit DAC can provide voltage levels corresponding to the values ​​(e.g., 10, 8, 6, 4, 7, 9, and 11) of the comparators 402g to 402a, respectively. In some embodiments, a resistor ladder, a regulator, and other devices can be used to provide signals at various voltage levels. In some embodiments, the signal from the amplifier 414 is passed to the non-inverting input of the comparators 402a to 402g through the level shift circuit 404. In some embodiments, the level shift circuit 404 uses switches 432 and 434 to provide the differential signal from the amplifier 414 as a single-ended signal to the comparators 402a to 402g. In some embodiments, the corresponding same signal is provided to the non-inverting input and non-inverting output of each comparator 402a to 402g in the calibration mode.

[0042] Level shift circuit 404 includes switches 432 and 434. Switches 432 and 434 may each be a transistor or a network of transistors. In some embodiments, ADC 108 is a current mode ADC and the threshold voltage is a threshold current and the level provided by level shift circuit 404 is a current level.

[0043] Switches 410 and 412 are configured to place amplifier 414 in a calibration mode. In some embodiments, switches 410 and 412 place the differential output of amplifier 414 at ground during a calibration operation in response to a calibration control signal at input 436. Switches 410 and 412 may each be a transistor or a transistor network.

[0044] Analyzer 442 is an on-chip circuit in calibration circuit 104 that is configured to receive outputs from comparators 402a to 402g and provide adjustments to the comparators to reduce mismatch errors. Analyzer 442 is configured to detect when the signal at outputs 408a to 408g switches or oscillates between a logic high and a logic low. In some embodiments, analyzer 442 may utilize a state circuit to detect whether the output state is changing in rapid succession to detect switching (e.g., continuously comparing a previous value with a current value to determine switching). In some embodiments, analyzer 442 includes an averaging circuit that averages each corresponding signal at a corresponding output over time to determine switching. A value of 0.5 over time indicates switching. When the corresponding output 408a to 408g switches, the threshold voltage is equal to the voltage level provided by level shift circuit 404. In calibration mode, level shift circuit 404 provides a signal at the signal input that is equal to the threshold voltage. In some embodiments, the signal input may be provided by a DAC (e.g., on-chip DAC 624). Analyzer 442 adjusts the offset control signal of each comparator 402a to 402g across a range until the corresponding output 408a to 408g switches. The offset control signal is set to the level, thereby tuning the comparator to the appropriate threshold voltage. In some embodiments, the offset control signal is received by an offset adjustment circuit internal to ADC 108.

[0045] In some embodiments, analyzer 442 increases the offset control signal until the corresponding output signal changes from a logic low to a logic high. Analyzer 442 then decreases the offset control signal until the output signal changes from a logic level low. Analyzer 442 repeats these operations until the output signal switches and then sets the offset control signal to the current level. In some embodiments, each of comparators 402a-402g for each I and Q path (e.g., 14 total) determines a corresponding offset control signal.

[0046] refer to Figure 3 In some embodiments, the ADC system 108 ( Figure 1) includes a frequency detector or estimator 500 (e.g., as part of calibration circuit 106). In some embodiments, frequency estimator 500 is an off-chip or on-chip circuit. Frequency detector or estimator 500 includes a low-pass filter 502, a zero crossing detector 504, a period estimator 506, a free-running counter 508, and a moving average circuit 512. Low-pass filter 502 allows an operational amplifier (e.g., amplifier 414 ( Figure 2 )). The filtered signal is provided to a zero crossing detector 504. The zero crossing detector 504 is configured to provide a signal when the filtered signal crosses a threshold value (e.g., zero volts). The zero crossing detector 504 may be an operational amplifier based circuit. The signal from the zero crossing detector 504 is provided to a period estimator 506, which estimates the period between the signals from the zero crossing detector 504 using the value from the free running counter 508. The period estimator 506 may be configured to sample the value in the free running counter 508 based on each pulse from the zero crossing detector 504 and subtract subsequent values ​​to estimate the period of the signal. The free running counter 508 counts the number of clock pulses received at its clock input. The moving average circuit 512 receives a difference value from the period estimator 506 to determine the average frequency of the signal received by the filter 502. In some embodiments, the calibration circuit 106 uses this average period or frequency value to adjust the loop circuit 122. The loop circuit 122 may be adjusted to provide an appropriate resonant frequency.

[0047] refer to Figure 4 , the first stage of circuit 600 is in calibration mode. The loop calibration operations of the first stage and the second stage may be performed by calibration circuit 106. Circuit 600 may be loop circuit 122 ( Figure 1 ) portion. In some embodiments, loop calibration may refer to any adjustment of a loop circuit or its stage that is desired to adjust the resonant frequency of the loop circuit or its stage. In some embodiments, the adjustment may be performed by increasing or decreasing the resistance and / or capacitance in the loop circuit or its stage. The first stage of circuit 600 includes DAC 604, summer 602, DC feedback circuit 608, and resonator 606. The second stage of circuit 600 includes DAC 624, summer 622, and resonator 626. The loop calibration operations of the first and second stages may be performed by calibration circuit 106. In some embodiments, each stage has a pole frequency for resonance. In some embodiments, a stage may refer to a portion of a circuit. The first stage may have components and connections similar to the second stage, and in some embodiments, the first and second stages may be directionally coupled in series, cascade, or parallel.

[0048] When in the calibration mode of the first stage, switch 628 is configured to disconnect resonator 626. In the calibration mode, a DAC override is performed so that the signal from ADC feedback circuit 640 is not provided to DAC 604 and DAC 624. DC feedback circuit 608 provides DC feedback to summer 602, which is provided to resonator 606. Because global feedback is not available in the calibration mode, DC feedback is provided. Switch 628 bypasses resonator 626.

[0049] Circuit 640 may be a comparator circuit 124 ( Figure 1 ) or a portion thereof and in normal operation provides a digital feedback signal to DACs 604 and 624 for application to summers 602 and 622. In some embodiments, a DAC override may be performed by setting the DAC input value to a particular value (e.g., 000, 1111). In some embodiments, in a calibration mode of the first stage, the analyzer 516 of the frequency estimator 500 determines the frequency of the signal provided by the resonator 606 and adjusts the capacitance (e.g., capacitances C1 and C2 in the resonator 606) until the appropriate resonant frequency is reached. In some embodiments, a trial and error method may be used by adjusting the values ​​of capacitances C1 and C2. In some embodiments, capacitances C1 and C2 are adjusted by adjusting a variable capacitor or selecting a capacitance path in the resonator 606. In some embodiments, a combination of values ​​of C1 and C2 is selected based on trial and error. In some embodiments, the desired resonant frequency of the first stage is 35 MHz. In some embodiments, calibration may be performed on the I and Q paths.

[0050] refer to Figure 5 , when in the calibration mode of the second stage, the switch 648 is configured to disconnect the resonator 606. In the calibration mode of the second stage, the DAC override is performed as described above. The DC feedback circuit 608 provides DC feedback to the summer 602, which is provided to the resonator 626. In some embodiments, in the calibration mode of the second stage, the analyzer 516 of the frequency estimator 500 determines the frequency of the signal provided by the resonator 626 and adjusts the capacitance (e.g., the capacitance C1 and C2 in the resonator 626) until the appropriate resonant frequency is reached. In some embodiments, the analyzer 516 of the frequency estimator 500 determines the frequency of the signal provided by the resonator 626 and adjusts the capacitance (e.g., the capacitance C1 and C2 in the resonator 626) until the appropriate resonant frequency of the second stage is reached. In some embodiments, the desired resonant frequency of the first stage is 13.8 MHz. In some embodiments, a trial and error method can be used by adjusting the values ​​of the capacitances C1 and C2 using techniques similar to those described above with respect to the resonator 606.

[0051] In some embodiments, a loop circuit may refer to a feedback circuit that includes a resistor and / or a capacitor and has a characteristic resonant frequency related to the value of the resistor and / or the capacitor. A comparator circuit may refer to a circuit that receives a signal, compares the signal to another signal, and provides an output related to the comparison. A comparator circuit may include one or more operational amplifiers configured to compare an analog signal to a threshold voltage or current and provide a digital output. In some embodiments, a frequency estimator may refer to any circuit configured to provide a measurement or estimation of the frequency or period of a signal (e.g., a signal in a loop circuit). In some embodiments, an analyzer may refer to any circuit configured to receive a measurement signal and provide a control signal. In some embodiments, an analyzer may be a circuit that receives a frequency measurement and provides a calibration control signal to adjust the loop circuit or a level of the loop circuit. In some embodiments, an analyzer may be a circuit that receives an output signal and adjusts an offset control signal to adjust the comparator circuit.

[0052] In some embodiments, calibration may be performed on the I and Q paths. In some embodiments, the second stage is calibrated before the first stage. In some embodiments, the I and Q paths of the second stage are calibrated before the first stage, followed by the I and Q paths of the first stage. In some embodiments, both comparator offset and loop calibration calibrate the I and Q paths in parallel. In some embodiments, the in-phase path may refer to circuitry for receiving and / or processing in-phase signals. In some embodiments, the quadrature path may refer to circuitry for receiving and / or processing quadrature signals.

[0053] In some embodiments, the digital components of the ADC system 100 may be implemented using dedicated or non-dedicated circuits or processor-based circuits including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complementary metal oxide semiconductor (CMOS), or the like. In some examples, memory for storing data and computer instructions, such as random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, or the like, is included. For example, all or part of an implementation may be: a circuit system including a central processing unit (CPU), a microcontroller, or a microprocessor; an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a field-programmable gate array (FPGA); or a circuit system including discrete logic or other circuit components (including analog circuit components, digital circuit components, or both); or any combination thereof.

[0054] The circuit system may include discrete interconnected hardware components and / or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a multi-chip module (MCM) of multiple integrated circuit dies in a common package, for example. In some embodiments, the integrated circuit package may be a combination of two or more packages.

[0055] In some embodiments, an operational amplifier may refer to an amplifier having a gain and an input impedance. In some embodiments, the gain and input impedance may be relatively high. In some embodiments, an operational amplifier may have an inverting and non-inverting input and output for performing operations on an input voltage. In some embodiments, an operational amplifier generally operates according to a current rule in which no current flows into the inverting and non-inverting inputs and a voltage rule in which the output of the operational amplifier attempts to ensure that the voltage difference between the inverting and non-inverting inputs is zero. In some embodiments, an inverting input may refer to a circuit input in which the signal change at the non-inverting output is 180° out of phase with the change at the inverting input. In some embodiments, a non-inverting input may refer to a circuit input in which the signal change at the non-inverting input is 180° out of phase with the change at the inverting output. In some embodiments, a non-inverting output may refer to a circuit output in which the signal change at the inverting input is 180° out of phase with the change at the non-inverting output. In some embodiments, an inverting output may refer to a circuit output in which the signal change at the non-inverting input is 180° out of phase with the change at the inverting output. In some embodiments, non-inverting inputs and outputs are labeled by positive signs and inverting inputs and outputs are labeled by negative signs.

[0056] In some embodiments, a switch may refer to any type of switching device, including, but not limited to, a transistor. A transistor may refer to any type of transistor, including a field effect transistor FET, an insulated gate FET, a bipolar junction transistor, and the like. In some embodiments, the transistor is a P-channel or N-channel metal oxide semiconductor field effect transistor (MOSFET). A P-channel transistor includes a P-channel, which is a channel consisting of a majority of hole carriers between the source and drain of the transistor. An N-channel transistor includes an N-channel, which is a channel consisting of a majority of electron carriers between the source and drain of the transistor. In some embodiments, the terms "drain" and "source" may be used interchangeably and may refer to a region of a transistor. In some embodiments, a gate may refer to a transistor structure used to control the opening (e.g., toward a non-conductive state) and closing (e.g., toward a conductive state) of a transistor.

[0057] The ADC system 100 can be used in various operating environments together with system components (e.g., hardware elements) of other devices. The ADC system 100 can be used in a network environment including a wired or wireless communication system, which includes one or more access points, one or more wireless communication devices that may include a transceiver, and network hardware components. The network environment may include a (DOCSIS) modem that enables high-bandwidth data transmission via an existing coaxial cable system associated with the transmission of a cable television program signal (CATVS). For example, the wireless communication device may include an access point, a cellular node, a television, a laptop, a tablet computer, a personal computer, and / or a cellular telephone device. In some embodiments, the network environment may be an Ethernet, an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, a satellite network, a cellular network, a WiFi network, and the like.

[0058] An access point (AP) may be operably coupled to network hardware via a local area network connection. Network hardware (which may include routers, gateways, switches, bridges, modems, system controllers, devices, etc.) may provide a local area network connection for a communication system. Each of the access points may have an associated antenna or antenna array for communicating with wireless communication devices in its area. Wireless communication devices may register with a specific access point to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configurations). For direct connections (e.g., point-to-point communications), some wireless communication devices may communicate directly via an assigned channel and a communication protocol. Some wireless communication devices may be mobile or relatively stationary relative to an access point.

[0059] In some embodiments, the ADC system 100 may include a central processing unit and a digital signal processor, which may be any logic circuit system that responds to and processes instructions fetched from a memory. The memory may be any type or variation of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash, NOR flash, and solid state drive (SSD).

[0060] refer to Figure 6 , the exemplary comparator offset calibration process 700 may be performed by the calibration circuit 104 ( Figure 1 ) is performed. In some embodiments, in operation 702, the calibration circuit 104 uses the comparators 402a to 402g ( Figure 2 ) provides an input signal at a threshold voltage level of one of the comparators 402a to 402g. In some embodiments, in operation 708, the calibration circuit 104 provides the threshold voltage to the comparators 402a to 402g ( Figure 2) In some embodiments, the threshold voltage and level of the input signal are equal. In some embodiments, the signals for operations 708 and 714 may be provided by DACs (DACs 604 and 624) and switches 432 and 434 ( Figure 2 ) may provide a connection for providing an appropriate signal. In operation 714, when the switching of the output of the comparator is monitored, the offset control signal is adjusted. In some embodiments, when the switching is detected in operation 718 (e.g., using an averaging circuit indicating a value of 0.5 over a period of time), the offset control signal is set at that level in operation 722. In some embodiments, comparators 402a to 402g ( Figure 2 ) and repeat process 700 for each of the above.

[0061] Any embodiment disclosed herein may be combined with any other embodiment, and reference to "embodiment", "some embodiments", "alternative embodiments", "various embodiments", "one embodiment" or the like is not necessarily mutually exclusive and is intended to indicate that a particular feature, structure or characteristic described in conjunction with an embodiment may be included in at least one embodiment. Such terms used herein do not necessarily all refer to the same embodiment. Any embodiment may be combined with any other embodiment inclusively or exclusively in any manner consistent with the aspects and embodiments disclosed herein. In the above description, for the sake of explanation, many details are set forth to provide a thorough understanding of the described embodiments. However, it should be understood by those skilled in the art that other embodiments may be practiced without some of these details. In other examples, structures and devices are shown in block diagram form. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that the features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, a single feature or some features of any described embodiment should not be considered necessary for each embodiment of the present invention, because other embodiments of the present invention may omit such features. Similarly, when an element is referred to as "connected" or "coupled" to another element in this article, it should be understood that the element may be directly connected to another element or have an intermediate element present between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements. A circuit or circuit system may refer to any active or passive components and connections thereof, and combinations thereof. A circuit system may further include or access instructions (e.g., software or firmware instructions) for execution by the circuit system. A circuit system may include discrete interconnected hardware components and / or may be combined, for example, on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a multi-chip module (MCM) of multiple integrated circuit dies in a common package. In some embodiments, an integrated circuit package may be a combination of two or more packages.

[0062] Although the examples of the above-described communication systems may include devices and APs operating according to the 802.11 standard, it should be understood that embodiments of the described systems and methods may operate according to other standards and use wireless communication devices other than devices configured as devices and APs. For example, multi-unit communication interfaces associated with cellular networks, satellite communications, vehicle communication networks, and other non-802.11 wireless networks may utilize the systems and methods described herein to achieve improved overall capacity and / or link quality without departing from the scope of the systems and methods described herein.

[0063] It should be noted that certain paragraphs of the present disclosure may refer to terms such as "first" and "second" in conjunction with devices, operating modes, transmission chains, loops, etc. to identify or distinguish them from each other. These terms are not intended to relate entities (such as first devices and second devices) only in time or according to a sequence, but in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities (such as devices) that can operate in a system or environment.

[0064] It should be understood that the above-described systems may provide multiples of any or each of those components and that these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the above-described systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture. The article of manufacture may be a floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or tape. In general, the computer-readable program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#, PROLOG) or any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0065] Although the above written description of the methods and systems enables one of ordinary skill in the art to make and use what is currently believed to be the best mode thereof, one of ordinary skill in the art should understand and appreciate the variations, combinations, and equivalents of the specific embodiments, methods, and examples present herein. Therefore, the methods and systems of the present invention should not be limited by the above-described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the present disclosure.

[0066] The transmitter and analog / digital conversion system have been described above with the aid of functional building blocks that illustrate the performance of specific important functions. The boundaries of these functional building blocks have been arbitrarily defined for ease of description. Functions and structures can be integrated together across such boundaries. Alternative boundaries can be defined as long as specific important functions are properly performed. Similarly, flow chart blocks have also been arbitrarily defined herein to illustrate specific important functionality. Within the scope of use, process boundaries and sequences can be defined in other ways and still perform specific important functionality. Therefore, such alternative definitions of both functional building blocks and flow chart blocks and sequences are within the scope and spirit of the present invention. It should also be recognized by a person of ordinary skill in the art that functional building blocks and other description blocks, modules and components herein can be implemented as described or by discrete components, application specific integrated circuits, processors executing appropriate software, and the like, or any combination thereof.

Claims

1. A device comprising: an analog / digital converter, comprising a loop circuit and a comparator circuit; a first circuit configured to provide comparator offset calibration of the comparator circuit; and A second circuit is configured to provide loop calibration of the loop circuit.

2. The apparatus of claim 1, wherein the second circuit comprises a frequency estimator and an analyzer, wherein the analyzer receives a frequency measurement from the frequency estimator for the loop circuit and adjusts a resistance or a capacitance in the loop circuit.

3. The device of claim 1, wherein the device is part of a transceiver provided in a single IC package.

4. The apparatus of claim 2, wherein the analyzer is configured to receive a first frequency measurement from the frequency estimator for a first stage of the loop circuit, adjust a resistance or capacitance of the first stage, receive a second frequency measurement from the frequency estimator for a second stage of the loop circuit, and adjust resistance or capacitance in the second stage and the loop circuit.

5. The apparatus of claim 1, wherein the first circuit is configured to detect switching of a comparator output.

6. The apparatus of claim 1, wherein the comparator circuit comprises seven 1-bit comparators.

7. The apparatus of claim 1, wherein the second circuit adjusts a capacitance of the loop circuit or a stage of the loop circuit.

8. An analog / digital converter, comprising: A loop circuit having a first stage and a second stage; A first circuit is configured to provide loop calibration of the first stage and loop calibration of the second stage.

9. The analog-to-digital converter of claim 8, wherein the first circuit comprises a frequency estimator and an analyzer, wherein the analyzer receives a first frequency measurement for the first stage from the frequency estimator and adjusts a resistance or a capacitance in the first stage.

10. The analog-to-digital converter of claim 9, wherein the analyzer receives a second frequency measurement from the frequency estimator for the second stage and adjusts a resistance or a capacitance in the second stage.

11. The analog-to-digital converter of claim 8, further comprising an integrated circuit (IC) package containing the first circuit and the loop circuit.

12. The analog-to-digital converter of claim 8, further comprising: A comparator circuit is coupled to the second stage.

13. The analog-to-digital converter of claim 12, further comprising: A second circuit is configured to provide comparator offset calibration for the comparator circuit.

14. The analog-to-digital converter of claim 13, wherein the second circuit is configured to detect switching of a comparator output.

15. The analog-to-digital converter of claim 8, wherein the first circuit adjusts a capacitance of the first stage.

16. A method comprising: providing comparator offset calibration of a comparator circuit of an analog-to-digital converter using on-chip circuitry; and Loop calibration of a loop circuit of the analog-to-digital converter is provided using the on-chip circuitry.

17. The method of claim 16, wherein the comparator circuit and the loop circuit are in a common phase path.

18. The method of claim 16, wherein the comparator circuit and the loop circuit are in quadrature paths.

19. The method of claim 16, wherein the loop calibration of the loop circuit uses a frequency estimator and an analyzer, wherein the analyzer receives a first frequency measurement from the frequency estimator for a first stage of the loop circuit and adjusts resistance or capacitance in the first stage.

20. The method of claim 16, wherein the comparator offset calibration comprises detecting switching of a comparator output.

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