A multi-step capacitance sensor readout circuit system and implementation method thereof

Abstract

The present invention discloses a multi-step capacitance sensor readout circuit and its implementation method, improves the incremental scaling capacitance sensor readout circuit; designs an improved chopping sampling method, does not introduce additional hardware overhead, makes full use of the working timing of the CDC, eliminates the sampling noise together with the offset and flicker noise of the first-stage integrator, and avoids the problems of increased power consumption and extended measurement time in common methods of multiple sampling average and sampling noise elimination technology. A self-biased floating inverting amplifier is prepared and used as the first-stage integrator, which improves the energy efficiency of the system and avoids the use of a common-mode feedback circuit. The present invention achieves high energy efficiency, high precision, and low latency, and can be widely used in the fields of robots, drones, etc.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to capacitance sensor circuit design technology, and specifically to a multi-step capacitance sensor readout circuit system and an implementation method thereof, and designs and implements a high-precision, high-energy-efficiency, and low-latency capacitance sensor readout circuit structure. Background Art

[0002] With the continuous evolution of capacitive sensor technology, the application scenarios of capacitive sensors have gradually expanded from traditional low-speed occasions (such as pressure and humidity measurement) to some real-time systems (such as robots and drones), which puts forward requirements for high resolution, high energy efficiency and low latency for the capacitive sensor readout circuit. The existing successive approximation capacitance-to-digital converter (SARCDC) has high energy efficiency, but its accuracy is low due to the thermal noise of the comparator; the ΔΣ capacitance-to-digital converter (ΔΣ CDC) improves the system accuracy through noise shaping and oversampling, but it usually requires a high-energy integrator. As a new circuit structure, the zoom capacitance-to-digital converter (Zoom CDC) can take into account both energy efficiency and accuracy, which has attracted widespread attention.

[0003] Zoom CDC is a multi-step capacitance sensor readout circuit that combines the advantages of SAR CDC and ΔΣ CDC. First, SAR CDC is used for coarse quantization to expand the dynamic range of CDC. After the coarse quantization is completed, the reference level of fine quantization is adjusted according to the quantization result, and ΔΣ CDC is used for fine quantization to improve the system accuracy. Since the input signal of the ΔΣ CDC integrator is a relatively small residual signal after coarse quantization, the power consumption of the integrator can be reduced and its linearity can be improved. The main limiting factors of Zoom CDC accuracy are sampling noise and the difficulty in eliminating the noise of the first-stage integrator. In the application context of real-time systems, the measurement time of Zoom CDC is short, the oversampling rate is small, and the sampling noise cannot be well attenuated due to the small number of averaging times. Traditional sampling noise elimination technology requires the introduction of additional amplifiers, which brings additional time and power consumption. For the first-stage integrator, the existing Zoom CDC adopts a closed-loop structure or an open-loop static structure, which has poor energy efficiency.

[0004] Therefore, the capacitance-to-digital converter (CDC) designed by the prior art is difficult to be applied to the requirements of real-time systems such as robots and drones for high-efficiency and high-precision CDC. Summary of the invention

[0005] In view of the problem that sampling noise and first-stage integrator noise in the above-mentioned prior art are difficult to reduce, the present invention provides a multi-step capacitance sensor readout circuit system and an implementation method thereof, which can be used to design and implement a multi-step capacitance sensor readout circuit system with high energy efficiency, high precision and low measurement time, which can be adapted to real-time application scenarios such as robots and drones.

[0006] The multi-step capacitance sensor readout circuit system proposed in the present invention is a new type of incremental scaling capacitance digital converter, which adopts a sampling noise elimination technology based on chopping, does not introduce additional hardware overhead, and adopts a self-biased floating inverting amplifier as the first-stage integrator. The self-biased floating inverting amplifier is a dynamic open-loop integrator, which improves the energy efficiency of the multi-step capacitance sensor readout circuit system. Through the above technology, the present invention can adapt to real-time application scenarios such as robots and drones.

[0007] The present invention defines the following terms and their corresponding English names:

[0008] Reference level: V REFP

[0009] Ground level: V REFN

[0010] Common mode level (the common mode level of the reference level and the ground level): V CM

[0011] The technical solution of the present invention is as follows:

[0012] A method for implementing a multi-step capacitance sensor readout circuit system is disclosed. A multi-step capacitance sensor readout circuit, namely an incremental scaling capacitance sensor readout circuit, is designed. No additional amplifier is introduced. The sampling noise is eliminated by using a chopping timing sequence. A dynamic open-loop integrator is used as the first-stage integrator to improve the system energy efficiency. The implementation method includes the following steps:

[0013] 1) Prepare a self-biased floating inverting amplifier and split the power supply capacitor into two parts to facilitate the adjustment of its specific parameters. The output node of the self-biased floating inverting amplifier adopts the improved chopping technology suitable for open-loop integrator proposed by the present invention, and exchanges the top plate and the bottom plate of each load capacitor, thereby eliminating the change of the output common-mode voltage of the self-biased floating inverting amplifier and maintaining the common-mode voltage stable.

[0014] 2) Prepare a multi-bit SAR CDC, including a sampling circuit, a coarse quantization digital-to-analog converter (DAC), a comparator, and a coarse quantization digital logic; the present invention designs a sampling noise elimination technology based on chopping, wherein the sampling circuit of the multi-bit SAR CDC adopts a sampling noise elimination technology based on chopping, that is, when sampling, the capacitor bottom plate is connected to the common mode level VCM After the sampling phase, the bottom plate is connected to the reference level V according to the chopping phase REFP or ground level V REFN .

[0015] 3) Prepare a multi-bit multi-stage ΔΣ CDC, which includes four parts: a fine quantization DAC, an integrator (including a first-stage integrator and multiple post-stage integrators), a quantizer, and a fine quantization digital logic. The first-stage integrator adopts the self-biased floating inverting amplifier proposed in the present invention.

[0016] The self-biased floating inverting amplifier includes five parts: power supply capacitor, load capacitor, input tube, common source and common gate tube, and "dummy" transistor (dummy tube). Among them, the input tube includes NMOS (N-channel Metal Oxide Semiconductor Field Effect Transistor, n-channel Metal Oxide Semiconductor Field Effect Transistor) transistor and PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor, p-channel Metal Oxide Semiconductor Field Effect Transistor), and the gates of the two transistors are connected together to form the gate of the input tube, which is connected to the sensing capacitor to be measured and the top plate of the DAC to achieve current reuse and improve the energy efficiency and noise efficiency of the self-biased floating inverting amplifier; the input tube uses a thick gate tube to reduce gate leakage. The source and drain of the "dummy" transistor are short-circuited and connected to the drain of the opposite input tube, and the gate of the "dummy" transistor is connected to the gate of the input tube; the gate length of the "dummy" transistor is the same as that of the input tube, and the gate width is half of the input tube, which eliminates the differential mode kickback noise and improves the accuracy of the multi-step capacitance sensor readout circuit system. The gate of the cascode is connected to the top or bottom plate of the supply capacitor.

[0017] When the self-biased floating inverting amplifier is working, the voltage difference between the top plate and the bottom plate of the power supply capacitor gradually decreases, the overdrive voltage of the common source and common gate tube gradually decreases, and the bias state transitions from the linear region to the saturation region. The self-biased floating inverting amplifier will gradually transition from a traditional floating inverting amplifier to a common source and common gate floating inverting amplifier, achieving a suitable integrator gain and a smaller leakage current. The power supply capacitor is split into two parts, large and small, and the parameters of the self-biased floating inverting amplifier are adjusted by controlling the disconnection time of the large power supply capacitor.

[0018] 4) Connect the top plates of the DAC of the multi-bit SAR CDC and the DAC of the multi-bit multi-order ΔΣ CDC together to form a larger DAC, that is, the multi-bit SAR CDC and the multi-bit multi-order ΔΣ CDC share a DAC component, and the shared DAC component is composed of two capacitor array top plates of different sizes connected together. The DAC in the multi-bit SAR CDC is a coarse quantization DAC, and the DAC of the multi-bit multi-order ΔΣ CDC is a fine quantization DAC.

[0019] The chopping-based sampling noise elimination technology is specifically:

[0020] During the sampling phase, connect the top and bottom plates of the DAC (the coarse quantization DAC and the fine quantization DAC) and the sensing capacitor to be measured to V CM In the conversion phase after the sampling phase, that is, the coarse quantization phase and the fine quantization phase, when the chopping phase is +1, the bottom plate of the sensing capacitor is connected to V REFP , the DAC bottom plate is connected to the corresponding digital code, and a residual voltage is generated on the top plate shared by the sensing capacitor and the DAC; when the chopping phase is -1, the bottom plate of the sensing capacitor is connected to V REFN , the DAC bottom plate is connected to the inverse of the corresponding digital code, and the top plate shared by the sensing capacitor and DAC generates a residual voltage with opposite polarity and sampling noise with the same polarity. The first-stage integrator (i.e., self-biased floating inverting amplifier) ​​of the fine-quantized multi-bit multi-order ΔΣ CDC performs a second chopping on the integrated residual signal, and finally eliminates the sampling noise after the digital code passes through the digital downsampling filter. In the fine quantization phase, the residual signal will be integrated and chopped for the second time. Since the integrator (i.e., the first-stage integrator) whose input is connected to the sensing capacitor and the DAC top plate used in the fine quantization phase is a dynamic open-loop integrator, the sampling noise will not be destroyed, so the sampling noise will be eliminated together with the offset and flicker noise of the first-stage integrator.

[0021] The improved chopping technique for a self-biased floating inverting amplifier is:

[0022] When the self-biased floating inverting amplifier is used as an open-loop integrator, small output common-mode voltage errors gradually accumulate, and the circuit will eventually fail to work properly. However, the output common-mode voltage change of the self-biased floating inverting amplifier is basically the same during each integration. The present invention utilizes the characteristic that the output common-mode voltage change of the self-biased floating inverting amplifier is almost the same during each integration. During the integration process, one plate of the load capacitor is connected to the output of the self-biased floating inverting amplifier, and the other plate is connected to V CM ,When the chopping phase changes, the top and bottom plates of each load capacitor are exchanged,,the output voltage is reversed, and the common-mode voltage error is canceled.

[0023] 5) A multi-bit SAR CDC is used as the first stage, a multi-bit multi-stage ΔΣ CDC is used as the second stage, the first-stage CDC (multi-bit SAR CDC) and the second-stage CDC (multi-bit multi-stage ΔΣ CDC) are connected through the top plate of a common DAC component, and a self-biased floating inverting amplifier is used as the first-stage integrator of the ΔΣ CDC, thereby obtaining an improved incremental scaling capacitive sensor readout circuit.

[0024] The present invention adopts the above method to prepare a multi-step capacitance sensor readout circuit system, including: a sampling circuit, a multi-bit SARCDC, and a multi-bit multi-order ΔΣ CDC. Among them, the sampling circuit is used to convert the capacitance value into a voltage signal; the multi-bit SARCDC is used as the first level of the system for the first step of coarse quantization; the ΔΣ CDC is used as the second level of the system for the second step of fine quantization. The multi-bit SAR CDC and the multi-bit multi-order ΔΣ CDC share a digital-to-analog converter (DAC), and the top plate of the DAC is connected to the top plate of the sensing capacitor to be measured. The DAC is composed of a capacitor array connected to two top plates of different sizes. When the two CDCs are working, the corresponding capacitor arrays are switched respectively. The capacitor array corresponding to the multi-bit SARCDC is called a coarse quantization DAC, and the capacitor array corresponding to the multi-bit multi-order ΔΣ CDC is called a fine quantization DAC.

[0025] A. Sampling circuit:

[0026] During the sampling phase, the top plate of the DAC shared by the sensing capacitor to be measured and the multi-bit SAR CDC and multi-bit multi-stage ΔΣ CDC is connected to V CM , the bottom plate is also connected to V CM , when the sampling switch is turned off, sampling noise charge is introduced. No discharge operation is performed on the top plate during the conversion process. The noise charge remains unchanged in the subsequent conversion process until the next sampling starts. After the sampling phase, when the chopping phase is +1, the bottom plate of the sensing capacitor is connected to V REFP , the DAC bottom plate is connected to the corresponding digital code; when the chopping phase is -1, the bottom plate of the sensing capacitor is connected to V REFN , the DAC baseplate is connected to the inverse of the corresponding digital code, and a chopping operation is performed again at the output position of the first-stage integrator. Finally, the sampling noise, the first-stage integrator offset and the first-stage integrator flicker noise (1 / f noise) are eliminated at the digital filter position.

[0027] B. The multi-bit SAR CDC consists of four parts: sampling circuit, coarse quantization DAC, comparator, and coarse quantization digital logic. Among them, the sampling circuit of SAR CDC and the system sampling circuit are combined into the same sampling circuit.

[0028] C. The multi-bit multi-stage ΔΣ CDC includes four parts: fine-quantization DAC, integrator, quantizer, and fine-quantization digital logic. Its characteristics are that a self-biased floating inverting amplifier is used as the first-stage integrator, and the common-mode feedback circuit adopts improved chopping technology to maintain the stability of the common-mode voltage output by the self-biased floating inverting amplifier.

[0029] Furthermore, the multi-bit SARCDC is 9 bits, of which 1 bit is redundant; the multi-bit multi-order ΔΣ CDC is 5 bits and 2nd order.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The present invention provides a sampling noise elimination technology based on chopping. The method fully utilizes the existing Zoom CDC basic structure without introducing additional hardware overhead, and fully utilizes the existing working timing of the CDC to eliminate the sampling noise together with the offset and 1 / f noise of the first-stage integrator, thereby avoiding the problems of increased power consumption and prolonged measurement time existing in two common methods, namely, multiple sampling average and traditional sampling noise elimination technology.

[0032] The present invention provides a high-energy-efficiency open-loop dynamic integrator implementation method, proposes a self-biased floating inverting amplifier structure, and uses it as the most critical first-stage integrator in the system. Due to the characteristics of current reuse, dynamic structure, open loop, etc., the structure has higher energy efficiency and noise efficiency than the traditional CDC integrator structure. In view of the above structure, the present invention also proposes an improved chopping technology that matches it, which solves the potential output common mode problem of the open-loop integrator without introducing any common mode feedback circuit, and further reduces the power consumption of the integrator module.

[0033] The present invention provides an incremental scaling capacitance sensor readout circuit, which applies the above technology to the entire capacitance-to-digital converter system, while achieving the application requirements of high energy efficiency, high precision and low measurement time, and is suitable for application scenarios such as robots and drones that require real-time monitoring and real-time control. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The structure diagram and working timing diagram of the incremental scaling capacitance sensor readout circuit of the present invention are shown in FIG. S is the capacitance sensor to be measured, i.e. the sensing capacitance, D SAR is the output digital code of SARCDC, D DSM is the output digital code of the ΔΣ CDC, D OUT is the output digital code of the entire CDC system. In the working sequence, SAR represents SARCDC for coarse quantization, and ΔΣM represents ΔΣ CDC for fine quantization. OSR is the oversampling rate of the system. G m1It is the first stage integrator.

[0035] Figure 2 Schematic diagram of the sampling circuit structure and working principle of the incremental scaling capacitance sensor readout circuit of the present invention. os represents the offset of the first-stage integrator, V n,kT / C is the sampling noise, V res represents the residual signal after quantization, Φ chop represents the chopping phase, D OUTP Represents a digital code, D OUTN Represents the inverse of a digital code.

[0036] Figure 3 The first stage integrator structure diagram of the incremental scaling capacitance sensor readout circuit of the present invention is a circuit diagram of a self-biased floating inverting amplifier. DD Represents the power supply voltage, V IP and V IN Represents the differential input signal, C R1 and C R2 is the power supply capacitor, V OP and V ON is the output voltage.

[0037] Figure 4 The schematic diagram of the improved chopping technology for the output position of the first-stage integrator of the incremental scaling capacitance sensor readout circuit of the present invention is shown in FIG. CM is the common-mode error current generated by the integrator, V Error,CM is the common-mode voltage error generated after each integration. DETAILED DESCRIPTION

[0038] The present invention will be further described below through specific implementation modes in conjunction with the accompanying drawings, but the scope of the present invention is not limited in any way.

[0039] The incremental scaling capacitance sensor readout circuit proposed in the present invention is composed of a coarse quantization CDC and a fine quantization CDC, wherein the coarse quantization CDC is a SARCDC, the fine quantization CDC is a ΔΣ CDC, and the coarse quantization CDC and the fine quantization CDC share a DAC. The present invention has both the high energy efficiency characteristics of the SARCDC and the high precision characteristics of the ΔΣ CDC. The present invention improves the sampling circuit and the most critical first-stage integrator of the ΔΣ CDC, further improving the precision and energy efficiency.

[0040] The overall structure of the present invention is a multi-step capacitance sensor readout circuit system, that is, an incremental scaling capacitance sensor readout circuit system. Based on the traditional structure, the present invention improves the sampling method and the implementation of the first-stage integrator. The incremental scaling capacitance sensor readout circuit of the present invention includes: a sampling circuit, a multi-bit successive approximation capacitance digital converter (SAR CDC), and a multi-bit multi-stage ΔΣ capacitance digital converter (ΔΣ CDC). Among them, the sampling circuit is used to convert the capacitance value into a voltage signal; the multi-bit SAR CDC is used as the first stage of the multi-step capacitance sensor readout circuit system for the first step of coarse quantization; the ΔΣ CDC is used as the second stage of the multi-step capacitance sensor readout circuit system for the second step of fine quantization. The multi-bit SAR CDC and the multi-bit multi-stage ΔΣ CDC share a digital-to-analog converter (DAC), and the top plate of the DAC is connected to the top plate of the sensing capacitor to be measured. The DAC is composed of a capacitor array connected to two top plates of different sizes. When the two CDCs are working, the corresponding capacitor arrays are switched respectively. The capacitor array corresponding to the multi-bit SAR CDC is called a coarse quantization DAC, and the capacitor array corresponding to the multi-bit multi-stage ΔΣ CDC is called a fine quantization DAC.

[0041] The components of the incremental scaling capacitive sensor readout circuit system proposed by the present invention (including: sampling circuit, coarse quantization SAR CDC, fine quantization ΔΣ CDC) are described in detail below:

[0042] A. Sampling Circuit Design

[0043] In specific implementation, the present invention designs and adopts a sampling noise elimination technology based on chopping. Its circuit structure is based on a traditional incremental zoom type capacitance sensor readout circuit, and improves the voltage connected to the bottom plate of the different phase sensing capacitor.

[0044] Specifically, during the sampling phase of the sampling circuit, the sensor capacitance to be measured ( Figure 1 C S ) and the common-mode level (V CM , the size is V REFP and V REFN The bottom plate is also connected to V CM At the same time, the digital codes of the multi-bit SAR CDC and ΔΣ CDC are cleared, and all the integrators of ΔΣ CDC are reset to eliminate the memory effect. After the sampling phase is completed, the bottom plate of the sensing capacitor is connected to the reference level V REFP or ground level V REFN, the change in the bottom plate voltage of the sensing capacitor transfers a portion of the charge proportional to the sensing capacitor to the top plate shared by the sensing capacitor and the DAC, and the charge will be quantized by the multi-bit SAR CDC and the multi-bit multi-order ΔΣ CDC respectively.

[0045] When the sampling switch is disconnected, sampling noise charge will be introduced. Since the method of the present invention does not perform any discharge operation on the top plate, the sampling noise charge remains unchanged in the subsequent conversion process until the next sampling starts. When the chopping phase is +1, the bottom plate of the sensing capacitor is connected to V REFP , the DAC bottom plate is connected to the corresponding digital code, so a residual charge is generated on the top plate shared by the sensing capacitor and the DAC, corresponding to a residual voltage; when the chopping phase is -1, the bottom plate of the sensing capacitor is connected to V REFN , the DAC bottom plate is connected to the inverse code of the corresponding digital code, so a residual charge of opposite polarity is generated on the top plate shared by the sensing capacitor and the DAC, corresponding to a residual voltage of opposite polarity. However, since the sampling noise charge is fixed on the top plate, the chopping does not change the polarity of the sampling noise, that is, in the two chopping phases, the sampling noise voltage corresponding to the sampling noise charge on the capacitor top plate is the same. The second chopping is performed after the first-stage integrator, which is equivalent to restoring the input signal (the signal corresponding to the residual voltage that needs to be finely quantized by ΔΣ CDC after coarse quantization) to a low frequency, converting the signal corresponding to the sampling noise to a high frequency, and finally eliminating the sampling noise after the digital code passes through the digital filter. This method also eliminates the offset and 1 / f noise of the first-stage integrator.

[0046] The sampling noise elimination technology based on chopping designed by the present invention is a new sampling method suitable for the capacitive sensor readout circuit, which is different from the sampling of the traditional capacitive sensor readout circuit. The existing chopping technology can eliminate offset and flicker noise, but cannot eliminate sampling noise. Some traditional capacitive sensor readout circuits do not use chopping technology; for capacitive sensor readout circuits using chopping technology, some work is system level chopping, which cannot eliminate sampling noise, and the rest of the work is limited by the working principle (mainly because a closed-loop integrator or closed-loop amplifier is used after the sampling circuit), and sampling noise cannot be eliminated. The sampling noise elimination technology based on chopping of the present invention is to perform two chopping operations at the first-stage integrator position of the sampling capacitor and the bottom plate of the DAC, and the fine-quantized multi-bit multi-order ΔΣ CDC. The first-stage integrator is a dynamic open-loop integrator structure (self-biased floating inverting amplifier), which can save the sampling noise and not be destroyed, so the sampling noise and the offset and flicker noise (also called 1 / f noise) of the first-stage integrator are in the same position in the system. Chopping technology can eliminate offset and flicker noise, so the sampling noise is also eliminated.

[0047] Compared with the prior art, the chopping-based sampling noise elimination technology proposed in the present invention does not introduce any hardware overhead, nor does it introduce any redundant time for processing the sampling noise, and therefore has lower power consumption and shorter measurement time.

[0048] B. Coarse SAR CDC Design

[0049] In specific implementation, the coarse quantization multi-bit SAR CDC used in the present invention comprises four parts: sampling circuit, coarse quantization DAC, comparator, and coarse quantization digital logic. Among them, the sampling circuit of SAR CDC and the system sampling circuit are combined into the same sampling circuit.

[0050] When working, the coarse quantization digital logic will change the digital code bit by bit according to the result of the comparator, and switch the corresponding capacitor unit of the DAC according to the digital code, so that the DAC top plate voltage gradually decreases and finally reaches the input voltage range allowed by the subsequent ΔΣ CDC.

[0051] During the SAR CDC coarse quantization process, the chopping phase remains unchanged, so the voltage on the sensor capacitor bottom plate does not change. During the subsequent ΔΣ CDC conversion, the SAR CDC DAC bottom plate will access the SAR CDC digital code or the inverse of the digital code according to the chopping phase.

[0052] C. Fine-scale ΔΣ CDC design

[0053] In specific implementation, the present invention designs and adopts a multi-bit multi-order ΔΣ CDC for fine quantization, which includes four parts: a fine quantization DAC, an integrator, a quantizer, and a fine quantization digital logic. The fine quantization DAC uses a smaller capacitance value than the coarse quantization DAC, and the capacitance size of the fine quantization DAC is larger than the minimum quantization step size of the coarse quantization DAC, ensuring that sufficient redundancy is retained between the multi-bit SAR CDC and the multi-bit multi-order ΔΣ CDC, and can tolerate errors that may occur in the quantization process of the multi-bit SAR CDC. The integrator part includes a first-stage integrator and a post-stage integrator, wherein the first-stage integrator uses a self-biased floating inverting amplifier. The specific design of the integrator is as follows:

[0054] C1. First-stage integrator design

[0055] In the specific implementation, the first-stage integrator adopts a self-biased floating inverting amplifier, which includes five parts: power supply capacitor, load capacitor, input tube, common source and common gate tube, and "virtual" transistor (dummy tube).

[0056] The input tube includes an NMOS transistor and a PMOS transistor, the gates of which are connected together and connected to the top plate of the sensing capacitor to be measured and the DAC to realize current multiplexing and improve the energy efficiency and noise efficiency of the self-biased floating inverting amplifier; the input tube adopts a thick gate tube to reduce gate leakage and protect the charge stored on the top plate of the sensing capacitor and the DAC; the input tube converts the input voltage into an output current and integrates it on the load capacitor. The gate of the "virtual" transistor is connected to the gate of the input tube, and the source and drain of the "virtual" transistor are short-circuited and connected to the drain of the opposite input tube; the gate length of the "virtual" transistor is the same as that of the input tube, and the gate width is half of that of the input tube, so the parasitic capacitance between the gate and drain of the "virtual" transistor is the same as that of the input tube. The existence of the "virtual" transistor causes the voltage change of the input tube drain to be coupled to its own gate and the gate of the opposite input tube at the same time, thereby eliminating the differential mode kickback noise and improving the accuracy of the multi-step capacitance sensor readout circuit system. The gate of the common source and common gate tube is connected to the top plate or bottom plate of the power supply capacitor according to the different positions. Among them, the drain of the opposite input tube is specifically as follows Figure 3 As shown, Figure 3 There are 4 rows of transistors in total. Take the bottom row of transistors as an example. The leftmost and rightmost transistors are input transistors, and the two middle transistors are dummy transistors. The gate of the second transistor on the left is connected to the gate of the left input transistor, and its source and drain are connected to the drain of the right input transistor.

[0057] When the self-biased floating inverting amplifier is working, the voltage difference between the top plate and the bottom plate of the power supply capacitor will gradually decrease, so the overdrive voltage of the common source and common gate tube will gradually decrease, and its bias state will gradually transition from the linear region to the saturation region, and the output impedance of the self-biased floating inverting amplifier will gradually increase. The self-biased floating inverting amplifier will gradually transition from a traditional floating inverting amplifier to a common source and common gate floating inverting amplifier, and to a certain extent, it has both the larger transconductance value of the traditional floating inverter and the smaller leakage of the common source and common gate floating inverting amplifier, thereby achieving a suitable integrator gain and a smaller leakage current. In the design of the present invention, the power supply capacitor is divided into two parts, large and small. By controlling the disconnection time of the large power supply capacitor, the speed of the self-biased floating inverting amplifier's transition from the traditional floating inverting amplifier to the common source and common gate floating inverting amplifier can be changed, thereby achieving the adjustment of the integrator parameters.

[0058] The self-biased floating inverting amplifier inherits the good common-mode rejection capability of the traditional floating inverting amplifier and the common-source and common-gate floating inverting amplifier. When used as an amplifier, it does not require any common-mode feedback loop to ensure that the output common-mode voltage changes are small. However, when the self-biased floating inverting amplifier is used as an open-loop integrator, small common-mode voltage changes will gradually accumulate. As the number of integrations of the integrator increases, the circuit will eventually fail to work properly. The output common-mode voltage change of the self-biased floating inverting amplifier is positively correlated with the input common-mode voltage change, and the input common-mode voltage change mainly comes from the common-mode kickback caused by the parasitic capacitance of the input tube. The size of the common-mode kickback has nothing to do with the differential input, that is, the output common-mode voltage change of the self-biased floating inverting amplifier is the same each time it is integrated. Chopping is required at the output position of the first-stage integrator to eliminate sampling noise, offset of the first-stage integrator, and 1 / f noise. The traditional chopping method will not affect the common-mode voltage and will not solve the above problems. The present invention improves the chopping operation mode of the first-stage integrator, and eliminates the change of the common-mode voltage output by the integrator by utilizing the characteristic that the output common-mode voltage of the self-biased floating inverting amplifier changes almost the same during each integration. Its operation mode is: during the integration process, one plate of the load capacitor is connected to the output node of the self-biased floating inverting amplifier, and one plate is connected to V CM , each time the chopping phase changes, the top and bottom plates of each load capacitor are swapped to achieve the reversal of the output voltage. Assuming that a certain integration process introduces a small output common-mode error on the load capacitor, in the next chopping phase, the capacitor flips and causes a common-mode error of opposite polarity to be pre-existing on the load capacitor. The common-mode error introduced by the integration process will cancel it out, thereby maintaining the output common-mode of the self-biased floating inverting amplifier to maintain a very small range of fluctuations, which has no effect on the performance of the self-biased floating inverting amplifier.

[0059] Compared with the existing technology, the entire first-stage integrator is an open-loop integrator based on a dynamic amplifier, and the input tube is a complementary input of an NMOS transistor and a PMOS transistor, which realizes current multiplexing and improves the energy efficiency and noise efficiency of the integrator. At the same time, the output common-mode problem of the first-stage integrator is solved by improving the chopping technology, and no common-mode feedback circuit is introduced, which further reduces power consumption and design complexity.

[0060] C2. Post-stage integrator design

[0061] For the incremental scaling capacitance sensor readout circuit, the noise of the back-stage integrator and the introduced error will be shaped by at least one order, so the accuracy of the entire CDC system is less affected, and the power consumption is usually small, so there is no need to do too much design. The incremental scaling capacitance sensor readout circuit of the present invention does not impose any structural restrictions on the back-stage integrator, and can use an integrator based on a voltage-controlled oscillator with a phase domain quantizer, or a noise-shaped successive approximation capacitance-to-digital converter, etc.

[0062] When the present invention is specifically implemented, the implementation of the incremental scaling capacitance sensor readout circuit system includes the following steps:

[0063] 1) Prepare a multi-bit SAR CDC, which includes four parts: sampling circuit, coarse quantization DAC, comparator, and coarse quantization digital logic. The sampling circuit adopts the sampling noise elimination technology based on chopping, that is, when sampling, the bottom plate of the capacitor is connected to V CM , when switching, the bottom plate is connected to V according to the chopping phase REFP or V REFN .

[0064] Structurally, multi-bit SAR CDC is used for coarse quantization.

[0065] 2) Prepare a multi-bit multi-stage ΔΣ CDC, which includes four parts: fine quantization DAC, integrator, quantizer, and fine quantization digital logic. The first-stage integrator adopts the self-biased floating inverting amplifier proposed by the present invention.

[0066] Structurally, multi-bit and multi-order ΔΣ CDC is used for fine quantization.

[0067] 3) The multi-bit SAR CDC and the multi-bit multi-step ΔΣ CDC share a DAC component, which consists of two capacitor arrays of different sizes connected to each other. The DAC of the multi-bit SAR CDC is a coarse quantization DAC, and the DAC of the multi-bit multi-step ΔΣ CDC is a fine quantization DAC.

[0068] 4) Prepare a self-biased floating inverting amplifier and split the power supply capacitor into two parts to adjust its specific working mode. The output node adopts the proposed improved chopping technology to exchange the top and bottom plates of each load capacitor to achieve chopping, thereby eliminating the change of the output common-mode voltage of the self-biased floating inverting amplifier and maintaining the common-mode voltage stable.

[0069] Structurally, a self-biased floating inverting amplifier is used as the most critical first-stage integrator in the system.

[0070] 5) Using a multi-bit SAR CDC as the first stage and a multi-bit multi-order ΔΣ CDC as the second stage, the first-stage CDC and the second-stage CDC are connected through a DAC top plate, and a self-biased floating inverting amplifier is used as the first-stage integrator of the ΔΣ CDC, an improved incremental scaling capacitive sensor readout circuit can be obtained.

[0071] like Figure 1As shown, when the incremental scaling capacitance sensor readout circuit of the present invention is specifically implemented, a 9-bit SARCDC is used for the first-level coarse quantization, one bit of which is redundant, and a 5-bit second-order ΔΣ CDC is used for the second-level fine quantization. The SARCDC and ΔΣ CDC share a DAC component. When the entire system is working, sampling is first performed, then a coarse quantization is performed, and then an OSR fine quantization is performed. During the fine quantization, the chopping phase is periodically modified to eliminate sampling noise and the offset and 1 / f noise of the first-level integrator. The digital code obtained by the coarse quantization and the digital code obtained by the fine quantization will pass through a digital filter, that is, a second-order downsampling filter, and finally obtain the digital output of the entire CDC system.

[0072] Specifically, its working mode is as follows:

[0073] 1) Sampling phase

[0074] like Figure 2 As shown, the sensing capacitor C S The top and bottom plates of the DACs shared by the multi-bit SAR CDC and the multi-bit multi-stage ΔΣ CDC are connected to V at the same time. CM , and the integrator of ΔΣ CDC is reset at the same time to realize the incremental function and simplify the design of the digital filter. When the sampling switch is disconnected, sampling noise will be introduced and fixed on the top plate of the capacitor until the next sampling. The sampling noise is in the same position as the offset and 1 / f noise of the first-stage integrator, and will be eliminated after the sampling phase through the sampling noise elimination technology based on chopping proposed by the present invention.

[0075] 2) Coarse quantization phase

[0076] Coarse quantization phase, chopping signal Φ Chop Remain unchanged, SARCDC performs 9-bit coarse quantization. During the quantization process, the capacitor elements of the DAC will be switched in sequence from large to small according to the comparator result, and the digital code will be saved through the latch. During the coarse quantization process, the reset state of the integrator of the ΔΣ CDC is still maintained.

[0077] 3) Fine quantization phase

[0078] The fine quantization phase will be OSR sub-quantized. In this stage, the SAR part of the digital code remains unchanged, and only the fine quantization DAC corresponding to ΔΣCDC is switched. The chopping phase changes continuously in the "+1, -1, -1, +1" pattern during the OSR sub-quantization process. Since the chopping occurs at the same time in C S And the capacitor bottom plate of the DAC and the output of the first-stage integrator, therefore, the residual signal will be chopped twice and returned to the low frequency, the sampling noise, the offset of the first-stage integrator, and the 1 / f noise of the first-stage integrator will be chopped once and will be modulated to the frequency of the chopped signal and finally eliminated by the digital filter.

[0079] For ΔΣ CDC, the thermal noise of the first-stage integrator is not shaped by noise like the input signal, so the first-stage integrator is usually the main noise source and the dominant power consumption of the entire CDC system. The circuit structure of the self-biased floating inverting amplifier proposed by the present invention is as follows: Figure 3 As shown in the figure, the overall structure is an open-loop integrator with higher noise efficiency and energy efficiency. The integrator input is connected to both PMOS and NMOS input tubes to achieve current multiplexing and reduce noise. The input tube is a thick-gate tube to reduce gate leakage. The source and drain of the "virtual" transistor are connected to eliminate the kickback noise of the differential mode and ensure the accuracy of the multi-step capacitance sensor readout circuit system. When the integrator is working, the power supply capacitor C R1 and C R2 The voltage difference between the top plate and the bottom plate gradually decreases, and the working state of the common source and common gate tube gradually transitions from the linear region to the saturation region. In order to further control the speed of the transition, C R1 Will disconnect in advance, by controlling C R1 The disconnection time allows for more detailed adjustment of the integrator parameters.

[0080] To solve the output common mode problem, the improved chopping technology proposed in the present invention is as follows: Figure 4 As shown. Figure 1 At different chopping phases indicated in the timing diagram, the top plate and bottom plate of the load capacitor of the first-stage integrator will be interchanged, thus canceling out the common-mode error generated by the integrator. Due to the natural common-mode rejection characteristics of the self-biased floating inverting amplifier, the output common-mode error generated by each integration is small, so the output common-mode of the entire integrator can be maintained within a very small range, avoiding the use of common-mode feedback circuits and reducing system complexity and power consumption.

[0081] The present invention provides a multi-step capacitance sensor readout circuit system and an implementation method thereof, which improves the incremental scaling capacitance sensor readout circuit, including: a sampling method based on chopping and a self-biased floating inverting amplifier. The sampling method designed by the present invention does not introduce additional hardware overhead, makes full use of the working timing of the CDC, eliminates the sampling noise together with the offset and 1 / f noise of the first-stage integrator, and avoids the problems of increased power consumption and prolonged measurement time existing in two common methods of multiple sampling averages and traditional sampling noise elimination technology. At the same time, the self-biased floating inverting amplifier provided by the present invention is used as a first-stage integrator, which improves the energy efficiency of the system and avoids the use of a common-mode feedback circuit. Compared with the existing capacitance sensor readout circuit, the present invention achieves the characteristics of high energy efficiency, high precision and low latency, and has broad application prospects in the fields of robots, drones, etc.

[0082] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for implementing a multi-step capacitance sensor readout circuit system, characterized in that: Design an incremental scaling capacitive sensor readout circuit without an additional amplifier, using chopping timing to eliminate sampling noise, and using a dynamic open-loop integrator as the first-stage integrator to improve system energy efficiency; including the following steps: 1) Prepare a self-biased floating inverting amplifier; The self-biased floating inverting amplifier comprises a power supply capacitor, a load capacitor, an input tube, a cascode tube and a dummy transistor; wherein the input tube comprises an NMOS transistor and a PMOS transistor, the gates of the two are connected together to form the gate of the input tube, which is connected to the sensing capacitor to be measured and the top plate of the digital-to-analog converter DAC; the source and drain of the dummy transistor are short-circuited and connected to the drain of the opposite input tube, and the gate of the dummy transistor is connected to the gate of the input tube; the gate length of the dummy transistor is the same as that of the input tube, and the gate width is half of that of the input tube; the gate of the cascode tube is connected to the top plate or the bottom plate of the power supply capacitor; When the self-biased floating inverting amplifier is working, the voltage difference between the top plate and the bottom plate of the power supply capacitor gradually decreases, the overdrive voltage of the common source and common gate tube gradually decreases, the bias state transitions from the linear region to the saturation region, and the self-biased floating inverting amplifier gradually transitions from a floating inverting amplifier to a common source and common gate floating inverting amplifier, achieving integrator gain and small leakage current; the power supply capacitor is split into two parts, large and small, and the parameters of the self-biased floating inverting amplifier are adjusted by controlling the disconnection time of the large power supply capacitor; 2) Prepare a multi-bit successive approximation capacitor-to-digital converter, i.e., a multi-bit SAR CDC, which includes a sampling circuit, a coarse quantization digital-to-analog converter DAC, a comparator, and a coarse quantization digital logic part; wherein, the sampling circuit uses a sampling noise elimination technology based on chopping to eliminate the sampling noise; during sampling, the bottom plate of the capacitor is connected to the common-mode level V CM After sampling the phase, the base plate is connected to the reference level V according to the chopping phase REFP or ground level V REFN ; 3) Prepare a multi-bit multi-stage ΔΣ capacitance-to-digital converter, i.e., a multi-bit multi-stage ΔΣCDC, which includes a fine-quantization DAC, an integrator, a quantizer, and a fine-quantization digital logic part; wherein the dynamic open-loop integrator used in the first-stage integrator is a self-biased floating inverting amplifier; the output node of the self-biased floating inverting amplifier adopts an improved chopping technology, swapping the top plate and the bottom plate of each load capacitor, eliminating the change of the output common-mode voltage of the self-biased floating inverting amplifier, and maintaining the common-mode voltage stable; The improved chopping technique is: when the self-biased floating inverting amplifier is used as an open-loop integrator, during the integration process, one plate of the load capacitor is connected to the output node of the self-biased floating inverting amplifier, and the other plate is connected to V CM ,When the chopping phase changes, the top and bottom plates of each load capacitor are exchanged to achieve the reversal of the output voltage and the cancellation of the common-mode voltage error; 4) Multi-bit SAR CDC and multi-bit multi-order ΔΣ CDC share a DAC component, which consists of two parts of capacitor arrays of different sizes connected to the top plate; 5) A multi-bit SAR CDC is used as the first stage, a multi-bit multi-order ΔΣ CDC is used as the second stage, the first stage and the second stage are connected through a common DAC top plate, and a self-biased floating inverting amplifier is used as the first stage integrator of the ΔΣ CDC, thereby obtaining an improved incremental scaling capacitive sensor readout circuit.

2. The method for implementing the multi-step capacitance sensor readout circuit system as claimed in claim 1, characterized in that: The chopping-based sampling noise elimination technique is to connect the top and bottom plates of the DAC and the sensor capacitor to be measured to V during the sampling phase. CM In the conversion phase after the sampling phase, that is, the coarse quantization phase and the fine quantization phase, when the chopping phase is +1, the bottom plate of the sensing capacitor is connected to V REFP , the DAC bottom plate is connected to the corresponding digital code, and a residual voltage is generated on the top plate shared by the sensing capacitor and the DAC; when the chopping phase is -1, the bottom plate of the sensing capacitor is connected to V REFN The DAC bottom plate is connected to the inverse code of the corresponding digital code, and a residual voltage with opposite polarity and a sampling noise with the same polarity are generated at the top plate shared by the sensing capacitor and the DAC; after the first-stage integrator, the integrated residual signal is chopped for the second time, and finally the digital code is passed through a digital downsampling filter to eliminate the sampling noise.

3. The method for implementing the multi-step capacitance sensor readout circuit system as claimed in claim 1, characterized in that: In step 3), the input tube of the self-biased floating inverting amplifier adopts a thick-gate tube.

4. A multi-step capacitance sensor readout circuit system prepared by the implementation method of the multi-step capacitance sensor readout circuit system according to claim 1, characterized in that: The multi-step capacitance sensor readout circuit system comprises: a sampling circuit, a multi-bit SARCDC and a multi-bit multi-stage ΔΣ CDC; wherein, The sampling circuit is used to convert the capacitance value into a voltage signal; The multi-bit SAR CDC is used as the first stage of the system for the first step of coarse quantization; ΔΣ CDC is used as the second level of the system for the second step of refinement; The multi-bit SAR CDC and the multi-bit multi-order ΔΣ CDC share a digital-to-analog converter DAC, and the top plate of the digital-to-analog converter DAC is connected to the top plate of the sensing capacitor to be measured; the digital-to-analog converter DAC is composed of a capacitor array connected by two top plates of different sizes, and the corresponding capacitor arrays are switched respectively when the two CDCs are working. The capacitor array corresponding to the multi-bit SAR CDC is a coarse quantization DAC, and the capacitor array corresponding to the multi-bit multi-order ΔΣ CDC is a fine quantization DAC.

5. The multi-step capacitance sensor readout circuit system as claimed in claim 4, characterized in that: The sampling circuit works in the following ways: During the sampling phase, the top plate of the DAC shared by the sensing capacitor to be measured and the multi-bit SAR CDC and multi-bit multi-stage ΔΣ CDC is connected to V CM , the bottom plate is also connected to V CM ; When the sampling switch is disconnected, sampling noise charge is introduced. No discharge operation is performed on the top plate during the conversion process, and the noise charge remains unchanged during the subsequent conversion process until the next sampling starts; After the sampling phase, when the chopping phase is +1, the bottom plate of the sensing capacitor is connected to V REFP , the DAC bottom plate is connected to the corresponding digital code; when the chopping phase is -1, the bottom plate of the sensing capacitor is connected to V REFN , the DAC base plate is connected to the inverse of the corresponding digital code, and a chopping operation is performed again at the output position of the first-stage integrator. Finally, the sampling noise, the first-stage integrator offset and the first-stage integrator 1 / f noise are eliminated at the digital filter position.

6. The multi-step capacitance sensor readout circuit system as claimed in claim 5, characterized in that: The multi-bit SAR CDC includes a sampling circuit, a coarse quantization DAC, a comparator, and a coarse quantization digital logic part; wherein the sampling circuit of the SAR CDC and the system sampling circuit are combined into the same sampling circuit.

7. The multi-step capacitance sensor readout circuit system as claimed in claim 6, characterized in that: The multi-bit multi-stage ΔΣ CDC includes a fine-quantization DAC, an integrator, a quantizer, and a fine-quantization digital logic part; a self-biased floating inverting amplifier is used as the first-stage integrator, and an improved chopping technique is used to maintain the stability of the common-mode voltage output by the self-biased floating inverting amplifier.

8. The multi-step capacitance sensor readout circuit system as claimed in claim 7, characterized in that: The multi-bit SAR CDC is 9 bits, with 1 bit of redundancy; the multi-bit multi-order ΔΣ CDC is 5 bits of 2nd order.

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