Multi-band multi-path interconnect

Abstract

The invention relates to a multi-band multi-path interconnect. An electronic device includes a first interconnect between a first circuit and a second circuit, the first interconnect not including a switch. A second interconnect may couple or connect a third circuit to the first interconnect via a first switch. A signal transmitted from the first circuit to the second circuit may have a higher priority and / or a different frequency than a signal transmitted from the third circuit to the second circuit. The first switch may be disposed near a first junction of the first interconnect and the second interconnect. In some embodiments, a ground potential or termination resistance may also be coupled to the first interconnect via a second switch. The second switch may be coupled to the first interconnect at a second junction proximate the first circuit.

Description

Background Art

[0001] The present disclosure relates generally to wireless communications and, more particularly, to interconnects or routing within and / or between integrated circuits for performing or facilitating wireless communications.

[0002] Communication circuits such as radio frequency and / or millimeter wave (mmWave) frequency communication circuits may include many interconnects or routes that are used to communicatively couple functional blocks (e.g., circuits and / or components) within (or between) an integrated circuit or chip. These interconnects may support multiple and / or different frequencies (e.g., multiple and / or different frequency bands) and may have different performance priorities. That is, interconnects for communications using some frequencies or frequency bands may have different (e.g., higher or lower) priorities than interconnects for communications using other frequencies or frequency bands. When necessary, switches can be used to communicatively couple different functional blocks via different interconnects. However, switches may cause undesirable loss of signals in the interconnects and / or performance degradation. Summary of the invention

[0003] The following describes a summary of certain embodiments disclosed herein. It should be understood that these aspects are presented only to provide the reader with a concise summary of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass a number of aspects that may not be described below.

[0004] In one embodiment, a radio frequency circuit includes: a first circuit; a second circuit; a first interconnection that couples the first circuit to the second circuit; a third circuit; and a second interconnection that couples the third circuit to the first interconnection via a first switch. The first interconnection is continuous.

[0005] In another embodiment, a tangible, non-transitory computer-readable medium stores instructions that cause a processing circuit to perform the following operations: receive an indication of a frequency of a signal to be sent from a first circuit to a second circuit through a first interconnect or from a third circuit to the second circuit through a second interconnect and the first interconnect; deactivate a first switch coupling the third circuit to the first interconnect and deactivate a second switch coupling the third interconnect to the first interconnect based on the frequency being associated with a priority; and activate the first switch and activate the second switch based on the frequency not being associated with the priority.

[0006] In another embodiment, an electronic device includes: one or more antennas; and a transceiver coupled to the one or more antennas. The transceiver includes: a first circuit; a second circuit; a first interconnect, the first interconnect coupling the first circuit to the second circuit; a third circuit; and a second interconnect coupling the third circuit to the first interconnect via a first switch. The first interconnect transmits a first signal of a first frequency from the first circuit to the second circuit, and the second interconnect transmits a second signal of a second frequency from the third circuit to the second circuit.

[0007] With respect to various aspects of the present disclosure, there may be various improvements to the above-mentioned features. Other features may also be incorporated in these various aspects. These improvements and additional features may exist individually or in any combination. For example, the various features discussed below with respect to one or more embodiments in the illustrated embodiments may be incorporated into any of the above-mentioned aspects of the present disclosure individually or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of the embodiments of the present disclosure, without limiting the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be better understood upon reading the following detailed description and referring to the drawings described below, in which like reference numerals refer to like parts.

[0009] Figure 1 is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 2 According to the embodiments of the present disclosure Figure 1 Functional diagram of electronic equipment;

[0011] Figure 3 According to the embodiments of the present disclosure Figure 1 A schematic diagram of a transmitter of an electronic device;

[0012] Figure 4 According to the embodiments of the present disclosure Figure 1 A schematic diagram of a receiver of an electronic device;

[0013] Figure 5A According to the embodiments of the present disclosure Figure 1 A schematic diagram of a radio frequency (RF) circuit of an electronic device of the present invention, the radio frequency (RF) circuit having: a first circuit; a second circuit; a third circuit; a first interconnection, the first interconnection coupling the first circuit and the second circuit; a second interconnection, the second interconnection coupling the third circuit and the first interconnection at a node, wherein the node is located near the first circuit;

[0014] Figure 5B A circuit according to an embodiment of the present disclosure operates in a first mode to send a high priority signal from a first circuit to a second circuit Figure 5A Schematic diagram of the RF circuit;

[0015] Figure 5C is a circuit according to an embodiment of the present disclosure that operates in a second mode to send a low priority signal from a third circuit to a second circuit Figure 5A Schematic diagram of the RF circuit;

[0016] Figure 6 is a method for operating according to an embodiment of the present disclosure Figure 5A A flowchart of a method for an RF circuit to send a high priority signal and a low priority signal to a second circuit;

[0017] Fig. 7A According to the embodiments of the present disclosure Figure 1 A schematic diagram of an RF circuit of an electronic device, the RF circuit having: a first circuit; a second circuit; a third circuit; a first interconnection, the first interconnection coupling the first circuit and the second circuit; a second interconnection, the second interconnection coupling the third circuit and the first interconnection at a first node, wherein the first node is located near the second circuit; and a second switch, the second switch coupled to a ground potential, the first interconnection at a second node that is a quarter of a lambda length away from the first node;

[0018] Figure 7B A circuit according to an embodiment of the present disclosure operates in a first mode to send a high priority signal from a first circuit to a second circuit Fig. 7A Schematic diagram of the RF circuit;

[0019] Figure 7C is a circuit according to an embodiment of the present disclosure that operates in a second mode to send a low priority signal from a third circuit to a second circuit Fig. 7A Schematic diagram of the RF circuit;

[0020] Figure 8 is a method for operating according to an embodiment of the present disclosure Fig. 7A A flowchart of a method for an RF circuit to send a high priority signal and a low priority signal to a second circuit;

[0021] Fig. 9A According to the embodiments of the present disclosure Figure 1Schematic diagram of an RF circuit of an electronic device, the RF circuit having: a first circuit; a second circuit; a third circuit; a first interconnection, the first interconnection coupling the first circuit and the second circuit; a second interconnection, the second interconnection coupling the third circuit and the first interconnection at a first node, wherein the first node is located near the second circuit; and a second switch, the second switch coupled to a resistor, a ground potential, and the first interconnection;

[0022] Fig. 9B A circuit according to an embodiment of the present disclosure operates in a first mode to send a high priority signal from a first circuit to a second circuit Fig. 9A Schematic diagram of the RF circuit;

[0023] Fig. 9C is a circuit according to an embodiment of the present disclosure that operates in a second mode to send a low priority signal from a third circuit to a second circuit Fig. 9A Schematic diagram of the RF circuit;

[0024] Fig.10 is a method for operating according to an embodiment of the present disclosure Fig. 9A A flowchart of a method for an RF circuit to send a high priority signal and a low priority signal to a second circuit;

[0025] Fig.11 According to the embodiments of the present disclosure Figure 1 Schematic diagram of an RF circuit of an electronic device, the RF circuit having: a first circuit; a second circuit; a third circuit; a fourth circuit; a first interconnection, the first interconnection coupling the first circuit and the second circuit; a second interconnection, the second interconnection coupling the third circuit and the first interconnection at a first node; a third interconnection, the third interconnection having a second switch, the second switch coupled to a resistor, a ground potential, and the first interconnection at a second node; and a fourth interconnection, the fourth interconnection coupling the fourth circuit and the first interconnection at a third node, wherein the first node and the third node are located near the second circuit; and

[0026] Fig.12 According to the embodiments of the present disclosure Figure 1 A schematic diagram of an RF circuit of an electronic device, the RF circuit having: a first circuit; a second circuit; a third circuit; a fourth circuit; a first interconnect, the first interconnect coupling the first circuit and the second circuit; a second interconnect, the second interconnect coupling a third switch and the first interconnect at a first node; a third interconnect having a second switch coupled to a resistor, a ground potential, and the first interconnect; and a third switch coupling the third circuit and the fourth circuit to the second interconnect. DETAILED DESCRIPTION

[0027] When introducing the elements of various embodiments of the present disclosure, the articles "one", "an" and "the" are intended to mean one or more elements present in the elements. The terms "including", "comprising" and "having" are intended to be inclusive, and mean that there may be additional elements other than the listed elements. In addition, it should be understood that the reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the features. In addition, specific features, structures or characteristics can be combined in any appropriate manner in one or more embodiments. The use of the terms "roughly", "close to", "about", "close to" and / or "substantially" should be understood to mean including close to a target (e.g., design, value and amount), such as within the limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). In addition, it should be understood that any exact value, number, measurement value, etc. provided herein can be conceived to include approximate values ​​of these exact values, numbers, measurement values, etc. (e.g., within the limits of suitable or conceivable error). Additionally, the term "set" may include one or more. That is, a set may include a single set of one member, but a set may also include sets of multiple members.

[0028] The present disclosure relates to interconnects or routing in and / or between integrated circuits for performing or facilitating communication. Interconnects may support multiple and / or different frequencies (e.g., multiple and / or different frequency bands) and may have different performance priorities. For example, a first interconnect coupling a first circuit and a second circuit may convey (e.g., transmit) a signal of a first frequency, which may have a higher priority than a second interconnect coupling the first interconnect and a third circuit at a node conveying (e.g., transmitting) a signal of a second frequency. The first circuit, the second circuit, and the third circuit may include any circuit or functional block for facilitating radio frequency operation, such as radio frequency front-end components (e.g., digital-to-analog converters (DACs), analog-to-digital converters (ADCs), filters, mixers, etc.). Although the present disclosure may relate to applying the disclosed embodiments to wireless communication systems, it should be understood that they may also be applied to wired communication systems, particularly where the operating frequency or data rate is sufficiently high (e.g., greater than 1 gigahertz (GHz), greater than 2 GHz, greater than 3 GHz, etc.), such as in the case of transmission line theory. Therefore, it may be desirable that the first interconnect has better performance than the second interconnect.

[0029] The switching circuit can be used to couple the first circuit to the second circuit or the third circuit, thus using the first interconnect or the second interconnect. For example, when it is desired to send a high priority signal between the first circuit and the second circuit, the first switch on the first interconnect can be activated or turned on to couple the first circuit to the second circuit, and the second switch on the second interconnect can be deactivated or turned off to decouple the third circuit from the first interconnect. In some embodiments, the length of the first interconnect may be greater than the length of the second interconnect. In addition, the first switch can be set to be closer to the node of the first interconnect and the second interconnect than the first circuit. For example, the first switch can be set within a threshold distance from the node, and the second switch can be set within a threshold distance from the first node. Therefore, when the second switch is deactivated, the load from the second switch is reduced or minimized, thereby providing a high or maximum non-operating path impedance, which prevents the signal from the third circuit from being transmitted to the first interconnect and thus transmitted to the second circuit. When it is desired to send a low priority signal over the second interconnect, the second switch on the second interconnect may be activated to couple the third circuit to the first interconnect and thus to the second circuit, while the first switch on the first interconnect may be deactivated to decouple the first circuit from the second circuit. However, when a high priority signal is sent over the first interconnect, the activated first switch may still provide a low or minimal operating path impedance that results in a non-zero power loss in the high priority signal (although less than the power loss when the first switch is deactivated).

[0030] Embodiments herein provide various interconnects or routes (e.g., between or within integrated circuits or chips) that reduce power loss in signals. To this end, embodiments disclosed herein include a first interconnect that does not include a switch between a first circuit (e.g., a first source circuit) and a second circuit (e.g., a target circuit). Therefore, the first interconnect may directly couple or connect the first circuit and the second circuit (e.g., without any intervening or intermediate components). The second interconnect may couple or connect a third circuit (e.g., a second source circuit) to the first interconnect via a first switch and thus couple or connect to the second circuit. A signal sent from the first circuit to the second circuit may have a higher priority and / or a different frequency than a signal sent from the third circuit to the second circuit. The first switch may be disposed near a first node of the first interconnect and the second interconnect (e.g., within a threshold distance from the first node). In addition, the first node may be disposed near the second circuit (e.g., within a threshold distance from the second circuit).

[0031] In some embodiments, the first node may be located near the first circuit (e.g., within a threshold distance from the first circuit). When it is desired to send a high priority signal between the first circuit and the second circuit, the first switch may be deactivated or turned off to decouple the third circuit from the first interconnect, and the first circuit may be activated or turned on. The absence of a switch on the first interconnect may reduce or minimize the loss of high priority signals sent from the first circuit to the second circuit, and the deactivated first switch may provide a high impedance on the non-operating path (of the second interconnect). When it is desired to send a low priority signal between the second circuit and the third circuit, the first switch may be activated or turned on to couple the third circuit to the first interconnect, and the first circuit may be deactivated or turned off, thereby providing a high impedance. Since the first node is located near the first circuit, reflections of low priority signals from the high impedance of the first circuit may be reduced or minimized.

[0032] In additional or alternative embodiments, the ground potential may also be coupled to the first interconnect via a second switch. The second switch may be coupled to the first interconnect at a second node that is one quarter lambda length away from the first node, where one quarter lambda length is the quotient of the speed of the wave of the signal traveling in the first interconnect (e.g., the speed of light) divided by the frequency of the signal. The second switch may be disposed near the second node (e.g., within a threshold distance from the second node). When it is desired to send a high priority signal between the first circuit and the second circuit, the first switch may be disabled or turned off to decouple the third circuit from the first interconnect, and the second switch system may be disabled or turned off to decouple the ground potential from the first interconnect. The absence of a switch on the first interconnect may reduce or minimize the loss of a high priority signal sent from the first circuit to the second circuit, while the disabled first switch may provide a high impedance on a non-operating path (of the second interconnect), and the disabled second switch may provide a high impedance near the ground potential, thereby at least partially preventing the high priority signal from traveling to the second circuit and / or the ground potential. When it is desired to send a low priority signal between the second circuit and the third circuit, the first switch may be activated or turned on to couple the third circuit to the first interconnect, and the second switch may be activated or turned on to couple the ground potential to the first interconnect. Thus, the second switch and the ground potential may provide a low impedance at a second node that is one quarter of a lambda length away from the first node, thereby resulting in a high impedance at the first node, thereby at least partially blocking the low priority signal from traveling to the first circuit and / or the ground potential.

[0033] In some embodiments, the terminal resistance may be coupled to the first interconnection via a second switch. The second switch may be coupled to the first interconnection at a second node near the first circuit (e.g., within a threshold distance from the first node). When it is desired to send a high priority signal between the first circuit and the second circuit, the first switch may be deactivated or turned off to decouple the third circuit from the first interconnection, the second switch may be deactivated or turned off to decouple the terminal resistance from the first interconnection, and the first circuit may be activated or turned on. The absence of a switch on the first interconnection may reduce or minimize the loss of high priority signals sent from the first circuit to the second circuit, while the deactivated first switch may provide a high impedance on the non-operating path (of the second interconnection), and the deactivated second switch may provide a high impedance near the terminal resistance, thereby at least partially preventing the high priority signal from traveling to the second circuit or the terminal resistance. When it is desired to send a low priority signal between the second circuit and the third circuit, the first switch may be activated or turned on to couple the third circuit to the first interconnection, and the second switch may be activated or turned on to couple the terminal resistance to the first interconnection, and the first circuit may be deactivated or turned off to provide a high impedance. The low priority signal may be split from the third circuit at the first node into a first portion traveling to the second circuit and a second portion traveling toward the high impedance of the disabled first circuit. However, since the second switch is activated, the second portion may not be reflected from the high impedance of the disabled first circuit, but may travel to the terminal resistor and be absorbed by the terminal resistor, thereby reducing or minimizing the reflection of the low priority signal.

[0034] Figure 1 is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include, among other things, one or more processors 12 (collectively referred to herein as a single processor for convenience, which may be implemented in any suitable form of processing circuitry), a memory 14, a non-volatile storage device 16, a display 18, input structures 22, an input / output (I / O) interface 24, a network interface 26, and a power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuits), software elements (including machine executable instructions), or a combination of hardware and software elements (which may be referred to as logical components). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to transmit and / or receive signals between each other. It should be noted that Figure 1 This is merely one example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10 .

[0035] By way of example, electronic device 10 may include any suitable computing device, including a desktop or laptop computer, a portable electronic or handheld electronic device (such as a wireless electronic device or a smart phone), a tablet device, a wearable electronic device, and other similar devices. In additional or alternative embodiments, electronic device 10 may include an access point, such as a base station, a router (e.g., a wireless or Wi-Fi router), a hub, a switch, etc. It should be noted that Figure 1 The processor 12 and other related items in the embodiment may be embodied in whole or in part as software, hardware, or both. Figure 1 Other related items in the electronic device 10 may be single independent processing modules, or may be fully or partially integrated into any of the other elements in the electronic device 10. The processor 12 may be implemented using a combination of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, a gated logic, a discrete hardware component, a dedicated hardware finite state machine, or any other suitable entity that can perform calculations or other manipulations of information. The processor 12 may include one or more application processors, one or more baseband processors, or both, and perform various functions described herein.

[0036] exist Figure 1 In the electronic device 10, the processor 12 may be operably coupled to the memory 14 and the non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article including one or more tangible computer-readable media. The tangible computer-readable medium may include the memory 14 and / or the non-volatile storage device 16, individually or collectively, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard drive, and optical disk. In addition, the program (e.g., operating system) encoded on such a computer program product may also include instructions that can be executed by the processor 12 to enable the electronic device 10 to provide various functions.

[0037] In certain embodiments, display 18 may facilitate a user viewing images generated on electronic device 10. In some embodiments, display 18 may include a touch screen that may facilitate a user interacting with a user interface of electronic device 10. Additionally, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light emitting diode (LED) displays, organic light emitting diode (OLED) displays, active matrix organic light emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0038] The input structures 22 of the electronic device 10 may enable a user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). As with the network interface 26, the I / O interface 24 may enable the electronic device 10 to interact with various other electronic devices. In some embodiments, the I / O interface 24 may include an I / O port for a hardwired connection to charge and / or manipulate content using a standard connector and protocol (such as a Lightning connector, a universal serial bus (USB), or other similar connectors and protocols). The network interface 26 may include, for example, one or more interfaces for a personal area network (PAN), such as an ultra-wideband (UWB) or Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN), such as one of the IEEE 802.11x family of protocols (e.g., ) networks; and / or wide area networks (WANs), such as any standards associated with the Third Generation Partnership Project (3GPP), including, for example, 3rd generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), 4th generation (4G) cellular networks, Long Term Evolution (LTE) networks, and / or Wide Area Networks (WANs). (LTE) cellular network, Long Term Evolution Licensed Assisted Access (LTE-LAA) cellular network, 5th Generation (5G) cellular network and / or New Radio (NR) cellular network, 6th Generation (6G) or beyond 6G cellular network, satellite network, non-terrestrial network, etc. Specifically, the network interface 26 may include, for example, one or more interfaces for using a cellular communication standard of the 5G specification including a millimeter wave (mmWave) frequency range (e.g., 24.25 gigahertz (GHz) to 300 GHz) that defines and / or implements a frequency range for wireless communication. The network interface 26 of the electronic device 10 may allow communication through the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0039] The network interface 26 may also include, for example, one or more interfaces for: a broadband fixed wireless access network (eg, ), mobile broadband wireless network (mobile ), asynchronous digital subscriber line (e.g., ADSL, VDSL), digital video terrestrial broadcasting Network and its extension DVB handheld devices Networks, ultra-wideband (UWB) networks, alternating current (AC) power lines, etc.

[0040] As shown, the network interface 26 may include a transceiver 30. In some embodiments, all or part of the transceiver 30 may be disposed within the processor 12. The transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas, and thus may include a transmitter and a receiver. The power supply 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0041] Figure 2 According to the embodiments of the present disclosure Figure 1 1 is a functional diagram of an electronic device 10. As shown, the processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) can be directly or indirectly communicatively coupled to each other (e.g., through or via another component, a communication bus, a network) to transmit and / or receive signals between each other.

[0042] The electronic device 10 may include a transmitter 52 and / or a receiver 54, both of which enable, for example, transmission and reception of signals between the electronic device 10 and an external device via a network (e.g., including a base station or access point) or a direct connection. As shown, the transmitter 52 and the receiver 54 may be combined into a transceiver 30. The electronic device 10 may also have one or more antennas 55A-55N electrically coupled to the transceiver 30. The antennas 55A-55N may be configured in an omnidirectional or directional configuration, such as a single beam, a dual beam, or a multi-beam arrangement. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in the antennas 55A-55N of an antenna group or module may be communicatively coupled to a corresponding transceiver 30, and each may emit a radio frequency signal that may be constructively and / or destructively combined to form a beam. The electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas suitable for various communication standards. In some embodiments, transmitter 52 and receiver 54 may transmit and receive information via other wired or wired systems or devices.

[0043] As shown, the various components of the electronic device 10 can be coupled together via a bus system 56. The bus system 56 may include, for example, a data bus and, in addition to the data bus, a power bus, a control signal bus, and a status signal bus. The components of the electronic device 10 may be coupled together or receive or provide input to each other using some other mechanism.

[0044] Figure 3is a schematic diagram of a transmitter 52 (e.g., a transmission circuit) according to an embodiment of the present disclosure. As shown, the transmitter 52 may receive outgoing data 60 to be transmitted via one or more antennas 55 in the form of a digital signal. A digital-to-analog converter (DAC) 62 of the transmitter 52 may convert the digital signal into an analog signal, and a modulator 64 may combine the converted analog signal with a carrier signal to generate a radio wave. A power amplifier (PA) 66 receives the modulated signal from the modulator 64. The power amplifier 66 may amplify the modulated signal to a suitable level to drive the transmission of the signal via one or more antennas 55. A filter 68 (e.g., a filter circuit and / or software) of the transmitter 52 may then remove unwanted noise from the amplified signal to generate a transmit signal 70 to be transmitted via one or more antennas 55. The filter 68 may include any suitable filter for removing unwanted noise from the amplified signal, such as a bandpass filter, a bandstop filter, a lowpass filter, a highpass filter, and / or a decimation filter.

[0045] The power amplifier 66 and / or the filter 68 may be referred to as part of a radio frequency front end (RFFE) (and more specifically, a transmit front end (TXFE) of the electronic device 10). In addition, the transmitter 52 may include any suitable additional components not shown, or may not include some of the components shown, so that the transmitter 52 can transmit the outgoing data 60 via one or more antennas 55. For example, the transmitter 52 may include a mixer and / or a digital upconverter. As another example, if the power amplifier 66 outputs an amplified signal within a desired frequency range or approximately within a desired frequency range (such that filtering the amplified signal may not be necessary), the transmitter 52 may not include the filter 68.

[0046] Figure 4 8 is a schematic diagram of a receiver 54 (e.g., receiving circuit) according to an embodiment of the present disclosure. As shown, the receiver 54 may receive a received signal 80 from one or more antennas 55 in the form of an analog signal. A low noise amplifier (LNA) 82 may amplify the received analog signal to a suitable level for processing by the receiver 54. A filter 84 (e.g., a filter circuit and / or software) may remove unwanted noise such as cross-channel interference from the received signal. The filter 84 may also remove additional signals received by one or more antennas 55 at a frequency different from the desired signal. The filter 84 may include one or more any suitable filters for removing unwanted noise or signals from the received signal, such as a bandpass filter, a bandstop filter, a low-pass filter, a high-pass filter, and / or a decimation filter. The low noise amplifier 82 and / or the filter 84 may be referred to as a part of the RFFE (and more specifically, the receiver front end (RXFE) of the electronic device 10).

[0047] The demodulator 86 may remove the RF carrier signal from the filtered signal and / or extract the demodulated signal (e.g., envelope signal) for processing. The analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert the signal into a digital signal of the incoming data 90 for further processing by the electronic device 10. In addition, the receiver 54 may include any suitable additional components not shown, or may not include some of the components shown, so that the receiver 54 can receive the received signal 80 via one or more antennas 55. For example, the receiver 54 may include a mixer and / or a digital down converter.

[0048] An electronic device 10 including a transceiver 30, a transmitter 52, a receiver 54, and / or an RFFE may include interconnects or routing in and / or between integrated circuits for performing or facilitating wireless communications. The interconnects may support multiple and / or different frequencies (e.g., multiple and / or different frequency bands) and may have different performance priorities. For example, a first interconnect coupling a first circuit and a second circuit may convey a signal of a first frequency, which may have a higher priority than a second interconnect coupling a first interconnect and a third circuit at a node conveying a signal of a second frequency. The first circuit, the second circuit, and the third circuit may include any circuit or functional block for facilitating radio frequency operations, such as RFFE components. These circuits may include any of the components discussed above that constitute the transceiver 30, the transmitter 52, and / or the receiver 54, as well as any other components that may facilitate wireless communications (e.g., amplifiers, power amplifiers, low noise amplifiers, DACs, ADCs, filters, mixers, digital upconverters, digital downconverters, modulators, demodulators, etc.). Specifically, the circuits may transmit or receive radio frequency signals (e.g., having a frequency between 3 kilohertz (kHz) and 300 GHz) between them through the interconnect. Thus, it may be desirable for the first interconnect to have better performance than the second interconnect. In some cases, the first interconnect may transmit signals having a frequency in one frequency band (e.g., in the 4G frequency band between 600 MHz and 2500 MHz, in the 5G frequency band between 450 MHz and 52.6 GHz, in the mmWave frequency range, etc.), while the second interconnect may transmit signals having a frequency in another frequency band. In other cases, the first interconnect and the second interconnect may transmit signals having a frequency in the same frequency band.

[0049] The switching circuit can be used to couple the first circuit to the second circuit or the third circuit, thus using the first interconnect or the second interconnect. For example, when it is desired to send a high priority signal between the first circuit and the second circuit, the first switch on the first interconnect can be activated or turned on to couple the first circuit to the second circuit, and the second switch on the second interconnect can be deactivated or turned off to decouple the third circuit from the first interconnect. In some embodiments, the length of the first interconnect may be greater than the length of the second interconnect. In addition, the first switch can be set to be closer to the node of the first interconnect and the second interconnect than the first circuit. For example, the first switch can be set within a threshold distance from the node, and the second switch can be set within a threshold distance from the first node. Therefore, when the second switch is deactivated, the load from the second switch is reduced or minimized, thereby providing a high or maximum non-operating path impedance, which prevents the signal from the third circuit from being transmitted to the first interconnect and thus transmitted to the second circuit. When it is desired to send a low priority signal over the second interconnect, the second switch on the second interconnect may be activated to couple the third circuit to the first interconnect and thus to the second circuit, while the first switch on the first interconnect may be deactivated to decouple the first circuit from the second circuit. However, when a high priority signal is sent over the first interconnect, the activated first switch may still provide a low or minimal operating path impedance that results in a non-zero power loss in the high priority signal (although less than the power loss when the first switch is deactivated).

[0050] Embodiments herein provide various interconnects or routes (e.g., between or within integrated circuits or chips) that reduce power loss in signals. To this end, embodiments disclosed herein include a first interconnect that does not include a switch between a first circuit (e.g., a first source circuit) and a second circuit (e.g., a target circuit). Therefore, the first interconnect may directly couple or connect the first circuit and the second circuit (e.g., without any intervening or intermediate components). The second interconnect may couple or connect a third circuit (e.g., a second source circuit) to the first interconnect via a first switch and thus couple or connect to the second circuit. A signal sent from the first circuit to the second circuit may have a higher priority and / or a different frequency than a signal sent from the third circuit to the second circuit. The first switch may be disposed near a first node of the first interconnect and the second interconnect (e.g., within a threshold distance from the first node). In addition, the first node may be disposed near the second circuit (e.g., within a threshold distance from the second circuit).

[0051] Figure 5A1 is a schematic diagram of a radio frequency (RF) circuit 100 of an electronic device 10 according to an embodiment of the present disclosure, the radio frequency (RF) circuit having: a first circuit 102 (e.g., a first source circuit "Block A"); a second circuit 104 (e.g., a destination circuit "Block B"), a third circuit 106 (e.g., a second source circuit "Block C"); a first interconnect 108, the first interconnect coupling the first circuit 102 and the second circuit 104; a second interconnect 110, the second interconnect coupling the third circuit 106 and the first interconnect 108 at a first node 112, wherein the first node 112 is located near the first circuit 102. The interconnects 108, 110 may include any suitable components of the communicatively coupled circuits of the electronic device 10, such as routing, routing paths, wires, conduits, metal traces, cables, etc., and may include single-ended or differential interconnects. Additionally, the first node 112 can be located within a threshold distance from the first circuit 102, such as within one or more centimeters (cm), within one or more millimeters (mm), within one or more micrometers (μm), within one or more nanometers (nm), etc. of the first circuit 102. In some implementations, the first node 112 can be within 20% or less, 10% or less, 5% or less, 2% or less, 1% or less, etc. of the length of the first interconnect 108 from the first circuit 102. This is to reduce or minimize reflections of signals sent from the third circuit 106 away from the first circuit 102 when the first circuit provides a high impedance, such as when the first circuit 102 is disabled or turned off.

[0052] The first switch 114 may be disposed on the second interconnect 110 to switch an operation mode of the RF circuit 100, for example, to switch between a first operation mode in which a signal (e.g., having a first priority or high priority) is sent from the first circuit 102 to the second circuit 104 through the first interconnect 108, and a second operation mode in which a signal (e.g., having a second priority or low priority) is sent from the third circuit 106 to the second circuit 104 through the second interconnect 110 and the first interconnect 108. The signal may be characterized as a high priority signal sent on the first interconnect 108 without a switch to reduce or minimize power loss (e.g., if a switch is disposed on the first interconnect 108, it may cause power loss). Therefore, the first interconnect 108 may be referred to as a direct, uninterrupted, continuous, continuous, solid and / or monolithic interconnect or coupling between the first circuit 102 and the second circuit 104 because there are no intervening or intermediate components between the first interconnect 108 and the first circuit 102 and the second circuit 104.

[0053] The signal may be of high priority because the processor 12 may determine or identify the signal as having a higher priority than, for example, a low priority signal sent from the third circuit 106 (or determine or identify the first circuit 102 as the entity or source sending the signal). The signal may be of low priority because the processor 12 may determine or identify the signal as having a lower priority than, for example, a high priority signal sent from the first circuit 102 (or determine or identify the third circuit 106 as the entity or source sending the signal). For example, the high priority signal may be associated with emergency services, voice calls, video streams, user data, configuration data, messaging services, video game streams, etc. The low priority signal may be associated with background services, non-critical applications, configuration data, messaging services, video game streams, etc. The high priority signal may have a frequency associated with a high priority or a frequency within a frequency range associated with a high priority (e.g., as identified or specified by the processor 12), and the low priority signal may have a frequency associated with a low priority or a frequency within a frequency range associated with a low priority (e.g., as identified or specified by the processor 12).

[0054] The first switch 114 can be disposed near the first node 112 to reduce or minimize high priority signals that are shunted from the first interconnect 108 and travel along the second interconnect 110 (e.g., when operating in the first operating mode). For example, the first switch 114 can be located within a threshold distance from the first node 112, such as within one or more cm, within one or more mm, within one or more um, within one or more nm, etc. of the first node 112. In some embodiments, the first switch 114 can be disposed within 20% or less, 10% or less, 5% or less, 2% or less, 1% or less, etc. of the length of the second interconnect 110 from the first node 112.

[0055] Figure 5B1 is a schematic diagram of an RF circuit 100 operating in a first mode to transmit a high priority signal 120 from a first circuit 102 to a second circuit 104 according to an embodiment of the present disclosure. As shown, in the first operating mode, the processor 12 may deactivate or turn off the first switch 114. The processor 12 may also activate or turn on the first circuit 102 to enable the first circuit 102 to transmit the high priority signal 120. It should be understood that activating the first circuit 102 may include powering on the first circuit 102, providing power to the first circuit 102, or activating a switching circuit that couples the first circuit to the first interconnect 108. In this manner, the high priority signal 120 may travel from the first circuit 102 to the second circuit 104 through the first interconnect 108 with reduced or minimized power loss due to the absence of a switching circuit disposed on the first interconnect 108. In addition, since the first switch 114 is disabled and disposed near the first node 112, it provides a high impedance 122 at the first switch 114 near the first node 112, thereby reducing or minimizing the path for the high priority signal 120 to travel on the second interconnect 110, blocking or preventing the high priority signal 120 from reaching the third circuit 106. The high impedance 122 can be any suitable impedance that blocks or prevents the high priority signal 120 from passing, such as 100 ohms or greater, 150 ohms or greater, 200 ohms or greater, 300 ohms or greater, 500 ohms or greater, etc.

[0056] Figure 5C 1 is a schematic diagram of an RF circuit 100 operating in a second mode to send a low priority signal 130 from a third circuit 106 to a second circuit 104 according to an embodiment of the present disclosure. As shown, in the second operating mode, the processor 12 may activate or turn on the first switch 114. The processor 12 may also deactivate or turn off the first circuit 102, thereby causing the first circuit 102 to provide a high impedance. It should be understood that deactivating the first circuit 102 may include powering off the first circuit 102, decoupling the first circuit 102 from a power source, or activating a switching circuit that couples the first circuit to the first interconnect 108. In this manner, the low priority signal 130 can travel from the third circuit 106 to the second circuit 104 through the second interconnect 110 and the first interconnect 108. Because the first circuit 102 is disabled and disposed near the first node 112 , its high impedance 132 can reduce or minimize a reflection path on the first interconnect 108 for the low priority signal 130 to travel, thereby reducing or minimizing any reflection of the low priority signal 130 to be received at the second circuit 104 .

[0057] Figure 61 is a flow chart of a method 140 for operating the RF circuit 100 to send a high priority signal (e.g., 120) and a low priority signal (e.g., 130) to the second circuit 104 according to an embodiment of the present disclosure. Any suitable device (e.g., a controller) that can control components of the electronic device 10 (such as the processor 12) can perform the method 140. In some embodiments, the method 140 can be implemented by using the processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium such as a memory 14 or a storage device 16. For example, the method 140 can be performed at least in part by one or more software components (such as an operating system of the electronic device 10, one or more software applications of the electronic device 10, etc.). Although the method 140 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps can be performed in an order different from the order shown, and that some described steps can be skipped or not performed at all.

[0058] In process block 142, the processor 12 receives an indication of the priority of the signal. Specifically, the processor 12 may intend to send the signal from the first circuit 102 or the third circuit 106 to the second circuit 104. In some embodiments, the processor 12 may receive an indication of the frequency of the signal and determine whether the signal frequency is within a frequency range (e.g., frequency band) associated with a high priority. Thus, the signal frequency may be within a 4G frequency band between 600 MHz and 2500 MHz, within a 5G frequency band between 450 MHz and 52.6 GHz, within a mmWave frequency range, etc. The signal may be transmitted by the transmitter 52 or received by the receiver 54.

[0059] In process block 144, the processor 12 determines whether the priority is a high priority. Specifically, the signal may be a high priority because the processor 12 may determine or identify the signal as having a higher priority than, for example, a low priority signal sent from the third circuit 106 (or determine or identify the first circuit 102 as the entity sending the signal). If the processor 12 determines that the priority is a high priority, then in process block 146, the processor 12 activates the first circuit 102 and deactivates the first switch 114 to decouple the third circuit 106 from the first interconnect 108. This may provide a lossless path for the high priority signal to travel from the first circuit 102 to the third circuit 106 (e.g., via the first interconnect 108 without the switch), wherein the high impedance 122 of the disabled switch 114 prevents the high priority signal from traveling to the third circuit 106. On the other hand, if the processor 12 determines that the signal frequency is not associated with a high priority, then in process block 148, the processor 12 deactivates the first circuit 102 and activates the first switch 114 to couple the third circuit 106 to the first interconnect 108. This can provide a path for low priority signals to travel from the third circuit 106 to the second circuit 104 (via the second interconnect 110 and the first interconnect 108) while reducing or minimizing reflections from the high impedance 132 of the deactivated first circuit 102. In this manner, the method 140 enables the processor 12 to operate the RF circuit 100 to send high priority signals (e.g., 120) and low priority signals (e.g., 130) to the second circuit 104.

[0060] In the case where the first circuit 102 and the third circuit 106 are disposed farther apart from each other (e.g., greater than 1 nm, greater than 1 um, greater than 1 mm, greater than 1 cm, etc.), excessive routing may be used for the second interconnect 110 because the first switch 114 and / or the first node 112 may be disposed near the first circuit 102 to reduce or minimize reflections of the low priority signal 130. An excessively long second interconnect 110 may result in excessive layout or integrated circuit area consumption.

[0061] Fig. 7A1 is a schematic diagram of an RF circuit 160 of an electronic device 10 according to an embodiment of the present disclosure, the RF circuit having: a first circuit 102; a second circuit 104; a third circuit 106; a first interconnect 108, the first interconnect coupling the first circuit 102 and the second circuit 104; a second interconnect 110, the second interconnect coupling the third circuit 106 and the first interconnect 108 at a first node 112, wherein the first node 112 is located near the second circuit 104; and a second switch 162, the second switch coupled to a ground potential 164, the first interconnect 108 at a second node 166 that is a quarter of a lambda length 168 away from the first node 112. As shown in the figure, the RF circuit 160 can avoid placing the first switch 114 and / or the first node 112 near the first circuit 102, and thus can avoid an excessively long second interconnect 110.

[0062] The quarter lambda length 168 is the quotient of the speed of the wave (e.g., the speed of light) of a signal (e.g., a low priority signal) traveling in the first interconnect 108 divided by the frequency of the signal. The quarter lambda length 168 can enable the low impedance provided by the second switch 162 and the ground potential 164 at the second node 166 to result in a high impedance at the first node 112 for a signal (e.g., a low priority signal) sent from the third circuit 106 to the second circuit 104, thereby at least partially blocking the signal from traveling to the first circuit 102 and / or the ground potential 164. The second switch 162 can be disposed near the second node 166. For example, the second switch 162 can be located within a threshold distance from the second node 166, such as within one or more cm, within one or more mm, within one or more um, within one or more nm, etc. of the second node 166. In some embodiments, the second switch 162 may be disposed within 20% or less, 10% or less, 5% or less, 2% or less, 1% or less, etc., of the length of the third interconnect 170 having the second switch 162 and the ground potential 164 from the second node 166.

[0063] Figure 7B1 is a schematic diagram of an RF circuit 160 operating in a first mode to send a high priority signal 120 from a first circuit 102 to a second circuit 104 according to an embodiment of the present disclosure. As shown, in the first operating mode, the processor 12 may disable or turn off the first switch 114 and the second switch 162. In this way, the high priority signal 120 may travel from the first circuit 102 to the second circuit 104 through the first interconnect 108, with reduced or minimized power loss due to the lack of a switching circuit on the first interconnect 108. In addition, since the first switch 114 is disabled and disposed near the first node 112, it provides a high impedance at the first switch 114 near the first node 112, thereby reducing or minimizing the path on the second interconnect 110 for the high priority signal 120 to travel, blocking or preventing the high priority signal 120 from reaching the third circuit 106. Similarly, because the second switch 162 is disabled and set near the second node 166, it provides a high impedance at the second switch 162 near the second node 166, thereby reducing or minimizing the path for the high priority signal 120 to travel on the third interconnect 170, blocking or preventing the high priority signal 120 from reaching the ground potential 164.

[0064] Figure 7C 1 is a schematic diagram of an RF circuit 160 operating in a second mode to send a low priority signal 130 from a third circuit 106 to a second circuit 104 according to an embodiment of the present disclosure. As shown, in the second operating mode, the processor 12 may activate or turn on the first switch 114 and the second switch 162. In this manner, the low priority signal 130 may travel from the third circuit 106 to the second circuit 104 via the second interconnect 110 and the first interconnect 108. In addition, the second switch 162 and the ground potential 164 may provide a low impedance at a second node 166 that is a quarter lambda length 168 away from the first node 112, thereby providing a high impedance 180 at the first node 112, thereby at least partially blocking the low priority signal 130 from traveling to the first circuit 102 and / or the ground potential 164.

[0065] Figure 81 is a flow chart of a method 190 for operating RF circuit 160 to send a high priority signal (e.g., 120) and a low priority signal (e.g., 130) to second circuit 104 according to an embodiment of the present disclosure. Any suitable device (e.g., a controller) that can control components of electronic device 10 (such as processor 12) can perform method 190. In some embodiments, method 190 can be implemented by using processor 12 to execute instructions stored in a tangible, non-transitory computer-readable medium (such as memory 14 or storage device 16). For example, method 190 can be performed at least in part by one or more software components (such as an operating system of electronic device 10), one or more software applications of electronic device 10, etc. Although method 190 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the described steps can be performed in an order different from the order shown, and that some of the described steps can be skipped or not performed at all.

[0066] In process block 142, the processor 12 receives an indication of the priority of the signal. In process block 144, the processor 12 determines whether the priority is associated with a high priority. In some embodiments, the processor 12 may determine whether the signal frequency is within a frequency range (e.g., a frequency band) associated with a high priority. If the processor 12 determines that the signal frequency is associated with a high priority, then in process block 192, the processor 12 disables the first switch 114 to decouple the third circuit 106 from the first interconnect 108, and disables the second switch 162 to decouple the ground potential 164 from the first interconnect 108. This can provide a lossless path for the high priority signal to travel from the first circuit 102 to the third circuit 106 (e.g., via the first interconnect 108 without a switch), wherein the high impedance of the disabled first switch 114 prevents the high priority signal from traveling to the third circuit 106, and the high impedance of the disabled second switch 162 prevents the high priority signal from traveling to the ground potential 164. On the other hand, if the processor 12 determines that the signal frequency is not associated with a high priority, then in process block 194, the processor 12 activates the first switch 114 to couple the third circuit 106 to the first interconnect 108, and activates the second switch 162 to couple the ground potential 164 to the first interconnect 108. This can provide a path for low priority signals to travel from the third circuit 106 to the second circuit 104 (via the second interconnect 110 and the first interconnect 108), while the second switch 162 and the ground potential 164 provide a high impedance 180 at the first node 112 (e.g., by providing a low impedance at the second node 166 that is one-quarter lambda length 168 away from the first node 112) to at least partially block the low priority signals from traveling to the first circuit 102 and / or the ground potential 164. In this manner, the method 190 enables the processor 12 to operate the RF circuit 160 to send high priority signals (e.g., 120) and low priority signals (e.g., 130) to the second circuit 104.

[0067] It should be noted that the performance of the high impedance blocking of the second switch 162 and the ground potential 164 may depend on the frequency of the low priority signal 130, because the quarter lambda length 168 is the quotient of the speed of the wave (e.g., the speed of light) of the signal (e.g., the low priority signal) traveling in the first interconnect 108 divided by the frequency of the signal. That is, if the frequency range of the low priority signal 130 generated or transmitted by the third circuit 106 is large (e.g., the low priority signal 130 has a wide bandwidth or may be included in different frequency bands over time), the equation sufficient to express the quarter lambda length 168 in frequency may not be satisfied, and the low priority signal 130 may not be effectively blocked, which may result in degradation of the low priority signal 130.

[0068] Fig. 9A1 is a schematic diagram of an RF circuit 200 of an electronic device 10 according to an embodiment of the present disclosure, the RF circuit having: a first circuit 102; a second circuit 104; a third circuit 106; a first interconnect 108, the first interconnect coupling the first circuit 102 and the second circuit 104; a second interconnect 110, the second interconnect coupling the third circuit 106 and the first interconnect 108 at a first node 112, wherein the first node 112 is located near the second circuit 104; and a second switch 162, the second switch coupled to the resistor 202, the ground potential 164 and the first interconnect 108 at a second node 166. There may be no limitation or requirement on the distance between the second node 166 and the first node 112, and more significantly, the distance does not depend on the frequency of the signal (e.g., the low priority signal) traveling on the first interconnect 108. This may enable the second circuit 104 and the third circuit 106 to operate with a wider bandwidth, and enable the low priority signal sent from the third circuit 106 to have a higher bandwidth than, for example, Fig. 7A The RF circuit 160 has a wider bandwidth.

[0069] and Fig. 7A As with the RF circuit 160 of FIG. 1 , the second switch 162 may be disposed near the second node 166. In addition, the second node 166 may be disposed near the first circuit 102. For example, the second node 166 may be located within a threshold distance from the first circuit 102, such as within one or more cm, within one or more mm, within one or more um, within one or more nm, etc. of the second node 166. In some embodiments, the second node 166 may be disposed on the first interconnect 108 within 20% or less, 10% or less, 5% or less, 2% or less, 1% or less, etc. of the length of the first interconnect 108 from the first circuit 102. The second switch 162 and the resistor 202 (e.g., one or more resistive elements, such as resistors) may have a combined resistance (referred to as the termination resistor 204) that is equal to or approximately equal to the characteristic impedance of the first interconnect 108. In some embodiments, the termination resistor 204 may include a combined resistance of the resistance of the second switch 162, the resistor 202, and any parasitic resistance associated with the termination resistor 204. For example, the terminal resistor 204 may include 20 ohms or less, 30 ohms or less, 50 ohms or less, 70 ohms or less, 100 ohms or less, 200 ohms or less, 500 ohms or less, 500 ohms or more, etc., such as 50 ohms. Since the terminal resistor 204 does not change with frequency, the second circuit 104 and the third circuit 106 can operate with a wider bandwidth and enable a low priority signal sent from the third circuit 106 to have a higher bandwidth than, for example, Fig. 7AThe third circuit 106 may include a plurality of functional blocks (e.g., circuits and / or components) operating at different frequencies and / or different frequency bands. The resistor 202 may include any suitable resistive element that, in combination with the second switch 162, provides a resistance that is equal to or approximately equal to the characteristic impedance of the first interconnect 108. For example, the resistor 202 may include a metal resistor.

[0070] Fig. 9B 1 is a schematic diagram of an RF circuit 200 operating in a first mode to transmit a high priority signal 120 from a first circuit 102 to a second circuit 104 according to an embodiment of the present disclosure. As shown, in the first operating mode, the processor 12 may deactivate or turn off the first switch 114 and the second switch 162. The processor 12 may also activate or turn on the first circuit 102 to enable the first circuit 102 to transmit the high priority signal 120. In this manner, the high priority signal 120 may travel from the first circuit 102 to the second circuit 104 through the first interconnect 108, with reduced or minimized power loss due to the absence of a switching circuit on the first interconnect 108. In addition, since the first switch 114 is deactivated and disposed near the first node 112, it provides a high impedance at the first switch 114 near the first node 112, thereby reducing or minimizing the path for the high priority signal 120 to travel on the second interconnect 110, blocking or preventing the high priority signal 120 from reaching the third circuit 106. Similarly, because the second switch 162 is disabled and set near the second node 166, it provides a high impedance at the second switch 162 near the second node 166, thereby reducing or minimizing the path for the high priority signal 120 to travel on the third interconnect 170 having the second switch 162, the resistor 202 and the ground potential 164, blocking or preventing the high priority signal 120 from reaching the resistor 202 and the ground potential 164.

[0071] Fig. 9C1 is a schematic diagram of an RF circuit 200 operating in a second mode to send a low priority signal 130 from a third circuit 106 to a second circuit 104 according to an embodiment of the present disclosure. As shown, in the second operating mode, the processor 12 may activate or turn on the first switch 114 and the second switch 162. The processor 12 may also deactivate or turn off the first circuit 102, thereby causing the first circuit 102 to provide a high impedance. Therefore, the low priority signal 130 may be split at the first node 112 into a first portion 210 that travels toward and is received by the second circuit 104 and a second portion 212 that travels toward the first circuit 102. Since the second switch 162 is activated, the second portion 212 of the low priority signal 130 may be absorbed by the terminal resistor 204, thereby reducing or minimizing any reflection of the low priority signal 130 to be received at the second circuit 104, rather than being reflected back to the second circuit 104 due to encountering the first circuit 102. In some cases, the second portion 212 of the low priority signal 130 may result in reduced or minimal power loss (e.g., 3 decibels (dB) or less) to the signal 130, as evidenced in the first portion 210 of the low priority signal 130. In this manner, the low priority signal 130 may travel from the third circuit 106 to the second circuit 104 via the second interconnect 110 and the first interconnect 108.

[0072] Fig.10 1 is a flow chart of a method 220 for operating the RF circuit 200 to send a high priority signal (e.g., 120) and a low priority signal (e.g., 130) to the second circuit 104 according to an embodiment of the present disclosure. Any suitable device (e.g., a controller) that can control components of the electronic device 10 (such as the processor 12) can perform the method 220. In some embodiments, the method 220 can be implemented by using the processor 12 to execute instructions stored in a tangible non-transitory computer-readable medium (such as the memory 14 or the storage device 16). For example, the method 220 can be performed at least in part by one or more software components (such as an operating system of the electronic device 10), one or more software applications of the electronic device 10, etc. Although the method 220 is described using a particular order of steps, it should be understood that the present disclosure contemplates that the steps described can be performed in an order different from the order shown, and that some of the described steps can be skipped or not performed at all.

[0073] In process block 142, the processor 12 receives an indication of the priority of the signal. In process block 144, the processor 12 determines whether the priority is a high priority. In some embodiments, the processor 12 may determine whether the signal frequency is within a frequency range (e.g., a frequency band) associated with a high priority. If the processor 12 determines that the signal frequency is associated with a high priority, then in process block 222, the processor 12 activates the first circuit 102, deactivates the first switch 114 to decouple the third circuit 106 from the first interconnect 108, and deactivates the second switch 162 to decouple the terminal resistor 204 from the first interconnect 108. This can provide a path with reduced or minimal loss for the high priority signal to travel from the first circuit 102 to the third circuit 106 (e.g., via the first interconnect 108 without a switch), wherein the high impedance of the disabled first switch 114 prevents the high priority signal from traveling to the third circuit 106, and the high impedance of the disabled second switch 162 prevents the high priority signal from traveling to the terminal resistor 204. On the other hand, if the processor 12 determines that the signal frequency is not associated with a high priority, then in process block 224, the processor 12 deactivates the first circuit 102, activates the first switch 114 to couple the third circuit 106 to the first interconnect 108, and activates the second switch 162 to couple the termination resistor 204 to the first interconnect 108. This may provide a path for a first portion (e.g., 210) of the low priority signal shunted from the first node 112 to travel from the third circuit 106 to the second circuit 104 (via the second interconnect 110 and the first interconnect 108), while the second switch 162 and the termination resistor 204 absorb a second portion (e.g., 212) of the low priority signal shunted from the first node 112 to reduce reflections of, minimize, or prevent the second portion of the low priority signal from reaching the second circuit 104. In this manner, the method 220 enables the processor 12 to operate the RF circuit 160 to send high priority signals (eg, 120 ) and low priority signals (eg, 130 ) to the second circuit 104 .

[0074] Although the above-described embodiments include coupling three circuits (e.g., 102, 104, 106) or functional blocks together via two interconnects (e.g., 108, 110), it should be understood that they may be applied to any suitable number of circuits or functional blocks (e.g., more than three circuits or functional blocks, more than five circuits or functional blocks, more than ten circuits or functional blocks, etc.). Fig.11is a schematic diagram of an RF circuit 230 according to an embodiment of the present disclosure, the RF circuit having: a first circuit 102; a second circuit 104; a third circuit 106; a fourth circuit 232; a first interconnect 108, the first interconnect coupling the first circuit 102 and the second circuit 104; a second interconnect 110, the second interconnect coupling the third circuit 106 and the first interconnect 108 at a first node 112; a third interconnect 170, the third interconnect having a second switch 162, the second switch coupled to a resistor 202, a ground potential 164 and the first interconnect 108 at a second node 166; and a fourth interconnect 234, the fourth interconnect coupling the fourth circuit 232 and the first interconnect 108 at a third node 236, wherein the first node 112 and the third node 236 are located near the second circuit 104.

[0075] As with the second interconnect 110, the fourth interconnect 234 may include a third switch 238, which may be disposed near the third node 236. For example, the third switch 238 may be located within a threshold distance from the third node 236, such as within one or more cm, within one or more mm, within one or more um, within one or more nm, etc. of the third node 236. In some embodiments, the second switch 162 may be disposed within 20% or less, 10% or less, 5% or less, 2% or less, 1% or less, etc. of the length of the fourth interconnect 234 from the third node 236. This may reduce or minimize the path on the fourth interconnect 234 for high priority signals sent from the first circuit 102 to travel along the fourth interconnect 234 when the third switch 238 is disabled or disconnected, thereby providing high impedance.

[0076] In addition, like the second node 166, the third node 236 can be disposed near the second circuit 104. For example, the third node 236 can be located within a threshold distance from the second circuit 104, such as within one or more cm, within one or more mm, within one or more um, within one or more nm, etc. of the second circuit 104. In some embodiments, the third node 236 can be disposed within 20% or less, 10% or less, 5% or less, 2% or less, 1% or less, etc. of the length of the fourth interconnect 234 of the second circuit 104.

[0077] Similar to Fig. 9AIn the RF circuit 200, when the first circuit 102 operates in the first mode to transmit a high priority signal (e.g., 120) from the first circuit 102 to the second circuit 104, the processor 12 may deactivate or turn off the first switch 114, the second switch 162, and the third switch 238. The processor 12 may also activate or turn on the first circuit 102 to enable the first circuit 102 to transmit the high priority signal 120. In this manner, the high priority signal 120 may travel from the first circuit 102 to the second circuit 104 through the first interconnect 108 with reduced or minimized power loss due to the absence of a switching circuit on the first interconnect 108. In addition, since the first switch 114 and the third switch 238 are disabled and disposed near the first node 112 and the third node 236, respectively, the switches 114 and 238 provide high impedance at the first switch 114 and the third switch 238 near the first node 112 and the third node 236, respectively, thereby reducing or minimizing the path for the high priority signal 120 to travel on the second interconnect 110 or the fourth interconnect 234, and blocking or preventing the high priority signal 120 from reaching the third circuit 106 or the fourth circuit 232. Similarly, since the second switch 162 is disabled and disposed near the second node 166, it provides high impedance at the second switch 162 near the second node 166, thereby reducing or minimizing the path for the high priority signal to travel on the third interconnect 170 having the second switch 162, the resistor 202, and the ground potential 164, and blocking or preventing the high priority signal 120 from reaching the resistor 202 and the ground potential 164.

[0078] When operating in the second mode to send a low priority signal (e.g., 130) from the third circuit 106 to the second circuit 104, the processor 12 may activate or turn on the first switch 114 and the second switch 162. The processor 12 may also deactivate or turn off the first circuit 102 and deactivate or turn off the third switch 238, so that the first circuit 102 and the third switch 238 provide a high impedance. Therefore, the low priority signal 130 may be split at the first node 112 into a first portion (e.g., 210) that travels toward and is received by the second circuit 104 and a second portion (e.g., 212) that travels toward the first circuit 102. Since the second switch 162 is activated, the second portion 212 of the low priority signal 130 may be absorbed by the terminal resistor 204, thereby reducing or minimizing any reflection of the low priority signal 130 to be received at the second circuit 104, rather than being reflected back to the second circuit 104 due to encountering the first circuit 102. In this manner, the low priority signal 130 may travel from the third circuit 106 to the second circuit 104 through the second interconnect 110 and the first interconnect 108 .

[0079] When operating in the third mode to send the second low priority signal from the fourth circuit 232 to the second circuit 104, the processor 12 may activate or turn on the third switch 238 and the second switch 162. The processor 12 may also deactivate or turn off the first circuit 102 and deactivate or turn off the first switch 114, so that the first circuit 102 and the third switch 114 provide a high impedance. Therefore, the second low priority signal may be split at the first node 112 into a first portion that travels toward and is received by the second circuit 104 and a second portion that travels toward the first circuit 102. Since the second switch 162 is activated, the second portion of the second low priority signal may be absorbed by the terminal resistor 204, thereby reducing or minimizing any reflection of the second low priority signal to be received at the second circuit 104, rather than being reflected back to the second circuit 104 due to encountering the first circuit 102. In this way, the second low priority signal can travel from the fourth circuit 232 to the second circuit 104 through the fourth interconnect 234 and the first interconnect 108. Furthermore, by being insensitive to or independent of the frequency of the transmitted signal, the third circuit 106 and the fourth circuit 232 can operate at different frequencies or provide a wide bandwidth of operating frequencies (thus transmitting signals of different and varying frequencies through the second interconnect 110 and the fourth interconnect 234). It should be understood that similar to the third circuit 106 and the fourth circuit 232, any number of additional circuits can be added on the corresponding interconnects (e.g., 110, 234) with corresponding switches (114, 238), and when in operation, the processor 12 can activate the corresponding switch of the termination resistor 204 and the second switch 162 while deactivating all other non-operating path switches, as described above with respect to the third circuit 106 and the fourth circuit 232.

[0080] Fig.12 is a schematic diagram of an RF circuit 250 according to an embodiment of the present disclosure, the RF circuit having: a first circuit 102; a second circuit 104; a third circuit 106; a fourth circuit 232; a first interconnect 108, which couples the first circuit 102 and the second circuit 104; a second interconnect 110, which couples a third switch 252 and the first interconnect 108 at a first node 112; a third interconnect 170, which has a second switch 162, which is coupled to a resistor 202, a ground potential 164 and the first interconnect 108 at a second node 166; and a third switch 252, which couples the third circuit 106 and the fourth circuit 232 to the second interconnect 110.

[0081] In some embodiments, the third switch 252 may be a multi-way switch, which is illustrated as a two-way switch because it is coupled to two circuits 106, 232. Fig. 9AThe RF circuit 200 operates in a similar manner, except that when operating in the second operating mode when a low priority signal (e.g., 130) is sent from the third circuit 106 to the second circuit 104, or when operating in the third operating mode when a second low priority signal is sent from the fourth circuit 232 to the second circuit 104, the processor 12 can operate the third switch 252 to couple to the source circuit (e.g., a source that sends a signal to the second circuit 104, the third circuit 106 for the second operating mode, or the fourth circuit 232 for the third operating mode). Fig.11 As with the RF circuit 230, it should be understood that in this case any number of additional circuits may be added by coupling one or more additional circuits to the multi-way switch 252 and operating the third switch 252 to couple to the source circuit.

[0082] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments may allow for various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0083] The technology presented and claimed herein is cited and applied to specific examples of a physical and practical nature that significantly improves the art and is therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended at the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements should not be interpreted in accordance with 35 U.S.C. 112(f).

[0084] It is understood that the use of personally identifiable information should be subject to privacy policies and practices that are generally recognized to meet or exceed industry or government requirements for maintaining user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of the authorized use should be clearly stated to users.

Claims

1. A radio frequency circuit, comprising: First Circuit; Second Circuit; a first interconnect coupling the first circuit to the second circuit, wherein the first interconnect is continuous; Third Circuit; and A second interconnect couples the third circuit to the first interconnect via a first switch.

2. The radio frequency circuit according to claim 1, wherein the first circuit, the second circuit or the third circuit comprises an amplifier, a digital-to-analog converter, an analog-to-digital converter, a filter, a mixer, a digital up-converter, a digital down-converter, a modulator or a demodulator.

3. The RF circuit of claim 1 , wherein the first interconnect is configured to transmit a first signal having a first frequency from the first circuit to the second circuit, and the second interconnect is configured to transmit a second signal having a second frequency from the third circuit to the second circuit.

4. The radio frequency circuit of claim 1, wherein the second interconnect is coupled to the first interconnect at a junction that is within 5% of a length of the first interconnect from the second circuit.

5. The radio frequency circuit of claim 1, wherein the resistive element is coupled to a second switch, and the second switch is coupled to the first interconnect.

6. The radio frequency circuit of claim 5, wherein a combined resistance of the second switch and the resistive element is equal to a characteristic impedance of the first interconnect.

7. The radio frequency circuit of claim 5, wherein the second switch is coupled to the first interconnect at a node that is within 5% of a length of the first interconnect from the first circuit.

8. A tangible, non-transitory computer-readable medium storing instructions that cause a processing circuit to: receiving an indication of a frequency of a signal to be sent from a first circuit to a second circuit through a first interconnect or from a third circuit to the second circuit through a second interconnect and the first interconnect; deactivating a first switch coupling the third circuit to the first interconnect and deactivating a second switch coupling a third interconnect to the first interconnect based on the frequency being associated with the priority; as well as The first switch is activated based on the frequency not being associated with the priority and the second switch is activated.

9. The tangible, non-transitory computer readable medium of claim 8, wherein a ground potential is coupled to the second switch on the third interconnect.

10. The tangible, non-transitory computer readable medium of claim 9, wherein the second interconnect is coupled to the first interconnect at a first node, the third interconnect is coupled to the first interconnect at a second node, and based on the frequency, the second node is one quarter lambda length away from the first node.

11. The tangible, non-transitory computer readable medium of claim 10, wherein the second switch and the ground potential provide a lower impedance at the second node and a higher impedance at the first node.

12. The tangible, non-transitory computer readable medium of claim 8, wherein the instructions cause the processing circuit to activate the first circuit based on the frequency being associated with the priority.

13. The tangible, non-transitory computer-readable medium of claim 8, wherein the instructions cause the processing circuit to: deactivate the first circuit based on the frequency not being associated with the priority.

14. The tangible, non-transitory computer readable medium of claim 8, wherein the priority is a high priority.

15. An electronic device, comprising: one or more antennas; and a transceiver coupled to the one or more antennas, the transceiver comprising: First circuit, Second circuit, A first interconnect coupling the first circuit to the a second circuit, wherein the first interconnect is configured to transmit a first signal of a first frequency from the first circuit to the second circuit, The third circuit, and A second interconnect couples the third circuit to the first interconnect via a first switch, wherein the second interconnect is configured to transmit a second signal at a second frequency from the third circuit to the second circuit.

16. The electronic device of claim 15, wherein the first interconnect does not include switching circuitry. 17 . The electronic device of claim 15 , wherein the first switch is configured to be disabled to send the first signal from the first circuit to the second circuit. 18 . The electronic device of claim 15 , wherein the first circuit is configured to activate to send the first signal from the first circuit to the second circuit.

19. The electronic device of claim 15, wherein the first switch is configured to activate to send the second signal from the third circuit to the second circuit. 20 . The electronic device of claim 15 , wherein the first circuit is configured to be disabled to send the second signal from the third circuit to the second circuit.

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