Semiconductor device and electronic apparatus

Abstract

The invention provides a semiconductor device and an electronic apparatus. The semiconductor device includes: a test signal generation circuit that modulates a test signal in a second operation mode to generate a third modulated signal and a fourth modulated signal; an amplifier circuit that, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to a first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to a second output terminal; a peak frequency detection circuit that measures the potential difference between the first output terminal and the second output terminal in the second operation mode, and detects a peak frequency at which the impedance of the sound reproduction device peaks; and a determination circuit that determines, in the second operation mode, whether or not the peak frequency is included in a reference frequency range determined on the basis of the frequency band of the test signal and temperature information of the sound reproduction device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic device. Background Art

[0002] Patent document 1 describes a speaker failure notification device that measures impedance that changes with structural changes in the speaker through a control unit, determines whether the measured impedance is within a specified range, and notifies the speaker of a failure if the impedance is determined to be outside the range.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2012-199854

[0004] In the speaker failure notification device described in Patent Document 1, it is determined whether the measured impedance is within a predetermined range. Therefore, if the impedance of the speaker changes due to temperature changes, there is a possibility that the speaker failure cannot be accurately determined. Summary of the invention

[0005] One embodiment of the semiconductor device of the present invention comprises: a first output terminal connected to a first terminal of a sound reproduction device; a second output terminal connected to a second terminal of the sound reproduction device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulation signal and a second modulation signal; a test signal generation circuit that modulates a test signal whose frequency is changed in a preset frequency band in a second operation mode to generate a third modulation signal and a fourth modulation signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to the first output terminal in the first operation mode, and outputs a second amplified signal obtained by amplifying the second modulation signal to the second output terminal. 2 amplified signal, outputting a third amplified signal obtained by amplifying the third modulated signal to the first output terminal in the second operation mode, and outputting a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit, measuring a potential difference between the first output terminal and the second output terminal in the second operation mode, detecting a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproducing device reaches a peak value; and a determination circuit, determining in the second operation mode whether the peak frequency is included in a reference frequency range, the reference frequency range being determined based on the frequency band of the test signal and temperature information, which is information related to the temperature of the sound reproducing device.

[0006] Another aspect of the semiconductor device of the present invention is connected to a sound source reproduction circuit, the sound source reproduction circuit comprising: an input terminal; a modulation circuit that modulates a signal input to the input terminal and outputs a first modulation signal and a second modulation signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to a first terminal of a sound reproduction device, and outputs a second amplified signal obtained by amplifying the second modulation signal to a second terminal of the sound reproduction device, the semiconductor device comprising: a first input terminal connected to the first terminal of the sound reproduction device; a second input terminal connected to the second terminal of the sound reproduction device; an output terminal connected to the input terminal of the sound source reproduction circuit; and a switch that operates in a first operation mode. In the second operation mode, a signal based on a sound source signal is output to the output terminal, and in the second operation mode, a test signal whose frequency is changed in a preset frequency band is output to the output terminal; a test signal generating circuit, which outputs the test signal to the switch in the second operation mode; a peak frequency detecting circuit, which measures the potential difference between the first input terminal and the second input terminal in the second operation mode, and detects the frequency of the test signal at which the impedance of the sound reproduction device reaches a peak, i.e., the peak frequency; and a determination circuit, which determines in the second operation mode whether the peak frequency is included in a reference frequency range, wherein the reference frequency range is determined based on the frequency band of the test signal and information related to the temperature of the sound reproduction device, i.e., temperature information.

[0007] One embodiment of an electronic device according to the present invention includes one embodiment of the semiconductor device and the sound reproduction device.

[0008] Another embodiment of the electronic device of the present invention comprises: a first output terminal connected to a first terminal of a sound reproduction device; a second output terminal connected to a second terminal of the sound reproduction device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulation signal and a second modulation signal, and modulates a test signal whose frequency is changed in a predetermined frequency band in a second operation mode to output a third modulation signal and a fourth modulation signal; a test signal generating circuit that outputs the test signal to the modulation circuit in the second operation mode; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to the first output terminal in the first operation mode, and outputs a first amplified signal obtained by amplifying the first modulation signal to the second output terminal. a second amplified signal obtained by amplifying the second modulated signal, outputting a third amplified signal obtained by amplifying the third modulated signal to the first output terminal in the second operation mode, and outputting a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit which measures a potential difference between the first output terminal and the second output terminal in the second operation mode, and detects a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproduction device reaches a peak value; and a determination circuit which determines whether the peak frequency is included in a reference frequency range in the second operation mode, the reference frequency range being determined based on the frequency band of the test signal and information related to the temperature of the sound reproduction device, i.e., temperature information. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a diagram showing a structural example of a semiconductor device according to the first embodiment.

[0010] Figure 2 This is a diagram showing an example of pulse width modulation for generating the modulation signal DOP.

[0011] Figure 3 FIG. 1 is a diagram showing an example of pulse width modulation for generating the modulation signal DON.

[0012] Figure 4 This is a diagram showing an example of the difference between the modulation signal DOP and the modulation signal DON.

[0013] Figure 5 This is a diagram showing an example of the relationship between the state of a speaker and the impedance characteristics.

[0014] Figure 6 This is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and its peripheral circuits.

[0015] Figure 7 This is a diagram showing a configuration example of a class D amplifier, a peak frequency detection circuit, and its peripheral circuits.

[0016] Figure 8 A diagram showing a configuration example of a differential low-pass filter.

[0017] Fig. 9 This is a diagram showing an example of the relationship between a test signal, a peak frequency, and a peak voltage.

[0018] Fig.10 It is a graph showing the temperature dependence of peak impedance and peak frequency.

[0019] Fig.11 This is a diagram showing the temperature dependency of the waveform of the output voltage of the differential low-pass filter.

[0020] Fig.12 This is a flowchart showing an example of a processing procedure of the inspection circuit in the calibration mode in the first embodiment.

[0021] Fig.13 This is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the first embodiment.

[0022] Fig.14 This is a diagram showing an example of a method of calculating the peak frequency and the peak voltage in the first embodiment.

[0023] Fig.15 This is a graph showing the relationship between temperature and peak frequency.

[0024] Fig.16 This is a graph showing the relationship between temperature and peak impedance.

[0025] Fig.17 This is a flowchart showing an example of a processing procedure of the inspection circuit in the calibration mode in the second embodiment.

[0026] Fig.18 This is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the second embodiment.

[0027] Fig.19 This is a diagram showing an example of a plurality of frequency blocks and a reference frequency block in the third embodiment.

[0028] Fig. 20 This is a flowchart showing an example of a processing procedure of the inspection circuit in the calibration mode in the third embodiment.

[0029] Fig.21 This is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the third embodiment.

[0030] Fig. 22 This is a diagram showing an example of a plurality of frequency blocks and a reference frequency block in the fourth embodiment.

[0031] Fig.23 This is a flowchart showing an example of a processing procedure of the inspection circuit in the calibration mode in the fourth embodiment.

[0032] Fig.24 This is a flowchart showing an example of a processing procedure of the inspection circuit in the inspection mode in the fourth embodiment.

[0033] Fig.25 It is a diagram showing a structural example of a semiconductor device according to a fifth embodiment.

[0034] Fig.26 FIG. 1 is a diagram showing another example of pulse width modulation for generating the modulation signal DON.

[0035] Fig. 27 This is a diagram showing another example of the difference between the modulation signal DOP and the modulation signal DON.

[0036] Fig.28 This is a functional block diagram of the electronic device according to this embodiment.

[0037] Fig.29 This is a diagram showing a configuration example of a warning device as an example of an electronic device.

[0038] Fig.30 It is a diagram showing a configuration example of an electronic device according to a modified example.

[0039] Description of symbols

[0040] 1: semiconductor device; 2: microcontroller unit; 3, 3-1 to 3-m: sound reproduction device; 10: communication interface circuit; 20: memory; 21-1 to 21-n: sound source data; 30: modulation circuit; 31: digital filter; 32: Σ-Δ modulation circuit; 33: pulse width modulation circuit; 41: switch; 42: switch; 50: amplifier circuit; 51P, 51N: class D amplifier; 60: test signal generation circuit; 61: determination circuit; 62: memory; 70: peak frequency detection circuit; 71: differential low-pass filter; 72: A / D conversion circuit; 73: peak time measurement circuit; 80 : Temperature sensor; 81: Switch; 82: Switch; 91: Output terminal; 92: Output terminal; 100: Sound source reproduction circuit; 110: Inspection circuit; 201-1~201-n: Inverter circuit; 202-1~202-n: Inverter circuit; 211: Operational amplifier; 212, 213, 214: Resistor; 215: Capacitor; 216: Resistor; 217: Capacitor; 218: Resistor; 219: Capacitor; 300: Electronic device; 300A: Warning device; 310: Processing unit; 320: Operation unit; 330: Storage unit; 340: Display unit; 400: Vehicle. DETAILED DESCRIPTION

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the structures described below are necessarily essential components of the present invention.

[0042] 1. Semiconductor devices

[0043] 1-1. First Embodiment

[0044] 1-1-1. Structure of semiconductor device

[0045] Figure 1 FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment. Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a communication interface circuit 10, a memory 20, a temperature sensor 80, switches 81 and 82, a sound source reproducing circuit 100, and a test circuit 110. The semiconductor device 1 is connected to a sound reproducing device 3. The semiconductor device 1 may be a semiconductor integrated circuit device of one chip, may be composed of semiconductor integrated circuit devices of multiple chips, and may be composed of at least a part of electronic components other than semiconductor integrated circuit devices.

[0046] The semiconductor device 1 has three operation modes: a normal operation mode, a test mode, and a calibration mode. The normal operation mode is an operation mode in which the sound reproduction device 3 reproduces sound. The test mode is an operation mode in which the state of the sound reproduction device 3 is determined. The calibration mode is a mode in which information required for determining the state of the sound reproduction device 3 is generated.

[0047] The memory 20 stores n sound source data 21-1 to 21-n. n is an integer greater than 1. The memory 20 may be, for example, a flash memory. The sound source data 21-1 to 21-n may be, for example, sound data after pulse code modulation or sound data after adaptive differential pulse code modulation. The sound source data 21-1 to 21-n may be, for example, data that is the basis of various sounds such as sounds obtained by imitating the sound of a person speaking, mechanical warning sounds, and effect sounds.

[0048] The communication interface circuit 10 is a circuit for data communication with the micro control unit 2. The communication interface circuit 10 may be, for example, an SPI interface circuit or an I2C interface circuit. SPI is the abbreviation of Serial Peripheral Interface, and I2C is the abbreviation of Inter-Integrated Circuit.

[0049] The communication interface circuit 10 receives various commands sent from the micro control unit 2, and generates various control signals corresponding to the received commands. For example, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the normal operation mode, the inspection mode, or the calibration mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 41, 42, 81, and 82 according to the operation mode. In addition, for example, when the communication interface circuit 10 receives a sound source reproduction command for causing the sound reproduction device 3 to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 as the sound source signal DI and inputs it to the sound source reproduction circuit 100, and instructs the sound source reproduction circuit 100 to reproduce by the sound reproduction device 3. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. In addition, for example, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i being reproduced, the communication interface circuit 100 instructs the sound source reproduction circuit 100 to stop the reproduction. Furthermore, for example, when receiving various setting commands related to sound source reproduction, the communication interface circuit 10 performs various settings on the sound source reproduction circuit 100 .

[0050] In this embodiment, the sound source signal DI input to the sound source reproduction circuit 100 is a pulse code modulated signal. When the sound source data 21-1 to 21-n are compressed sound data or sound data after adaptive differential pulse code modulation, the sound source data 21-i to be reproduced is converted into the sound source signal DI as a pulse code modulated signal by a decoder (not shown).

[0051] The sound source reproducing circuit 100 converts the sound source signal DI into amplified signals DOXP and DOXN as sound signals, and outputs them to the sound reproducing device 3. Thus, sounds corresponding to the amplified signals DOXP and DOXN are output from the sound reproducing device 3. For example, the sound reproducing device 3 may be a speaker or a buzzer. In addition, the sound output from the sound reproducing device 3 may be, for example, a sound obtained by imitating the sound of a person speaking, or various sounds such as a mechanical warning sound and an effect sound.

[0052] like Figure 1 As shown, in this embodiment, the sound source reproduction circuit 100 includes a modulation circuit 30 , switches 41 and 42 , and an amplifier circuit 50 .

[0053] The modulation circuit 30 receives the sound source signal DI as input, modulates the signal based on the sound source signal DI, and outputs the modulation signals DOP and DON. The signal based on the sound source signal DI can be the sound source signal DI itself, or can be a signal after some processing is performed on the sound source signal DI. In this embodiment, the modulation circuit 30 includes a digital filter 31, a Σ-Δ modulation circuit 32, and a pulse width modulation circuit 33.

[0054] The digital filter 31 is a low-pass filter that inputs the sound source signal DI and outputs the signal DF after the high-frequency noise contained in the sound source signal DI is reduced. The Σ-Δ modulation circuit 32 inputs the signal DF from the digital filter 31, oversamples the signal DF at a sampling ratio of n times to perform Σ-Δ modulation, thereby outputting a Σ-Δ modulated signal DS with noise biased to the high-frequency band. n is an integer greater than 2. Therefore, when the sampling frequency of the sound source signal DI is set to fs, the sampling frequency of the signal DF output from the digital filter 31 is fs, and the sampling frequency of the Σ-Δ modulated signal DS is n×fs. The digital filter 31 functions as an anti-aliasing filter that reduces the high-frequency noise that is folded back into the signal band due to oversampling of the Σ-Δ modulation circuit 32.

[0055] The pulse width modulation circuit 33 performs pulse width modulation on the Σ-Δ modulation signal DS and outputs modulation signals DOP and DON. The modulation signals DOP and DON are 1-bit digital signals. When the sampling frequency of the Σ-Δ modulation signal DS is n×fs, the sampling frequency of the modulation signals DOP and DON is n×m×fs. Here, when the number of bits of the Σ-Δ modulation signal DS is M, m=2 M .

[0056] In this way, the modulation circuit 30 performs Σ-Δ modulation on the signal obtained by digitally filtering the sound source signal DI, and further performs pulse width modulation to output the modulation signals DOP and DON.

[0057] The pulse width modulation for generating the modulation signal DOP and the pulse width modulation for generating the modulation signal DON are different in manner. Figure 2 is a diagram showing an example of pulse width modulation for generating a modulation signal DOP. Figure 3 FIG. 1 is a diagram showing an example of pulse width modulation for generating the modulation signal DON. Figure 2 and Figure 3 This is an example of a case where the number of bits M of the Σ-Δ modulation signal DS is 4. Figure 2 and Figure 3 In the embodiment, the Σ-Δ modulation signal DS is updated with a period T as a cycle, and the modulation signals DOP and DON are high or low in each of the 16 intervals T1 to T16 obtained by dividing the period T. That is, the length of the period T is 1 / (n×fs), and the length of each of the intervals T1 to T16 is 1 / (n×m×fs).

[0058] like Figure 2As shown, the modulation signal DOP is a Σ-Δ modulation signal DS, and the higher the value is, the longer the high level time is. For example, when the Σ-Δ modulation signal DS is "-7" in decimal, that is, "1001" in binary, one interval T1 of the modulation signal DOP is high, and 15 intervals T2 to T16 are low. In addition, for example, when the Σ-Δ modulation signal DS is "0" in decimal, that is, "0000" in binary, the modulation signal DOP is high in 8 intervals T1 to T8, and is low in 8 intervals T9 to T16. In addition, for example, when the Σ-Δ modulation signal DS is "7" in decimal, that is, "0111" in binary, the modulation signal DOP is high in 15 intervals T1 to T15, and is low in 1 interval T16.

[0059] like Figure 3 As shown, the modulation signal DON is a Σ-Δ modulation signal DS, and the time of high level is shorter as the value is larger. For example, when the Σ-Δ modulation signal DS is "-7" in decimal, that is, "1001" in binary, 15 intervals T1 to T15 of the modulation signal DON are high level, and 1 interval T16 is low level. In addition, for example, when the Σ-Δ modulation signal DS is "0" in decimal, that is, "0000" in binary, 8 intervals T1 to T8 of the modulation signal DON are high level, and 8 intervals T9 to T16 are low level. In addition, for example, when the Σ-Δ modulation signal DS is "7" in decimal, that is, "0111" in binary, one interval T1 of the modulation signal DON is high level, and 15 intervals T2 to T16 are low level.

[0060] Therefore, for example, when the Σ-Δ modulation signal DS is decimal "-7", "0", "7", the difference between the modulation signal DOP and the modulation signal DON is as follows: Figure 4 shown.

[0061] Return to Figure 1 As described above, the switch 41 outputs one of the modulation signal DOP and the modulation signal TP to the class D amplifier 51P of the amplifier circuit 50 according to the control signal output from the communication interface circuit 10. Specifically, the switch 41 outputs the modulation signal DOP to the class D amplifier 51P when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulation signal TP to the class D amplifier 51P when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0062] In addition, the switch 42 outputs one of the modulation signal DON and the modulation signal TN to the class D amplifier 51N of the amplifier circuit 50 according to the control signal output from the communication interface circuit 10. Specifically, the switch 42 outputs the modulation signal DON to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the normal operation mode, and outputs the modulation signal TN to the class D amplifier 51N when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0063] The amplifier circuit 50 receives the modulation signals DOP and DON as input in the normal operation mode, and outputs the amplified signals DOXP and DOXN obtained by amplifying the modulation signals DOP and DON to the output terminals 91 and 92 of the semiconductor device 1. In addition, the amplifier circuit 50 receives the modulation signals TP and TN as input in the inspection mode and the calibration mode, and outputs the amplified signals DOXP and DOXN obtained by amplifying the modulation signals TP and TN to the output terminals 91 and 92 of the semiconductor device 1.

[0064] In the present embodiment, the amplifier circuit 50 includes two class D amplifiers 51P and 51N. The class D amplifier 51P outputs an amplified signal DOXP obtained by amplifying the modulation signal DOP to an output terminal 91 in the normal operation mode, and outputs an amplified signal DOXP obtained by amplifying the modulation signal TP to an output terminal 91 in the inspection mode and the calibration mode. The class D amplifier 51N outputs an amplified signal DOXN obtained by amplifying the modulation signal DON to an output terminal 92 in the normal operation mode, and outputs an amplified signal DOXN obtained by amplifying the modulation signal TN to an output terminal 92 in the inspection mode and the calibration mode. The output terminal 91 is connected to the terminal P1 of the sound reproduction device 3, and the output terminal 92 is connected to the terminal P2 of the sound reproduction device 3. Then, the sound reproduction device 3 reproduces a sound of a magnitude corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN. It is preferable that the sound reproduction device 3 outputs a desired sound indicated by the sound source reproduction command in the normal operation mode, and outputs a tiny sound that is difficult for human ears to hear in the inspection mode and the calibration mode. That is, it is preferable that the volume reproduced by the sound reproduction device 3 in the inspection mode and the calibration mode is smaller than the minimum value of the volume reproduced by the sound reproduction device 3 in the normal operation mode. In other words, it is preferable that the voltage difference between the amplified signal DOXP and the amplified signal DOXN in the inspection mode and the calibration mode is smaller than the voltage difference between the amplified signal DOXP and the amplified signal DOXN when the minimum sound is output from the sound reproduction device 3 in the normal operation mode. This makes it difficult for the user to realize that the semiconductor device 1 is operating in the inspection mode or the calibration mode.

[0065] The inspection circuit 110 is a circuit for inspecting the sound reproducing device 3 .

[0066] Figure 51 is a diagram showing an example of the relationship between the state of a speaker and the impedance characteristics as an example of the sound reproduction device 3. Figure 5 In the figure, the horizontal axis is the frequency of the input signal of the speaker, and the vertical axis is the impedance value of the speaker. G1 is an example of the impedance characteristics of the speaker when it is normal. The frequency of the input signal at which the impedance of the speaker becomes a peak, that is, the peak frequency, varies depending on the type of speaker, but when the speaker is normal, it is at least included in the frequency band above the lower limit of the human audible range, that is, 20Hz and below the frequency used in the buzzer warning sound, that is, 3kHz. G2 is an example of the impedance characteristics of the speaker when the magnet is broken and falls off. If the magnet of the speaker falls off, it becomes only a coil, so as it becomes a high-frequency band, the impedance value slowly rises and the peak frequency disappears. G3 is an example of the impedance characteristics of the speaker when the conical paper is broken. When the conical paper, which serves as the vibration surface of the speaker, is broken, no bass will appear, and the peak frequency will shift to the high-frequency band side.

[0067] Thus, the peak frequency changes depending on the state of the speaker. Therefore, in the present embodiment, the inspection circuit 110 detects the peak frequency of the sound reproduction device 3 in the inspection mode, and determines the state of the sound reproduction device 3 based on the detected peak frequency. In addition, the inspection circuit 110 detects the peak frequency of the sound reproduction device 3 in the calibration mode, and generates information required for determining the state of the sound reproduction device 3 based on the detected peak frequency.

[0068] In this embodiment, the inspection circuit 110 includes a test signal generating circuit 60, a determination circuit 61, a memory 62, and a peak frequency detection circuit 70. The test signal generating circuit 60 and the peak frequency detection circuit 70 operate in the inspection mode and the calibration mode, and stop operating in the normal operation mode. In addition, the determination circuit 61 operates in the inspection mode, and stops operating in the normal operation mode and the calibration mode.

[0069] The test signal generating circuit 60 modulates the test signal whose frequency is changed in a preset frequency band to generate modulation signals TP and TN. The frequency band in which the test signal generating circuit 60 changes the frequency of the test signal can be arbitrarily set by the microcontroller unit 2, for example, it can be a frequency band of 10 Hz or more and 3 kHz or less. In the present embodiment, the test signal generating circuit 60 performs pulse width modulation on the test signal to generate modulation signals TP and TN. The pulse width modulation method of the test signal generating circuit 60 is the same as the pulse width modulation method of the pulse width modulation circuit 33.

[0070] The peak frequency detection circuit 70 measures the potential difference between the output terminal 91 and the output terminal 92, and detects the peak frequency, which is the frequency of the test signal at which the impedance of the sound reproduction device 3 reaches a peak. In addition, the peak frequency detection circuit 70 also detects the peak voltage, which is the voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal reaches the peak frequency. As described later, the peak frequency and the peak voltage vary depending on the temperature of the sound reproduction device 3.

[0071] The memory 62 includes a non-volatile memory (not shown) that stores table information that associates a plurality of temperatures with a plurality of peak frequencies related to the sound reproduction device 3. The table information also specifies the correspondence between a plurality of temperatures and a plurality of peak voltages related to the sound reproduction device 3. The memory 62 also includes a non-volatile memory (not shown) that stores various temporarily generated data.

[0072] The determination circuit 61 determines whether the peak frequency detected by the peak frequency detection circuit 70 is included in the reference frequency range. The reference frequency range is a frequency range determined based on the frequency band of the test signal and the temperature information as information related to the temperature of the sound reproduction device 3. In the present embodiment, the determination circuit 61 obtains the temperature signal output from the temperature sensor 80 as temperature information, and calculates the reference frequency range based on the obtained temperature signal and the table information stored in the memory 62. In addition, the determination circuit 61 further determines whether the peak voltage detected by the peak frequency detection circuit 70 is included in the reference voltage range. The reference voltage range is a voltage range determined based on the frequency band of the test signal and the temperature information as information related to the temperature of the sound reproduction device 3. The determination circuit 61 calculates the reference voltage range based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62. And in the present embodiment, the determination circuit 61 determines the state of the sound reproduction device 3, such as whether the sound reproduction device 3 has a fault, based on the determination results of whether the peak frequency is included in the reference frequency range and the determination results of whether the peak voltage is included in the reference voltage range. In addition, the details of the processing of the determination circuit 61 will be described later.

[0073] The temperature sensor 80 detects the temperature and outputs a temperature signal having a magnitude corresponding to the detected temperature. Figure 1 In the embodiment, the temperature sensor 80 is built into the semiconductor device 1 to directly detect the temperature of the semiconductor device 1. The temperature of the semiconductor device 1 and the temperature of the sound reproduction device 3 change in the same manner depending on the temperature of the semiconductor device 1 and the surroundings of the sound reproduction device 3, so the temperature of the sound reproduction device 3 is indirectly detected. However, the temperature sensor 80 may be provided outside the semiconductor device 1 and near the sound reproduction device 3 to directly detect the temperature of the sound reproduction device 3.

[0074] The switch 81 switches whether to electrically connect or disconnect the output terminal 91 of the semiconductor device 1 and the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. Specifically, the switch 81 electrically disconnects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 91 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0075] Similarly, the switch 82 switches whether to electrically connect or disconnect the output terminal 92 of the semiconductor device 1 from the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. Specifically, the switch 82 electrically disconnects the output terminal 92 from the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the output terminal 92 to the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0076] In this way, the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91 and 92 through the switches 81 and 82 in the normal operation mode, and is electrically connected to the output terminals 91 and 92 in the inspection mode and the calibration mode to measure the potential difference between the output terminals 91 and 92, thereby detecting the peak frequency and the peak voltage.

[0077] When receiving a command to read the information of the determination result of the determination circuit 61 from the micro control unit 2, the communication interface circuit 10 obtains the information of the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 can recognize the state of the sound reproduction device 3 based on the information of the determination result and execute various processes according to the state of the sound reproduction device 3.

[0078] 1-1-2. Status determination of sound reproduction device

[0079] Figure 6 and Figure 7 1 is a diagram showing a configuration example of class D amplifiers 51P and 51N, a peak frequency detection circuit 70, and peripheral circuits thereof. Figure 6 Indicates the structure in normal operation mode. Figure 7 Indicates the structure in check mode and calibration mode.

[0080] like Figure 6 as well as Figure 7As shown, the class D amplifier 51P has a plurality of inverter circuits 201-1 to 201-n, and the class D amplifier 51N has a plurality of inverter circuits 202-1 to 202-n. n is an integer greater than 2, and can be, for example, about 10 to 100. The inverter circuits 201-1 to 201-n are respectively composed of a pair of PMOS transistors and an NMOS transistor, and the node where the drain of the PMOS transistor is connected to the drain of the NMOS transistor, that is, the output terminal, is connected to the output terminal 91. Similarly, the inverter circuits 202-1 to 202-n are respectively composed of a pair of PMOS transistors and an NMOS transistor, and the node where the drain of the PMOS transistor is connected to the drain of the NMOS transistor, that is, the output terminal, is connected to the output terminal 92.

[0081] like Figure 6 As shown, in the normal operation mode, the modulation signal DOP is input to each input terminal of the inverter circuits 201-1 to 201-n of the class D amplifier 51P via the switch 41, and the modulation signal DON is input to each input terminal of the inverter circuits 202-1 to 202-n of the class D amplifier 51N via the switch 42. That is, in the normal operation mode, the inverter circuits 201-1 to 201-n of the class D amplifier 51P are connected in parallel between the modulation circuit 30 and the output terminal 91 of the semiconductor device 1, and the inverter circuits 202-1 to 202-n of the class D amplifier 51N are connected in parallel between the modulation circuit 30 and the output terminal 92 of the semiconductor device 1. As a result, the on-resistance R of the class D amplifier 51P is onP The on-resistance R of the class D amplifier 51N becomes 1 / n of the on-resistance of the inverter circuit 201-1. onN This becomes 1 / n of the on-resistance of the inverter circuit 202 - 1 .

[0082] The amplifier circuit 50 outputs an amplified signal DOXP obtained by amplifying the modulation signal DOP to an output terminal 91, and outputs an amplified signal DOXN obtained by amplifying the modulation signal DON to an output terminal 92. The output terminals 91 and 92 are connected to the terminals P1 and P2 of the sound reproduction device 3, respectively. The impedance R between the terminal P1 and the terminal P2 is sp For example, the on-resistance R of the class D amplifier 51P is 4Ω to 128Ω. onP and the on-resistance R of the class D amplifier 51N onN is the impedance R of the sound reproduction device 3 sp About 1 / 10 to 1 / 100 of the original.

[0083] In addition, if Figure 6 As shown, in the normal operation mode, the switches 81 and 82 are non-conductive, and the peak frequency detection circuit 70 and the output terminals 91 and 92 of the semiconductor device 1 are electrically disconnected.

[0084] On the other hand, Figure 7 As shown, in the inspection mode and the calibration mode, the modulation signal TP is input to each input terminal of a part of the inverter circuits 201-1 to 201-n of the class D amplifier 51P via the switch 41, and each output terminal of another part of the inverter circuits of the inverter circuits 201-1 to 201-n becomes high impedance. For example, in the inspection mode and the calibration mode, the modulation signal TP is input to the input terminal of the inverter circuit 201-1, and each output terminal of the inverter circuits 201-2 to 201-n becomes high impedance. Similarly, the modulation signal TN is input to each input terminal of a part of the inverter circuits 202-1 to 202-n of the class D amplifier 51N via the switch 42, and each output terminal of another part of the inverter circuits of the inverter circuits 202-1 to 202-n becomes high impedance. For example, in the test mode and the calibration mode, the modulation signal TN is input to the input terminal of the inverter circuit 202-1, and the output terminals of the inverter circuits 202-2 to 202-n become high impedance. onP and the on-resistance R of the class D amplifier 51N onN With impedance R sp About the same.

[0085] In addition, if Figure 7 As shown, in the inspection mode and the calibration mode, the switches 81 and 82 are turned on, and the peak frequency detection circuit 70 is electrically connected to the output terminals 91 and 92 of the semiconductor device 1 .

[0086] The peak frequency detection circuit 70 includes a differential low-pass filter 71 , an A / D conversion circuit 72 , and a peak time measurement circuit 73 .

[0087] The differential low-pass filter 71 receives the voltage of the output terminal 91 and the voltage of the output terminal 92 via the switches 81 and 82 in the inspection mode and the calibration mode. That is, the differential low-pass filter 71 receives the amplified signals DOXP and DOXN, reduces the noise components of the high frequency band superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference between the amplified signals DOXP and DOXN. The cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the test signal generating circuit 60 changes the frequency of the test signal. For example, when the test signal generating circuit 60 changes the frequency of the test signal in a frequency band above 10 Hz and below 3 kHz, the cutoff frequency of the differential low-pass filter 71 is higher than 3 kHz. Since the cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the frequency of the test signal is changed, the frequency components contained in the frequency band are not attenuated by the differential low-pass filter 71.

[0088] Figure 8 71 is a diagram showing a configuration example of a differential low-pass filter. Figure 8 As shown, the differential low-pass filter 71 includes an operational amplifier 211 , five resistors 212 , 213 , 214 , 216 , 218 , and three capacitors 215 , 217 , 219 .

[0089] In the inspection mode and the calibration mode, the amplified signal DOXP output to the output terminal 91 of the semiconductor device 1 is input to one end of the resistor 212. In addition, the amplified signal DOXN output to the output terminal 92 of the semiconductor device 1 is input to one end of the resistor 213. The other end of the resistor 212, one end of the resistor 214, and one end of the capacitor 215 are connected to the non-inverting input terminal of the operational amplifier 211. The other end of the resistor 213, one end of the resistor 216, one end of the capacitor 217, one end of the resistor 218, and one end of the capacitor 219 are connected to the inverting input terminal of the operational amplifier 211.

[0090] The other end of the resistor 214 and the other end of the capacitor 215 are connected to the output terminal of the operational amplifier 211. The other end of the resistor 216 and the other end of the capacitor 217 are grounded, and the other end of the resistor 218 and the other end of the capacitor 219 are supplied with a power supply voltage.

[0091] The differential low-pass filter 71 configured in this way reduces the high-frequency noise component superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference of the amplified signals DOXP and DOXN, that is, the potential difference between the output terminal 91 and the output terminal 92, from the output terminal of the operational amplifier 211. When the power supply voltage is VDD and the ground voltage is 0V, when the potential difference between the output terminal 91 and the output terminal 92, which reduces the high-frequency noise component, is positive, the voltage V' is higher than VDD×1 / 2, and when the potential difference between the output terminal 91 and the output terminal 92, which reduces the high-frequency noise component, is negative, the voltage V' is lower than VDD×1 / 2.

[0092] The amplitude voltage V'(pp) of the voltage V' and the impedance R of the sound reproduction device 3 sp , the on-resistance R of the class D amplifier 51P onP and the on-resistance R of the class D amplifier 51N onN There is a relationship as shown in formula (1). According to formula (1), the impedance R sp The larger the voltage V', the larger the amplitude, so the impedance R sp When it reaches the peak value, the amplitude of the voltage V' becomes maximum.

[0093]

[0094] return Figure 7 As described above, the A / D conversion circuit 72 converts the output voltage V' of the differential low-pass filter 71 into an m-bit digital signal and outputs it as an m-bit data DT. m is an integer greater than 2. The integer m is set to an appropriate value according to the requirements of the detection accuracy of the peak frequency, the size of the peak frequency detection circuit 70, etc.

[0095] The peak time measurement circuit 73 measures the peak time, which is the time when the potential difference between the output terminal 91 and the output terminal 92 becomes the maximum, based on the data DT, which is the output signal of the A / D conversion circuit 72. Specifically, the peak time measurement circuit 73 measures the time when the data DT becomes the maximum as the peak time. In addition, the peak time measurement circuit 73 measures the output voltage V' of the differential low-pass filter 71 at the peak time as the peak voltage. Specifically, the peak time measurement circuit 73 measures the maximum value of the data DT as the peak voltage.

[0096] As described above, when the impedance R of the sound reproduction device 3 sp When the impedance R of the sound reproduction device 3 is at its maximum sp When the impedance R is at its peak value, the amplitude of the voltage V' is maximum. sp The peak impedance R peak When the potential difference between the output terminal 91 and the output terminal 92 is the maximum. Since the frequency of the test signal changes sequentially at a predetermined timing, the impedance R of the sound reproduction device 3 is uniquely determined based on the peak time measured by the peak time measurement circuit 73. sp The peak impedance R peak Thus, the peak frequency detection circuit 70 detects the peak frequency by measuring the time when the potential difference between the output terminal 91 and the output terminal 92 is the maximum, that is, the peak time, in the inspection mode and the calibration mode. In addition, the peak frequency detection circuit 70 also detects the peak voltage, that is, the voltage obtained by amplifying the potential difference between the output terminal 91 and the output terminal 92 when the frequency of the test signal is the peak frequency, in the inspection mode and the calibration mode.

[0097] In the following, it is assumed that the peak frequency detected by the peak frequency detection circuit 70 in the inspection mode is f peak The peak frequency detected by the peak frequency detection circuit 70 in the calibration mode is F peak Similarly, let the peak voltage detected by the peak frequency detection circuit 70 in the inspection mode be v peak , the peak voltage detected by the peak frequency detection circuit 70 in the calibration mode is V peak Provide explanation.

[0098] Fig. 9 It represents the test signal and peak frequency f in the inspection mode.peak And the peak voltage v peak A diagram showing an example of the relationship between . Fig. 9 In the example of FIG. 1 , the test signal generating circuit 60 continuously changes the frequency of the test signal in a frequency band of 10 Hz to 3 kHz while maintaining the amplitude of the test signal at a constant voltage V1. When the sound reproduction device 3 is normal, the peak frequency f of the test signal is changed. peak , the output voltage V' of the differential low-pass filter 71 becomes the peak voltage v peak On the other hand, when the sound reproduction device 3 fails, although not shown in the figure, the peak frequency f peak , peak voltage v peak Therefore, the determination circuit 61 can be based on the peak frequency f peak , peak voltage v peak To determine the state of the sound reproduction device 3. Fig. 9 As shown, when a disconnection occurs between the semiconductor device 1 and the sound reproduction device 3, the output voltage V' of the differential low-pass filter 71 is fixed to the power supply voltage. peak The predetermined voltage which is higher than the power supply voltage of the differential low-pass filter 71 is V err When the output voltage V' of the differential low-pass filter 71 is greater than the voltage V err High, that is, the data DT ratio and voltage V err When the corresponding digital value is large, it can be determined as a disconnection fault.

[0099] like Fig.10 As shown, the peak impedance R peak , peak frequency f peak The higher the temperature of the sound reproduction device 3, the higher the impedance R sp The larger the impedance R is, the lower the temperature of the sound reproduction device 3 is. sp For example, if the temperature range for ensuring the operation of the sound reproduction device 3 is -40°C to 80°C, the peak impedance R at a high temperature such as 80°C is peak_High Greater than the peak impedance R at room temperature such as 25°C peak_Nor In addition, the peak impedance R at low temperatures such as -40°C peak_Low The peak impedance R at room temperature is less than 25°C. peak_Nor .like Fig.10 As shown, the higher the temperature of the sound reproduction device 3 is, the higher the peak frequency f peak The lower the temperature of the sound reproduction device 3, the lower the peak frequency f peak Therefore, the peak frequency f at high temperatures such as 80°C peak_HighPeak frequency f at room temperature lower than 25°C peak_Nor In addition, the peak frequency f at low temperatures such as -40°C peak_Low Higher than the peak frequency f at room temperature such as 25°C peak_Nor .

[0100] Since the peak impedance R peak , peak frequency f peak Varies with temperature, so Fig.11 As shown in FIG. 1 , the waveform of the output voltage V' of the differential low-pass filter 71 also changes according to the temperature. Therefore, the determination circuit 61 calculates the reference frequency range corresponding to the temperature based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62, and determines the peak frequency f detected by the peak frequency detection circuit 70. peak In addition, the determination circuit 61 calculates the reference voltage range corresponding to the temperature based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62, and determines whether the peak voltage v detected by the peak frequency detection circuit 70 is within the reference frequency range. peak Is it included in the reference voltage range?

[0101] In addition, the test signal in calibration mode, the peak impedance R peak With peak frequency F peak And the peak voltage V peak The relationship with Fig. 9 , Fig.10 as well as Fig.11 The same, therefore, the illustration and description are omitted.

[0102] 1-1-3. Processing of calibration mode

[0103] In this embodiment, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the calibration mode from the micro control unit 2, the operation mode of the semiconductor device 1 is switched to the calibration mode. Then, the inspection circuit 110 performs a predetermined process in the calibration mode. In this embodiment, the semiconductor device 1 and the sound reproduction device 3 are housed in a thermostatic chamber, and the inspection circuit 110 performs a predetermined process in synchronization with the switching of the thermostatic chamber to a plurality of temperatures.

[0104] Fig.12 2 is a flowchart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode.

[0105] First, in step S1, the determination circuit 61 determines whether table information should be generated. For example, the determination circuit 61 may determine whether table information is stored in the memory 62, and determine that table information should be generated if table information is not stored. In addition, for example, the determination circuit 61 may determine that table information should be generated if the communication interface circuit 10 receives a command from the microcontroller to instruct generation of table information.

[0106] When the determination circuit 61 determines in step S1 that the table information should be generated, it waits until the predetermined temperature is reached in step S2. For example, the temperature of the thermostatic bath is set to a predetermined temperature, and the determination circuit 61 detects the temperature T based on the temperature signal output from the temperature sensor 80, and determines whether the temperature T has reached the predetermined temperature based on the obtained temperature T.

[0107] Next, in step S3, the test signal generation circuit 60 starts to output the test signal obtained by sweeping the frequency. In step S4, the determination circuit 61 obtains the peak frequency F peak , peak voltage V peak , temperature T.

[0108] Next, in step S5, the determination circuit 61 determines the peak frequency F obtained in step S4. peak , peak voltage V peak , temperature T is stored in the volatile memory of the memory 62 .

[0109] Next, in step S6, the determination circuit 61 determines whether the peak frequency F is obtained at all the required temperatures. peak , peak voltage V peak , temperature T, in step S7, wait until the next temperature is reached.

[0110] Then, the determination circuit 61 repeats the processing of steps S3 to S7 until the peak frequency F is obtained at all the required temperatures. peak , peak voltage V peak , until the temperature T. Thus, the determination circuit 61 obtains the peak frequency F at a low temperature such as -40°C. peak_Low , peak voltage V peak_Low , Temperature T Low , peak frequency F at room temperature such as 25°C peak_Nor , peak voltage V peak_Nor , Temperature T Nor , peak frequency F at high temperatures such as 80°C peak_High , peak voltage V peak_High , Temperature T High , stored in the volatile memory of memory 62.

[0111] Next, in step S8, the determination circuit 61 uses the plurality of peak frequencies F stored in the volatile memory of the memory 62 in step S5 to determine the peak frequencies F. peak , peak voltage V peak , temperature T, generate the temperature T and peak frequency F peak , peak voltage V peak The corresponding table information is stored in the nonvolatile memory of the memory 62. For example, the determination circuit 61 generates a temperature T at a low temperature such as -40°C. Low With peak frequency F peak_Low , peak voltage V peak_Low Correspondingly, the temperature T at room temperature such as 25°C Nor With peak frequency F peak_Nor , peak voltage V peak_Nor Correspondingly, the high temperature T at 80°C or the like High With peak frequency F peak_High , peak voltage V peak_High The corresponding table information.

[0112] When the determination circuit 61 determines in step S1 that the table information is not to be generated, the processing of steps S2 to S8 is not performed.

[0113] Next, in step S9, the determination circuit 61 sets α and β, and ends the processing in the calibration mode. α is a constant for determining the aforementioned reference frequency range in consideration of the characteristic deviation of the sound reproduction device 3, and β is a constant for determining the aforementioned reference voltage range in consideration of the characteristic deviation of the sound reproduction device 3. For example, the constants α and β are stored in a nonvolatile memory of the memory 62, and the determination circuit 61 reads the constants α and β from the nonvolatile memory and sets them in a predetermined internal register.

[0114] 1-1-4. Processing of inspection mode

[0115] In this embodiment, when the communication interface circuit 10 receives a command to switch the operation mode of the semiconductor device 1 to the inspection mode from the micro control unit 2, the operation mode of the semiconductor device 1 is switched to the inspection mode. Alternatively, the operation mode of the semiconductor device 1 may be automatically switched to the inspection mode when the power supply voltage starts to be supplied to the semiconductor device 1. Then, the inspection circuit 110 performs a predetermined process in the inspection mode.

[0116] Fig.13 This is a flowchart showing an example of the processing procedure of the inspection circuit 110 in the inspection mode.

[0117] First, in step S11, the test signal generation circuit 60 starts to output the test signal obtained by scanning the frequency. In step S12, the determination circuit 61 obtains the peak frequency f peak , peak voltage v peak and temperature t.

[0118] Next, in step S13, the determination circuit 61 calculates the peak frequency F′ corresponding to the temperature t obtained in step S12 based on the table information stored in the nonvolatile memory of the memory 62. peak , peak voltage V' peak . Fig.14 is the peak frequency F' peak , peak voltage V' peak A diagram showing an example of a method for calculating . Fig.14 In the example, a low temperature T such as -40°C is stored. Low With peak frequency F peak_Low , peak voltage V peak_Low Correspondingly, the temperature T at room temperature such as 25°C Nor With peak frequency F peak_Nor , peak voltage V peak_Nor Correspondingly, the temperature T at high temperature such as 80°C High With peak frequency F peak_High , peak voltage V peak_High The corresponding table information. Temperature t is the temperature T High With temperature T Nor Therefore, the determination circuit 61 uses the peak frequency F peak_High and peak frequency F peak_Nor , calculate the peak frequency F' by linear interpolation peak Similarly, the determination circuit 61 uses, for example, the peak voltage V peak_High and peak voltage V peak_Nor , calculate the peak voltage V' by linear interpolation peak In addition, if the temperature t is the temperature T Nor With temperature T Low The determination circuit 61 uses, for example, the peak frequency F peak_Nor and peak frequency F peak_Low , calculate the peak frequency F' by linear interpolation peak , using the peak voltage V peak_Nor and peak voltage V peak_Low , calculate the peak voltage V' by linear interpolation peak .

[0119] Next, in step S14, the determination circuit 61 determines whether the peak voltage v obtained in step S12 is peak Is it higher than the voltage Verr At the peak voltage v peak Higher than the voltage V err In the case of the above, in step S15, the determination circuit 61 determines that there is a failure and ends the processing in the inspection mode.

[0120] On the other hand, at the peak voltage v peak is the voltage V err In the following cases, in step S16, the determination circuit 61 determines whether the peak frequency f obtained in step S12 is peak Is it included in the ratio F' peak -α is high and higher than F' peak +α low range is the reference frequency range. At the peak frequency f peak If it is not included in the reference frequency range, the determination circuit 61 determines in step S18 that there may be a failure, and ends the processing in the inspection mode.

[0121] On the other hand, at the peak frequency f peak If it is included in the reference frequency range, in step S17, the determination circuit 61 determines whether the peak voltage v obtained in step S12 is peak Is it included in the ratio V' peak -β is high and higher than V' peak +β low range is the reference voltage range. peak If it is not within the reference voltage range, in step S18, the determination circuit 61 determines that there may be a fault and ends the processing in the inspection mode. peak If it is included in the reference voltage range, the determination circuit 61 determines that it is normal in step S19, and the processing in the inspection mode ends.

[0122] In addition, the terminal P1 of the sound reproduction device 3 is an example of the “first terminal”, and the terminal P2 of the sound reproduction device 3 is an example of the “second terminal”. In addition, the output terminal 91 of the semiconductor device 1 is an example of the “first output terminal”, and the output terminal 92 of the semiconductor device 1 is an example of the “second output terminal”. In addition, the modulation signal DOP is an example of the “first modulation signal”, and the modulation signal DON is an example of the “second modulation signal”. In addition, the modulation signal TP is an example of the “third modulation signal”, and the modulation signal TN is an example of the “fourth modulation signal”. In addition, the amplified signal DOXP after the modulation signal DOP is amplified is an example of the “first amplified signal”, and the amplified signal DOXN after the modulation signal DON is amplified is an example of the “second amplified signal”. In addition, the amplified signal DOXP after the modulation signal TP is amplified is an example of the “third amplified signal”, and the amplified signal DOXN after the modulation signal TN is amplified is an example of the “fourth amplified signal”. In addition, the normal operation mode is an example of the “first operation mode”, and the inspection mode is an example of the “second operation mode”.

[0123] The semiconductor device 1 of the first embodiment is configured to allow one sound-reproducing device 3 to output sound, but may be configured to allow a plurality of sound-reproducing devices to output sound.

[0124] 1-1-5. Effects

[0125] As described above, according to the semiconductor device 1 of the first embodiment, in the normal operation mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN obtained by respectively amplifying the modulation signals DOP and DON based on the sound source signal DI to the output terminals 91 and 92, thereby enabling the sound reproduction device 3 to reproduce the sound. On the other hand, in the test mode, the amplifier circuit 50 outputs the amplified signals DOXP and DOXN obtained by respectively amplifying the modulation signals TP and TN based on the test signal to the output terminals 91 and 92, thereby enabling the peak frequency detection circuit 70 to measure the potential difference between the output terminal 91 and the output terminal 92, and detect the peak frequency f at which the impedance of the sound reproduction device 3 reaches a peak value. peak Then, the determination circuit 61 determines the peak frequency f peak Is it included in the reference frequency range, at the peak frequency f peakIf the sound reproduction device 3 is not included in the reference frequency range, it can be determined that the sound reproduction device 3 may have a fault. The reference frequency range is determined based on the frequency band of the test signal and the temperature information of the sound reproduction device 3, and therefore changes appropriately according to the temperature of the sound reproduction device 3. Specifically, the determination circuit 61 can calculate an appropriate reference frequency range corresponding to the temperature of the sound reproduction device 3 based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62. Therefore, according to the semiconductor device 1 of the first embodiment, even if the temperature changes, the accuracy of the fault determination of the sound reproduction device 3 can be maintained.

[0126] In the semiconductor device 1 of the first embodiment, the amplifier circuit 50 is used for generating the amplified signals DOXP and DOXN for causing the sound reproducing device 3 to reproduce the sound in the normal operation mode and for adjusting the peak frequency f in the test mode. peak Therefore, according to the semiconductor device 1 of the first embodiment, it is possible to generate a signal necessary for detecting a failure of the sound reproducing device 3 by a small-scale circuit.

[0127] In the semiconductor device 1 of the first embodiment, the determination circuit 61 further determines the peak voltage v peak Is it within the reference voltage range, for example, the peak voltage v peak If the reference voltage range is not included, it can be determined that the sound reproduction device 3 may have a fault. The reference voltage range is determined based on the frequency band of the test signal and the temperature information of the sound reproduction device 3, and therefore changes appropriately according to the temperature of the sound reproduction device 3. Therefore, even if the peak frequency f peak If the peak voltage v is within the reference frequency range, peak Even if the reference voltage is not within the range, the determination circuit 61 can determine that the sound reproduction device 3 may be faulty. Therefore, the semiconductor device 1 of the first embodiment reduces the possibility of erroneously determining that the sound reproduction device 3 is normal when the sound reproduction device 3 may be faulty.

[0128] According to the semiconductor device 1 of the first embodiment, the impedance R sp When the potential difference between the output terminal 91 and the output terminal 92 reaches a peak value, the peak frequency detection circuit 70 can detect the peak frequency f by measuring the time when the potential difference between the output terminal 91 and the output terminal 92 reaches the maximum. peak .

[0129] In addition, according to the semiconductor device 1 of the first embodiment, in the peak frequency detection circuit 70, the differential low-pass filter 71 reduces the noise component of the high-frequency band superimposed on the amplified signals DOXP and DOXN due to the modulation of the test signal, the A / D conversion circuit 72 converts the output voltage of the differential low-pass filter 71 into data DT, and the peak time measurement circuit 73 can easily perform high-precision measurement.

[0130] Furthermore, according to the semiconductor device 1 of the first embodiment, the impedance R of the sound reproduction device 3 is sp Since the peak frequency f is not dependent on the voltage of the amplified signals DOXP and DOXN, the peak frequency f can be detected in the test mode when the sound reproduction device 3 reproduces a very small sound that is difficult for human ears to hear. peak And the peak voltage v peak Therefore, according to the semiconductor device 1 of the first embodiment, it is possible to make it difficult for the user to be aware that the semiconductor device 1 is operating in the inspection mode.

[0131] 1-2. Second Embodiment

[0132] Hereinafter, regarding the semiconductor device 1 of the second embodiment, the same reference numerals are used for the same structures as those of the first embodiment, and the same description as that of the first embodiment is omitted or simplified, and the contents different from the first embodiment are mainly described.

[0133] The structure of the semiconductor device 1 of the second embodiment is Figure 1 In the semiconductor device 1 of the second embodiment, the processing of the determination circuit 61 is different from that of the first embodiment.

[0134] In the second embodiment, the temperature T and the peak frequency F related to the sound reproduction device 3 are stored in the nonvolatile memory of the memory 62. peak In addition, the temperature T and the peak voltage V related to the sound reproduction device 3 are stored in the non-volatile memory of the memory 62. peak relational information.

[0135] As shown in formula (2), temperature T and peak frequency F peak The relationship between temperature T and peak frequency F may also be an n-order polynomial with temperature T as a variable. n is a predetermined integer greater than 2. For example, peak The relationship is Fig.15 The 3 points shown indicate a situation where Fig.15 As shown by the middle dotted line, the square root of the peak frequency Fpeak is approximately equal to the quadratic approximation of the temperature T. Therefore, the relational expression between the temperature T and the peak frequency Fpeak becomes a 4th-order polynomial with the temperature T as a variable.

[0136] F peak =a n T n +a n-1 T n-1 +…+a1T+a0…(2)

[0137] In addition, as shown in equation (3), the relationship between temperature T and peak voltage Vpeak may also be an m-order polynomial with temperature T as a variable. m is a predetermined integer greater than 2. For example, in the case where the relationship between temperature T and peak impedance Rpeak is given by Fig.16 The 3 points shown indicate a situation where Fig.16 As shown by the dotted line in the middle, the peak impedance Rpeak is approximately a linear expression of the temperature T. The peak voltage Vpeak is proportional to the peak impedance Rpeak, so the relationship between the temperature T and the peak voltage Vpeak is a linear polynomial with the temperature T as a variable.

[0138] V peak =b n T n +b n-1 T n-1 +…+b1T+b0…(3)

[0139] The determination circuit 61 determines whether the peak frequency fpeak detected by the peak frequency detection circuit 70 is included in the reference frequency range, similarly to the first embodiment. Similar to the first embodiment, the reference frequency range is a frequency range determined based on the frequency band of the test signal and the temperature information related to the temperature of the sound reproduction device 3, i.e., the temperature information.

[0140] In the second embodiment, the determination circuit 61 obtains the temperature signal output from the temperature sensor 80 as temperature information, and calculates the reference frequency range based on the obtained temperature signal and the information of the relationship (2) between the temperature T and the peak frequency Fpeak stored in the memory 62. In addition, the determination circuit 61 calculates the reference voltage range based on the temperature signal output from the temperature sensor 80 and the information of the relationship (3) between the temperature T and the peak voltage Vpeak stored in the memory 62.

[0141] Fig.17 This is a flowchart showing an example of the processing procedure of the inspection circuit 110 in the calibration mode in the second embodiment.

[0142] First, in step S101, the determination circuit 61 determines whether the relational expressions (2) and (3) should be generated. For example, the determination circuit 61 may determine whether the information of the relational expressions (2) and (3) is stored in the memory 62, and determine that the relational expressions (2) and (3) should be generated when the information of the relational expressions (2) and (3) is not stored. In addition, for example, when the communication interface circuit 10 receives a command from the microcontroller to instruct the generation of the relational expressions (2) and (3), the determination circuit 61 may determine that the relational expressions (2) and (3) should be generated.

[0143] When the determination circuit 61 determines in step S101 that the relational expressions (2) and (3) should be generated, the determination circuit 61 waits until a predetermined temperature is reached in step S102.

[0144] Next, in step S103 , the test signal generation circuit 60 starts to output a test signal obtained by sweeping the frequency. In step S104 , the determination circuit 61 obtains the peak frequency Fpeak, the peak voltage Vpeak, and the temperature T.

[0145] Next, in step S105, the determination circuit 61 determines the peak frequency F obtained in step S104. peak , peak voltage V peak , temperature T is stored in the volatile memory of the memory 62 .

[0146] Next, in step S106, the determination circuit 61 determines whether the peak frequency F is obtained at all the required temperatures. peak , peak voltage V peak , temperature T, in step S107, wait until the next temperature is reached.

[0147] Then, the determination circuit 61 repeats the processing of steps S103 to S107 until the peak frequency F is obtained at all the required temperatures. peak , peak voltage V peak , until the temperature T. Thus, the determination circuit 61 obtains the peak frequency F at a low temperature such as -40°C. peak_Low , peak voltage V peak_Low , Temperature T Low , peak frequency F at room temperature such as 25°C peak_Nor , peak voltage V peak_Nor , Temperature T Nor , peak frequency F at high temperatures such as 80°C peak_High , peak voltage V peak_High , Temperature T High , stored in the volatile memory of memory 62.

[0148] Next, in step S108, the determination circuit 61 uses the plurality of peak frequencies F stored in the volatile memory of the memory 62 in step S105 to determine the peak frequencies F of the volatile memory. peak , peak voltage V peak , temperature T, calculate the temperature T and peak frequency F peak , peak voltage V peak The information of the relational expressions (2) and (3) is stored in the non-volatile memory in the memory 62. The information of the relational expression (2) may be, for example, the coefficient a n Similarly, the information of relation (3) can be, for example, the coefficient b n ~the value of b0.

[0149] When the determination circuit 61 determines in step S101 that table information is not to be generated, the processing of steps S102 to S108 is not performed.

[0150] Next, in step S109, the determination circuit 61 sets α and β, and ends the processing in the calibration mode. α is a constant for determining the aforementioned reference frequency range in consideration of the characteristic deviation of the sound reproduction device 3, and β is a constant for determining the aforementioned reference voltage range in consideration of the characteristic deviation of the sound reproduction device 3. For example, the constants α and β are stored in a nonvolatile memory of the memory 62, and the determination circuit 61 reads the constants α and β from the nonvolatile memory and sets them in a predetermined internal register.

[0151] Fig.18 This is a flowchart showing an example of the processing procedure of the inspection circuit 110 in the inspection mode in the second embodiment.

[0152] First, in step S111, the test signal generation circuit 60 starts to output the test signal obtained by scanning the frequency. In step S112, the determination circuit 61 obtains the peak frequency f peak , peak voltage v peak , temperature t.

[0153] Next, in step S113, the determination circuit 61 calculates the peak frequency F′ corresponding to the temperature t obtained in step S112 based on the relational expressions (2) and (3) stored in the nonvolatile memory of the memory 62. peak , peak voltage V' peak That is, the determination circuit 61 substitutes the temperature t into the temperature T as the variable of the relational expression (2) to calculate the peak frequency F peak , the calculated peak frequency F peak As the peak frequency F' peak Similarly, the determination circuit 61 substitutes the temperature t into the temperature T as the variable of the relational expression (3) to calculate the peak voltage Vpeak , the calculated peak voltage V peak As the peak voltage V' peak .

[0154] Next, in step S114, the determination circuit 61 determines whether the peak voltage v obtained in step S112 is peak Is it higher than the voltage V err At the peak voltage v peak Ratio voltage V err If it is high, in step S115, the determination circuit 61 determines that there is a failure and ends the processing in the inspection mode.

[0155] On the other hand, at the peak voltage v peak is the voltage V err In the following cases, in step S116, the determination circuit 61 determines whether the peak frequency f obtained in step S112 is peak Is it included in the ratio F' peak -α is high and higher than F' peak +α low range is the reference frequency range. At the peak frequency f peak If it is not included in the reference frequency range, in step S118 , the determination circuit 61 determines that there may be a failure, and ends the processing in the inspection mode.

[0156] On the other hand, at the peak frequency f peak If it is included in the reference frequency range, in step S117, the determination circuit 61 determines whether the peak voltage v obtained in step S112 is peak Is it included in the ratio V' peak -β is high and higher than V' peak +β low range is the reference voltage range. peak If it is not within the reference voltage range, in step S118, the determination circuit 61 determines that there may be a fault and ends the processing in the inspection mode. peak If it is within the reference voltage range, the determination circuit 61 determines that it is normal in step S119, and the processing in the inspection mode ends.

[0157] The other structures and functions of the semiconductor device 1 according to the second embodiment are the same as those of the first embodiment, and thus the description thereof will be omitted.

[0158] The semiconductor device 1 of the second embodiment is configured to allow one sound-reproducing device 3 to output sound, but may be configured to allow a plurality of sound-reproducing devices to output sound.

[0159] According to the semiconductor device 1 of the second embodiment described above, the determination circuit 61 can calculate an appropriate reference frequency range corresponding to the temperature of the sound reproduction device 3 based on the temperature signal output from the temperature sensor 80 and the information of the relational expression stored in the memory 62. Therefore, according to the semiconductor device 1 of the second embodiment, even if the temperature changes, the accuracy of the failure determination of the sound reproduction device 3 can be maintained.

[0160] Furthermore, according to the semiconductor device 1 of the second embodiment, the same effects as those of the semiconductor device 1 of the first embodiment are achieved.

[0161] 1-3. Third Embodiment

[0162] Hereinafter, regarding the semiconductor device 1 of the third embodiment, the same reference numerals are used for the same structures as those in the first embodiment or the second embodiment, and the same description as that in the first embodiment or the second embodiment is omitted or simplified, and the contents different from the first embodiment and the second embodiment are mainly described.

[0163] The structure of the semiconductor device 1 of the third embodiment is Figure 1 In the semiconductor device 1 of the third embodiment, the processing of the determination circuit 61 is different from that of the first and second embodiments.

[0164] In the third embodiment, information of a reference frequency block including a peak frequency corresponding to a reference temperature among a plurality of frequency blocks obtained by dividing a predetermined frequency range is stored in the nonvolatile memory of the memory 62. The reference temperature is, for example, a normal temperature such as 25°C.

[0165] Fig.19 FIG. 1 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block. Fig.19 In the example, the prescribed frequency range is a range of 10 Hz to 10000 Hz, and the frequency range is divided into 6 frequency blocks F1 to F6. Frequency block F1 is a range of 10 Hz to 30 Hz. Frequency block F2 is a range of 31 Hz to 100 Hz. Frequency block F3 is a range of 101 Hz to 300 Hz. Frequency block F4 is a range of 301 Hz to 1000 Hz. Frequency block F5 is a range of 1001 Hz to 3000 Hz. Frequency block F6 is a range of 3001 Hz to 10000 Hz. If the temperature range for ensuring the operation of the sound reproduction device 3 is -40°C to 80°C, the reference temperature is a normal temperature such as 25°C, including the peak frequency F at normal temperature. peak_Nor The frequency block F3 is the reference frequency block. Fig.19 In one example, due to the peak frequency F peak_Nor The frequency is close to the lower limit frequency of the frequency block F3, so the peak frequency F at high temperature such as 80°C is peak_HighThe peak frequency F at low temperature such as -40°C included in the frequency block F2 before the frequency block F3 peak_Low Contained in frequency block F3. On the contrary, at the peak frequency F peak_Nor When the upper limit frequency of the frequency block F3 is approached, the peak frequency F at a high temperature such as 80°C peak_High The peak frequency F at low temperatures such as -40°C is included in the frequency block F3. peak_Low That is, if the state of the sound reproduction device 3 is normal, the peak frequency f detected in the inspection mode is peak It is contained in the frequency range consisting of the reference frequency block and the frequency blocks before and after the reference frequency block, and is independent of the temperature t.

[0166] The determination circuit 61 determines the peak frequency f detected by the peak frequency detection circuit 70 in the same manner as in the first embodiment. peak Whether it is included in the reference frequency range. As in the first embodiment, the reference frequency range is a frequency range determined based on the frequency band of the test signal and the temperature information related to the temperature of the sound reproduction device 3. However, in the third embodiment, the temperature information is information about the temperature range for ensuring the operation of the sound reproduction device 3, and the reference frequency range is a frequency range consisting of a reference frequency block and frequency blocks before and after the reference frequency block. The reference frequency range includes a peak frequency f corresponding to the temperature range for ensuring the operation of the sound reproduction device 3. peak range.

[0167] Fig. 20 This is a flowchart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode in the third embodiment.

[0168] First, in step S201, the determination circuit 61 determines whether the reference frequency block should be calculated. For example, the determination circuit 61 may determine whether the information of the reference frequency block is stored in the memory 62, and determine that the reference frequency block should be calculated if the information of the reference frequency block is not stored. In addition, for example, when the communication interface circuit 10 receives a command instructing the calculation of the reference frequency block from the microcontroller, the determination circuit 61 determines that the reference frequency block should be calculated.

[0169] When the determination circuit 61 determines in step S201 that the reference frequency block should be calculated, the determination circuit 61 waits until a predetermined temperature is reached in step S202 .

[0170] Next, in step S203, the test signal generation circuit 60 starts to output the test signal obtained by scanning the frequency. In step S204, the determination circuit 61 obtains the peak frequency F peak .

[0171] Next, in step S205, the determination circuit 61 determines the peak frequency F obtained in step S204 from among the plurality of frequency blocks obtained by dividing the predetermined frequency range. peak The frequency block is used as the reference frequency block, the information of the reference frequency block is stored in the non-volatile memory of the memory 62, and the processing in the calibration mode is ended.

[0172] Fig.21 This is a flowchart showing an example of the processing procedure of the inspection circuit 110 in the inspection mode in the third embodiment.

[0173] First, in step S211, the test signal generation circuit 60 starts to output the test signal obtained by scanning the frequency. In step S212, the determination circuit 61 obtains the peak frequency f peak , peak voltage v peak .

[0174] Next, in step S213, the determination circuit 61 determines whether the peak voltage v obtained in step S212 is peak Is it higher than the voltage V err At the peak voltage v peak Ratio voltage V err If it is high, in step S214, the determination circuit 61 determines that there is a failure, and ends the processing in the inspection mode.

[0175] On the other hand, at the peak voltage v peak is the voltage V err In the following case, in step S215, the determination circuit 61 determines whether the peak frequency f obtained in step S212 is peak Whether it is included in the reference frequency range formed by the reference frequency block or the frequency blocks before and after it. peak If it is not included in the reference frequency range, in step S216 , the determination circuit 61 determines that there may be a failure, and ends the processing in the inspection mode.

[0176] On the other hand, at the peak frequency f peak If it is included in the reference frequency range, the determination circuit 61 determines that it is normal in step S217, and ends the processing in the inspection mode.

[0177] The other structures and functions of the semiconductor device 1 according to the third embodiment are the same as those of the first embodiment, and thus the description thereof will be omitted.

[0178] The semiconductor device 1 of the third embodiment is configured to allow one sound-reproducing device 3 to output sound, but may be configured to allow a plurality of sound-reproducing devices to output sound.

[0179] In the semiconductor device 1 of the third embodiment described above, the reference frequency range is a frequency range including a range of peak frequencies corresponding to the temperature range for ensuring the operation of the sound reproduction device 3, which is composed of a reference frequency block including a peak frequency corresponding to the reference temperature and frequency blocks before and after the reference frequency block. Therefore, even if the peak frequency changes due to a change in the temperature of the sound reproduction device 3, the detected peak frequency f peak Therefore, according to the semiconductor device 1 of the third embodiment, the possibility of erroneously determining that a failure has occurred when the sound reproducing device 3 is normal can be reduced.

[0180] Furthermore, according to the semiconductor device 1 of the third embodiment, the same effects as those of the semiconductor device 1 of the first embodiment are achieved.

[0181] 1-4. Fourth Embodiment

[0182] Hereinafter, with respect to the semiconductor device 1 of the fourth embodiment, the same figure numbers are used to mark the same structures as any one of the first to third embodiments, and the descriptions that are the same as any one of the first to third embodiments are omitted or simplified, and the contents that are different from any one of the first to third embodiments are mainly described.

[0183] In the fourth embodiment, the nonvolatile memory of the memory 62 stores information on a reference frequency block including a range of peak frequencies corresponding to a temperature range ensuring operation of the sound reproduction device 3 among a plurality of frequency blocks obtained by dividing a predetermined frequency range.

[0184] Fig. 22 FIG. 1 is a diagram showing an example of a plurality of frequency blocks and a reference frequency block. Fig. 22 In the example, the specified frequency range is a range of 10 Hz to 10000 Hz, and the frequency range is divided into 6 frequency blocks F1 to F6. Frequency block F1 is a range of 10 Hz to 30 Hz. Frequency block F2 is a range of 31 Hz to 50 Hz. Frequency block F3 is a range of 51 Hz to 300 Hz. Frequency block F4 is a range of 301 Hz to 1000 Hz. Frequency block F5 is a range of 1001 Hz to 3000 Hz. Frequency block F6 is a range of 3001 Hz to 10000 Hz. If the temperature range for ensuring the operation of the sound reproduction device 3 is -40°C to 80°C, the peak frequency F at 80°C, which is the highest temperature, is peak_High , as the peak frequency F at room temperature such as 25°C peak_Nor , the peak frequency F at -40°C, the lowest temperature peak_Low All are contained in one frequency block F3. This frequency block F3 is a reference frequency block. That is, if the state of the sound reproduction device 3 is normal, the peak frequency f detected in the test mode ispeak are all contained in the reference frequency block and have nothing to do with temperature t.

[0185] The determination circuit 61 determines the peak frequency f detected by the peak frequency detection circuit 70 in the same manner as in the first embodiment. peak Whether it is included in the reference frequency range. As in the first embodiment, the reference frequency range is a frequency range determined based on the frequency band of the test signal and the temperature information related to the temperature of the sound reproduction device 3. However, in the fourth embodiment, the temperature information is information about the temperature range for ensuring the operation of the sound reproduction device 3, and the reference frequency range is a frequency range of the reference frequency block. The reference frequency range includes the peak frequency f corresponding to the temperature range for ensuring the operation of the sound reproduction device 3. peak range.

[0186] Fig.23 This is a flowchart showing an example of a processing procedure of the inspection circuit 110 in the calibration mode in the fourth embodiment.

[0187] First, in step S301, the determination circuit 61 determines whether the reference frequency block should be calculated. For example, the determination circuit 61 may determine whether the information of the reference frequency block is stored in the memory 62, and determine that the reference frequency block should be calculated if the information of the reference frequency block is not stored. In addition, for example, when the communication interface circuit 10 receives a command instructing the calculation of the reference frequency block from the microcontroller, the determination circuit 61 determines that the reference frequency block should be calculated.

[0188] When the determination circuit 61 determines in step S301 that the reference frequency block should be calculated, the determination circuit 61 waits until a predetermined temperature is reached in step S302 .

[0189] Next, in step S303, the test signal generation circuit 60 starts to output the test signal obtained by scanning the frequency. In step S304, the determination circuit 61 obtains the peak frequency F peak , peak voltage V peak , temperature T.

[0190] Next, in step S305, the determination circuit 61 determines the peak frequency F obtained in step S304. peak , peak voltage V peak , temperature T is stored in the volatile memory of the memory 62 .

[0191] Next, in step S306, the determination circuit 61 determines whether the peak frequency F is obtained at all the required temperatures. peak , peak voltage V peak , temperature T, in step S307, wait until the next temperature is reached.

[0192] Then, the determination circuit 61 repeats the processing of steps S303 to S307 until the peak frequency F is obtained at all the required temperatures. peak , peak voltage V peak , until the temperature T. Thus, the determination circuit 61 obtains the peak frequency F at, for example, -40°C as the lowest temperature. peak_Low , peak voltage V peak_Low , Temperature T Low , as the peak frequency F at room temperature such as 25°C peak_Nor , peak voltage V peak_Nor , Temperature T Nor 、Peak frequency F at 80°C as the highest temperature peak_High , peak voltage V peak_High , Temperature T High , stored in the volatile memory of memory 62.

[0193] Next, in step S308, the determination circuit 61 determines the peak frequency F at the highest temperature of the volatile memory stored in the memory 62 in step S305. peak_High and the peak frequency F at the lowest temperature peak_Low Whether it is included in the same frequency block among a plurality of frequency blocks obtained by dividing a predetermined frequency range.

[0194] When the peak frequency F peak_High and peak frequency F peak_Low If they are not included in the same frequency block, in step S309, the determination circuit 61 corrects the multiple frequency blocks so that the peak frequency F peak_High and peak frequency F peak_Low are contained in the same frequency block. For example, Fig.19 As shown, when the peak frequency F peak_High Contained in frequency block F2 and with peak frequency F peak_Low When included in the frequency block F3, the frequency at the boundary between the frequency block F2 and the frequency block F3 is reduced and corrected to the above Fig. 22 As shown in the peak frequency F peak_High and peak frequency F peak_Low In this case, it is preferable to make correction so that the lower limit frequency of the frequency block F3 is equal to the peak frequency F peak_High The difference between them is large enough, and the upper limit frequency of the frequency block F3 is equal to the peak frequency F peak_Low The difference between them is big enough.

[0195] The determination circuit 61 repeats the processing of steps S302 to S309 until the peak frequency F peak_High and peak frequency F peak_Lowcontained in the same frequency block.

[0196] Furthermore, the determination circuit 61 determines the peak frequency F peak_High and peak frequency F peak_Low When they are included in the same frequency block, in step S310 , the frequency block is taken as a reference frequency block, and the information of the reference frequency block is stored in the nonvolatile memory of the memory 62 .

[0197] Finally, in step S311, the determination circuit 61 calculates the ratio B of the peak impedance to the steady-state impedance at room temperature, stores it in the memory 62, and ends the processing in the calibration mode. sp For example, the determination circuit 61 calculates the peak voltage V at room temperature. peak_Nor The ratio to the minimum value of the output voltage V' of the differential low-pass filter 71 is taken as the ratio B of the peak impedance to the steady-state impedance at room temperature.

[0198] Fig.24 This is a flowchart showing an example of the processing procedure of the inspection circuit 110 in the inspection mode in the fourth embodiment.

[0199] First, in step S321, the test signal generation circuit 60 starts to output the test signal obtained by scanning the frequency. In step S322, the determination circuit 61 obtains the peak voltage v peak and the maximum value of the voltage V' for each frequency block.

[0200] Next, in step S323, the determination circuit 61 calculates the ratio B' of the maximum impedance to the steady-state impedance for each frequency block, and stores it in the memory 62. For example, the determination circuit 61 calculates the ratio of the maximum value of the voltage V' of each frequency block to the minimum value of the voltage V' in the entire frequency range as the ratio B' of the maximum impedance to the steady-state impedance of each frequency block.

[0201] Next, in step S324, the determination circuit 61 determines whether the peak voltage v obtained in step S322 is peak Is it higher than the voltage V err At the peak voltage v peak Ratio voltage V err If it is high, in step S325, the determination circuit 61 determines that there is a failure, and ends the processing in the inspection mode.

[0202] On the other hand, at the peak voltage v peak is the voltage V errIn the following cases, in step S326, the determination circuit 61 determines whether the frequency block with the largest ratio B' calculated in step S323 is consistent with the reference frequency block. If the frequency block with the largest ratio B' is inconsistent with the reference frequency block, in step S328, the determination circuit 61 determines that there may be a failure and ends the processing in the inspection mode.

[0203] On the other hand, when the frequency block with the largest ratio B' coincides with the reference frequency block, in step S327, the determination circuit 61 determines whether the maximum value of the ratio B' is included in the range larger than B-γ and smaller than B+γ relative to the ratio B stored in the memory 62. γ is a constant for determining the range of possible values ​​of the ratio B' in consideration of the characteristic deviation of the sound reproduction device 3. When the maximum value of the ratio B' is not included in the range, in step S328, the determination circuit 61 determines that there may be a fault and ends the processing in the inspection mode. In addition, when the maximum value of the ratio B' is included in the range, in step S329, the determination circuit 61 determines that it is normal and ends the processing in the inspection mode.

[0204] The other structures and functions of the semiconductor device 1 according to the fourth embodiment are the same as those of the first embodiment, and thus the description thereof will be omitted.

[0205] The semiconductor device 1 of the fourth embodiment is configured to allow one sound-reproducing device 3 to output sound, but may be configured to allow a plurality of sound-reproducing devices to output sound.

[0206] In the semiconductor device 1 of the fourth embodiment, since the reference frequency range is a frequency range of a reference frequency block including a peak frequency range corresponding to a temperature range in which the operation of the sound reproduction device 3 is ensured, even if the peak frequency changes due to a temperature change of the sound reproduction device 3, the detected peak frequency f peak Therefore, according to the semiconductor device 1 of the fourth embodiment, the possibility of erroneously determining that a failure has occurred when the sound reproducing device 3 is normal is reduced.

[0207] Furthermore, according to the semiconductor device 1 of the fourth embodiment, the same effects as those of the semiconductor device 1 of the first embodiment are achieved.

[0208] 1-5. Fifth Implementation

[0209] Hereinafter, with respect to the semiconductor device 1 of the fifth embodiment, the same figure numbers are used to mark the same structures as any one of the first to fourth embodiments, and the descriptions that are the same as any one of the first to fourth embodiments are omitted or simplified, and the contents that are different from any one of the first to fourth embodiments are mainly described.

[0210] Fig.25 FIG. 5 is a diagram showing a configuration example of a semiconductor device according to a fifth embodiment. Fig.25 As shown, the semiconductor device 1 of the fifth embodiment is connected to the sound source reproduction circuit 100a and the sound reproduction device 3a. Specifically, the output terminal 95 of the semiconductor device 1 is connected to the input terminal 103 of the sound source reproduction circuit 100a, the input terminal 93 of the semiconductor device 1, the output terminal 101 of the sound source reproduction circuit 100a, and the terminal P1a of the sound reproduction device 3a are connected, and the input terminal 94 of the semiconductor device 1, the output terminal 102 of the sound source reproduction circuit 100a, and the terminal P2a of the sound reproduction device 3a are connected.

[0211] The semiconductor device 1 of the fifth embodiment includes a communication interface circuit 10, a memory 20, a temperature sensor 80, switches 83, 84, 85, and a test circuit 110. The semiconductor device 1 may be a semiconductor integrated circuit device of one chip, may be composed of semiconductor integrated circuit devices of multiple chips, and may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0212] When receiving a command to switch the operation mode of the semiconductor device 1 to the normal operation mode, the inspection mode, or the calibration mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 83, 84, and 85 according to the operation mode. In addition, for example, when receiving a sound source reproduction command for causing the sound reproduction device 3a to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the input terminal 103 of the sound source reproduction circuit 100a via the switch 85 and the output terminal 95, and instructs the sound source reproduction circuit 100a to reproduce by the sound reproduction device 3a. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. In addition, for example, when receiving a sound source stop command for the sound source data 21-i being reproduced, the communication interface circuit 10 instructs the sound source reproduction circuit 100a to stop the reproduction. Furthermore, for example, when receiving various setting commands related to sound source reproduction, the communication interface circuit 10 performs various settings on the sound source reproduction circuit 100 a .

[0213] The switch 85 outputs either a signal based on the sound source signal DIa or a test signal TST to the output terminal 95 in accordance with a control signal output from the communication interface circuit 10. Specifically, the switch 85 outputs a signal based on the sound source signal DIa to the output terminal 95 in the normal operation mode, and outputs the test signal TST to the output terminal 95 in the inspection mode or the calibration mode. The signal based on the sound source signal DIa may be the sound source signal DIa itself, or may be a signal obtained by subjecting the sound source signal DIa to some processing.

[0214] The sound source reproduction circuit 100a converts the signal input from the input terminal 103 into amplified signals DOXPa and DOXNa, and outputs the amplified signals DOXPa and DOXNa to the output terminals 101 and 102, respectively. When the signal input from the input terminal 103 is a signal based on the sound source signal DIa, the sound source reproduction circuit 100a converts the signal based on the sound source signal DIa into amplified signals DOXPa and DOXNa as sound signals, and outputs them to the output terminals 101 and 102, respectively. As a result, the sound corresponding to the amplified signals DOXPa and DOXNa is output from the sound reproduction device 3a. In addition, when the signal input from the input terminal 103 is a test signal TST, the test signal TST is converted into amplified signals DOXPa and DOXNa, and outputs them to the output terminals 101 and 102, respectively.

[0215] For example, the sound reproduction device 3a may be a speaker or a buzzer. The sound output from the sound reproduction device 3a may be a sound imitating a human voice, a mechanical warning sound, an effect sound, or other various sounds.

[0216] like Fig.25 As shown, in this embodiment, the sound source reproduction circuit 100a includes a modulation circuit 30a and an amplifier circuit 50a. The sound source reproduction circuit 100a may be a semiconductor integrated circuit device of one chip, may be composed of semiconductor integrated circuit devices of multiple chips, or may be composed of at least a part of electronic components other than semiconductor integrated circuit devices.

[0217] The modulation circuit 30a modulates the signal input to the input terminal 103 and outputs the modulation signals DOPa and DONa. Specifically, the modulation circuit 30a includes a digital filter 31a, a Σ-Δ modulation circuit 32a, and a pulse width modulation circuit 33a. The Σ-Δ modulation circuit 32a performs Σ-Δ modulation on the signal DFa after the digital filter 31a performs digital filtering on the signal input to the input terminal 103 and outputs the Σ-Δ modulation signal DSa. The pulse width modulation circuit 33a performs pulse width modulation and outputs the modulation signals DOPa and DONa. When the signal input from the input terminal 103 is a signal based on the sound source signal DIa, the modulation circuit 30a modulates the signal based on the sound source signal DIa and outputs the modulation signals DOPa and DONa. When the signal input from the input terminal 103 is a test signal TST, the test signal TST is modulated and outputs the modulation signals DOPa and DONa. In addition, the detailed processing of the digital filter 31a, the Σ-Δ modulation circuit 32a and the pulse width modulation circuit 33a is the same as the processing of the digital filter 31, the Σ-Δ modulation circuit 32 and the pulse width modulation circuit 33 in any one of the first to fourth embodiments, so their description is omitted.

[0218] The amplifier circuit 50a outputs an amplified signal DOXPa obtained by amplifying the modulation signal DOPa to the output terminal 101, and outputs an amplified signal DOXNa obtained by amplifying the modulation signal DONa to the output terminal 102. Specifically, the amplifier circuit 50a includes two class D amplifiers 51Pa and 51Na, and the class D amplifier 51Pa outputs an amplified signal DOXPa obtained by amplifying the modulation signal DOPa to the output terminal 101, and the class D amplifier 51Na outputs an amplified signal DOXNa obtained by amplifying the modulation signal DONa to the output terminal 102. The output terminal 101 is connected to the terminal P1a of the sound reproduction device 3a, and the output terminal 102 is connected to the terminal P2a of the sound reproduction device 3a, so that the sound reproduction device 3a reproduces the sound of a magnitude corresponding to the voltage difference between the amplified signal DOXPa and the amplified signal DOXNa.

[0219] Therefore, when the semiconductor device 1 inputs a signal based on the sound source signal DIa to the input terminal 103 of the sound source reproduction circuit 100a, the sound reproduction device 3a outputs the desired sound instructed by the sound source reproduction command. In addition, it is preferable that when the semiconductor device 1 inputs the test signal TST to the input terminal 103 of the sound source reproduction circuit 100a, the sound reproduction device 3a outputs a tiny sound that is difficult for human ears to hear.

[0220] In the inspection mode, the inspection circuit 110 of the semiconductor device 1 detects the peak frequency f of the sound reproducing device 3a. peak , based on the detected peak frequency fpeak To determine the state of the sound reproduction device 3a. In addition, in the calibration mode, the inspection circuit 110 detects the peak frequency F of the sound reproduction device 3a. peak , and based on the detected peak frequency F peak Information required for determining the state of the sound reproducing device 3a is generated.

[0221] The inspection circuit 110 includes a test signal generating circuit 60, a determination circuit 61, a memory 62, and a peak frequency detection circuit 70. The test signal generating circuit 60 and the peak frequency detection circuit 70 operate in the inspection mode and the calibration mode, and stop operating in the normal operation mode. In addition, the determination circuit 61 operates in the inspection mode, and stops operating in the normal operation mode and the calibration mode.

[0222] The test signal generation circuit 60 generates a test signal TST whose frequency varies within a preset frequency band. The frequency band in which the test signal generation circuit 60 varies the frequency of the test signal TST can be arbitrarily set by the microcontroller unit 2, and may be, for example, a frequency band of 10 Hz to 3 kHz.

[0223] The peak frequency detection circuit 70 measures the potential difference between the input terminal 93 and the input terminal 94, and detects the peak frequency f which is the frequency of the test signal TST at which the impedance of the sound reproduction device 3a reaches a peak. peak Or peak frequency F peak In addition, the peak frequency detection circuit 70 also detects the frequency of the test signal TST as the peak frequency f peak Or peak frequency F peak The voltage after the potential difference between the input terminal 93 and the input terminal 94 is amplified is the peak voltage v peak Or peak voltage V peak As mentioned above, the peak frequency f peak 、F peak , peak voltage v peak 、V peak It changes according to the temperature of the sound-reproducing device 3a.

[0224] The memory 62 includes a non-volatile memory (not shown) in which table information is stored that associates a plurality of temperatures with a plurality of peak frequencies related to the sound reproduction device 3a. The table information also specifies the correspondence between a plurality of temperatures and a plurality of peak voltages related to the sound reproduction device 3a. In addition, the memory 62 includes a volatile memory (not shown) that stores various temporarily generated data.

[0225] The determination circuit 61 determines the peak frequency f detected by the peak frequency detection circuit 70. peakWhether it is included in the reference frequency range. The reference frequency range is a frequency range determined based on the frequency band of the test signal TST and the temperature information related to the temperature of the sound reproduction device 3a. In this embodiment, the determination circuit 61 obtains the temperature signal output from the temperature sensor 80 as the temperature information, and calculates the reference frequency range based on the obtained temperature signal and the table information stored in the memory 62. In addition, the determination circuit 61 further determines the peak voltage v detected by the peak frequency detection circuit 70. peak The reference voltage range is a voltage range determined based on the frequency band of the test signal TST and the temperature information related to the temperature of the sound reproduction device 3a. The determination circuit 61 calculates the reference voltage range based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62. In addition, in the present embodiment, the determination circuit 61 determines whether the reference voltage range is within the reference voltage range based on the peak frequency f peak Whether it is included in the reference frequency range, the peak voltage v peak The state of the sound reproducing device 3 a such as whether the sound reproducing device 3 a has a malfunction is determined based on the determination result of whether the voltage is within the reference voltage range.

[0226] The temperature sensor 80 detects the temperature and outputs a temperature signal having a magnitude corresponding to the detected temperature. Fig.25 In the embodiment, the temperature sensor 80 is built into the semiconductor device 1 and directly detects the temperature of the semiconductor device 1. The temperature of the semiconductor device 1 and the temperature of the sound reproduction device 3a change similarly depending on the temperature of the semiconductor device 1 and the surroundings of the sound reproduction device 3a, so the temperature of the sound reproduction device 3a is indirectly detected. However, the temperature sensor 80 may be provided inside the sound source reproduction circuit 100a or outside the semiconductor device 1 and near the sound reproduction device 3a to directly detect the temperature of the sound reproduction device 3a.

[0227] The configurations and details of the processing of the test signal generating circuit 60 , the determination circuit 61 , and the peak frequency detecting circuit 70 are the same as those of any of the first to fourth embodiments, and thus description thereof will be omitted.

[0228] The switch 83 switches whether to electrically connect or disconnect the input terminal 93 of the semiconductor device 1 and the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. Specifically, the switch 83 electrically disconnects the input terminal 93 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the input terminal 93 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0229] Similarly, the switch 84 switches whether to electrically connect or disconnect the input terminal 94 of the semiconductor device 1 and the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. Specifically, the switch 84 electrically disconnects the input terminal 94 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the normal operation mode, and electrically connects the input terminal 94 and the peak frequency detection circuit 70 when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode.

[0230] In this way, the peak frequency detection circuit 70 is electrically disconnected from the input terminals 93 and 94 through the switches 83 and 84 in the normal operation mode, and is electrically connected to the input terminals 93 and 94 in the inspection mode and the calibration mode, and measures the potential difference between the output terminal 101 and the output terminal 102 of the sound source reproduction circuit 100a to detect the peak frequency f peak And the peak voltage v peak Or the peak frequency F peak And the peak voltage V peak .

[0231] When receiving a command to read the information of the determination result of the determination circuit 61 from the micro control unit 2, the communication interface circuit 10 obtains the information of the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 can recognize the state of the sound reproduction device 3a based on the information of the determination result and perform various processes corresponding to the state of the sound reproduction device 3a.

[0232] The other structures and functions of the semiconductor device 1 according to the fifth embodiment are the same as those of any of the first to fourth embodiments, and thus description thereof will be omitted.

[0233] The semiconductor device 1 according to the fifth embodiment is configured to allow one sound-reproducing device 3 a to output sound, but may be configured to allow a plurality of sound-reproducing devices to output sound.

[0234] In the fifth embodiment, the terminal P1a of the sound reproduction device 3a is an example of the "first terminal", and the terminal P2a of the sound reproduction device 3 is an example of the "second terminal". In addition, the input terminal 93 of the semiconductor device 1 is an example of the "first input terminal", and the input terminal 94 of the semiconductor device 1 is an example of the "second input terminal". In addition, the modulation signal DOPa is an example of the "first modulation signal", and the modulation signal DONa is an example of the "second modulation signal". In addition, the amplified signal DOXPa is an example of the "first amplified signal", and the amplified signal DOXNa is an example of the "second amplified signal". In addition, the normal operation mode is an example of the "first operation mode", and the inspection mode is an example of the "second operation mode".

[0235] According to the semiconductor device 1 of the fifth embodiment described above, it is possible to determine whether the sound reproducing device 3a may have a failure even if the sound source reproducing circuit 100a that causes the sound reproducing device 3a to output sound is provided outside the semiconductor device 1. In addition, according to the semiconductor device 1 of the fifth embodiment, the same effects as those of any of the semiconductor devices 1 of the first to fourth embodiments are achieved.

[0236] 1-6. Modifications

[0237] In each of the above-mentioned embodiments, the memory 20 storing the sound source data 21-1 to 21-n is built into the semiconductor device 1, but instead of the memory 20, an external memory storing the sound source data 21-1 to 21-n may be connected to the semiconductor device 1, and the semiconductor device 1 reads the sound source data 21-i as the sound source signal DI from the external memory. Alternatively, instead of the memory 20, the microcontroller 2 may have a memory storing the sound source data 21-1 to 21-n built into it, and the microcontroller 2 may read the sound source data 21-i from the memory and send it to the semiconductor device 1 as the sound source signal DI.

[0238] In addition, in each of the above-mentioned embodiments, as the modulation method of the pulse width modulation circuit 33, Figure 2 to Figure 4 For example, the pulse width modulation used to generate the modulation signal DOP is Figure 2 In the same way, the pulse width modulation used to generate the modulation signal DON is Fig.26 In the manner shown. Fig.26 In the example, the modulation signal DON is Figure 2 The signal after the logic level of the modulation signal DOP shown is inverted, the larger the value of the Σ-Δ modulation signal DS is, the shorter the high level time is. For example, when the Σ-Δ modulation signal DS is "-7" in decimal, that is, "1001" in binary, one interval T1 of the modulation signal DON is a low level, and 15 intervals T2 to T16 are high levels. In addition, for example, when the Σ-Δ modulation signal DS is "0" in decimal, that is, "0000" in binary, 8 intervals T1 to T8 of the modulation signal DON are low levels, and 8 intervals T9 to T16 are high levels. In addition, for example, when the Σ-Δ modulation signal DS is "7" in decimal, that is, "0111" in binary, 15 intervals T1 to T15 of the modulation signal DON are low levels, and 1 interval T16 is a high level. Therefore, for example, when the Σ-Δ modulation signal DS is "-7", "0", and "7" in decimal, the difference between the modulation signal DOP and the modulation signal DON is as follows: Fig. 27 shown.

[0239] 2. Electronic devices

[0240] Fig.28 1 is a functional block diagram showing an example of the configuration of an electronic device according to this embodiment using the semiconductor device 1 according to this embodiment.

[0241] like Fig.28 As shown, the electronic device 300 of this embodiment includes a semiconductor device 1, m sound reproduction devices 3-1 to 3-m, a processing unit 310, an operation unit 320, a storage unit 330, and a display unit 340. In addition, the electronic device 300 of this embodiment may be configured to omit or change Fig.28 part of the structural elements, or adding other structural elements.

[0242] The processing unit 310 performs control processing of each unit of the electronic device 300 and various data processing. For example, the processing unit 310 sends various commands to the semiconductor device 1 and controls the operation of the semiconductor device 1. In addition, the processing unit 310 performs various processing corresponding to the operation signal from the operation unit 320, and performs processing of sending display signals for causing the display unit 340 to display various information. For example, the processing unit 310 may also be the aforementioned micro control unit 2.

[0243] The operation unit 320 is an input device composed of operation keys, push button switches, etc., and outputs an operation signal corresponding to the user's operation to the processing unit 310.

[0244] The storage unit 330 stores programs and data for the processing unit 310 to perform various calculations and control processes. The storage unit 330 is implemented by, for example, a hard disk, a floppy disk, MO, MT, various memories, CD-ROM, DVD-ROM, or the like.

[0245] The display unit 340 is a display device composed of an LCD or the like, and displays various information based on an input display signal. LCD is an abbreviation of Liquid Crystal Display. The display unit 340 may also be provided with a touch panel that functions as the operation unit 320.

[0246] In the normal operation mode, the semiconductor device 1 generates a sound signal based on various commands sent from the processing unit 310, and outputs the sound signal to the sound reproduction device 3-1. Thus, the desired sound is output from the sound reproduction device 3-1. The sound reproduction device 3-1 corresponds to the above-mentioned sound reproduction device 3. In addition, in the inspection mode and calibration, the semiconductor device 1 outputs the amplified signals DOXP and DOXN based on the test signal to the sound reproduction device 3-1. Thus, the sound is output from the sound reproduction device 3-1, and it is preferable to output a small sound that is difficult for human ears to hear. That is, it is preferable that the volume reproduced by the sound reproduction device 3-1 in the inspection mode and calibration is smaller than the minimum value of the volume reproduced by the sound reproduction device 3-1 in the normal operation mode. Thus, it is difficult for the user to realize that the semiconductor device 1 is operating in the inspection mode or calibration mode. In addition, it is also possible that the semiconductor device 1 inspects the sound reproduction device 3-1 and sends the inspection result to the processing unit 310, and the processing unit 310 determines whether the sound reproduction device 3-1 has a fault or a fault mode. When a failure occurs in the sound reproduction device 3-1, the processing unit 310 can, for example, cause any of the sound reproduction devices 3-2 to 3-m to reproduce a sound notifying that the failure has occurred in the sound reproduction device 3-1, or can switch the output destination of the sound signal from the sound reproduction device 3-1 to any of the sound reproduction devices 3-2 to 3-m.

[0247] The semiconductor device 1 can generate a signal necessary for detecting a failure of the sound reproducing device 3 - 1 , and thus can realize an electronic device 300 with high reliability.

[0248] As such an electronic device 300, various electronic devices can be considered, for example, warning devices, various household electrical appliances such as rice cookers, IH cooking heaters, vacuum cleaners, washing machines, electronic watches, mobile, laptop, tablet and other personal computers, mobile terminals such as smart phones and mobile phones, digital cameras, inkjet printers and other inkjet ejection devices, routers, switches and other storage area network devices, local area network devices, mobile terminal base station devices, televisions, cameras, video recorders, car navigation devices, real-time clock devices, pagers, electronic notepads, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, anti-theft TV monitors, electronic binoculars, POS terminals, electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasonic diagnostic devices, electronic endoscopes and other medical equipment, fish finders, various measuring equipment, measuring instruments for vehicles, aircraft, ships, etc., flight simulators, head-mounted displays, motion search, motion tracking, motion controllers, pedestrian autonomous navigation devices, etc.

[0249] Fig.293 is a diagram showing a configuration example of a warning device 300A as an example of an electronic device 300. Fig.29 In, with Fig.28 The same components are denoted by the same reference numerals. Fig.29 The warning device 300A shown is mounted on a vehicle 400. The sound reproducing device 3-1 is a speaker, and the sound reproducing devices 3-2 to 3-5 are buzzers.

[0250] The processing unit 310 sends various sound reproduction commands to the semiconductor device 1 based on signals from various sensors (not shown). The various sounds include, for example, sounds imitating human voices for notifying abnormalities of the brakes, engine oil, power steering, brake override system, etc., driving with half doors, wobbling driving, driving with the parking brake not released, not wearing seat belts, approach of the vehicle ahead, etc., warning sounds, and effect sounds for notifying turn signals, danger, reversing, etc.

[0251] The semiconductor device 1 generates a sound signal based on a part of a plurality of sound source data corresponding to various sounds and outputs it to the sound reproduction device 3-1 based on a command from the processing unit 310. Alternatively, the semiconductor device 1 may check the sound reproduction device 3-1 and send the check result to the processing unit 310, and the processing unit 310 may determine whether the sound reproduction device 3-1 has a fault or a fault mode. When a fault occurs in the sound reproduction device 3-1, the processing unit 310 may, for example, cause any one of the sound reproduction devices 3-2 to 3-5 to reproduce a sound notifying that the sound reproduction device 3-1 has a fault, or may switch the output destination of the sound signal from the sound reproduction device 3-1 to any one of the sound reproduction devices 3-2 to 3-5.

[0252] The semiconductor device 1 can generate a signal necessary for detecting a failure of the sound reproducing device 3 - 1 , and thus can realize a highly reliable warning device 300A.

[0253] In addition, the electronic device 300 is not limited to Fig.28 The structure shown, for example, may also have Fig.25 In the semiconductor device 1 and the sound source reproduction circuit 100a of the fifth embodiment shown in the figure, the semiconductor device 1 instructs the sound source reproduction circuit 100a to cause any of the sound reproduction devices 3-1 to 3-m to output sound. Alternatively, the electronic device 300 may include Fig.30 In the semiconductor device 1 and the sound source reproducing circuit 100 a shown, the semiconductor device 1 causes the sound reproducing device 3 to output sound, and instructs the sound source reproducing circuit 100 a to cause another sound reproducing device 3 a to output sound.

[0254] exist Fig.30 In, with Fig.25The same components are denoted by the same reference numerals. Fig.30 The structure and function of the sound source reproduction circuit 100a are similar to those of Fig.25 The semiconductor device 1 is connected to the sound source reproduction circuit 100a and the sound reproduction devices 3 and 3a. Specifically, the output terminal 91 of the semiconductor device 1 is connected to the terminal P1 of the sound reproduction device 3, and the output terminal 92 of the semiconductor device 1 is connected to the terminal P2 of the sound reproduction device 3. The output terminal 95 of the semiconductor device 1 is connected to the input terminal 103 of the sound source reproduction circuit 100a, the input terminal 93 of the semiconductor device 1 and the output terminal 101 of the sound source reproduction circuit 100a are connected to the terminal P1a of the sound reproduction device 3a, and the input terminal 94 of the semiconductor device 1 and the output terminal 102 of the sound source reproduction circuit 100a are connected to the terminal P2a of the sound reproduction device 3a.

[0255] The semiconductor device 1 includes a communication interface circuit 10, a memory 20, a temperature sensor 80, switches 81, 82, 83, 84, 85, 86, a sound source reproducing circuit 100, and a test circuit 110. The semiconductor device 1 may be a semiconductor integrated circuit device of one chip, may be composed of semiconductor integrated circuit devices of multiple chips, and may be at least partially composed of electronic components other than semiconductor integrated circuit devices.

[0256] When receiving a command to switch the operation mode of the semiconductor device 1 to the normal operation mode, the inspection mode, or the calibration mode, the communication interface circuit 10 generates a control signal for switching the connection of the switches 81, 82, 83, 84, 85, and 86 according to the operation mode. In addition, for example, when receiving a sound source reproduction command for causing the sound reproduction device 3 to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the sound source reproduction circuit 100 as a sound source signal DI, and instructs the sound source reproduction circuit 100 to reproduce by the sound reproduction device 3. In addition, when receiving a sound source reproduction command for causing the sound reproduction device 3a to reproduce the sound source data 21-i, the communication interface circuit 10 reads the sound source data 21-i from the memory 20 and inputs it to the input terminal 103 of the sound source reproduction circuit 100a via the switch 85 and the output terminal 95, and instructs the sound source reproduction circuit 100a to reproduce by the sound reproduction device 3a. The sound source data 21-i is any one of the sound source data 21-1 to 21-n stored in the memory 20. In addition, for example, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i being reproduced by the sound reproduction device 3, it instructs the sound source reproduction circuit 100 to stop the reproduction. In addition, when the communication interface circuit 10 receives a sound source stop command for the sound source data 21-i being reproduced by the sound reproduction device 3a, it instructs the sound source reproduction circuit 100a to stop the reproduction. In addition, for example, when the communication interface circuit 10 receives various setting commands related to the sound source reproduction of the sound source reproduction circuit 100, it performs various settings on the sound source reproduction circuit 100. In addition, when the communication interface circuit 10 receives various setting commands related to the sound source reproduction of the sound source reproduction circuit 100a, it performs various settings on the sound source reproduction circuit 100a.

[0257] The switch 85 outputs either a signal based on the sound source signal DIa or a test signal TST to the output terminal 95 in accordance with a control signal output from the communication interface circuit 10. Specifically, the switch 85 outputs a signal based on the sound source signal DIa to the output terminal 95 in the normal operation mode, and outputs the test signal TST to the output terminal 95 in the inspection mode or the calibration mode. The signal based on the sound source signal DIa may be the sound source signal DIa itself, or may be a signal obtained by subjecting the sound source signal DIa to some processing.

[0258] The switch 86 outputs either a signal based on the sound source signal DI or a test signal TST to the sound source reproduction circuit 100 in accordance with a control signal output from the communication interface circuit 10. Specifically, the switch 86 outputs a signal based on the sound source signal DI to the sound source reproduction circuit 100 in the normal operation mode, and outputs the test signal TST to the sound source reproduction circuit 100 in the inspection mode or the calibration mode. The signal based on the sound source signal DI may be the sound source signal DI itself, or may be a signal obtained by performing some processing on the sound source signal DI.

[0259] The sound source reproduction circuit 100, in the normal operation mode, converts a signal based on the input sound source signal DI into amplified signals DOXP and DOXN, and outputs the amplified signals DOXP and DOXN to the output terminals 91 and 92, respectively. Thus, sounds corresponding to the amplified signals DOXP and DOXN are output from the sound reproduction device 3. In addition, the sound source reproduction circuit 100, in the inspection mode or the calibration mode, converts the input test signal TST into amplified signals DOXP and DOXN, and outputs them to the output terminals 91 and 92, respectively.

[0260] For example, the sound reproduction devices 3 and 3a may be speakers or buzzers. The sounds outputted from the sound reproduction devices 3 and 3a may be sounds imitating human speech, mechanical warning sounds, effect sounds, and other sounds.

[0261] like Fig.30 As shown, the sound source reproduction circuit 100 includes a modulation circuit 30 and an amplifier circuit 50. The modulation circuit 30 modulates the input signal and outputs modulation signals DOP and DON. Specifically, the modulation circuit 30 includes a digital filter 31, a Σ-Δ modulation circuit 32, and a pulse width modulation circuit 33. The Σ-Δ modulation circuit 32 performs Σ-Δ modulation on the signal DF after digital filtering of the signal input to the digital filter 31 and outputs the Σ-Δ modulation signal DS, and the pulse width modulation circuit 33 performs pulse width modulation and outputs the modulation signals DOP and DON. The modulation circuit 30 modulates the signal based on the input sound source signal DI in the normal operation mode and outputs the modulation signals DOP and DON. In the inspection mode or calibration mode, the modulation circuit 30 modulates the input test signal TST and outputs the modulation signals DOP and DON. In addition, the detailed processing of the digital filter 31, the Σ-Δ modulation circuit 32 and the pulse width modulation circuit 33 is the same as the processing of the digital filter 31, the Σ-Δ modulation circuit 32 and the pulse width modulation circuit 33 in any one of the first to fourth embodiments, so their description is omitted.

[0262] The amplifier circuit 50 outputs an amplified signal DOXP obtained by amplifying the modulation signal DOP to an output terminal 91, and outputs an amplified signal DOXN obtained by amplifying the modulation signal DON to an output terminal 92. Specifically, the amplifier circuit 50 includes two class D amplifiers 51P and 51N, and the class D amplifier 51P outputs an amplified signal DOXP obtained by amplifying the modulation signal DOP to an output terminal 91, and the class D amplifier 51N outputs an amplified signal DOXN obtained by amplifying the modulation signal DON to an output terminal 92. The output terminal 91 is connected to the terminal P1 of the sound reproduction device 3, and the output terminal 92 is connected to the terminal P2 of the sound reproduction device 3, so that the sound reproduction device 3 reproduces a sound of a magnitude corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN.

[0263] Therefore, when a signal based on the sound source signal DI is input to the sound source reproduction circuit 100, the sound reproduction device 3 outputs the desired sound indicated by the sound source reproduction command. In addition, when the test signal TST is input to the sound source reproduction circuit 100, the sound reproduction device 3 preferably outputs a tiny sound that is difficult for human ears to hear.

[0264] The switch 81 switches whether the output terminal 91 of the semiconductor device 1 is electrically connected to or disconnected from the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. The switch 82 switches whether the output terminal 92 of the semiconductor device 1 is electrically connected to or disconnected from the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. The switch 83 switches whether the input terminal 93 of the semiconductor device 1 is electrically connected to or disconnected from the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10. The switch 84 switches whether the input terminal 94 of the semiconductor device 1 is electrically connected to or disconnected from the peak frequency detection circuit 70 according to the control signal output from the communication interface circuit 10.

[0265] Specifically, when the operation mode of the semiconductor device 1 is the normal operation mode, the switches 81 and 82 electrically disconnect the output terminals 91 and 92 from the peak frequency detection circuit 70, and the switches 83 and 84 electrically disconnect the input terminals 93 and 94 from the peak frequency detection circuit 70. In addition, when the operation mode of the semiconductor device 1 is the inspection mode or the calibration mode, the switches 81 and 82 electrically connect the output terminals 91 and 92 to the peak frequency detection circuit 70, and the switches 83 and 84 electrically disconnect the input terminals 93 and 94 from the peak frequency detection circuit 70, or the switches 83 and 84 electrically connect the input terminals 93 and 94 to the peak frequency detection circuit 70, and the switches 81 and 82 electrically disconnect the output terminals 91 and 92 from the peak frequency detection circuit 70. That is, in the inspection mode or the calibration mode, switches 81 and 82 are exclusively connected to switches 83 and 84. When switches 81 and 82 are connected, switches 83 and 84 are disconnected, and when switches 83 and 84 are connected, switches 81 and 82 are disconnected.

[0266] In the test mode, the test circuit 110 detects the peak frequency f of the sound reproduction device 3 or 3a. peak , based on the detected peak frequency f peak Determine the state of the sound reproduction device 3, 3a. In the calibration mode, the inspection circuit 110 detects the peak frequency F of the sound reproduction device 3, 3a. peak , based on the detected peak frequency F peak Information required for determining the status of the sound reproducing device 3 or 3a is generated.

[0267] The inspection circuit 110 includes a test signal generating circuit 60, a determination circuit 61, a memory 62, and a peak frequency detection circuit 70. The test signal generating circuit 60 and the peak frequency detection circuit 70 operate in the inspection mode and the calibration mode, and stop operating in the normal operation mode. In addition, the determination circuit 61 operates in the inspection mode, and stops operating in the normal operation mode and the calibration mode.

[0268] The test signal generation circuit 60 generates a test signal TST whose frequency varies within a preset frequency band. The frequency band in which the test signal generation circuit 60 varies the frequency of the test signal TST can be arbitrarily set by the microcontroller unit 2, and may be, for example, a frequency band of 10 Hz to 3 kHz.

[0269] When switches 81 and 82 are turned on, the peak frequency detection circuit 70 measures the potential difference between the output terminal 91 and the output terminal 92, and detects the peak frequency f which is the frequency of the test signal TST at which the impedance of the sound reproduction device 3 reaches a peak. peak Or peak frequency F peak In addition, the peak frequency detection circuit 70 also detects the frequency of the test signal TST as the peak frequency fpeak Or peak frequency F peak The voltage after the potential difference between the output terminal 91 and the output terminal 92 is amplified is the peak voltage v peak Or peak voltage V peak When switches 83 and 84 are turned on, the peak frequency detection circuit 70 measures the potential difference between input terminal 93 and input terminal 94, and detects the frequency of the test signal TST at which the impedance of the sound reproduction device 3a reaches a peak, that is, the peak frequency f peak Or peak frequency F peak In addition, when switches 83 and 84 are turned on, the peak frequency detection circuit 70 also detects the frequency of the test signal TST as the peak frequency f peak Or peak frequency F peak The voltage after the potential difference between the input terminal 93 and the input terminal 94 is amplified is the peak voltage v peak Or peak voltage V peak As mentioned above, the peak frequency f peak 、F peak , peak voltage v peak 、V peak It changes according to the temperature of the sound-reproducing device 3a.

[0270] The memory 62 includes a non-volatile memory (not shown) in which table information is stored that associates a plurality of temperatures with a plurality of peak frequencies related to the sound reproduction device 3, 3a. The table information also specifies the correspondence between a plurality of temperatures and a plurality of peak voltages related to the sound reproduction device 3, 3a. In addition, the memory 62 includes a volatile memory (not shown) that stores various temporarily generated data.

[0271] The determination circuit 61 determines the peak frequency f detected by the peak frequency detection circuit 70. peak The reference frequency range is determined based on the frequency band of the test signal TST and the temperature information related to the temperature of the sound reproduction device 3, 3a. In this embodiment, the determination circuit 61 obtains the temperature signal output from the temperature sensor 80 as the temperature information, and calculates the reference frequency range based on the obtained temperature signal and the table information stored in the memory 62. In addition, the determination circuit 61 further determines the peak voltage v detected by the peak frequency detection circuit 70. peak The reference voltage range is a voltage range determined based on the frequency band of the test signal TST and the temperature information related to the temperature of the sound reproduction device 3, 3a. The determination circuit 61 calculates the reference voltage range based on the temperature signal output from the temperature sensor 80 and the table information stored in the memory 62. In addition, in the present embodiment, the determination circuit 61 calculates the reference voltage range based on the peak frequency fpeak Whether it is included in the reference frequency range, the peak voltage v peak The state of the sound reproducing device 3, 3a, such as whether the sound reproducing device 3, 3a has a fault, is determined based on the determination result of whether the voltage is within the reference voltage range.

[0272] The temperature sensor 80 detects the temperature and outputs a temperature signal having a magnitude corresponding to the detected temperature. Fig.30 In the embodiment, the temperature sensor 80 is built into the semiconductor device 1 to directly detect the temperature of the semiconductor device 1. The temperature of the semiconductor device 1 and the temperature of the sound reproduction device 3, 3a vary in the same manner depending on the temperature of the semiconductor device 1 and the surrounding areas of the sound reproduction device 3, 3a. Therefore, the temperature of the sound reproduction device 3, 3a is detected indirectly. However, the temperature sensor 80 may be provided outside the semiconductor device 1 and near the sound reproduction device 3 to directly detect the temperature of the sound reproduction device 3. In addition, a temperature sensor different from the temperature sensor 80 may be provided inside the sound source reproduction circuit 100a and near the sound reproduction device 3a to directly detect the temperature of the sound reproduction device 3a. In this case, the determination circuit 61 determines the peak frequency f detected when the switches 83, 84 are turned on. peak When determining whether the frequency is included in the reference frequency range, a temperature signal output from a temperature sensor different from the temperature sensor 80 may be obtained as the temperature information.

[0273] The configurations and details of the processing of the test signal generating circuit 60 , the determination circuit 61 , and the peak frequency detecting circuit 70 are the same as those of any of the first to fourth embodiments, and thus description thereof will be omitted.

[0274] When receiving a command to read the information of the determination result of the determination circuit 61 from the micro control unit 2, the communication interface circuit 10 obtains the information of the determination result from the determination circuit 61 and transmits it to the micro control unit 2. The micro control unit 2 can recognize the state of the sound reproduction device 3, 3a based on the information of the determination result and perform various processes corresponding to the state of the sound reproduction device 3, 3a.

[0275] Fig.30 The other configurations and functions of the semiconductor device 1 shown are the same as those of any of the first to fifth embodiments, and thus descriptions thereof are omitted.

[0276] In addition, the terminal P1 of the sound reproduction device 3 is an example of the “first terminal”, and the terminal P2 of the sound reproduction device 3 is an example of the “second terminal”. In addition, the output terminal 91 of the semiconductor device 1 is an example of the “first output terminal”, and the output terminal 92 of the semiconductor device 1 is an example of the “second output terminal”. In addition, the modulation signal DOP obtained by modulating the signal based on the sound source signal DI is an example of the “first modulation signal”, and the modulation signal DON obtained by modulating the signal based on the sound source signal DI is an example of the “second modulation signal”. In addition, the modulation signal DOP obtained by modulating the test signal TST is an example of the “third modulation signal”, and the modulation signal DON obtained by modulating the test signal TST is an example of the “fourth modulation signal”. In addition, the amplified signal DOXP obtained by amplifying the modulation signal DOP obtained by modulating the signal based on the sound source signal DI is an example of the “first amplified signal”, and the amplified signal DOXN obtained by amplifying the modulation signal DON obtained by modulating the signal based on the sound source signal DI is an example of the “second amplified signal”. In addition, the amplified signal DOXP obtained by amplifying the modulation signal DOP obtained by modulating the test signal TST is an example of the "third amplified signal", and the amplified signal DOXN obtained by amplifying the modulation signal DON obtained by modulating the test signal TST is an example of the "fourth amplified signal". In addition, the normal operation mode is an example of the "first operation mode", and the inspection mode is an example of the "second operation mode".

[0277] In addition, Fig.30 In the example, the semiconductor device 1 instructs one sound source reproduction circuit 100a to cause the sound reproduction device 3a to output sound, but it may also instruct a plurality of sound source reproduction circuits 100a to cause a plurality of sound reproduction devices 3a to output sound. Fig.29 In the illustrated warning device 300A, the semiconductor device 1 can cause at least one of the sound reproducing devices 3-1 to 3-5 to output sound, and instruct one or more sound source reproducing circuits 100a to cause at least one of the sound reproducing devices 3-1 to 3-5 to output sound.

[0278] The present invention is not limited to the present embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0279] The above-mentioned embodiments and modifications are merely examples, and the present invention is not limited thereto. For example, the embodiments and modifications may be appropriately combined.

[0280] The present invention includes structures that are substantially the same as the structures described in the embodiments, such as structures with the same functions, methods and results, or structures with the same purposes and effects. In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that play the same role and effect as the structures described in the embodiments, or structures that can achieve the same purpose. In addition, the present invention includes structures that add known technology to the structures described in the embodiments.

[0281] The following contents are derived from the above-mentioned embodiments and modifications.

[0282] One embodiment of a semiconductor device comprises: a first output terminal connected to a first terminal of a sound reproduction device; a second output terminal connected to a second terminal of the sound reproduction device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulation signal and a second modulation signal; a test signal generation circuit that modulates a test signal whose frequency varies in a preset frequency band in a second operation mode to generate a third modulation signal and a fourth modulation signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to the first output terminal in the first operation mode, and outputs a second amplified signal obtained by amplifying the second modulation signal to the second output terminal. a large signal, which outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal in the second operation mode, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit, which measures a potential difference between the first output terminal and the second output terminal in the second operation mode, and detects a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproduction device reaches a peak value; and a determination circuit, which determines in the second operation mode whether the peak frequency is included in a reference frequency range, the reference frequency range being determined based on the frequency band of the test signal and information related to the temperature of the sound reproduction device, i.e., temperature information.

[0283] According to the semiconductor device, in the first operation mode, the amplifier circuit outputs the first amplified signal obtained by amplifying the first modulated signal based on the sound source signal to the first output terminal, and outputs the second amplified signal obtained by amplifying the second modulated signal based on the sound source signal to the second output terminal, thereby the sound reproduction device can reproduce the sound. On the other hand, in the second operation mode, the amplifier circuit outputs the third amplified signal obtained by amplifying the third modulated signal based on the test signal to the first output terminal, and outputs the fourth amplified signal obtained by amplifying the fourth modulated signal based on the test signal to the second output terminal, thereby the peak frequency detection circuit can measure the potential difference between the first output terminal and the second output terminal, and detect the peak frequency at which the impedance of the sound reproduction device reaches a peak value. Furthermore, the determination circuit determines whether the peak frequency is included in the reference frequency range, and for example, when the peak frequency is not included in the reference frequency range, it can be determined that the sound reproduction device may have a fault. The reference frequency range is determined based on the frequency band of the test signal and the temperature information of the sound reproduction device, and therefore changes appropriately according to the temperature of the sound reproduction device. Therefore, according to the semiconductor device, even if the temperature changes, the accuracy of the fault determination of the sound reproduction device can be maintained.

[0284] In addition, in the semiconductor device, the amplifier circuit is used for generating the first amplified signal and the second amplified signal for causing the sound reproducing device to reproduce the sound in the first operation mode, and generating the third amplified signal and the fourth amplified signal required for detecting the peak frequency in the second operation mode. Therefore, according to the semiconductor device, it is possible to generate the signal required for detecting a failure of the sound reproducing device by a small-scale circuit.

[0285] In one embodiment of the semiconductor device, the determination circuit may obtain a temperature signal output from a temperature sensor as the temperature information, and calculate the reference frequency range based on the obtained temperature signal and table information that corresponds multiple temperatures related to the sound reproduction device and multiple peak frequencies.

[0286] According to the semiconductor device, it is possible to calculate an appropriate reference frequency range corresponding to the temperature of the sound reproduction device based on the temperature signal output from the temperature sensor and the table information that associates a plurality of temperatures with a plurality of peak frequencies. Therefore, according to the semiconductor device, the accuracy of the fault determination of the sound reproduction device can be maintained even if the temperature changes.

[0287] In one embodiment of the semiconductor device, the determination circuit may acquire a temperature signal output from a temperature sensor as the temperature information, and calculate the reference frequency range based on the acquired temperature signal and information of a relationship between temperature and the peak frequency.

[0288] According to the semiconductor device, an appropriate reference frequency range corresponding to the temperature of the sound reproduction device can be calculated based on the temperature signal output from the temperature sensor and the information of the relationship between the temperature and the peak frequency. Therefore, according to the semiconductor device, the accuracy of the fault determination of the sound reproduction device can be maintained even if the temperature changes.

[0289] In one embodiment of the semiconductor device, the temperature information may be information of a temperature range for ensuring the operation of the sound reproduction device, and the reference frequency range is a frequency range consisting of a reference frequency block including the peak frequency corresponding to the reference temperature among a plurality of frequency blocks obtained by dividing a specified frequency range, and frequency blocks before and after the reference frequency block, and the frequency range includes the range of the peak frequency corresponding to the temperature range.

[0290] In the semiconductor device, the reference frequency range is a frequency range including a range of peak frequencies corresponding to a temperature range in which the operation of the sound reproduction device is ensured, which is composed of a reference frequency block including a peak frequency corresponding to a reference temperature and frequency blocks before and after the reference frequency block. Therefore, even if the peak frequency changes due to a change in the temperature of the sound reproduction device, the detected peak frequency is included in the reference frequency range. Therefore, according to the semiconductor device, the possibility of erroneously determining that a failure has occurred when the sound reproduction device is normal is reduced.

[0291] In one embodiment of the semiconductor device, the temperature information may be information about a temperature range for ensuring the operation of the sound reproduction device, and the reference frequency range may be a frequency range of a reference frequency block including a range of peak frequencies corresponding to the temperature range among a plurality of frequency blocks obtained by dividing a specified frequency range.

[0292] In the semiconductor device, since the reference frequency range is a frequency range of a reference frequency block including a range of peak frequencies corresponding to a temperature range in which the operation of the sound reproduction device is guaranteed, even if the peak frequency changes due to a change in the temperature of the sound reproduction device, the detected peak frequency is included in the reference frequency range. Therefore, according to the semiconductor device, the possibility of erroneously determining that a failure has occurred when the sound reproduction device is normal is reduced.

[0293] In one embodiment of the semiconductor device, it may be that, in the second operation mode, the peak frequency detection circuit also detects a peak voltage, wherein the peak voltage is a voltage obtained by amplifying the potential difference between the first output terminal and the second output terminal when the frequency of the test signal is the peak frequency, and in the second operation mode, the determination circuit also determines whether the peak voltage is included in a reference voltage range, wherein the reference voltage range is determined based on the frequency band of the test signal and the temperature information.

[0294] In the semiconductor device, the determination circuit further determines whether the peak voltage is included in the reference voltage range. For example, when the peak voltage is not included in the reference voltage range, it can be determined that the sound reproduction device may have failed. The reference voltage range is determined based on the frequency band of the test signal and the temperature information of the sound reproduction device, and thus changes appropriately according to the temperature of the sound reproduction device. Therefore, even if the peak frequency is included in the reference frequency range, if the peak voltage is not included in the reference voltage range, the determination circuit can determine that the sound reproduction device may have failed. Therefore, according to the semiconductor device, the possibility of erroneously determining that the sound reproduction device is normal when the sound reproduction device may have failed can be reduced.

[0295] In one aspect of the semiconductor device, in the second operation mode, the peak frequency detection circuit may detect the peak frequency by measuring a time when a potential difference between the first output terminal and the second output terminal is maximum.

[0296] According to this semiconductor device, when the impedance of the sound reproduction device reaches a peak, the potential difference between the first output terminal and the second output terminal also reaches a peak. Therefore, the peak frequency detection circuit can detect the peak frequency by measuring the time when the potential difference between the first output terminal and the second output terminal reaches a maximum.

[0297] In one embodiment of the semiconductor device, the peak frequency detection circuit may include: a differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input; an A / D conversion circuit to convert the output voltage of the differential low-pass filter into a digital signal; and a peak time measurement circuit to measure the time when the potential difference between the first output terminal and the second output terminal is maximum based on the digital signal.

[0298] According to this semiconductor device, the differential low-pass filter reduces the high-frequency noise component superimposed on the third amplified signal and the fourth amplified signal by modulating the test signal, the A / D conversion circuit converts the output voltage of the differential low-pass filter into a digital signal, and the peak time measurement circuit can easily perform high-precision measurement.

[0299] In one aspect of the semiconductor device, a cutoff frequency of the differential low-pass filter may be higher than a maximum frequency of the frequency band.

[0300] According to this semiconductor device, since the cutoff frequency of the differential low-pass filter is higher than the maximum frequency of the frequency band in which the frequency of the test signal changes, the frequency components included in the frequency band are not attenuated by the differential low-pass filter, and the peak time measurement circuit can perform high-precision measurement.

[0301] Another embodiment of a semiconductor device is connected to a sound source reproduction circuit, the sound source reproduction circuit comprising: an input terminal; a modulation circuit that modulates a signal input to the input terminal and outputs a first modulation signal and a second modulation signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to a first terminal of a sound reproduction device, and outputs a second amplified signal obtained by amplifying the second modulation signal to a second terminal of the sound reproduction device, the semiconductor device comprising: a first input terminal connected to the first terminal of the sound reproduction device; a second input terminal connected to the second terminal of the sound reproduction device; an output terminal connected to the input terminal of the sound source reproduction circuit; and a switch that, in a first operation mode, outputs a first amplified signal obtained by amplifying the first modulation signal to a first terminal of the sound reproduction device, and outputs a second amplified signal obtained by amplifying the second modulation signal to a second terminal of the sound reproduction device. A signal based on a sound source signal is output to the output terminal, and in a second action mode, a test signal whose frequency is changed within a preset frequency band is output to the output terminal; a test signal generating circuit, which outputs the test signal to the switch in the second action mode; a peak frequency detecting circuit, which measures the potential difference between the first input terminal and the second input terminal in the second action mode, and detects the frequency of the test signal at which the impedance of the sound reproduction device reaches a peak, i.e., the peak frequency; and a determination circuit, which determines in the second action mode whether the peak frequency is included in a reference frequency range, wherein the reference frequency range is determined based on the frequency band of the test signal and information related to the temperature of the sound reproduction device, i.e., temperature information.

[0302] According to the semiconductor device, in the first operation mode, the amplifier circuit of the sound source reproduction circuit outputs the first amplified signal obtained by amplifying the first modulated signal based on the sound source signal to the first output terminal, and outputs the second amplified signal obtained by amplifying the second modulated signal based on the sound source signal to the second output terminal, thereby the sound reproduction device can reproduce the sound. On the other hand, in the second operation mode, the amplifier circuit of the sound source reproduction circuit outputs the second amplified signal obtained by amplifying the first modulated signal based on the test signal to the first output terminal, and outputs the second amplified signal obtained by amplifying the second modulated signal based on the test signal to the second output terminal, thereby the peak frequency detection circuit can measure the potential difference between the first output terminal and the second output terminal of the sound source reproduction circuit, and detect the peak frequency at which the impedance of the sound reproduction device reaches a peak. Furthermore, the determination circuit determines whether the peak frequency is included in the reference frequency range, and for example, when the peak frequency is not included in the reference frequency range, it can be determined that the sound reproduction device may have a fault. The reference frequency range is determined based on the frequency band of the test signal and the temperature information of the sound reproduction device, and thus changes appropriately according to the temperature of the sound reproduction device. Therefore, according to this semiconductor device, when the external sound source reproducing circuit causes the sound reproducing device to output sound, even if the temperature changes, the accuracy of the failure determination of the sound reproducing device can be maintained.

[0303] One embodiment of an electronic device includes one embodiment of the semiconductor device and the sound reproduction device.

[0304] According to this electronic device, since the semiconductor device capable of generating a signal necessary for detecting a failure of the sound reproducing device is provided, reliability can be improved.

[0305] In one aspect of the electronic device, the volume reproduced by the sound reproduction device in the second operation mode may be smaller than a minimum value of the volume reproduced by the sound reproduction device in the first operation mode.

[0306] According to this electronic device, the sound output from the sound reproduction device in the second operation mode is a subtle sound that is difficult for a human to hear, so that the user can be less aware that the semiconductor device is operating in the second operation mode.

[0307] Another embodiment of the electronic device comprises: a first output terminal connected to a first terminal of a sound reproduction device; a second output terminal connected to a second terminal of the sound reproduction device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulation signal and a second modulation signal, and modulates a test signal whose frequency is changed in a predetermined frequency band in a second operation mode to output a third modulation signal and a fourth modulation signal; a test signal generating circuit that outputs the test signal to the modulation circuit in the second operation mode; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to the first output terminal in the first operation mode, and outputs a first amplified signal obtained by amplifying the first modulation signal to the second output terminal. a second amplified signal obtained by amplifying the second modulated signal, outputting a third amplified signal obtained by amplifying the third modulated signal to the first output terminal in the second operation mode, and outputting a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode, and detects a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproduction device reaches a peak value; and a determination circuit that determines whether the peak frequency is included in a reference frequency range in the second operation mode, the reference frequency range being determined based on the frequency band of the test signal and information related to the temperature of the sound reproduction device, i.e., temperature information.

[0308] According to the electronic device, in the first operation mode, the amplifier circuit outputs the first amplified signal after amplifying the first modulated signal based on the sound source signal to the first output terminal, and outputs the second amplified signal after amplifying the second modulated signal based on the sound source signal to the second output terminal, thereby the sound reproduction device can reproduce the sound. On the other hand, in the second operation mode, the amplifier circuit outputs the third amplified signal after amplifying the third modulated signal based on the test signal to the first output terminal, and outputs the fourth amplified signal after amplifying the fourth modulated signal based on the test signal to the second output terminal, thereby the peak frequency detection circuit can measure the potential difference between the first output terminal and the second output terminal, and detect the peak frequency at which the impedance of the sound reproduction device reaches a peak. In addition, the determination circuit determines whether the peak frequency is included in the reference frequency range. For example, if the peak frequency is not included in the reference frequency range, it can be determined that the sound reproduction device may have a fault. The reference frequency range is determined based on the frequency band of the test signal and the temperature information of the sound reproduction device, and therefore changes appropriately according to the temperature of the sound reproduction device. Therefore, according to the electronic device, even if the temperature changes, the accuracy of the fault determination of the sound reproduction device can be maintained.

[0309] In addition, in the electronic device, the amplifier circuit is used for generating the first amplified signal and the second amplified signal for causing the sound reproduction device to reproduce the sound in the first operation mode, and generating the third amplified signal and the fourth amplified signal required for detecting the peak frequency in the second operation mode. Therefore, according to the electronic device, it is possible to generate the signal required for detecting a failure of the sound reproduction device by a small-scale circuit.

Claims

1. A semiconductor device comprising: a first output terminal connected to a first terminal of a sound reproduction device; a second output terminal connected to a second terminal of the sound reproduction device; a modulation circuit that modulates a signal based on the sound source signal in a first operation mode and outputs a first modulation signal and a second modulation signal; a test signal generating circuit that modulates a test signal whose frequency is varied within a preset frequency band in a second operation mode to generate a third modulated signal and a fourth modulated signal; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproducing device reaches a peak value; as well as A determination circuit determines whether the peak frequency is included in a reference frequency range in the second operation mode, the reference frequency range being determined based on the frequency band of the test signal and temperature information which is information related to the temperature of the sound reproducing device.

2. The semiconductor device according to claim 1, wherein The determination circuit acquires a temperature signal output from a temperature sensor as the temperature information, and calculates the reference frequency range based on the acquired temperature signal and table information in which a plurality of temperatures related to the sound reproduction device and a plurality of peak frequencies are associated with each other.

3. The semiconductor device according to claim 1, wherein The determination circuit acquires a temperature signal output from a temperature sensor as the temperature information, and calculates the reference frequency range based on the acquired temperature signal and information of a relational expression between temperature and the peak frequency.

4. The semiconductor device according to claim 1, wherein The temperature information is information about a temperature range within which the sound reproduction device is guaranteed to operate. The reference frequency range is a frequency range consisting of a reference frequency block including the peak frequency corresponding to the reference temperature and frequency blocks before and after the reference frequency block among multiple frequency blocks obtained by dividing the specified frequency range, and the frequency range includes the range of the peak frequency corresponding to the temperature range.

5. The semiconductor device according to claim 1, wherein The temperature information is information about a temperature range within which the sound reproduction device is guaranteed to operate. The reference frequency range is a frequency range of a reference frequency block including the range of the peak frequency corresponding to the temperature range among a plurality of frequency blocks obtained by dividing a predetermined frequency range.

6. The semiconductor device according to claim 1, wherein The peak frequency detection circuit further detects a peak voltage in the second operation mode, wherein the peak voltage is a voltage obtained by amplifying a potential difference between the first output terminal and the second output terminal when the frequency of the test signal is the peak frequency. The determination circuit determines whether the peak voltage is included in a reference voltage range in the second operation mode, and the reference voltage range is determined based on the frequency band of the test signal and the temperature information.

7. The semiconductor device according to claim 1, wherein The peak frequency detection circuit detects the peak frequency by measuring a time when the potential difference between the first output terminal and the second output terminal is maximum in the second operation mode.

8. The semiconductor device according to claim 7, wherein: The peak frequency detection circuit comprises: a differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input; An A / D conversion circuit converts the output voltage of the differential low-pass filter into a digital signal; as well as The peak time measuring circuit measures a time when the potential difference between the first output terminal and the second output terminal is maximum based on the digital signal.

9. The semiconductor device according to claim 8, wherein: The cutoff frequency of the differential low-pass filter is higher than the maximum frequency of the frequency band.

10. A semiconductor device connected to a sound source reproduction circuit, The sound source reproduction circuit includes: an input terminal; a modulation circuit that modulates a signal input to the input terminal and outputs a first modulation signal and a second modulation signal; and an amplifier circuit that outputs a first amplified signal obtained by amplifying the first modulation signal to a first terminal of a sound reproduction device, and outputs a second amplified signal obtained by amplifying the second modulation signal to a second terminal of the sound reproduction device. The semiconductor device comprises: a first input terminal connected to the first terminal of the sound reproduction device; a second input terminal connected to the second terminal of the sound reproduction device; an output terminal connected to the input terminal of the sound source reproduction circuit; a switch that outputs a signal based on a sound source signal to the output terminal in a first operation mode and outputs a test signal having a frequency varied within a preset frequency band to the output terminal in a second operation mode; a test signal generating circuit that outputs the test signal to the switch in the second operation mode; a peak frequency detection circuit that measures a potential difference between the first input terminal and the second input terminal in the second operation mode and detects a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproducing device reaches a peak value; as well as A determination circuit determines whether the peak frequency is included in a reference frequency range in the second operation mode, the reference frequency range being determined based on the frequency band of the test signal and temperature information which is information related to the temperature of the sound reproducing device.

11. An electronic device comprising: The semiconductor device according to any one of claims 1 to 10; and The sound reproduction device.

12. The electronic device according to claim 11, wherein: The volume reproduced by the sound-reproducing device in the second operation mode is smaller than a minimum value of the volume reproduced by the sound-reproducing device in the first operation mode.

13. An electronic device comprising: a first output terminal connected to a first terminal of a sound reproduction device; a second output terminal connected to a second terminal of the sound reproduction device; a modulation circuit that modulates a signal based on a sound source signal in a first operation mode to output a first modulation signal and a second modulation signal, and that modulates a test signal whose frequency is varied in a preset frequency band in a second operation mode to output a third modulation signal and a fourth modulation signal; a test signal generating circuit that outputs the test signal to the modulation circuit in the second operation mode; an amplifier circuit that, in the first operation mode, outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, and outputs a second amplified signal obtained by amplifying the second modulated signal to the second output terminal, and, in the second operation mode, outputs a third amplified signal obtained by amplifying the third modulated signal to the first output terminal, and outputs a fourth amplified signal obtained by amplifying the fourth modulated signal to the second output terminal; a peak frequency detection circuit that measures a potential difference between the first output terminal and the second output terminal in the second operation mode and detects a peak frequency, which is a frequency of the test signal at which the impedance of the sound reproducing device reaches a peak value; as well as A determination circuit determines whether the peak frequency is included in a reference frequency range in the second operation mode, the reference frequency range being determined based on the frequency band of the test signal and temperature information which is information related to the temperature of the sound reproducing device.

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