Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system, and the preparation method of the semiconductor device comprises the steps: firstly obtaining a substrate comprising a stop layer, then forming a semiconductor layer on the stop layer, and then forming a semiconductor cylinder in the semiconductor layer. The semiconductor cylinders are arranged in an array in a first direction and a second direction and extend in a third direction, and the first direction, the second direction and the third direction intersect with one another. And finally, forming a grid line structure extending along the third direction, wherein the grid line structure is positioned between two adjacent rows of semiconductor cylinders in the first direction. The semiconductor layer is formed on the stop layer, so that when the semiconductor cylinder is formed in the semiconductor layer through an etching process, the etching process can be stopped on the stop layer, and the etching uniformity of the semiconductor layer can be improved.

Description

Technical Field

[0001] The present application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and a method for manufacturing the same, and a storage system. Background Art

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in integrated circuits. For example, a storage unit of a dynamic random access memory (DRAM) may include a transistor and a capacitor structure, and the transistor controls the writing or reading of data in the capacitor structure.

[0003] However, in three-dimensional integrated DRAM, a transistor and a capacitor structure constitute a storage unit. In the preparation process, how to improve the etching process is a problem that needs to be solved urgently.

[0004] Application Contents

[0005] The purpose of the present application is to provide a semiconductor device and a method for manufacturing the same, aiming to improve the etching uniformity of forming a semiconductor column.

[0006] In a first aspect, the present application provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0007] obtaining a substrate including a stop layer;

[0008] forming a semiconductor layer on the stop layer;

[0009] forming semiconductor columns in the semiconductor layer, the semiconductor columns are arranged in an array in a first direction and a second direction and extend along a third direction, the first direction, the second direction and the third direction intersecting each other;

[0010] A gate line structure extending along the third direction is formed, and the gate line structure is located between two rows of semiconductor pillars adjacent to each other in the first direction.

[0011] In some embodiments, the step of forming a semiconductor column in the semiconductor layer includes:

[0012] forming a first trench extending along the first direction, and forming a spacer in the first trench, wherein the first trench penetrates the semiconductor layer along the third direction and has the stop layer as a bottom;

[0013] A second trench extending along the second direction is formed, wherein the second trench penetrates the semiconductor layer and the spacer along the third direction to separate the semiconductor layer into a plurality of semiconductor pillars.

[0014] In some embodiments, the semiconductor layer includes amorphous silicon, and the step of forming a gate line structure extending along the third direction includes:

[0015] forming a bottom isolation structure at the bottom of the second trench;

[0016] A channel layer, a first insulating layer, a gate layer and a filling insulating layer are sequentially formed on the sidewalls of the second trench and are located on the bottom isolation structure.

[0017] In some embodiments, the step of forming a gate line structure extending along the third direction further includes:

[0018] A second insulating layer is formed between the sidewall of the semiconductor pillar and the channel layer.

[0019] In some embodiments, the semiconductor layer includes polysilicon, and the step of forming a gate line structure extending along the third direction includes:

[0020] forming a bottom isolation structure at the bottom of the second trench;

[0021] A first insulating layer, a gate layer and a filling insulating layer are sequentially formed on the sidewalls of the second trench and are located on the bottom isolation structure.

[0022] In some embodiments, the method for preparing the semiconductor device further includes:

[0023] Performing ion doping on an end of the semiconductor column away from the stop layer to form a source electrode;

[0024] A capacitor is formed on a side of the semiconductor column facing away from the stop layer.

[0025] In some embodiments, the method for preparing the semiconductor device further includes:

[0026] removing the substrate;

[0027] Performing ion doping on an end of the semiconductor column away from the capacitor to form a drain;

[0028] A bit line connected to the drain is formed.

[0029] In some embodiments, the method for preparing the semiconductor device further includes:

[0030] forming an isolation trench extending along the second direction, wherein the isolation trench penetrates the semiconductor layer and the spacer along the third direction and is located between two adjacent second trenches;

[0031] forming a sacrificial layer in the isolation trench and the second trench;

[0032] removing the sacrificial layer located in the isolation trench;

[0033] forming a shielding structure in the isolation trench;

[0034] The sacrificial layer located in the second trench is removed.

[0035] In some embodiments, the step of forming a gate line structure extending along the third direction further includes:

[0036] Etching the sidewall of the second trench to expand the width of the second trench in the first direction;

[0037] Wherein, the width of the second trench along the first direction is greater than the width of the isolation trench along the first direction.

[0038] In some embodiments, the step of obtaining a substrate including a stop layer comprises:

[0039] obtaining a substrate;

[0040] An oxide layer is formed on the substrate as the stop layer.

[0041] In a second aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0042] A semiconductor structure manufactured by the method for manufacturing a semiconductor device in any of the above embodiments.

[0043] In a third aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0044] Semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction, wherein the first direction, the second direction and the third direction intersect each other;

[0045] a gate line structure extending along the third direction and located between two adjacent rows of semiconductor columns in the first direction;

[0046] Wherein, the semiconductor column includes polycrystalline silicon or amorphous silicon.

[0047] In some embodiments, the semiconductor pillar comprises amorphous silicon, and the semiconductor device further comprises:

[0048] A channel layer, located between the semiconductor column and the gate line structure;

[0049] The first insulating layer is located between the channel layer and the gate line structure.

[0050] In some embodiments, the semiconductor device further comprises:

[0051] The second insulating layer is located between the channel layer and the semiconductor column.

[0052] In a fourth aspect, the present application provides a storage system, including:

[0053] The semiconductor device in any of the above embodiments;

[0054] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

[0055] The present application provides a semiconductor device and a method for manufacturing the same, and a storage system. The method for manufacturing the semiconductor device includes first obtaining a substrate including a stop layer, then forming a semiconductor layer on the stop layer, and then forming a semiconductor column in the semiconductor layer. The semiconductor columns are arranged in an array in a first direction and a second direction and extend along a third direction, and the first direction, the second direction, and the third direction intersect with each other. Finally, a gate line structure extending along the third direction is formed, and the gate line structure is located between two adjacent rows of semiconductor columns in the first direction. Since the semiconductor layer is formed on the stop layer, when the semiconductor column is formed in the semiconductor layer by an etching process, the etching process can stop on the stop layer, thereby improving the etching uniformity of the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0057] Figure 1 is a schematic flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application;

[0058] Figure 2a-2q is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application;

[0059] Figure 3 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0061] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0062] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0063] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0064] This article uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the third direction. The first direction, the second direction, and the third direction intersect with each other, that is, X, Y, and Z intersect with each other, for example, they may be perpendicular to each other, or at a certain angle.

[0065] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0066] See also Figure 1 , Figure 1 is a schematic diagram of a method for preparing a semiconductor device provided in some embodiments of the present application. Figure 2a-2q , Figure 2a-2q is a schematic diagram of the structure of a semiconductor device during the preparation process provided by some embodiments of the present application. Figure 2d yes Figure 2cSchematic diagram of the cross-section structure along A-A1. Figure 2f yes Figure 2e Schematic diagram of the structure along B-B1, Figure 2h yes Figure 2g Schematic diagram of the cross-section structure along C-C1. Figure 2j yes Figure 2i Schematic diagram of the cross-sectional structure along D-D1. Figure 2l yes Figure 2k Schematic diagram of the cross-sectional structure along E-E1. Figure 2n and Figure 2o yes Figure 2m The cross-sectional structure schematic diagram along F-F1. The method for preparing the semiconductor device comprises the following steps S1-S4.

[0067] Step S1: obtaining a substrate 10 including a stop layer 101 .

[0068] See also Figure 2b Taking the preparation of the substrate 10 by oneself as an example, specifically, a substrate 102 may be obtained first, and then an oxide layer may be formed on the substrate 102 as a stop layer 101 to form the substrate 10. The substrate 102 may be a semiconductor substrate, such as a silicon (Si), germanium (Ge), SiGe substrate, etc. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe, etc. The oxide layer may be formed on the substrate 102 by an oxidation process or a deposition process, and the oxide layer may be silicon oxide.

[0069] In some embodiments, the substrate 10 can be directly obtained, for example, the substrate 10 including the stop layer 101 can be directly purchased from a manufacturer.

[0070] Step S2 : forming a semiconductor layer 20 on the stop layer 101 .

[0071] like Figure 2b As shown, a semiconductor layer 20 may be formed on the stop layer 101 by a deposition process. The semiconductor layer 20 may be made of a semiconductor material, such as polycrystalline silicon or amorphous silicon. Figure 2a The schematic diagram of the top view of the semiconductor layer 20 is shown. The substrate 102, the oxide layer and the semiconductor layer 20 may form a silicon on insulator (SOI) structure.

[0072] The deposition process of the semiconductor layer 20 may be, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering and other methods.

[0073] Step S3: forming semiconductor pillars 21 in the semiconductor layer 20, wherein the semiconductor pillars 21 are arranged in an array in a first direction (X) and a second direction (Y) and extend along a third direction (Z), wherein the first direction (X), the second direction (Y) and the third direction (Z) intersect with each other.

[0074] In some embodiments, step S3 may include: 1) referring to Figure 2c and Figure 2d , forming a first trench T1 extending along the first direction (X), and forming a spacer 22 in the first trench T1, wherein the first trench T1 penetrates the semiconductor layer 20 along the third direction (Z) and has the stop layer 101 as the bottom; 2) referring to Figure 2e and Figure 2f , forming a second trench T2 extending along the second direction (Y), wherein the second trench T2 penetrates the semiconductor layer 20 and the spacer 22 along the third direction (Z) to separate the semiconductor layer 20 into a plurality of semiconductor pillars 21.

[0075] Specifically, Figure 2d As shown, the semiconductor layer 20 may be etched to form the first trench T1 and the semiconductor wall 20a, and the etching process stops on the stop layer 101, so the bottom of the first trench T1 is located on the stop layer 101. Before etching, a protective layer 30 and a hard mask layer 40 may be formed on the semiconductor layer 20. The protective layer 30 is used to prevent the top of the semiconductor layer 20 from being damaged during the etching process, and the hard mask layer 40 is patterned to form the first trench T1. The protective layer 30 may include silicon oxide, and the hard mask layer 40 may include silicon nitride.

[0076] Then, the first trench T1 is filled with a spacer 22, which may include but is not limited to any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The patterns of the semiconductor wall 20a and the spacer 22 are as follows: Figure 2c As shown, the semiconductor walls 20 a extend along the first direction (X) and are arranged at intervals along the second direction (Y), and the spacers 22 are formed in other regions of the semiconductor layer 20 except the semiconductor walls 20 a.

[0077] like Figure 2e and Figure 2fAs shown, the semiconductor wall 20 a and the spacer 22 are then etched to form a second trench T2 extending along the second direction (Y), and the second trench T2 separates the semiconductor wall 20 a into a plurality of semiconductor pillars 21 .

[0078] In some embodiments, a height H2 of the second trench T2 in the third direction (Z) may be smaller than a height H1 of the first trench T1 in the third direction (Z).

[0079] Step S4: forming a gate line structure 50 extending along the third direction (Z), wherein the gate line structure 50 is located between two adjacent rows of semiconductor pillars 21 in the first direction (X).

[0080] In some embodiments, the material of the semiconductor layer 20 may include amorphous silicon, that is, the semiconductor pillar 21 may include amorphous silicon. Step S4 may include the following steps: 1) Referring to Figure 2k and Figure 2l , etching the sidewall of the second trench T2 to expand the width of the second trench T2 in the first direction (X) to form a second trench T2'; 2) referring to Figure 2m and Figure 2n , forming a bottom isolation structure 51 at the bottom of the second trench T2'; 3) forming a channel layer 52, a first insulating layer 53, a gate layer 54 and a filling insulating layer 55 on the sidewall of the second trench T2' in sequence on the bottom isolation structure 51. The material of the channel layer 52 may include semiconductor materials, such as silicon (single crystal silicon or polycrystalline silicon), germanium or silicon carbide.

[0081] Specifically, in Figure 2e On the basis of the present invention, the second trench T2 is further etched to expand the width of the second trench T2 in the first direction (X), so as to form a gate line structure 50 in the second trench T2'. The second trench T2' after the width is expanded is as shown in FIG. Figure 2k and Figure 2l As shown. Figure 2m and Figure 2n As shown, a bottom isolation structure 51 is first formed at the bottom of the second trench T2', and then a channel layer 52, a first insulating layer 53, a gate layer 54 and a filling insulating layer 55 are sequentially deposited on the sidewalls of the second trench T2'. The channel layer 52 can be used as a channel, the first insulating layer 53 can be used as a gate insulating layer, and the channel layer 52 and the gate layer 54 can form a transistor. Since the height H2 of the second trench T2' in the third direction (Z) can be less than the height H1 of the first trench T1 in the third direction (Z), a semiconductor layer 20 is still left between the bottom isolation structure 51 and the stop layer 101, and the bottom isolation structure 51 can isolate the gate layer 54 from the semiconductor layer 20.

[0082] Among them, the bottom isolation structure 51 can be a single film layer, such as a silicon oxide layer or a silicon nitride layer. The bottom isolation structure 51 can also be a composite film layer, for example, including a silicon oxide layer and a silicon nitride layer. The materials of the first insulating layer 53 and the filling insulating layer 55 can be one or more of silicon oxide, silicon nitride and silicon oxynitride. The gate layer 54 can be one or more of conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0083] In some embodiments, a second insulating layer (not shown) may be formed between the sidewall of the semiconductor pillar 21 and the channel layer 52. The second insulating layer may isolate the channel layer 52 from the semiconductor pillar 21 to improve the performance of the device. The second insulating layer may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0084] In some other embodiments, the material of the semiconductor layer 20 may include polysilicon, and the semiconductor pillar 21 may be used as a channel without the need to form a channel layer 52. Figure 2o , step S4 may only include: 1) forming a bottom isolation structure 51 at the bottom of the second trench T2'; 2) sequentially forming a first insulating layer 53, a gate layer 54 and a filling insulating layer 55 on the sidewall of the second trench T2'. Therefore, the semiconductor pillar 21 and the gate layer 54 may constitute a transistor, and the semiconductor pillar 21 serves as a channel of the transistor. The bottom isolation structure 51 may isolate the bottom of the semiconductor pillar 21 from the bottom of the gate layer 54 to prevent channel leakage.

[0085] The gate layer 54 may include an anti-diffusion layer 541 (eg titanium nitride) and a metal layer 541 (eg tungsten), and the anti-diffusion layer 541 is located between the first insulating layer 53 and the metal layer 541 .

[0086] See also Figure 2e-2j The method for preparing the semiconductor device may further include the following steps: 1) forming an isolation trench T3 extending along the second direction (Y), wherein the isolation trench T3 penetrates the semiconductor layer 20 and the spacer 22 along the third direction (Z) and is located between two adjacent second trenches T2; 2) forming a sacrificial layer 60 in the isolation trench T3 and the second trench T2; 3) removing the sacrificial layer 60 located in the isolation trench T3; 4) forming a shielding structure 70 in the isolation trench T3; 5) removing the sacrificial layer 60 located in the second trench T2.

[0087] like Figure 2eAs shown, the isolation trench T3 and the second trench T2 can be formed under the same mask, the isolation trench T3 and the second trench T2 can be arranged alternately along the first direction (X), and the length of the second trench T2 along the second direction (Y) can be greater than the length of the isolation trench T3 along the second direction (Y).

[0088] like Figure 2g and Figure 2h As shown, in order to form the shielding structure 70 only in the isolation trench T3, the second trench T2 and the isolation trench T3 are filled with a sacrificial layer 60, and the sacrificial layer 60 may be carbon or spin-on carbon (Spin On Carbon, SOC). Figure 2i and Figure 2j As shown, the sacrificial layer 60 in the isolation trench T3 is then removed, and a shielding structure 70 is formed in the isolation trench T3. The shielding structure 70 may include an insulating layer and a metal layer (not shown) formed in sequence, and the metal layer includes but is not limited to metal tungsten (W), metal cobalt (Co), metal copper (Cu), metal aluminum (Al) or other metal materials. Finally, the sacrificial layer 60 in the second trench T2 is removed, and the above step S4 is performed.

[0089] It should be noted that if Figure 2m As shown, the shielding structure 70 separates a semiconductor pillar 21 located between two rows of second trenches T2' into two sub-semiconductor pillars 21a. Therefore, the gate layer 54 in a gate line structure 50 can control the two rows of sub-semiconductor pillars 21a located on both sides thereof. The annular gate layer 54 can be separated into two rows of gates, and the two rows of gates respectively control the conduction of the two rows of sub-semiconductor pillars 21a on both sides of the gate layer 54.

[0090] In some embodiments, see Figure 2p The method for preparing the semiconductor device may further include: 1) Figure 2n On the basis of, ion doping is performed on the end of the channel layer 52 away from the stop layer 101 to form a source, and then a capacitor 80 connected to the source is formed; 2) the substrate 10 is removed, ion doping is performed on the end of the channel layer 52 away from the capacitor 80 to form a drain 52D, and a bit line 90 connected to the drain 52D is formed.

[0091] In some embodiments, see Figure 2q The method for preparing the semiconductor device may further include: 1) Figure 2o On the basis of, ion doping is performed on the end of the semiconductor pillar 21 away from the stop layer 101 to form a source, and then a capacitor 80 is formed on the side of the semiconductor pillar 21 away from the stop layer 101; 2) the substrate 10 is removed, and ion doping is performed on the end of the semiconductor pillar 21 away from the capacitor 80 array to form a drain 52D, and a bit line 90 connected to the drain 52D is formed.

[0092] The semiconductor pillar 21 may be polysilicon as a channel, and the capacitor 80 may be connected to the source of the semiconductor pillar 21. The method for preparing the semiconductor device may further include annealing the polysilicon of the semiconductor pillar 21 to reduce impurities in the polysilicon channel, thereby better controlling the switching current.

[0093] The method for preparing a semiconductor device provided in an embodiment of the present application first obtains a substrate 10 including a stop layer 101, and then forms a semiconductor layer 20 on the substrate 10. Therefore, the etching process of the first trench T1 during the formation of the semiconductor pillar can be stopped on the stop layer 101, thereby improving the etching uniformity of the first trench T1, reducing the etching difficulty, and improving the etching process window. In addition, the semiconductor pillar can be directly used as a channel and a gate line layer 54 to form a transistor to control the capacitor 80 to store data.

[0094] The present application also provides a semiconductor device, which includes a semiconductor structure prepared by the method for preparing a semiconductor device in any of the above embodiments. For example, the semiconductor structure may include a substrate 10 , that is, a stop layer 101 .

[0095] The present application also provides a semiconductor device, which can be referred to as Figure 2m , Figure 2p and Figure 2q The semiconductor device includes a semiconductor column and a gate line structure 50. The semiconductor columns are arranged in an array in a first direction (X) and a second direction (Y) and extend along a third direction (Z), and the first direction (X), the second direction (Y) and the third direction (Z) intersect each other. The gate line structure 50 extends along the third direction (Z) and is located between two adjacent rows of semiconductor columns in the first direction (X). The semiconductor column includes polycrystalline silicon or amorphous silicon.

[0096] In some embodiments, the semiconductor device can be manufactured by the method for manufacturing a semiconductor device provided in the above embodiments. Figure 2p As shown, the semiconductor pillar 21 includes amorphous silicon, and the semiconductor device further includes a channel layer 52 and a first insulating layer 53 . The channel layer 52 is located between the semiconductor pillar 21 and the gate line structure 50 , and the first insulating layer 53 is located between the channel layer 52 and the gate line structure 50 .

[0097] In some embodiments, the semiconductor device may further include a second insulating layer (not shown), where the second insulating layer is located between the channel layer 52 and the semiconductor pillar 21 .

[0098] In other embodiments, the semiconductor device can be manufactured by the method for manufacturing a semiconductor device provided in the above embodiments. Figure 2q As shown, the semiconductor pillar 21 includes polysilicon, and the semiconductor device further includes a first insulating layer 53 , and the first insulating layer 53 is located between the semiconductor pillar 21 and the gate line structure 50 .

[0099] In the semiconductor device provided in the embodiment of the present application, amorphous silicon can be used as the semiconductor pillar, and a channel layer 52 connected to the gate structure can be formed on the sidewall of the semiconductor pillar. The semiconductor pillar of amorphous silicon can reduce the cost. Polycrystalline silicon can also be directly used as the channel layer 52 to simplify the structure and reduce the cost.

[0100] The semiconductor device can be a memory or a part of a memory. The semiconductor device can be used as a computer memory in a memory system or as a buffer in a memory system.

[0101] In some embodiments, the semiconductor device can be used as an auxiliary in a solid-state drive, which can improve the read and write performance of the solid-state drive. Currently, high-end solid-state drive products mostly choose to embed dynamic random access memory to improve product performance and random read and write speeds. For example, when writing files, especially small files, the small files are processed by the dynamic random access memory and then stored in the flash memory, making the solid-state drive storage more efficient and faster.

[0102] See also Figure 3 , Figure 3 1 is a schematic diagram of the structure of a storage system provided by some embodiments of the present application. The storage system 100 includes a semiconductor device 101 and a controller 102. The semiconductor device 101 may include any semiconductor device in the above embodiments. The semiconductor device 101 may be a memory or a part of a memory. The controller 102 is electrically connected to the semiconductor device 101 and is used to control the semiconductor device 101 to store data. The semiconductor device 101 may perform an operation of storing data based on the control of the controller 102.

[0103] The semiconductor device 101 includes a semiconductor column and a gate line structure. The semiconductor columns are arranged in an array in a first direction and a second direction and extend along a third direction, and the first direction, the second direction and the third direction intersect each other. The gate line structure extends along the third direction and is located between two rows of semiconductor columns adjacent to each other in the first direction. The semiconductor column includes polycrystalline silicon or amorphous silicon.

[0104] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: obtaining a substrate including a stop layer; forming a semiconductor layer on the stop layer; forming semiconductor columns in the semiconductor layer, the semiconductor columns are arranged in an array in a first direction and a second direction and extend along a third direction, the first direction, the second direction and the third direction intersecting each other; A gate line structure extending along the third direction is formed, and the gate line structure is located between two rows of semiconductor pillars adjacent to each other in the first direction.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a semiconductor column in the semiconductor layer comprises: forming a first trench extending along the first direction, and forming a spacer in the first trench, wherein the first trench penetrates the semiconductor layer along the third direction and has the stop layer as a bottom; A second trench extending along the second direction is formed, wherein the second trench penetrates the semiconductor layer and the spacer along the third direction to separate the semiconductor layer into a plurality of semiconductor pillars.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The semiconductor layer includes amorphous silicon, and the step of forming a gate line structure extending along the third direction includes: forming a bottom isolation structure at the bottom of the second trench; A channel layer, a first insulating layer, a gate layer and a filling insulating layer are sequentially formed on the sidewalls of the second trench and are located on the bottom isolation structure.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of forming a gate line structure extending along the third direction further includes: A second insulating layer is formed between the sidewall of the semiconductor pillar and the channel layer.

5. The method for preparing a semiconductor device according to claim 2, characterized in that: The semiconductor layer includes polysilicon, and the step of forming a gate line structure extending along the third direction includes: forming a bottom isolation structure at the bottom of the second trench; A first insulating layer, a gate layer and a filling insulating layer are sequentially formed on the sidewalls of the second trench and are located on the bottom isolation structure.

6. The method for preparing a semiconductor device according to claim 1, wherein: The method for preparing the semiconductor device further includes: Performing ion doping on an end of the semiconductor column away from the stop layer to form a source electrode; A capacitor is formed on a side of the semiconductor column facing away from the stop layer.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The method for preparing the semiconductor device further includes: removing the substrate; Performing ion doping on an end of the semiconductor column away from the capacitor to form a drain; A bit line connected to the drain is formed.

8. The method for preparing a semiconductor device according to claim 2, characterized in that: The method for preparing the semiconductor device further includes: forming an isolation trench extending along the second direction, wherein the isolation trench penetrates the semiconductor layer and the spacer along the third direction and is located between two adjacent second trenches; forming a sacrificial layer in the isolation trench and the second trench; removing the sacrificial layer located in the isolation trench; forming a shielding structure in the isolation trench; The sacrificial layer located in the second trench is removed.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The step of forming a gate line structure extending along the third direction further includes: Etching the sidewall of the second trench to expand the width of the second trench in the first direction; Wherein, the width of the second trench along the first direction is greater than the width of the isolation trench along the first direction.

10. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of obtaining a substrate including a stop layer comprises: obtaining a substrate; An oxide layer is formed on the substrate as the stop layer.

11. A semiconductor device, characterized in that: The semiconductor device comprises: A semiconductor structure manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 10.

12. A semiconductor device, characterized in that: The semiconductor device comprises: Semiconductor pillars are arranged in an array in a first direction and a second direction and extend along a third direction, wherein the first direction, the second direction and the third direction intersect each other; a gate line structure extending along the third direction and located between two adjacent rows of semiconductor columns in the first direction; Wherein, the semiconductor column includes polycrystalline silicon or amorphous silicon.

13. The semiconductor device according to claim 12, characterized in that The semiconductor column comprises amorphous silicon, and the semiconductor device further comprises: A channel layer, located between the semiconductor column and the gate line structure; The first insulating layer is located between the channel layer and the gate line structure.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device further comprises: The second insulating layer is located between the channel layer and the semiconductor column.

15. A storage system, characterized in that: include: The semiconductor device according to claim 11; A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

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