Microelectronic devices and memory devices including vertically spaced transistors and memory devices, and related electronic systems

Abstract

The invention relates to microelectronic devices and memory devices including vertically spaced transistors and memory devices, and related electronic systems. A microelectronic device includes a first transistor structure including a plurality of vertical levels of a channel region; a second transistor structure adjacent to the first transistor structure and including an additional plurality of vertical levels of a channel region; a memory device vertically overlying the first transistor structure and the second transistor structure; a first conductive contact structure contacting the first transistor structure; and a second conductive contact structure contacting the second transistor structure.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application No. 63 / 516,823, filed on July 31, 2023, "MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS" and also claims the benefit of the filing date of U.S. patent application No. 18 / 745,962, filed on June 17, 2024, "MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS." Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to microelectronic devices including memory cells comprising vertically spaced transistors and storage devices and to related memory devices and electronic systems. Background Art

[0004] Microelectronic device designers often wish to increase the integration or density of features within a microelectronic device by reducing the size of individual features and reducing the separation distance between adjacent features. In addition, microelectronic device designers often attempt to design an architecture that is not only compact but also provides performance advantages and simplified design.

[0005] One example of a semiconductor device is a memory device. A memory device is generally provided as an internal integrated circuit in a computer or other electronic device. There are many types of memory, including but not limited to random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (RRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin torque transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.

[0006] A typical memory cell of a memory device includes one access device (e.g., a transistor) and one memory storage structure (e.g., a capacitor). Modern applications of semiconductor devices may employ a large number of memory cells arranged into a memory array exhibiting rows and columns of memory cells. The memory cells may be electrically accessed through digit lines (e.g., bit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of memory cells of the memory array. The memory array may be two-dimensional (2D) so as to exhibit a single level (e.g., a single level, a single level) of memory cells, or may be three-dimensional (3D) so as to exhibit multiple levels (e.g., multiple levels, multiple levels) of memory cells.

[0007] To improve the operating parameters of the memory cell, some have formed so-called two-transistor-one-capacitor memory cells, in which the memory device communicates with two transistors, and some have desired to increase the capacitance of the memory device. However, increasing the number of transistors used for each memory cell undesirably increases the area occupied by the memory cell and reduces the packing density of the memory cells of the array. In addition, increasing the capacitance of the memory device increases the area occupied by the memory cell. Summary of the invention

[0008] In some embodiments, a microelectronic device includes: a first transistor structure, which includes multiple vertical levels of a channel region; a second transistor structure, which is adjacent to the first transistor structure and includes an additional multiple vertical levels of the channel region; a storage device, which vertically overlies the first transistor structure and the second transistor structure; a first conductive contact structure, which contacts the first transistor structure; and a second conductive contact structure, which contacts the second transistor structure.

[0009] In an additional embodiment, a memory device includes: a memory cell array, each memory cell of the memory cell array includes a first transistor and a second transistor; and a capacitor vertically overlying the first transistor and the second transistor and electrically communicating with each of the first transistor and the second transistor. The memory device further includes a first conductive line and a second conductive line horizontally spaced apart from the first conductive line in a first horizontal direction, at least some memory cells of the memory cell array being configured to be electrically connected to each of the first conductive line and the second conductive line.

[0010] In a further embodiment, an electronic device includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a vertical transistor stack including vertical transistor pairs, the transistors of each of the vertical transistor pairs being vertically spaced apart from each other; and a stack structure including capacitors. Each capacitor structure includes: a first electrode configured to be in electrical communication with a first transistor in the vertical transistor pair; and a second electrode configured to be in electrical communication with a second transistor in the vertical transistor pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A to Figure 1V is a simplified partial top view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure ( Figure 1A , Figure 1E , Figure 1G , Figure 1L and Figure 1T ) and simplified partial cross-section diagram ( Figure 1B to Figure 1D , Figure 1F , Figure 1H to Figure 1K , Figure 1M to Figure 1S and Figure 1U to Figure 1V ).

[0012] Figure 2 is a block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but are merely idealized representations used to describe the embodiments herein. Elements and features common between the figures may retain the same numerical designations, except that for ease of following the description, the reference number begins with the number of the figure in which the element is introduced or most fully described.

[0014] The following description provides specific details, such as material type, material thickness, and processing conditions, in order to provide a detailed description of the embodiments described herein. However, it will be understood by those skilled in the art that the embodiments disclosed herein can be practiced without adopting these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., a semiconductor device, a memory device, such as a DRAM memory device), an apparatus, a memory device, or an electronic system, or a complete microelectronic device, an apparatus, a memory device, or an electronic system including a conductive contact structure. The structure described below does not form a complete microelectronic device, an apparatus, a memory device, or an electronic system. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions for forming a complete microelectronic device, an apparatus, a memory device, or an electronic system from a structure can be performed by conventional techniques.

[0015] The figures presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. Changes in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances may be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions described, but rather include shape deviations due to, for example, manufacturing. For example, a region described or described as box-shaped may have rough and / or nonlinear features, and a region described or described as circular may include some rough and / or linear features. In addition, the sharp angles described may be rounded, and vice versa. Therefore, the regions described in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. In addition, common elements between the figures may retain the same numerical designations.

[0016] As used herein, the term "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0017] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the structure and one or more of the devices in a predetermined manner.

[0018] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" are referenced to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "lateral" direction is a direction generally parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction generally perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the accompanying drawings, a "horizontal" or "lateral" direction may be perpendicular to the indicated "Z" axis and may be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; and a "vertical" or "longitudinal" direction may be parallel to the indicated "Z" axis, may be perpendicular to the indicated "X" axis, and may be perpendicular to the indicated "Y" axis.

[0019] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to each other mean and include features of one (or several) disclosed entities that are positioned closest to (e.g., closest to) each other. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not match one (or several) disclosed entities of the "adjacent" features may be disposed between the "adjacent" features.

[0020] As used herein, spatially relative terms (e.g., "under," "beneath," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," "right," and the like) may be used to describe the relationship of one element or feature to another element or feature as illustrated in the figures for the purpose of convenience of description. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figures is inverted, then what is described as "under other elements or features" or "under other elements or features" or "below other elements or features" or "at the bottom of other elements or features" would then be oriented as "over other elements or features" or "at the top of other elements or features." Thus, one of ordinary skill in the art will understand that the term "under" may encompass both above and below orientations, depending on the context in which the term is used. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.

[0021] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, the phrase "coupled to" means that structures are operatively connected to each other, such as by a direct ohmic connection or electrically connected through an indirect connection (such as through another structure).

[0024] As used herein, the term "substantially" with reference to a given parameter, property, or condition means and includes the degree to which one of ordinary skill in the art would understand that the given parameter, property, or condition is satisfied with a certain degree of variation (e.g., within an acceptable tolerance). For example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90.0% satisfied, at least 95.0% satisfied, at least 99.0% satisfied, at least 99.9% satisfied, or even 100.0% satisfied.

[0025] As used herein, "about" or "approximately" with reference to a numerical value of a particular parameter includes the numerical value, and the degree of deviation from the numerical value that a person of ordinary skill in the art would understand is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with reference to a numerical value may include additional numerical values ​​within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0026] A chemical formula (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y) refers to a material that contains an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios and does not limit the chemical structure, the insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" refers to and includes chemical compounds with element compositions that cannot be represented by well-defined natural number ratios and violate the law of definite proportions. In addition, an "insulating structure" refers to and includes a structure formed by and including an insulating material.

[0027] Unless otherwise indicated by the context, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth.

[0028] According to embodiments described herein, a memory cell array includes memory cells, each memory cell individually including two transistors and one storage device (e.g., a two-transistor-one-capacitor (2T-1C)) memory cell. The memory cells may individually include a storage device vertically spaced apart from the transistor. The transistors may be vertically spaced apart from each other. In some such embodiments, the second vertical transistor of the memory cell may be positioned within the horizontal boundary of the first vertical transistor of the memory cell. The first transistor and the second transistor may be electrically connected to an electrode of the storage device. In some embodiments, the first transistor and the second transistor are electrically connected to different electrodes of the storage device. In some embodiments, each of the first transistor and the second transistor includes multiple vertical levels of channel regions vertically spaced apart from each other. The storage device may vertically overlie the transistor and may include multiple levels of electrode material and dielectric material. The multiple levels of electrode material and dielectric material may facilitate increasing the capacitance of the storage device compared to a storage device formed in a single vertical plane.

[0029] Figure 1A to Figure 1V 1 is a diagram illustrating various views of a microelectronic device structure at different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM memory device) according to an embodiment of the present disclosure (described in further detail below). With the description provided below, one of ordinary skill in the art will readily appreciate that the methods described herein can be used to form a variety of devices. In other words, the methods of the present disclosure can be used when it is desired to form a microelectronic device.

[0030] Figure 1A is a simplified partial top view of a microelectronic device structure 100 according to an embodiment of the present disclosure. Figure 1B It passes through Figure 1A A simplified partial cross-sectional view of the microelectronic device structure 100 taken along the section line BB. Figure 1A and Figure 1B The microelectronic device structure 100 includes active areas 105 (eg, active areas 105) separated from each other by first trenches 107 extending in a first horizontal direction (eg, in the X direction) and first insulating materials 103 extending in a second horizontal direction (eg, in the Y direction). Figure 1A ). The first trench 107 may be separated by a portion of the first insulating material 103. Figure 1A 's view, it will be understood that the Z axis goes in and out of the view of the page.

[0031] refer to Figure 1B The microelectronic device structure 100 includes a stacked structure 101, which includes a vertically alternating (e.g., in the Z direction) sequence of first materials 104 and second materials 106, which are arranged in a level 108 and vertically overly (e.g., in the Z direction) a base structure 102.

[0032] The stacked structure 101 may be formed to include any desired number of levels 108. By way of non-limiting example, the stacked structure 101 may be formed to include eight (8) levels 108. In other embodiments, the stacked structure 101 may be formed to include less than eight (8) levels 108, such as less than or equal to four (4) levels 108. In some embodiments, the stacked structure 101 is formed to include two (2) levels 108. As described in further detail herein, the number of levels 108 may correspond to the number of memory cells (e.g., memory cell 190 ( Figure 1U , Figure 1V )) of a transistor structure (eg, transistor structure 160 ( Figure 1U , Figure 1V ))'s equivalent channel length.

[0033] The base structure 102 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate including a semiconductive material. As used herein, the term "bulk substrate" refers to and includes not only a silicon substrate, but also a silicon-on-insulator (SOI) substrate (e.g., a silicon-on-sapphire (SOS) substrate and a silicon-on-glass (SOG) substrate), a silicon epitaxial layer on a base semiconductive foundation, and other substrates formed of and including one or more semiconductive materials (e.g., one or more of the following materials: silicon material, such as single crystal silicon or polycrystalline silicon; silicon germanium; germanium; gallium arsenide; gallium nitride; indium phosphide). In some embodiments, the base structure 102 includes a silicon wafer.

[0034] The second material 106 of each level 108 of the stacked structure 101 may be formed of and include at least one material that is selectively removable relative to the first material 104. The second material 106 may be selectively etched relative to the first material 104 during common (e.g., collective, mutual) exposure to a first etchant; and the first material 104 may be selectively etched relative to the second material 106 during common exposure to a second, different etchant. As used herein, a material is "selectively etched" relative to another material if the material exhibits an etching rate that is at least about five times (5x), such as about ten times (10x), about twenty times (20x), or about forty times (40x) the etching rate of the other material.

[0035] The first material 104 may be formed of and include, for example, a semiconductive material (eg, silicon) or an oxide material (eg, silicon dioxide). In some embodiments, the first material 104 includes silicon, such as epitaxially grown silicon. In some embodiments, the first material 104 includes single crystal silicon.

[0036] The second material 106 may have a different material composition than the first material 104 and may have an etching selectivity relative to the first material 104. The second material 106 may be made of and include silicon germanium, polysilicon, a nitride material (e.g., silicon nitride (Si3N4)), or an oxynitride material (e.g., silicon oxynitride). In some embodiments, such as when the first material 104 includes silicon, the second material 106 includes silicon germanium, such as epitaxially grown silicon germanium. In other embodiments, such as when the first material 104 includes silicon, the second material 106 includes polysilicon. In yet other embodiments, such as when the first material 104 includes silicon dioxide, the second material 106 includes silicon nitride or silicon oxynitride.

[0037] The first insulating material 103 may be formed of and include one or more of at least one insulating material, such as one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x )、ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y)), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y In some embodiments, the first insulating material 103 is made of a dielectric oxide material (eg, SiO x (e.g. SiO2)) is formed and includes the material.

[0038] The second insulating material 110 may vertically overlie (eg, in the Z direction) the stacked structure 101. The second insulating material 110 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 103. In some embodiments, the second insulating material 110 includes silicon dioxide.

[0039] refer to Figure 1B , the first trench 107 may extend vertically (e.g., in the Z direction) through the second insulating material 110, the stacked structure 101, and at least partially through the base structure 102. A horizontally extending (e.g., in the X direction, in the Y direction) surface of the base structure 102 may be exposed through the first trench 107. In addition, the horizontal sides of the first material 104 and the second material 106 may be exposed through the first trench 107.

[0040] Figure 1C is Figure 1A and Figure 1B A simplified partial cross-sectional view of the microelectronic device structure 100 at a processing stage subsequent to the illustrated processing stage. Figure 1C , the portion of the second material 106 exposed by defining the sidewalls of the first trench 107 can be removed selectively relative to the first material 104. Selectively removing the second material 106 relative to the first material 104 can form a recess 112 defined by an exposed portion of the second material 106 recessed relative to the first trench 107 (e.g., in the Y direction) and an exposed portion of the first material 104 (e.g., extending in the Y direction).

[0041] In some embodiments, portions of the steps of the first material 104 are removed during the removal of the second material 106 through the first trench 107. In some embodiments, horizontally extending portions (e.g., in the Y direction) of the steps of the first material 104 that are vertically separated from each other (e.g., in the Z direction) by the recesses 112 may be partially removed so that portions of the first material 104 that are close to the first trench 107 and exposed by the recesses 112 have a thickness (e.g., in the Z direction) less than other portions of the first material 104 that are far from the first trench 107.

[0042] In some embodiments, a portion of the second material 106 is removed selectively relative to the first material 104 by exposing the second material 106 to one or both of a dry etching process and a wet etching process. As a non-limiting example, the second material 106 may be removed selectively relative to the first material 104 by exposing the second material 106 to a dry etch comprising one or both of hydrogen fluoride (HF) and methanol (CH3OH); followed by plasma treatment with one or more of carbon tetrafluoride (CF4), fluorine (F2), ammonia (NH3), argon, and chlorine trifluoride (ClF3).

[0043] After forming the recess 112 , a third insulating material 114 may be formed within the first trench 107 and within the recess 112 on the exposed surfaces of the first material 104 , the second material 106 , and the base structure 102 .

[0044] The third insulating material 114 may be formed by, for example, depositing a liner material including the third insulating material 114 and removing portions of the liner material from the surface of the base structure 102 and from a surface of the first material 104 extending horizontally (e.g., in the X direction, in the Y direction) near the first trench 107. The third insulating material 114 may remain on the surface of the second material 106 and extend vertically (e.g., in the Z direction) between vertically adjacent (e.g., in the Z direction) steps of the first material 104 at a position away from the first trench 107.

[0045] The third insulating material 114 may be formed of and include an insulating material having an etching selectivity relative to the first material 104, the second material 106, and the dielectric material 116. In some embodiments, the third insulating material 114 includes a nitride material (e.g., silicon nitride (Si3N4)) or an oxynitride material (e.g., silicon oxynitride). In some embodiments, the third insulating material 114 includes silicon nitride.

[0046] After forming the third insulating material 114, a dielectric material 116 may be formed on a horizontally extending (e.g., in the X direction, in the Y direction) surface of the first material 104. In some embodiments, the dielectric material 116 grows on an exposed surface of the first material 104. As a non-limiting example, the dielectric material 116 may be formed by exposing the surface of the first material 104 to oxygen at a high temperature (e.g., at a temperature in a range of about 900° C. to about 1,200° C.).

[0047] In other embodiments, the dielectric material 116 is formed by depositing the dielectric material 116 on the surfaces defining the recess 112 (e.g., the surfaces of the first material 104 extending horizontally (e.g., in the X direction, in the Y direction)) and the surfaces of the third insulating material 114 extending vertically (e.g., in the Z direction). Portions of the dielectric material 116 on the vertically extending surfaces of the third insulating material 114 and on the surfaces within the first trench 107 and outside the first trench 107 may be removed.

[0048] The dielectric material 116 may also be referred to herein as a "gate dielectric material". As further described herein in detail, the dielectric material 116 vertically intersects (eg, in the Z direction) the first material 104 and the conductive material (eg, the conductive material 118). Figure 1D ))between.

[0049] The dielectric material 116 may be formed of and include an insulating material. As limiting examples, the dielectric material 116 may include one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material such as silicon nitride (Si3N4), an oxynitride such as silicon oxynitride, another gate dielectric material, a dielectric carbonitride material such as silicon carbon nitride (SiCN), or a dielectric carbon oxynitride material such as silicon oxycarbon nitride (SiOCN).

[0050] Figure 1D is Figure 1C A simplified partial cross-sectional view of the microelectronic device structure 100 at a processing stage subsequent to the illustrated processing stage. Figure 1D After forming the dielectric material 116, the dielectric material 116 in the recess 112 may be formed on the surface of the dielectric material 116 in the recess 112 and on the surface of the vertical extension (e.g., in the Z direction) of the first material 104 defining the sidewalls of the first trench 107. Figure 1C ) to form a conductive material 118.

[0051] After forming the conductive material 118, the recess 112 ( Figure 1C ) and on the surface of the conductive material 118 in the first trench 107. In some embodiments, the fourth insulating material 120 substantially fills the remaining portion of the recess 112.

[0052] The conductive material 118 may be formed of and include a conductive material such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), a material including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof, conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other materials exhibiting conductivity.

[0053] The fourth insulating material 120 may be formed of an insulating material and include an insulating material, such as one or more of the following: at least one dielectric oxide material (eg, silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x )、ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )), and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y In some embodiments, the fourth insulating material 120 is made of a dielectric oxide material (eg, SiO x (e.g. SiO2)) is formed and includes the material.

[0054] After forming the conductive material 118 and the fourth insulating material 120, portions of the fourth insulating material 120 may be removed from within the first trench 107 and from the vertically uppermost (e.g., in the Z direction) surface of the microelectronic device structure 100. The fourth insulating material 120 may remain in the recesses 112 ( Figure 1C ) part of the location.

[0055] After removing portions of the fourth insulating material 120, portions of the conductive material 118 may be removed from within the first trench 107 and from the vertically uppermost (e.g., in the Z direction) surface of the microelectronic device structure 100. The exposed portions of the conductive material 118 defining the sidewalls of the first trench 107 may be recessed (e.g., in the Y direction) relative to the surface of the fourth insulating material 120. In some embodiments, the conductive material 118 is selectively removed (e.g., in the Y direction) relative to the fourth insulating material 120 and the first material 104 by exposing the conductive material 118 to a dry etchant including, for example, sulfur hexafluoride (SF6) and nitrogen (N2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), fluorine (F2), and methyl fluoride (CH3F). However, the present disclosure is not limited thereto, and the conductive material 118 may be selectively removed relative to the fourth insulating material 120 and the first material 104.

[0056] After removing portions of the conductive material 118, the remaining portions of the conductive material 118 may form conductive structures 122. The conductive structures 122 may vertically overlie (e.g., in the Z direction) and vertically underlie (e.g., in the Z direction) portions of each of the first materials 104. In some embodiments, vertically adjacent (e.g., in the Z direction) conductive structures 122 between vertically adjacent (e.g., in the Z direction) levels of the first material 104 are spaced apart from each other by the fourth insulating material 120. The dielectric material 116 may be vertically interposed (e.g., in the Z direction) between the conductive structures 122 and the first material 104.

[0057] Conductive structures 122 may extend horizontally (e.g., in the X direction) as lines and may extend through an array region of microelectronic device structure 100. As described in further detail herein, conductive structures 122 may be referred to herein as "first conductive lines," "access lines," or "word lines," respectively.

[0058] After recessing a portion of the conductive material 118 and forming the conductive structure 122, a fifth insulating material 124 may be formed between a horizontal edge (e.g., in the Y direction) of the conductive structure 122 and the first trench 107. After forming the fifth insulating material 124, a portion of the fifth insulating material 124 within the first trench 107 may be removed.

[0059] The fifth insulating material 124 may be formed of and include one or more of the materials described above with reference to the third insulating material 114. In some embodiments, the fifth insulating material 124 includes substantially the same material composition as the third insulating material 114. In some embodiments, the fifth insulating material 124 includes silicon nitride.

[0060] The channel regions 125 can be formed in a step of the first material 104 between vertically adjacent (e.g., in the Z direction) steps of the second material 106. The channel regions 125 can be individually located vertically between vertically adjacent (e.g., in the Z direction) conductive structures 122 (e.g., in the Z direction). The conductive structures 122 are separated from the channel regions 125 by the dielectric material 116. As described in further detail herein, different vertical steps (e.g., in the Z direction) of the channel regions 125 can form vertically spaced (e.g., in the Z direction) transistor structures (e.g., transistor structure 160 ( Figure 1U , Figure 1V )) to form a vertically stacked (eg, in the Z direction) transistor structure, each transistor structure including a plurality of (eg, more than one) levels of channel regions 125.

[0061] In some embodiments, the conductive structures 122 are vertically stacked relative to each other (eg, in the Z direction) and are vertically spaced apart from each other (eg, in the Z direction) by the channel region 125 , the dielectric material 116 , and the fourth insulating material 120 .

[0062] Figure 1E is Figure 1D A simplified partial top view of the microelectronic device structure 100 at a processing stage subsequent to the illustrated processing stage. Figure 1F is Figure 1E Simplified partial cross-sectional view of microelectronic device structure 100 at a processing stage after the illustrated processing stage. After forming fifth insulating material 124, conductive material 126 may be formed within first trench 107 and between horizontally adjacent (e.g., in the X direction) portions of first insulating material 103. Thus, different portions of conductive material 126 may be electrically isolated from each other by first insulating material 103. After forming conductive material 126, horizontally extending portions (e.g., in the X direction, in the Y direction) of conductive material 126 may be removed, such as by exposing conductive material 126 to a dry etching process including one or more of trichlorofluoromethane (CFCL3), trifluorochloromethane (CF3CL), bromotrifluoromethane (CF3Br), CF4, hexafluoroethane (C2F6), SF6, and a mixture of hydrogen bromide (HBr) and oxygen (O2). Removing horizontally extending portions of conductive material 126 may electrically isolate different portions of conductive material 126 separated from each other by first trench 107.

[0063] The conductive material 126 may contact the sidewalls of the step of the first material 104 and the sides of the fifth insulating material 124 and the fourth insulating material 120. In use and operation, the conductive material 126 may be in electrical communication with the first material 104. In some such embodiments, current flows between the conductive material 126 and the first material 104 (e.g., from the conductive material 126 to the first material 104, and from the first material 104 to the conductive material 126).

[0064] In some embodiments, after removing the vertically lowermost (eg, in the Z direction) portion of the conductive material 126 , a portion of the base structure 102 is removed through the first trench 107 .

[0065] Conductive material 126 may be formed of and include a conductive material, such as one or more of the materials described above with reference to conductive material 118. In some embodiments, the conductive material includes conductively doped polysilicon, such as N+ doped polysilicon.

[0066] Figure 1G is Figure 1E and Figure 1F A simplified partial top view of the microelectronic device structure 100 at a processing stage subsequent to the illustrated processing stage. Figure 1H It passes through Figure 1G 1 is a simplified partial cross-sectional view of the microelectronic device structure 100 taken along section line HH. Fig. 1I It passes through Figure 1H A simplified partial cross-sectional view of the microelectronic device structure 100 taken along section line II. Figure 1G , the conductive structure 122 is illustrated with a dashed line to indicate that it is located in a different vertical plane (e.g., in the Z direction) than other portions of the microelectronic device structure 100, such as vertically below (e.g., in the Z direction) the vertically uppermost (e.g., in the Z direction) upper surface of the microelectronic device structure 100. For clarity and ease of understanding of the description, Figure 1G The portion of the microelectronic device structure 100 that is vertically positioned below the uppermost surface of the microelectronic device structure 100 (eg, in the Z direction) is illustrated. Figure 1G The relative positions of the various structures and components of the microelectronic device structure 100 in the XY plane are illustrated. As a non-limiting example, although the conductive structures 122 and the conductive material 126 may not be at the vertically uppermost (e.g., in the Z direction) surface of the microelectronic device structure 100, Figure 1G The conductive structure 122 and the conductive material 126 are illustrated to show the relative positions of the conductive structure 122 and the conductive material 126 with respect to other components and structures of the microelectronic device structure 100 .

[0067] Common Reference Figure 1G to Figure 1I, a horizontally extending (eg, in the Y direction) portion of the conductive material 126 may be removed to electrically isolate a horizontally adjacent (eg, in the Y direction) portion of the conductive material 126. In addition, and with reference to Figure 1H In some embodiments, the conductive contact structures 136 may be formed to extend vertically (eg, in the Z direction) at least partially through the first trenches 107 ( Figure 1F , Figure 1G ), and are each individually configured to be in electrical communication with some (e.g., half) of the channel regions 125 that are immediately horizontally adjacent (e.g., in the Y direction) to the conductive contact structure 136. In some embodiments, about half of the conductive contact structure 136 is configured to be in electrical communication with the vertically uppermost (e.g., in the Z direction) half of the channel regions 125 (e.g., the vertically uppermost four levels of the channel regions 125), and may be referred to herein as the first conductive contact structure 136A; and the other half of the first conductive contact structure 136A is configured to be in electrical communication with the vertically lowermost (e.g., in the Z direction) half of the channel regions 125 (e.g., the vertically lowermost four levels of the channel regions 125), and may be referred to herein as the second conductive contact structure 136B. The first conductive contact structure 136A and the second conductive contact structure 136B are collectively referred to herein as the conductive contact structures 136.

[0068] In some embodiments, first conductive contact structures 136A horizontally adjacent to each other in a first horizontal direction (e.g., in the X direction) may be horizontally aligned with each other in a second horizontal direction (e.g., in the Y direction); and first conductive contact structures 136A horizontally adjacent to each other in the second horizontal direction may be horizontally offset from each other in the first horizontal direction. Similarly, second conductive contact structures 136B horizontally adjacent to each other in a first horizontal direction (e.g., in the X direction) may be horizontally aligned with each other in the second horizontal direction (e.g., in the Y direction); and second conductive contact structures 136B horizontally adjacent to each other in the second horizontal direction may be horizontally offset from each other in the first horizontal direction. In addition, in some embodiments, second conductive contact structures 136B horizontally adjacent to first conductive contact structures 136A in a first horizontal direction (e.g., in the X direction) may be horizontally aligned with first conductive contact structures 136A in a second horizontal direction (e.g., in the Y direction).

[0069] In some embodiments, the first conductive contact structures 136A are horizontally aligned with each other (eg, in the X direction) and can be positioned at the first region 139A ( Figure 1G and the second conductive contact structures 136B are horizontally aligned with each other (eg, in the X direction) and positioned in the second region 139B (of the microelectronic device structure 100) Figure 1G). The first regions 139A may alternate horizontally (eg, in the X direction) with the second regions 139B, as described above with reference to the first conductive lines 138A and the second conductive lines 138B.

[0070] Common Reference Figure 1G and Figure 1H , a mask material may be formed over the first region 139A of the microelectronic device structure 100; a portion of a second conductive contact structure 136B may be formed in the first trench 107 in the second region 139B and on the surface of the conductive material 126; and a sixth insulating material 132 may be formed in the remaining portion of the first trench 107. After forming the second conductive contact structure 136B and a portion of the sixth insulating material 132, the conductive material 126, a portion of the first conductive contact structure 136A, and the sixth insulating material 132 may be removed from the vertically uppermost (e.g., in the Z direction) portion of the first trench 107, such as from the vertically uppermost half of the layer of the first material 104 and the second material 106.

[0071] Continue to refer Figure 1H , the liner material 133 may be formed on the surface of the vertically uppermost (e.g., in the Z direction) step of the first material 104 and the second material 106, such as the vertically uppermost half of the step within the first trench 107 in the second region 139B. After forming the liner material 133, an additional portion of the second conductive contact structure 136B may be formed within the first trench 107, on the surface of the liner material 133, and in electrical communication with the previously formed portion of the second conductive contact structure 136B to form a second conductive contact structure 136B that extends vertically (e.g., in the Z direction) through substantially the entire stacked structure 101. The liner material 133 may electrically isolate the vertically uppermost (e.g., in the Z direction) (e.g., the vertically uppermost half) step of the channel region 125 from the second conductive contact structure 136B.

[0072] refer to Fig. 1I , in the second zone 139B ( Figure 1G ) to form a second conductive contact structure 136B ( Figure 1G , Figure 1H), a mask material may be formed over the second region 139B, and a first conductive contact structure 136A may be formed in the first region 139A. As a non-limiting example, the conductive material 126 may be removed from the vertically lower (e.g., in the Z direction) portion of the first trench 107, and the sixth insulating material 132 may be formed in the lower portion of the first trench 107 within the first region 139A. After the sixth insulating material 132 is formed in the vertically lower portion of the first trench 107, an additional portion of the conductive material 126 may be formed on the surface of the step of the first material 104 in the vertically upper (e.g., in the Z direction) portion of the first trench 107 within the first region 139A; an additional first conductive contact structure 136A may be formed on the surface of the conductive material 126 and in contact with the conductive material 126, and an additional portion of the sixth insulating material 132 may be formed in the remaining portion of the first trench 107 within the first region 139A.

[0073] Therefore, reference Figure 1H and Fig. 1I , the first conductive contact structure 136A ( Figure 1G , Figure 1H ) may be configured to be electrically connected to the vertically lowermost (e.g., in the Z direction) level of the channel region 125, and not to be electrically connected to the vertically uppermost (e.g., in the Z direction) level of the channel region 125 (e.g., the first conductive contact structure 136A may be electrically isolated from the vertically uppermost level of the channel region 125 by the liner material 133); and the second conductive contact structure 136B ( Figure 1G , Fig. 1I ) may be configured to be electrically connected to the vertically uppermost (eg, in the Z direction) step of the channel region 125 and not to be electrically connected to the vertically lowermost (eg, in the Z direction) step of the channel region.

[0074] After forming a first conductive contact structure 136A in an upper portion of the first trench 107 and configured to be in electrical communication with a vertically upper (e.g., in the Z direction) half of the step of the channel region 125, and forming a second conductive contact structure 136B in a lower and upper portion of the first trench 107 and configured to be in electrical communication with a vertically lower (e.g., in the Z direction) half of the step of the channel region 125, a conductive line 138 may be formed over the microelectronic device structure 100 and in electrical communication with the first conductive contact structure 136A and the second conductive contact structure 136B. For example, the first conductive line 138A may be formed to be in electrical communication with the first conductive contact structure 136A in the first region 139A, and the second conductive line 138B may be formed to be in electrical communication with the second conductive contact structure 136B in the second region 139B. In other words, the first conductive contact structure 136A can electrically connect the first conductive line 138A in contact with the first conductive contact structure 136A to the first material 104 of the layer of the first material 104 by means of the conductive material 126; and the second conductive contact structure 136B can electrically connect the second conductive line 138B in contact with the second conductive contact structure 136B to the first material 104 of the layer of the first material 104 by means of the conductive material 126. In use and operation, applying a voltage to, for example, the conductive structure 122 can induce a current in the first material 104 vertically between the conductive structures 122 (for example, in the Z direction) and electrically connect the conductive line 138 to a storage device (for example, the storage device 176 ( Figure 1U , Figure 1V )).

[0075] Therefore, in some embodiments, half of the conductive lines 138 (e.g., the first conductive lines 138A) are configured to be electrically connected to the vertically uppermost (e.g., in the Z direction) half of the vertical steps of the channel region 125 (e.g., through the corresponding first conductive contact structure 136A); and the other half of the conductive lines 138 (e.g., the second conductive lines 138B) are configured to be electrically connected to the vertically lowermost (e.g., in the Z direction) half of the vertical steps of the channel region 125 (e.g., through the corresponding other half of the second conductive contact structure 136B). The first conductive lines 138A and the second conductive lines 138B may be collectively referred to as conductive lines 138 herein.

[0076] The first conductive lines 138A may be horizontally alternated with the second conductive lines 138B (e.g., in the X direction) such that each of the first conductive lines 138A and the second conductive lines 138B is horizontally adjacent to the other of the first conductive lines 138A and the second conductive lines 138B (e.g., in the X direction). The conductive lines 138 that are directly horizontally adjacent to each other (e.g., in the X direction) may be in electrical communication with the conductive contact structure 136, which in turn is in electrical communication with different levels of the channel region 125 (e.g., the first conductive line 138A is in electrical communication with the vertically uppermost (e.g., in the X direction) half of the channel region 125 by means of the first conductive contact structure 136A, and the second conductive line 138B that is horizontally immediately adjacent to the first conductive line 138A (e.g., in the X direction) is in electrical communication with the vertically lowermost (e.g., in the Z direction) half of the channel region 125 by means of the second conductive contact structure 136B).

[0077] In some embodiments, the first conductive line 138A is horizontally aligned with the corresponding first conductive contact structure 136A (e.g., in the X direction); and the second conductive line 138B is horizontally aligned with the corresponding second conductive contact structure 136B (e.g., in the X direction). In other words, the conductive lines 138 may individually contact the conductive contact structures 136, which are horizontally aligned with each other in a first direction (e.g., in the X direction) and horizontally spaced apart from each other in a second direction (e.g., in the Y direction). In some such embodiments, the individual conductive lines 138 may contact the first conductive contact structures 136A that are positioned within the horizontal boundaries of each other (e.g., in the X direction).

[0078] The first conductive line 138A and the first conductive contact structure 136A may be located in a first region 139A ( Figure 1G and the second conductive line 138B and the second conductive contact structure 136B may be positioned in the second region 139B (of the microelectronic device structure 100) Figure 1G ). The first regions 139A may alternate horizontally (eg, in the X direction) with the second regions 139B, as described above with reference to the first conductive lines 138A and the second conductive lines 138B.

[0079] Conductive line 138 may extend horizontally (e.g., in the Y direction) substantially perpendicular to conductive structure 122. Conductive line 138 may be used as a digit line (e.g., a data line, a bit line). Since conductive contact structure 136 contacts conductive line 138 and is configured to be electrically connected to conductive line 138, conductive contact structure 136 may be used as a digit line contact (also referred to herein as a "digit line contact structure"). Conductive line 138 may vertically overlie (e.g., in the Z direction) conductive structure 122. Reference Figure 1G , although in Figure 1G, but it will be understood that the conductive structure 122 is vertically below the conductive line 138 (eg, in the Z direction). The conductive structure 122 does not contact the conductive line 138. Figure 1G 138) to indicate that they are positioned below other portions of the microelectronic device structure 100 (e.g., for example, the conductive line 138). The relative vertical positions (e.g., in the Z direction) of the various components of the microelectronic device structure 100 are illustrated in phantom in the other top views herein to indicate that they are positioned below other portions of the microelectronic device structure 100 (e.g., for example, the conductive line 138). Figure 1H and Fig. 1I ), while the relative horizontal positioning (e.g., in the X direction, in the Y direction) is best illustrated in the top view (e.g., for example, Figure 1G ) is best illustrated in .

[0080] The conductive contact structure 136 and the conductive line 138 may each be formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive material 118. In some embodiments, the conductive contact structure 136 and the conductive line 138 each include tungsten.

[0081] The liner material 133 and the sixth insulating material 132 may each be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 103. In some embodiments, the liner material 133 and the sixth insulating material 132 each include silicon dioxide.

[0082] Although the conductive material 126 has been described and illustrated as being formed into the first trench 107 ( Figure 1G ), but the present disclosure is not limited thereto. In other embodiments, the conductive material 126 may be formed into a contact structure, substantially similar to the conductive contact structure 136, the conductive material 126 being in contact with the channel region 125 and being horizontally (e.g., in the Y direction) between the channel region and the conductive contact structure 136. In other embodiments, the conductive material 126 may be formed relative to the first insulating material 103 ( Figure 1A , Figure 1G ) is selectively epitaxially grown on the first material 104, so that portions of the conductive material 126 on horizontally opposite sides (e.g., in the Y direction) of the first trench 107 are electrically isolated from each other. In some embodiments, the conductive material 126 is doped with one or more dopants to increase the conductivity of the conductive material 126. As a non-limiting example, portions of the conductive material 126 within the horizontal boundary of the conductive contact structure 136 (e.g., in the X direction) and horizontally interposed between the conductive contact structure 136 and the channel region 125 (e.g., in the Y direction) may be doped, while other locations of the conductive material 126 may not be doped.

[0083] Figure 1J to Figure 1K is Figure 1G to Figure 1I A simplified partial cross-sectional view of the microelectronic device structure 100 at a processing stage subsequent to the illustrated processing stage. Figure 1J The cross-sectional view is through Figure 1H The plane of illustration is the same plane as the one taken, and Figure 1K The cross-sectional view is through Fig. 1I The illustrated planes are cut from the same plane, but at a position greater than that of the respective reference Figure 1H and Fig. 1I The processing stages illustrated and described are later processing stages.

[0084] refer to Figure 1J and Figure 1K After forming the conductive contact structure 136 and the conductive line 138, a seventh insulating material 140 is formed over the conductive line 138. The seventh insulating material 140 may be formed of and include one or more of the materials described above with reference to the first insulating material 103. In some embodiments, the seventh insulating material 140 includes an oxide material, such as silicon dioxide.

[0085] After forming the seventh insulating material 140, the microelectronic device structure 100 can be vertically inverted (e.g., turned upside down in the Z direction) and attached (e.g., bonded) to a carrier wafer 142 including a second base structure 144 and an oxide material 146 overlying the second base structure 144 to form a microelectronic device structure assembly 150 including the microelectronic device structure 100 and the carrier wafer 142. The carrier wafer 142 can be configured to facilitate safe handling of the microelectronic device structure assembly 150 for further processing of the microelectronic device structure 100. The carrier wafer 142 can include a conventional carrier structure and is therefore not described in detail herein.

[0086] The oxide material 146 may be formed of and include an oxide insulating material, such as at least one dielectric oxide material (eg, silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x In some embodiments, the oxide material 146 includes silicon dioxide. In some embodiments, the oxide material 146 and the seventh insulating material 140 include substantially the same material composition (eg, silicon dioxide).

[0087] The carrier wafer 142 may be attached to the microelectronic device structure 100 by contacting the seventh insulating material 140 of the microelectronic device structure 100 with the oxide material 146 of the carrier wafer 142. After the seventh insulating material 140 and the oxide material 146 are in contact, the microelectronic device structure 100 and the carrier wafer 142 may be exposed to an annealing condition to form a bond (e.g., an oxide-to-oxide bond) between the seventh insulating material 140 of the microelectronic device structure 100 and the oxide material 146 of the carrier wafer 142 to form the microelectronic device structure assembly 150. In some embodiments, the microelectronic device structure 100 and the carrier wafer 142 are exposed to a temperature greater than, for example, 800° C. to form the oxide-to-oxide bond and attach the microelectronic device structure 100 to the carrier wafer 142.

[0088] After attaching the microelectronic device structure 100 to the carrier wafer 142, the base structure 102 may be removed (e.g., thinned, etched), for example, by exposing the base structure 102 to one or more etchants or by exposing the base structure 102 to a CMP process. Figure 1H , Fig. 1I In some embodiments, the base structure 102 is removed by exposing the base structure 102 to an etchant formulated and configured to stop on the insulating material (eg, the sixth insulating material 132 , the third insulating material 114 , the dielectric material 116 , the fifth insulating material 124 ).

[0089] After removing the base structure 102 ( Figure 1H , Fig. 1I ), an eighth insulating material 152 is formed over the microelectronic device structure assembly 150 to cover the exposed portions of the conductive contact structure 136 and the conductive material 126. The eighth insulating material 152 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 103. In some embodiments, the eighth insulating material 152 includes silicon dioxide.

[0090] Figure 1L to Figure 1N is Figure 1J and Figure 1K A simplified partial top view of the microelectronic device assembly 150 at a processing stage subsequent to the illustrated processing stage ( Figure 1L ) and simplified partial cross-sectional view ( Figure 1L and Figure 1M ). Figure 1M It passes through Figure 1L The section line MM of Figure 1N It passes through Figure 1N The section line NN is taken.

[0091] Common Reference Figure 1L and Figure 1NAfter forming the eighth insulating material 152, a second trench 130 may be formed between first trenches 107 that are horizontally adjacent (eg, in the Y direction) in the stacked structure 101. In some embodiments, the second trench 130 ( Figure 1L ) may extend horizontally in a horizontal direction (eg, in the X direction) substantially parallel to the first trench 107 and substantially parallel to the conductive structure 122. The second trench 130 may extend vertically (eg, in the Z direction) through at least a portion of the base structure 102.

[0092] After forming the second trench 130, the second material 106 may be selectively removed relative to the first material 104 through the second trench 130. Figure 1J , Figure 1K ), thereby leaving a gap (e.g., in the Z direction) between vertically adjacent (e.g., in the Z direction) steps of the first material 104. Removal of the second material 106 through the second trench 130 can expose vertically extending (e.g., in the Z direction) sidewalls of the third insulating material 114. In some embodiments, the third insulating material 114 serves as an etch stop material and substantially reduces or prevents removal of the conductive material 118 of the conductive structure 122 during the selective removal of the second material 106.

[0093] By exposing the second material 106 to one or both of a vapor phase etching process and a dry etching process, the second material 106 may be removed selectively relative to the first material 104. As a non-limiting example, by exposing the second material 106 to a vapor phase etching process including hydrogen fluoride and methanol (CH3OH), followed by exposing the second material 106 to a plasma including one or more of CF4, F2, NH3, argon (Ar), and chlorine trifluoride (ClF3) (e.g., a mixture of CF4, F2, and NH3, or a mixture of Ar and Fe), the second material 106 may be removed selectively relative to the first material 104.

[0094] In selectively removing the second material 106 relative to the first material 104 ( Figure 1J , Figure 1K ), the second trench 130 and the region between the vertically adjacent (e.g., in the Z direction) steps of the first material 104 (e.g., in the Z direction) may be filled with the ninth insulating material 155. The vertical steps of the ninth insulating material 155 may vertically alternate with the vertical steps of the first material 104, and a stacked structure 135 including a vertical alternating sequence of steps 134 may be formed, each step 134 including a vertical step of the first material 104 and a vertical step of the ninth insulating material 155.

[0095] The formation of the second trench 130 can form electrically isolated transistor structures 160, each transistor structure 160 individually including multiple levels of the channel region 125, each level of the channel region 125 is positioned between vertically adjacent (e.g., in the Z direction) levels of the ninth insulating material 155. Each isolated transistor structure 160 can include approximately half of the levels of the channel region 125 of the stacked structure 135.

[0096] In some embodiments, the channel regions 125 of the transistor structures 160 each include a so-called "all around gate" (GAA) transistor. As a non-limiting example, the conductive structure 122 may substantially surround the channel regions 125 of the transistor structures 160, and each channel region 125 may be surrounded by conductive structures 122 vertically above the channel region 125 (e.g., in the Z direction), vertically below the channel region 125 (e.g., in the Z direction), and horizontally around the channel region 125 (e.g., in the X direction, such as in the first insulating material 103 ( Figure 1A ) and the portion between the channel region 125).

[0097] The horizontal boundaries (eg, in the X direction, in the Y direction) of each of the vertically adjacent (eg, in the Z direction) channel regions 125 of the transistor structure 160 may be individually positioned within the horizontal boundaries of the other channel regions 125 of the transistor structure 160 .

[0098] In some embodiments, vertically (e.g., in the Z direction) transistor structures 160 (one of which is illustrated in a dashed box 160A) individually include vertically (e.g., in the Z direction) steps of the channel region 125, such as about half of the steps of the channel region 125 vertically; and vertically lower (e.g., in the Z direction) transistor structures 160 (one of which is illustrated in a dashed box 160B) individually include vertically lower (e.g., in the Z direction) steps of the channel region 125, such as about half of the steps of the channel region 125 vertically lower. In some embodiments, the microelectronic device structure assembly 150 includes two steps of transistor structures 160 that are vertically spaced apart from each other, and each step of the transistor structures 160 individually includes multiple vertical steps (e.g., vertically spaced apart steps) of the channel region 125. In some embodiments, each transistor structure 160 includes four (4) steps of the channel region 125 that are vertically adjacent to each other (e.g., in the Z direction). Figure 1M and Figure 1N The four upper transistor structures 160A and the four (4) lower transistor structures 160B are each illustrated individually.

[0099] After replacing the second material 106 with the ninth insulating material 155 ( Figure 1J , Figure 1K), additional conductive contact structures 156 (including third conductive contact structures 156A and fourth conductive contact structures 156B) may be formed vertically through the eighth insulating material 152 and through at least some levels of the ninth insulating material 155 and the first material 104. Each additional conductive contact structure 156 may be individually electrically connected to half of the vertical levels of the channel region 125. For example, each of the additional conductive contact structures 156 is individually in contact with the channel region 125 of one of the transistor structures 160 (e.g., one of the upper or lower transistor structures 160).

[0100] The additional conductive contact structures 156 include: first additional conductive contact structures 156A (also referred to as "third conductive contact structures 156A"), each of which is individually configured to communicate with, for example, a storage device structure (eg, a storage device ( Figure 1U , Figure 1V )) is electrically connected to the upper electrode; and a second additional conductive contact structure 156B (also referred to as a "fourth conductive contact structure 156B"), each of which is individually configured to communicate with, for example, a storage device (e.g., a storage device ( Figure 1U , Figure 1V )). The first additional conductive contact structure 156A and the second additional conductive contact structure 156B are collectively referred to herein as additional conductive contact structures 156. In some embodiments, along the conductive line 138, alternating pairs of additional conductive contact structures 156 are electrically connected to the conductive line 138. For example, a pair of first additional conductive contact structures 156A can be electrically connected to the conductive line 138 and horizontally spaced apart (e.g., in the Y direction) from a pair of second additional conductive contact structures 156 that are electrically connected to the conductive line 138.

[0101] Continue to refer Figure 1M and Figure 1N , half of the first additional conductive contact structure 156A contacts a first transistor structure (e.g., upper transistor structure 160A) in the transistor structures 160, and the other half of the first additional conductive contact structure 156A contacts a second transistor structure (e.g., lower transistor structure 160B) in the transistor structures 160. In addition, half of the second additional conductive contact structure 156B contacts a first transistor structure (e.g., upper transistor structure 160A) in the transistor structures 160, and the other half of the second additional conductive contact structure 156B contacts a second transistor structure (e.g., lower transistor structure 160B) in the transistor structures 160.

[0102] In some embodiments, the additional conductive contact structure 156 contacts, for example, a drain region of the transistor structure 160, and the conductive contact structure 136 contacts a source region of the transistor structure 160, and the multiple channel regions 125 of each of the transistor structures 160 are horizontally between the source region and the drain region (for example, in the Y direction).

[0103] The additional conductive contact structures 156 that are horizontally adjacent (e.g., in the Y direction) to the same conductive line 138 in electrical communication may each extend vertically (e.g., in the Z direction) to the same location within the stacked structure 135 and be in electrical communication with the vertically aligned (e.g., in the Z direction) transistor structure 160. As a non-limiting example, the additional conductive contact structures 156 that are electrically connected to the second conductive line 138B may be in electrical communication with the vertically aligned (e.g., in the Z direction) transistor structure 160 (e.g., in the Z direction). Figure 1M and Figure 1N In the view of FIG. 1 , the microelectronic device structure 100 is relative to Figure 1H and Fig. 1I is flipped vertically), and the additional conductive contact structure 156 in electrical communication with the first conductive line 138A may be in electrical communication with the vertically lower (eg, in the Z direction) transistor structure 160.

[0104] The additional conductive contact structures 156 in electrical communication with the conductive line 138 may be horizontally aligned with each other (e.g., in the X direction). In some embodiments, the additional conductive contact structures 156 are positioned within the horizontal boundaries of the conductive line 138 contacted by the respective additional conductive contact structures 156 (e.g., in the X direction). In some embodiments, the additional conductive contact structures 156 are horizontally aligned with the conductive contact structures 136 (e.g., in the X direction) and may be positioned within the horizontal boundaries of the conductive contact structures 136 (e.g., in the X direction).

[0105] The additional conductive contact structures 156 may each be formed of and include a conductive material, such as one or more of the materials described above with reference to the conductive material 118 of the conductive structure 122. In some embodiments, the additional conductive contact structures 156 each include substantially the same material composition as the conductive contact structures 136. In some embodiments, the additional conductive contact structures 156 each include tungsten.

[0106] After forming the additional conductive contact structure 156 , the microelectronic device structure assembly 150 can be exposed to a chemical mechanical planarization process to remove conductive material from the vertical uppermost surface (eg, in the Z direction) of the microelectronic device structure assembly 150 , such as from the upper surface of the eighth insulating material 152 .

[0107] Fig.1O is Figure 1L to Figure 1NA simplified partial cross-sectional view of a microelectronic device structure assembly 150 at a processing stage subsequent to the illustrated processing stage. Fig.1O The cross section passes through Figure 1M The plane is the same as the plane shown in the figure, but the plane is smaller than the reference Figure 1M The processing stages illustrated and described are later processing stages.

[0108] refer to Fig.1O After forming the additional conductive contact structure 156, a tenth insulating material 158 may be formed above the surface of the microelectronic device structure assembly 150, conductive pad structures 161 (for example, conductive interconnect structures, conductive connector structures, conductive redistribution structures) may be individually formed to be electrically connected to the additional conductive contact structure 156, and additional portions of the tenth insulating material 158 may be formed above the conductive pad structures 161.

[0109] As described in further detail herein, the conductive pad structure 161 can be configured to electrically connect the additional conductive contact structure 156 to a storage device (eg, storage device 176 ( Figure 1U , Figure 1V )) electrodes and provide sufficient area for electrically connecting (e.g., landing) the electrodes of the memory device during formation of the memory device.

[0110] After forming the tenth insulating material 158 and the conductive pad structure 161, the stacked structure 162 includes a vertically alternating (e.g., in the Z direction) sequence of insulating structures 164 and sacrificial structures 166. The vertically alternating sequence of insulating structures 164 and sacrificial structures 166 may be arranged in pairs, each pair including an insulating structure 164 and a sacrificial structure 166 vertically adjacent (e.g., in the Z direction) to the insulating structure 164. In some embodiments, one of the sacrificial structures 166 vertically overlies (e.g., in the Z direction) the tenth insulating material 158 and the additional conductive contact structure 156 and directly contacts the structures.

[0111] Insulating structure 164 may be formed of and include insulating materials, such as one or more of the materials described above with reference to first insulating material 103. In some embodiments, insulating structure 164 includes silicon dioxide.

[0112] The sacrificial structure 166 may be formed of and include at least one material (e.g., at least one insulating material) that is selectively removable relative to the insulating structure 164. The sacrificial structure 166 may be selectively etched relative to the insulating structure 164 during co-exposure (e.g., collectively, mutually) to a first etchant; and the insulating structure 164 may be selectively etched relative to the sacrificial structure 166 during co-exposure to a second, different etchant. As a non-limiting example, depending on the material composition of the insulating structure 164, the sacrificial structure 166 may be formed of at least one dielectric oxide material (e.g., AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x one or more of the above), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g. SiO x N y ), at least one dielectric oxycarbide material (e.g. SiO x C y ), at least one hydrogenated dielectric oxycarbide material (e.g. SiC x O y H z ), at least one dielectric carbon oxynitride material (e.g. SiO x C z N y ) and at least one semiconductive material (such as polysilicon) and include the materials. In some embodiments, the sacrificial structures 166 each include a dielectric nitride material, such as SiN y (eg, Si 3 N 4 ). The sacrificial structure 166 may be selectively etched relative to the insulating structure 164 , for example, during common exposure to a wet etchant including phosphoric acid (H 3 PO 4 ).

[0113] The tenth insulating material 158 may be formed of and include an insulating material, such as one or more of the materials described above with reference to the first insulating material 103. In some embodiments, the tenth insulating material 158 includes silicon dioxide.

[0114] The conductive pad structures 161 may each be formed of and include a conductive material, such as one or more of the materials described above with reference to the additional conductive contact structures 156. In some embodiments, the conductive pad structures 161 each include tungsten.

[0115] Figure 1P and Figure 1Q is Fig.1OA simplified partial cross-sectional view of a microelectronic device structure assembly 150 at a processing stage subsequent to the illustrated processing stage. Figure 1P The cross section passes through Fig.1O The plane is the same as the plane shown in the figure, but the plane is smaller than the reference Fig.1O The processing stages illustrated and described are later processing stages. Figure 1Q The cross section passes through Figure 1N The plane is the same as the plane shown in the figure, but the plane is smaller than the reference Figure 1N The processing stages illustrated and described are later processing stages.

[0116] After forming the stacked structure 162, openings 168 may be formed in the stacked structure 162 to expose the vertical uppermost (e.g., in the Z direction) surface of the tenth insulating material 158. After forming the openings 168. The openings 168 may be formed vertically directly above the conductive pad structures 161 (e.g., in the Z direction) and within the horizontal boundaries of the conductive pad structures 161 (e.g., in the X direction, in the Y direction), respectively.

[0117] The openings 168 may be individually formed by, for example, sequentially removing portions of the insulating structures 164 and the sacrificial structures 166, for example, through a mask material. Portions of the insulating structures 164 and the sacrificial structures 166 may be removed by exposing the insulating structures 164 and the sacrificial structures 166 to one or more dry etchants, such as one or more of CF4 (e.g., a mixture of CF4, O2, and N2), CHF3, CCl2F2, NF3 (e.g., a mixture of NF3 and O2), and SF6.

[0118] In some embodiments, exposed portions of the tenth insulating material 158 may be removed through at least some of the openings 168 to expose the conductive pad structures 161 that are vertically underlying (e.g., in the Z direction). As a non-limiting example, in some embodiments, exposed portions of the tenth insulating material 158 may be removed from alternating pairs of the openings 168. In some embodiments, the conductive pad structures 161 that are electrically connected to the first additional conductive contact structure 156A may be exposed through the openings, while the conductive pad structures 161 that are electrically connected to the second additional conductive contact structure 156B are not exposed through the openings 168. As a non-limiting example, a masking material may be formed over the conductive pad structures 161 that are electrically connected to the second additional conductive contact structure 156B, and the tenth insulating material 158 that is vertically over the conductive pad structures 161 that are electrically connected to the first additional conductive contact structure 156A may be removed to expose the conductive pad structures 161. After exposing the conductive pad structures 161, the masking material may be removed.

[0119] Common Reference Figure 1P and Figure 1QIn some embodiments, several pairs of openings 168 exposing the conductive pad structure 161 electrically connected to the second additional conductive contact structure 156B may be horizontally spaced apart from each other in a first horizontal direction (eg, in the Y direction) and a second horizontal direction (eg, in the X direction).

[0120] Continue to refer Figure 1P and Figure 1Q After forming the opening 168 and exposing some of the conductive pad structures 161 (e.g., half of the conductive pad structures 161, such as the conductive pad structures 161 electrically connected to the second additional conductive contact structure 156B), a portion of the sacrificial structure 166 may be selectively removed relative to the insulating structure 164 and the tenth insulating material 158. As a non-limiting example, the portion of the sacrificial structure 166 may be selectively removed relative to the insulating structure 164 and the tenth insulating material 158 by exposing the sacrificial structure 166 to a wet etchant (e.g., phosphoric acid).

[0121] In some embodiments, the size and location of the opening 168 corresponds to the active area 105 ( Figure 1L ) size and shape. However, the present disclosure is not limited thereto, and the size and shape of the opening 168 may be different from the size and shape described. Figure 1P and Figure 1Q Various amounts of sacrificial structures 166 are illustrated as remaining, but the disclosure is not limited in this regard. In other embodiments, sacrificial structures 166 may be more completely selectively removed (eg, substantially completely removed) and replaced with an insulating material.

[0122] Figure 1R and Figure 1S is Figure 1P and Figure 1Q A simplified partial cross-sectional view of a microelectronic device structure assembly 150 at a processing stage subsequent to the illustrated processing stage. Figure 1R Passing through Figure 1P The plane is the same as the plane shown in the figure, but the plane is smaller than the reference Figure 1P The processing stages illustrated and described are later processing stages. Figure 1S Passing through Figure 1Q The plane is the same as the plane shown in the figure, but the plane is smaller than the reference Figure 1Q The processing stages illustrated and described are later processing stages.

[0123] After selectively removing portions of the sacrificial structure 166, a first electrode material 170 may be formed on surfaces of the remaining portions of the insulating structure 164 and the sacrificial structure 166. After forming the first electrode material 170, a dielectric material 172 (also referred to as a "capacitor dielectric" material) may be formed on surfaces of the first electrode material 170. In some embodiments, the first electrode material 170 and the dielectric material 172 are formed by deposition (e.g., by ALD).

[0124] In some embodiments, the first electrode material 170 is formed to contact one half of the conductive pad structure 161, such as the conductive pad structure 161 that is electrically connected to the second additional conductive contact structure 156B. The first electrode material 170 may be electrically insulated from the other half of the conductive pad structure 161, such as the conductive pad structure 161 that is electrically connected to the first additional conductive contact structure 156A (e.g., for example, by means of a tenth insulating material 158).

[0125] The first electrode material 170 may be formed of and include a conductive material such as, for example, one or more of the following: a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), a material including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO x ), ruthenium oxide (RuO x ), alloys thereof, conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium), polysilicon, and other materials exhibiting conductivity. In some embodiments, the first electrode material 170 includes titanium nitride.

[0126] The dielectric material 172 may be formed from and include one or more of the following: silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, titanium dioxide (TiO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO3) (STO), barium titanate (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), ferroelectric materials (e.g., ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT)) and high-k dielectric materials.

[0127] Figure 1T to Figure 1V is Figure 1R and Figure 1S A simplified partial top view of the microelectronic device assembly 150 at a processing stage subsequent to the illustrated processing stage ( Figure 1T ) and simplified partial cross-sectional view ( Figure 1Uand Figure 1V ). Figure 1U It passes through Figure 1T The section line UU of Figure 1V It passes through Figure 1T The section line VV is taken. Figure 1T to Figure 1V The processing stages may facilitate the formation of microelectronic device 192 .

[0128] After forming the first electrode material 170 and the dielectric material 172, portions of the first electrode material 170 and the dielectric material 172 may be removed from the surface of the tenth insulating material 158 to pass through the opening 168 ( Figure 1R , Figure 1S ) exposes a portion of the tenth insulating material 158; and the exposed portion of the tenth insulating material 158 may be removed through the opening 168 to expose a portion of the vertically underlying (e.g., in the Z direction) conductive pad structure 161 that is not electrically connected to the first electrode material 170, such as the conductive pad structure 161 that is electrically connected to the first additional conductive contact structure 156A. In some embodiments, half of the conductive pad structure 161 (e.g., the other half of the conductive pad structure 161 that is not exposed before forming the first electrode material 170) is exposed through the first electrode material 170 and the dielectric material 172. In some embodiments, such a conductive pad structure 161 may not be electrically connected to the first electrode material 170.

[0129] After exposing the conductive pad structure 161 that is electrically connected to the first additional conductive contact structure 156A, the second electrode material 174 may be formed in the opening 168 ( Figure 1R , Figure 1S ) and on the surface of the dielectric material 172 to form a memory device 176. Each memory device 176 includes a first electrode material 170, a second electrode material 174, and a dielectric material 172 between the first electrode material 170 and the second electrode material 174.

[0130] The second electrode material 174 of half of the memory device 176 may be individually in contact with a conductive pad structure 161 , such as a conductive pad structure 161 that is electrically connected to one of the first additional conductive contact structures 156A. The second electrode material 174 of the other half of the memory device 176 may not be electrically connected to the conductive pad structure 161 .

[0131] The second electrode material 174 may be formed of and include a conductive material, such as one or more of the materials described above with reference to the first electrode material 170. In some embodiments, the second electrode material 174 includes substantially the same material composition as the first electrode material 170.

[0132] refer to Figure 1T, the storage device 176 can be positioned vertically above the transistor structure 160 (e.g., in the Z direction) and within the horizontal boundaries of the transistor structure 160 (e.g., in the X direction, in the Y direction), and the storage device 176 is configured to be in electrical communication with the transistor structure 160 (e.g., for example, through the first additional conductive contact structure 156A and the second additional conductive contact structure 156B). Figure 1T In the embodiment, only one of the memory devices 176 is illustrated for clarity and ease of understanding of the description. However, it should be understood that the microelectronic device structure assembly 150 includes a plurality of memory devices 176, such as one memory structure 176 for each pair of upper transistor structure 160A and lower transistor structure 160B. The cross-sectional shape of the memory device 176 may be substantially rectangular, square, circular, or elliptical. In other embodiments, the cross-sectional shape of the memory device 176 is substantially rectangular or square.

[0133] Common Reference Figure 1T , Figure 1U and Figure 1V , the transistor structures 160 and the memory devices 176 may form a memory cell 190 of a microelectronic device 192, illustrated by the dashed box 190. Each of the memory cells 190 may individually include: a lower transistor structure 160, which is electrically connected to a memory device 176 vertically overlying (e.g., in the Z direction) the lower transistor structure 160 by means of an additional conductive contact structure 156 (e.g., one of the first additional conductive contact structure 156A or the second additional conductive contact structure 156B); and an upper transistor structure 160A, which is electrically connected to a memory device 176 vertically overlying the upper transistor structure 160A by means of the other of the additional conductive contact structures 156 (e.g., the other of the first additional conductive contact structure 156A or the second additional conductive contact structure 156B).

[0134] In some embodiments, each memory cell 190 includes a first transistor structure 160 (e.g., one of the lower transistor structure 160B and the upper transistor structure 160A) electrically connected to the first conductive line 138A (e.g., by means of one of the conductive contact structures 136) and a second transistor structure 160 (e.g., the other of the lower transistor structure 160B and the upper transistor structure 160A) electrically connected to a second conductive line 138B that is horizontally adjacent to the first conductive line 138A (e.g., in the X direction) (e.g., by means of one of the conductive contact structures 136).

[0135] Each of the memory cells 190 may include a plurality of (e.g., two or more, such as two) transistor structures 160. In some embodiments, each of the memory cells 190 includes two transistor structures 160 that are operably in communication with the storage device 176 (e.g., electrically connected to the storage device 176). In some embodiments, each of the transistor structures 160 individually includes multiple vertical levels of the channel region 125. In some such embodiments, the memory cell 190 may be referred to as a so-called two-transistor-one-capacitor (2T-1C) memory cell. The transistor structures 160 of a single memory cell 190 may be stacked vertically relative to each other (e.g., in the Z direction). As a non-limiting example, the memory cell 190 may individually include two transistor structures 160 that are vertically spaced apart from each other (e.g., in the Z direction). A first transistor structure in the transistor structures 160 may be closer to the storage device 176 than a second transistor structure in the transistor structures 160; and the second transistor structure in the transistor structures 160 may be closer to the conductive line 138 than the first transistor structure in the transistor structures 160.

[0136] Forming memory cell 190 to include transistor structures 160 that individually include multiple levels of channel regions 125 that are vertically spaced apart from one another (e.g., in the Z direction) facilitates forming memory cell 190 to include a channel region that exhibits a greater ion distribution and a greater channel length than a conventional memory cell that does not include vertically stacked transistor structures. For example, vertically stacking channel regions 125 of the same transistor structure 160 facilitates increasing the channel length of transistor structure 160 without increasing the horizontal footprint of transistor structure 160 (e.g., in the X direction, in the Y direction), thereby facilitating increasing the density of memory cell 190.

[0137] Forming the microelectronic device structure assembly 150 to include a memory cell 190 including a plurality (e.g., two) of transistor structures 160 that are vertically spaced apart from one another (e.g., in the Z direction) can facilitate forming the memory cell 190 to exhibit reduced read disturbance as compared to conventional microelectronic devices including 1T-1C memory cells without increasing the horizontal area occupied by the memory cell 190 (e.g., in the X direction, in the Y direction). Additionally, forming the memory device 176 vertically above the transistor structure 160 (e.g., in the Z direction) facilitates forming the memory device 176 to exhibit a desired capacitance, which can be based at least in part on the number of levels of the memory device 176 (and, therefore, its height). Thus, the capacitance of the memory device 176 can be increased or decreased by increasing or decreasing, respectively, the number of levels of the first electrode material 170, the dielectric material 172, and the second electrode material 174 that define the memory device 176. Thus, the capacitance of the memory device 176 can be increased or decreased without increasing or decreasing the horizontal area occupied by the memory device 176 and, therefore, the memory cell 190. Additionally, because memory cell 190 comprises a 2T-1C memory cell, a read operation of memory cell 190 may not require a reference voltage for a sense amplifier (e.g., a DVC2 sense amplifier reference voltage), thereby reducing processing and operating costs of memory cell 190. In some embodiments, memory cell 190 may be configured to provide an equivalent read signal compared to a conventional 1T-1C memory cell, but with a lower capacitance (e.g., of storage device 176).

[0138] Although transistor structures 160 have been described and illustrated as individually including multiple vertical levels of channel regions 125, the present disclosure is not limited thereto. In other embodiments, transistor structures 160 individually include only one level of channel regions 125, and memory cell 190 includes two transistor structures 160, each transistor structure 160 including a single channel region 125. The channel region 125 of each of the transistor structures 160 may be vertically spaced apart (e.g., in the Z direction) from the channel region 125 of another transistor structure 160.

[0139] Although memory cell 190 has been described and illustrated as including two transistor structures 160, each of which is in electrical communication with a different one of conductive lines 138 (e.g., by means of different conductive contact structures 136), the present disclosure is not limited thereto. In other embodiments, memory cell 190 may include two transistor structures 160, each of which is in electrical communication with the same conductive line 138. In some such embodiments, the transistor structures 160 of memory cell 190 may be referred to as including or being in electrical communication with a "shared" conductive line 190.

[0140] Therefore, according to some embodiments of the present disclosure, a microelectronic device includes: a first transistor structure, which includes multiple vertical levels of a channel region; a second transistor structure, which is adjacent to the first transistor structure and includes an additional multiple vertical levels of the channel region; a storage device, which vertically overlies the first transistor structure and the second transistor structure; a first conductive contact structure, which contacts the first transistor structure; and a second conductive contact structure, which contacts the second transistor structure.

[0141] Therefore, according to some embodiments of the present disclosure, a memory device includes: a memory cell array, each memory cell of the memory cell array includes a first transistor and a second transistor; and a capacitor vertically overlying the first transistor and the second transistor and electrically communicating with each of the first transistor and the second transistor. The memory device further includes a first conductive line and a second conductive line horizontally spaced apart from the first conductive line in a first horizontal direction, and at least some memory cells of the memory cell array are configured to be electrically connected to each of the first conductive line and the second conductive line.

[0142] The microelectronic device (e.g., microelectronic device 192 ( Figure 1T , Figure 1U , Figure 1V )) may be included in embodiments of the electronic system of the present disclosure. For example, Figure 2 203 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-capable tablet computer (e.g., or Tablet computers), as well as electronic books, navigation devices, etc. The electronic system 203 includes at least one memory device 205. The memory device 205 may include, for example, an embodiment of a microelectronic device previously described herein (e.g., as previously described with reference to Figure 1T , Figure 1U and Figure 1V In the microelectronic device 192 described.

[0143] The electronic system 203 may further include at least one electronic signal processor device 207 (commonly referred to as a "microprocessor"). The electronic signal processor device 207 may optionally include an embodiment of one or more of the microelectronic devices and microelectronic device structures previously described herein. The electronic system 203 may further include one or more input devices 209 for inputting information into the electronic system 203 by a user, such as a mouse or other pointing device, a keyboard, a touch pad, buttons, or a control panel. The electronic system 203 may further include one or more output devices 211 (e.g., a monitor, a display, a printer, an audio output jack, a speaker, etc.) for outputting information (e.g., visual or audio output) to the user. In some embodiments, the input device 209 and the output device 211 may include individual touch screen devices that can be used both to input information to the electronic system 203 and to output visual information to the user. The input device 209 and the output device 211 may be in electrical communication with one or more of the memory device 205 and the electronic signal processor device 207.

[0144] Thus, in at least some embodiments, an electronic system includes: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and including at least one microelectronic device. The at least one microelectronic device includes: a vertical transistor stack including vertical transistor pairs, the transistors of each of the vertical transistor pairs being vertically spaced apart from each other; and a stack structure including capacitors. Each capacitor structure includes: a first electrode configured to be in electrical communication with a first transistor in the vertical transistor pair; and a second electrode configured to be in electrical communication with a second transistor in the vertical transistor pair.

[0145] Additional non-limiting example embodiments of the present disclosure are set forth below.

[0146] Embodiment 1: A microelectronic device comprises: a first transistor structure including a plurality of vertical steps of a channel region; a second transistor structure adjacent to the first transistor structure and including an additional plurality of vertical steps of a channel region; a storage device vertically overlying the first transistor structure and the second transistor structure; a first conductive contact structure contacting the first transistor structure; and a second conductive contact structure contacting the second transistor structure.

[0147] Embodiment 2: The microelectronic device of Embodiment 1, further comprising a conductive line configured to be in electrical communication with the first transistor structure.

[0148] Embodiment 3: The microelectronic device of Embodiment 2, further comprising an additional conductive line configured to be in electrical communication with the second transistor structure.

[0149] Embodiment 4: The microelectronic device of Embodiment 1, wherein the second transistor structure is horizontally spaced apart from the first transistor structure in a first horizontal direction.

[0150] Embodiment 5: The microelectronic device of Embodiment 4, further comprising: a conductive line configured to be in electrical communication with the first transistor structure; and an additional conductive line configured to be in electrical communication with the second transistor structure and horizontally spaced apart from the conductive line in a second horizontal direction.

[0151] Embodiment 6: The microelectronic device of any one of Embodiments 1 to 5, wherein the memory device exhibits a generally rectangular cross-sectional shape.

[0152] Embodiment 7: The microelectronic device of any one of embodiments 1 to 6, wherein the first conductive contact structure is horizontally offset from the second conductive contact structure.

[0153] Embodiment 8: The microelectronic device of any one of Embodiments 1 to 7, wherein the first conductive contact structure and the second conductive contact structure are configured to be in electrical communication with a same conductive line.

[0154] Embodiment 9: The microelectronic device of any one of Embodiments 1 to 8, wherein the plurality of vertical steps of the channel region of the first transistor structure are vertically offset from the additional plurality of vertical steps of the channel region of the second transistor structure.

[0155] Embodiment 10: The microelectronic device of any one of embodiments 1 to 9, wherein the first transistor structure is vertically aligned with the second crystal structure.

[0156] Embodiment 11: A memory device comprising: a memory cell array, each memory cell of the memory cell array comprising: a first transistor and a second transistor; and a capacitor vertically overlying the first transistor and the second transistor and electrically connected to each of the first transistor and the second transistor; and a first conductive line; and a second conductive line horizontally spaced apart from the first conductive line in a first horizontal direction, at least some of the memory cells of the memory cell array being configured to be electrically connected to each of the first conductive line and the second conductive line.

[0157] Embodiment 12: The memory device of Embodiment 11, wherein each of the first transistor and the second transistor individually comprises multiple vertical steps of a channel region.

[0158] Embodiment 13: The memory device of one of Embodiments 11 and 12, wherein: the first conductive line is positioned within a horizontal boundary of the first transistor; and the second conductive line is positioned within a horizontal boundary of the second transistor.

[0159] Embodiment 14: The memory device of any of Embodiments 11-13, wherein the first transistor is vertically spaced apart from the second transistor.

[0160] Embodiment 15: The memory device according to any one of embodiments 11 to 14, further comprising: a first conductive contact structure electrically connecting the first conductive line to the first transistor; and a second conductive contact structure electrically connecting the second conductive line to the second transistor.

[0161] Embodiment 16: The memory device of Embodiment 15, wherein: the first conductive contact structure is horizontally spaced apart from the second conductive contact structure in the first horizontal direction; and the first conductive contact structure is horizontally aligned with the second conductive contact structure in the second horizontal direction.

[0162] Embodiment 17: The memory device of any of Embodiments 11 to 16, wherein the capacitor comprises a first electrode material, a second electrode material, and a plurality of vertical steps of dielectric material between the first electrode material and the second electrode material.

[0163] Embodiment 18: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising: a vertical transistor stack comprising vertical transistor pairs, the transistors of each of the vertical transistor pairs being vertically spaced apart from each other; and a stack structure comprising capacitors, each capacitor comprising: a first electrode configured to be electrically connected to a first transistor in the vertical transistor pair; and a second electrode configured to be electrically connected to a second transistor in the vertical transistor pair.

[0164] Embodiment 19: The electronic system of Embodiment 18, each transistor of the vertical transistor pair comprising a vertically spaced channel region.

[0165] Embodiment 20: The electronic system of one of embodiments 18 and 19, wherein: the first transistor of one of the vertical transistor pairs is electrically connected to the first conductive line; and the second transistor of the one of the vertical transistor pairs is electrically connected to the second conductive line.

[0166] Although specific illustrative embodiments have been described in conjunction with the figures, those of ordinary skill in the art will recognize and appreciate that the embodiments encompassed by the present disclosure are not limited to the embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of the embodiments encompassed by the present disclosure (e.g., the embodiments claimed below, including legal equivalents). Additionally, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being included within the scope of the present disclosure.

Claims

1. A microelectronic device comprising: a first transistor structure comprising a plurality of vertical steps of a channel region; a second transistor structure adjacent to the first transistor structure and including an additional plurality of vertical steps of a channel region; a storage device vertically overlying the first transistor structure and the second transistor structure; a first conductive contact structure contacting the first transistor structure; as well as A second conductive contact structure contacts the second transistor structure.

2. The microelectronic device of claim 1, further comprising a conductive line configured to be in electrical communication with the first transistor structure.

3. The microelectronic device of claim 2, further comprising an additional conductive line configured to be in electrical communication with the second transistor structure. 4 . The microelectronic device of claim 1 , wherein the second transistor structure is horizontally spaced apart from the first transistor structure in a first horizontal direction.

5. The microelectronic device according to claim 4, further comprising: a conductive line configured to be in electrical communication with the first transistor structure; and An additional conductive line is configured to be in electrical communication with the second transistor structure and is horizontally spaced apart from the conductive line in a second horizontal direction.

6. A microelectronic device as claimed in any one of claims 1 to 5, wherein the memory device exhibits a generally rectangular cross-sectional shape.

7. The microelectronic device of any one of claims 1 to 5, wherein the first conductive contact structure is horizontally offset from the second conductive contact structure.

8. The microelectronic device of claim 1, wherein the first conductive contact structure and the second conductive contact structure are configured to be in electrical communication with a same conductive line.

9. The microelectronic device of any one of claims 1 to 5, wherein the plurality of vertical steps of the channel region of the first transistor structure are vertically offset from the additional plurality of vertical steps of the channel region of the second transistor structure.

10. The microelectronic device of any one of claims 1 to 5, wherein the first transistor structure is vertically aligned with the second transistor structure.

11. A memory device comprising: A memory cell array, each memory cell of the memory cell array comprising: A first transistor and a second transistor; and a capacitor vertically overlying the first transistor and the second transistor and in electrical communication with each of the first transistor and the second transistor; and a first conductive line; and A second conductive line is horizontally spaced apart from the first conductive line in a first horizontal direction, at least some of the memory cells of the memory cell array being configured to be in electrical communication with each of the first conductive line and the second conductive line.

12. The memory device of claim 11, wherein each of the first transistor and the second transistor individually comprises multiple vertical steps of channel regions.

13. The memory device of claim 11, wherein: The first conductive line is positioned within a horizontal boundary of the first transistor; and The second conductive line is positioned within a horizontal boundary of the second transistor.

14. The memory device of any one of claims 11-13, wherein the first transistor is vertically spaced apart from the second transistor.

15. The memory device of any one of claims 11 to 13, further comprising: a first conductive contact structure electrically connecting the first conductive line to the first transistor; and A second conductive contact structure electrically connects the second conductive line to the second transistor.

16. The memory device of claim 15, wherein: The first conductive contact structure is horizontally spaced apart from the second conductive contact structure in the first horizontal direction; and The first conductive contact structure is horizontally aligned with the second conductive contact structure in a second horizontal direction.

17. The memory device of any one of claims 11-13, wherein the capacitor comprises a first electrode material, a second electrode material, and multiple vertical steps of dielectric material between the first electrode material and the second electrode material.

18. An electronic system comprising: Input device; Output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising: a vertical transistor stack comprising vertical transistor pairs, the transistors of each of the vertical transistor pairs being vertically spaced apart from one another; and A stack structure comprising capacitors, each capacitor comprising: a first electrode configured to be in electrical communication with a first transistor of the vertical transistor pair; and A second electrode is configured to be in electrical communication with a second transistor of the vertical transistor pair.

19. The electronic system of claim 18, each transistor of the vertical transistor pair comprising a vertically spaced channel region.

20. The electronic system according to one of claims 18 and 19, wherein: A first transistor of one of the vertical transistor pairs is in electrical communication with a first conductive line; and The second transistor of the one of the vertical transistor pair is in electrical communication with a second conductive line.

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