I2C bus state monitoring and fault recovery and isolation circuit

Abstract

An I2C bus state monitoring and fault recovery and isolation circuit is applied to an electronic system, the electronic system is provided with a master device and an I2C bus which is electrically connected with a plurality of slave devices to communicate with each other, and a data line and a clock line of the master device are correspondingly and electrically connected with a serial data line and a serial clock line of the I2C bus; the I2C bus state monitoring and fault recovery and isolation circuit reads a data signal transmitted by the data line and a clock signal transmitted by the clock line, and analyzes the data signal and the clock signal to obtain address information and a bit representing read / write operation. When the bit representing the read / write operation is received and the logic relationship between the data signal and the clock signal is judged not to accord with the I2C bus transmission protocol, and a slave device communicated with the master device is judged to be faulty according to the bit representing the read / write operation, the slave device is found according to the address information and is subjected to troubleshooting action; therefore, the I2C bus is ensured not to be influenced by the fault device and can still maintain normal operation.

Description

Technical Field

[0001] The present invention relates to a bus state monitoring circuit, in particular to an I 2 C bus status monitoring and fault recovery and isolation circuit. Background Art

[0002] See also Figure 1 As shown, I is often used in circuit systems. 2 The I C bus 1 connects different devices (or parts) to perform various functions. 2 C bus 1 is a two-wire multi-master-slave (Master, Slave) communication bus, that is, I 2 The circuit interface of I C bus 1 has only two signal lines, namely the serial clock line SCL and the serial data line SDA. 2 All devices on the C bus 1 must be connected and communicate with each other through these two signal lines. 2 C bus 1 allows multiple master devices (Master) and multiple slave devices (Slave) to exist. There is no problem as long as the addresses do not conflict with each other and the number of devices does not exceed the upper limit of the electrical characteristics of the bus.

[0003] But in actual use, I 2 There are many types of devices on the I2C bus, and their usage methods and control program reliability vary. The response speed of the slave devices varies greatly. Therefore, once any device in the system fails to respond or takes too long to respond, it may cause the entire system I2C bus to fail. 2 The I C bus 1 hangs, thus affecting the operation of the entire system. However, the existing circuit system does not actively 2 C bus 1 is used to monitor the fault status. 2 When the C bus 1 is reading and writing normally, it is judged as a failure and 9 clocks are sent to try to restore the system I 2 If the C bus 1 fails to recover, the entire circuit system will be in a fault state or even collapse.

[0004] Therefore, an active and real-time monitoring method is developed. 2 C bus status circuit, so that once it detects the I 2 When an abnormal state occurs that the C-bus transmission protocol does not comply, it is necessary to promptly troubleshoot or isolate the faulty device that caused the abnormal state to avoid the failure of a single device affecting the operation of the entire system. Summary of the invention

[0005] The object of the present invention is to provide a 2C bus status monitoring and fault recovery and isolation circuit, which can monitor I 2 C bus status and find the I 2 When an abnormality occurs on the I C bus, the 2 C bus abnormal device to troubleshoot or isolate the I 2 C bus can maintain normal operation and improve I 2 C bus reliability.

[0006] The present invention is a kind of 2 The circuit is applied to an electronic system, wherein the electronic system has an I2C bus state monitoring and fault recovery and isolation circuit for electrically connecting a master device and a plurality of slave devices to communicate with each other. 2 C bus, the data and clock lines of the master device are connected to the I 2 The serial data line and the serial clock line of the I C bus are electrically connected correspondingly; the 2 The I C bus status monitoring and fault recovery and isolation circuit includes a reading unit, a decoding unit and a fault elimination unit; the reading unit is electrically connected to the data line and the clock line of the master device and only receives the electronic system master device information; the fault elimination unit is electrically connected to the reading unit, the decoding unit and the slave device; and the I 2 The I2C bus state monitoring and fault recovery and isolation circuit performs the following monitoring procedures: the reading unit reads the data signal transmitted by the data line and the clock signal transmitted by the clock line; the decoding unit parses the data signal and the clock signal to obtain address information and a bit representing a read / write operation, wherein the address information is the address of one of the slave devices to be communicated by the master device, and the bit representing a read / write operation indicates that the master device is to read or write data to the slave device; the fault elimination unit determines that the logical relationship between the data signal and the clock signal does not meet the I2C bus state monitoring and fault recovery and isolation circuit; the reading ... 2 C bus transmission protocol and determines that the slave device fails according to the bit representing the read / write operation provided by the decoding unit, the fault elimination unit finds the slave device according to the address information provided by the decoding unit and performs a fault elimination action on the slave device.

[0007] In some implementation cases of the present invention, the troubleshooting unit determines that the logical relationship between the data signal and the clock signal does not meet I 2 The situations of C bus transmission protocol include one of the following three: 1. The level of the clock signal is continuously logic 1, and the level of the data signal is continuously logic 0, and the duration exceeds 1 second; 2. No confirmation bit (ACK) appears in the data signal, and the duration exceeds 1 second; and 3. The level of the clock signal is continuously logic 0, and the duration exceeds 1 second.

[0008] In some implementation cases of the present invention, the troubleshooting unit includes a plurality of power switch control circuits corresponding to the number of the slave devices, the power switch control circuits are respectively electrically connected to the respective slave devices to control whether to supply power to the respective slave devices, and a comparison table is stored in the troubleshooting unit, the comparison table records the power switch control circuits corresponding to the addresses of the respective slave devices; the troubleshooting action is that the troubleshooting unit searches the comparison table according to the address information of the slave device to obtain the power switch control circuit electrically connected to the corresponding slave device, and cuts off the power supply of the slave device through the power switch control circuit, so that the slave device is disconnected from the I 2 After the I C bus is isolated for a period of time, power is supplied to the slave device again, so that the slave device can reconnect to the I C bus. 2 C bus is electrically connected, the I 2 The C bus status monitoring and fault recovery and isolation circuit executes the monitoring program again.

[0009] In some implementation cases of the present invention, the troubleshooting unit includes a plurality of reset circuits corresponding to the number of the slave devices, the reset circuits are respectively electrically connected to the respective slave devices to perform a reset operation on the respective slave devices, and a comparison table is stored in the troubleshooting unit, the comparison table records the reset circuits corresponding to the addresses of the respective slave devices; the troubleshooting action is that the troubleshooting unit searches the comparison table according to the address information of the slave device to obtain the reset circuit electrically connected to the corresponding slave device, and sends a reset signal through the reset circuit to perform a reset operation on the slave device and temporarily disconnect it from the I 2 C bus, the slave device completes the reset and then reconnects to the I 2 C bus is electrically connected, the I 2 The C bus status monitoring and fault recovery and isolation circuit executes the monitoring program again.

[0010] In some implementation cases of the present invention, the I 2 After the C bus status monitoring and fault recovery and isolation circuit executes the monitoring program on the slave device for N times, if the slave device is still in a fault state, the fault elimination unit will keep the slave device in a power-off state, record a fault information related to the slave device, and transmit I 2 The abnormality of the I C bus is notified to the central processor of the electronic system, so that the central processor can 2 The C bus abnormality notification checks the fault information recorded by the fault elimination unit and the central processor performs other further processing, such as notifying the system administrator, etc.; wherein N is greater than or equal to 2.

[0011] In some implementation cases of the present invention, the I 2The I C bus status monitoring and fault recovery and isolation circuit also includes a signal on-off circuit corresponding to the number of the slave devices, each of which is arranged on a corresponding circuit connected to the I C bus status monitoring and fault recovery and isolation circuit. 2 The clock line and the data line of the I C bus are electrically connected to control the clock line and the data line of each slave device to communicate with the I C bus. 2 C bus is turned on or off; and the fault elimination unit further comprises a plurality of switch control pins, which are respectively electrically connected to each of the signal on-off circuits to control the operation of each of the signal on-off circuits, and the comparison table also records the switch control pins corresponding to the addresses of each of the slave devices; the I 2 After the C bus status monitoring and fault recovery and isolation circuit executes the monitoring program on the slave device for N times, if the slave device is still in a fault state, the fault elimination unit searches the comparison table according to the address information of the slave device to obtain the switch control pin corresponding to the slave device, and controls the corresponding signal on-off circuit through the switch control pin to connect the clock line and the data line of the slave device to the I2C bus status monitoring and fault recovery and isolation circuit. 2 C bus is disconnected, so that the slave device is 2 C bus is completely isolated; where N is greater than or equal to 2.

[0012] In some implementation cases of the present invention, the troubleshooting unit determines that the logical relationship between the data signal and the clock signal does not meet I 2 C bus transmission protocol and determines that the master device fails according to the bit representing the read / write operation provided by the decoding unit and the confirmation bit in the data signal indicating normal communication, the troubleshooting unit transmits a master device abnormality notification to the central processor of the electronic system, so that the central processor performs the troubleshooting action on the master device according to the master device abnormality notification.

[0013] The beneficial effects of the present invention are: 2 C bus status monitoring and fault recovery and isolation circuit automatically and in real time reads the I 2 The logic relationship between the clock signal transmitted on the I C bus and the data signal transmitted on the data line is used to determine the I 2 The I C bus is abnormal and the faulty device that caused the abnormality is the master device or a slave device communicating with the master device, and the faulty device is removed or isolated in real time to ensure that the I C bus is abnormal. 2 The C bus will not be affected by the faulty device and can still maintain normal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 isI 2 C bus physical architecture diagram.

[0015] Figure 2The present invention I 2 A circuit block diagram of an embodiment of a C-bus status monitoring and fault recovery and isolation circuit.

[0016] Figure 3 isI 2 C bus transmission signal waveform basic timing diagram. DETAILED DESCRIPTION

[0017] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0018] Before the present invention is described in detail, it should be noted that similar components are denoted by the same reference numerals in the following description.

[0019] See also Figure 2 , is the present invention I 2 An embodiment of a C bus state monitoring and fault recovery and isolation circuit (hereinafter referred to as state monitoring circuit 2) is applied to Figure 2 The electronic system 100 shown in FIG. 1 has an I / O interface for a master device (Master) M and a plurality of slave devices (Slave) (this embodiment takes six slave devices S1, S2, ... S6 as an example, but is not limited thereto) to be electrically connected to communicate with each other. 2 The master device M has a data line DA and a clock line CL connected to the I 2 A serial data line SDA and a serial clock line SCL of the I C bus 10 are electrically connected to each other; a data line DA and a clock line CL of each slave device S1-S6 are also electrically connected to the I C bus 10; 2 The serial data line SDA and the serial clock line SCL of the I C bus 10 are electrically connected to each other. It is worth mentioning that one or some slave devices may also be an I 2 C bus expander, and multiple slave devices can be connected through the I 2 C bus extender with the I 2 C bus 10 is electrically connected, thereby allowing the I 2 The C bus 10 electrically connects more slave devices.

[0020] According to I 2 C bus transmission protocol (hereinafter referred to as I 2 C protocol) specified transmission timing, I 2 C communication is always initiated by the master device M, and the master device M outputs a clock signal to I through the clock line CL. 2 The serial clock line SCL of the C bus 10, and the master device M controls different slave devices S1-S6 in a serial manner according to different addresses of each slave device S1-S6. 2The C protocol defines two basic bus operations: read (R) and write (W). It is a serial synchronous communication method with a master-slave structure. Figure 3 As shown in the basic timing diagram, the start bit (START) indicates that the bus starts communicating, and the stop bit (STOP) indicates that the communication ends. Each time the master and slave exchange data, an acknowledgment bit (ACK) needs to be sent to indicate that the communication is normal. That is, if the master device M writes (W) data to a slave device, then the slave device sends an acknowledgment bit (ACK) after receiving the data; if the master device M reads data from a slave device, then the master device M sends an acknowledgment bit (ACK) after receiving the data. Each frame of data consists of a start bit (START), an address (ADDRESS, consisting of bits 1 to 7), a bit representing a read / write operation (R / W) (bit 8), data (DATA, consisting of bits 1 to 8), an acknowledgment bit (ACK) (bit 9), and a stop bit (STOP). And I 2 The data transmitted on the serial data line SDA of the C bus 10 can only be changed when the clock signal on the serial clock line SCL is logic 0 (low level), that is, when the clock signal on the serial clock line SCL is logic 1 (high level), the data transmitted on the serial data line SDA needs to remain unchanged to ensure that the receiver can sample the correct data.

[0021] See also Figure 2 As shown, the state monitoring circuit 2 of this embodiment mainly includes a reading unit 21 , a decoding unit 22 electrically connected to the reading unit 21 , and a fault elimination unit 23 electrically connected to the reading unit 21 and the decoding unit 22 .

[0022] The reading unit 21 is electrically connected to the data line DA and the clock line CL of the host device M to read the data signal (eg, Figure 3 ) and the clock signal transmitted by the clock line CL (eg Figure 3 As shown), and provides the data signal and the clock signal to the decoding unit 22 and the troubleshooting unit 23 to execute the following monitoring procedures.

[0023] After receiving the data signal and the clock signal, the decoding unit 22 performs the decoding according to the above I 2C protocol defines the clock timing and data transmission format, decodes the data signal and the clock signal to obtain address information and a bit representing a read / write operation from the data signal, the address information is the address of one of the slave devices S1 to S6 (for example, the slave device S3) with which the master device M wants to communicate, and if the value of the bit representing the read / write operation is (1), it indicates that the master device M wants to read data from the slave device S3, and if the value of the bit representing the read / write operation is (0), it indicates that the master device M wants to write data to the slave device S3; and the decoding unit 22 provides the address information of the slave device S3 and the bit representing the read / write operation to the troubleshooting unit 23.

[0024] The fault elimination unit 23 pre-records that the logical relationship between the data signal and the clock signal does not conform to I 2 C protocol leads to I 2 The following situations occur when C bus 10 is abnormal:

[0025] 1. The level of the clock signal is continuously at logic 1, and the level of the data signal is continuously at logic 0, and the duration exceeds 1 second;

[0026] 2. No ACK bit appears in the data signal and lasts for more than 1 second; and

[0027] 3. The level of the clock signal remains at logic 0 for a period of more than 1 second.

[0028] And if Figure 2 As shown, the troubleshooting unit 23 includes six power switch control circuits P1~P6 and six reset circuits R1~R6 corresponding to the number of the slave devices S1~S6, the power switch control circuits P1~P6 are respectively electrically connected to each of the slave devices S1~S6 to control whether power is supplied to each of the slave devices S1~S6; the reset circuits R1~R6 are respectively electrically connected to each of the slave devices S1~S6 to perform a reset action on each of the slave devices S1~S6.

[0029] In addition, the state monitoring circuit 2 further includes six signal on-off circuits SW1-SW6 corresponding to the number of the slave devices S1-S6, each of which is provided at the corresponding slave device S1-S6. 2 The C bus 10 is electrically connected to the clock line CL and the data line DA to control the clock line CL and the data line DA of each of the slave devices S1-S6 and the I 2 The C bus 10 is turned on or off. The fault elimination unit 23 further comprises six switch control pins K1-K6, which are electrically connected to the signal on-off circuits SW1-SW6 respectively to control the operation of the signal on-off circuits SW1-SW6.

[0030] In addition, the troubleshooting unit 23 also stores a comparison table, as shown in Table 1 below, which records the addresses of the slave devices S1 to S6 and the power switch control circuits P1 to P6, the reset circuits R1 to R6 and the switch control pins K1 to K6 corresponding to each other.

[0031]

[0032] Table 1

[0033] Thus, the fault elimination unit 23 receives the clock signal transmitted on the clock line CL from the master device M and / or the data signal transmitted on the data line DA (also the I 2 C bus 10), determining that the logical relationship of the data signal and / or the clock signal does not conform to I 2 C protocol caused the I 2 When an abnormality occurs on the I C bus 10, the bit representing the read / write operation provided by the decoding unit 22 is used to determine the cause of the I C bus 10. 2 The abnormality of the C bus 10 is either in the master device M or the slave device S3.

[0034] For example, according to I 2 The C protocol stipulates that if the value of the bit representing the read / write operation is (1), it means that the instruction of the master device M is read (R). At this time, the data transmission direction is from the slave device S3 to the master device M, that is, at the rhythm (frequency) of the clock signal sent by the master device M via its clock line CL, the slave device S3 should output the data signal to the I through its data line DA. 2 The serial data line SDA of the C bus 10 transmits data to the master device M through the data line DA of the master device M, and the master device M sends an acknowledgment bit (ACK) signal after receiving the data. The acknowledgment bit is sent by the master device M or the slave device S3 after the master and slave exchange data to indicate that the communication is normal. Therefore, if the communication is abnormal, the acknowledgment bit will not appear in the data signal. At this time, if the troubleshooting unit 23 determines that the clock signal on the clock line CL of the master device M continues to be logic 1 and the data signal on the data line DA continues to be logic 0, and the duration of both exceeds 1 second, because the clock signal is sent by the master device M, the troubleshooting unit 23 determines that the master device M has a fault; or, the troubleshooting unit 23 determines that the master device M should be at the 9th clock (see Figure 3) responds to the confirmation bit (ACK) but does not respond and the duration exceeds 1 second, the fault elimination unit 23 determines that the master device M has a fault; or, when the fault elimination unit 23 determines that the level of the clock signal is continuously logic 0 and the duration exceeds 1 second, it determines that the slave device S3 has a fault.

[0035] If the value of the bit representing the read / write operation is (0), it means that the instruction of the master device M is write (W). At this time, the data transmission direction is the master device M → the slave device S3, that is, the master device M outputs a data signal to the I through its data line DA according to the rhythm (frequency) of the clock signal generated by it. 2 The serial data line SDA of the C bus 10 transmits data to the slave device S3 through the data line DA of the slave device S3, and the slave device S3 sends an acknowledgement bit (ACK) after receiving the data. At this time, if the fault elimination unit 23 determines that the clock signal on the clock line CL of the master device M is continuously logical 1 and the data signal on the data line DA is continuously logical 0 and the duration of both exceeds 1 second, because the clock signal and the data signal are both sent by the master device M, the fault elimination unit 23 determines that the master device M has a fault; or, the fault elimination unit 23 determines that the slave device S3 should be at the 9th clock (see Figure 3 ) responds to the confirmation bit (ACK) but does not respond and the duration exceeds 1 second, the fault elimination unit 23 determines that the slave device S3 has failed; or, when the fault elimination unit 23 determines that the level of the clock signal is continuously logic 0 and the duration exceeds 1 second, it determines that the master device M has failed.

[0036] Therefore, when the fault elimination unit 23 determines that the slave device S3 fails, the fault elimination unit 23 finds the slave device S3 according to the address information provided by the decoding unit 22 and performs a fault elimination action on the slave device S3.

[0037] Specifically, the fault elimination unit 23 searches the comparison table (as shown in Table 1 above) according to the address information (S3-ADD) of the slave device S3 to obtain the power switch control circuit P3, the reset circuit R3 and the switch control pin K3 electrically connected to the slave device S3; and the fault elimination action is that the fault elimination unit 23 cuts off the power supply of the slave device S3 through the power switch control circuit P3, so that the slave device S3 (faulty device) is disconnected from the I 2 After the I C bus 10 is isolated (disconnected) for a period of time (e.g., a few seconds), power is supplied to the slave device S3 again, so that the slave device S3 is reconnected to the I C bus 10. 2 The C bus 10 is electrically connected.

[0038] Alternatively, the fault elimination action is that the fault elimination unit 23 sends a reset signal through the reset circuit R3 to reset the slave device S3 and temporarily disconnect it from I 2 C bus 10, so that the slave device S3 completes the reset and then reconnects to the I 2 The C bus 10 is electrically connected.

[0039] After completing the troubleshooting action, the troubleshooting unit 23 notifies the master device M through a central processor 101 of the electronic system 100 to try to communicate with the slave device S3 again, and then the status monitoring circuit 2 executes the above-mentioned monitoring program again to obtain the status of the I 2 Whether the signal transmitted on the C bus 10 is still abnormal, if so, it means that the slave device S3 has not yet eliminated the fault, and the fault elimination unit 23 will perform the above-mentioned fault elimination action on the slave device S3 again.

[0040] In addition, when the state monitoring circuit 2 executes the monitoring program on the slave device S3 for N (for example, N=3-5) times and the slave device S3 still cannot eliminate the fault, the fault elimination unit 23 keeps the slave device S3 in the power-off state, that is, the fault elimination unit 23 cuts off the power of the slave device S3 through the power switch control circuit P3; or, the fault elimination unit 23 can also control the corresponding signal on-off circuit SW3 through the switch control pin K3 to connect the clock line CL and the data line DA of the slave device S3 to the I 2 The I C bus 10 is disconnected, so that the slave device S3 is disconnected from the I 2 C bus 10 is completely isolated (disconnected), thereby ensuring that the I 2 The other slave devices S1, S2, S4-S6 on the I C bus 10 can communicate normally with the master device M, protecting the entire I 2 The C bus 10 is not affected by the faulty device (slave device S3) and can still maintain normal operation. At the same time, the fault elimination unit 23 records a fault message related to the slave device S3 and sends an I 2 The CPU 101 is notified of an abnormality of the I C bus, so that the CPU 101 can 2 The C bus abnormality notification checks the fault information recorded in the status monitoring circuit 2 through a communication interface (such as but not limited to the SPI bus) and promptly notifies the relevant system administrator for processing.

[0041] Furthermore, when the troubleshooting unit 23 determines that the main device M fails, the troubleshooting unit 23 will transmit a main device abnormality notification to the central processor 101, and the central processor 101 will perform a troubleshooting action on the main device M according to the main device abnormality notification, such as resetting the main device M.

[0042] It is worth mentioning that the above-mentioned power switch control circuit P1~P6, the reset circuit R1~R6 and the signal on-off circuit SW1~SW6 can be used one by one or all of them according to the design requirements of the circuit system; and the state monitoring circuit 2 of this embodiment can be but not limited to being implemented by a microcontroller unit (Microcontroller Unit, abbreviated as MCU), and can also be implemented by the above-mentioned central processing unit or other circuits such as a field programmable gate array (FieldProgrammable Gate Array, abbreviated as FPGA).

[0043] In summary, in the above embodiment, the state monitoring circuit 2 reads the logical relationship between the clock signal transmitted on the clock line CL of the master device M and the data signal transmitted on the data line DA in real time to determine whether the I 2 Whether an abnormality occurs on the I C bus 10 and whether the faulty device causing the abnormality on the bus is the master device M or a slave device communicating with the master device M, and troubleshooting or isolating the faulty device in real time to ensure the safety of the entire I C bus 10. 2 The I C bus 10 will not be affected by the faulty device and can still maintain normal operation, which greatly improves the 2 The reliability of the C-bus 10 truly achieves the efficacy and purpose of the present invention.

Claims

1. A kind of I 2 The circuit is applied to an electronic system having an I2C bus state monitoring and fault recovery and isolation circuit for electrically connecting a master device and a plurality of slave devices to communicate with each other. 2 C bus, a data line and a clock line of the master device and the I 2 A serial data line and a serial clock line of the C bus are electrically connected correspondingly; characterized in that: TheI 2 C bus status monitoring and fault recovery and isolation circuits include: a reading unit electrically connected to the data line and the clock line of the master device; a decoding unit electrically connected to the reading unit; and a fault elimination unit, which is electrically connected to the reading unit, the decoding unit and the slave device; and the I 2 The C bus status monitoring and fault recovery and isolation circuit performs the following monitoring procedures: The reading unit reads the data signal transmitted by the data line and the clock signal transmitted by the clock line; The decoding unit parses the data signal and the clock signal to obtain address information and a bit representing a read / write operation, wherein the address information is an address of one of the slave devices to be communicated by the master device, and the bit representing a read / write operation indicates that the master device is to read or write data to the slave device; The fault elimination unit determines that the logical relationship between the data signal and the clock signal does not meet the I 2 C bus transmission protocol and determines that the slave device fails according to the bit representing the read / write operation provided by the decoding unit, the fault elimination unit finds the slave device according to the address information provided by the decoding unit and performs a fault elimination action on the slave device.

2. The method according to claim 1 2 C bus status monitoring and fault recovery and isolation circuit, characterized by: The fault elimination unit determines that the logical relationship between the data signal and the clock signal does not meet the I 2 The C bus transmission protocol includes one of the following three situations:

1. The level of the clock signal is continuously at logic 1, and the level of the data signal is continuously at logic 0, and the duration exceeds 1 second; 2. No confirmation bit appears in the data signal and the duration exceeds 1 second; and 3. The level of the clock signal remains at logic 0 for a period of more than 1 second.

3. The method according to claim 1 2 C bus status monitoring and fault recovery and isolation circuit, characterized by: The troubleshooting unit comprises a plurality of power switch control circuits corresponding to the number of the slave devices, the power switch control circuits are respectively electrically connected to the slave devices to control whether to supply power to the slave devices, and a comparison table is stored in the troubleshooting unit, the comparison table records the power switch control circuits corresponding to the addresses of the slave devices; the troubleshooting action is that the troubleshooting unit searches the comparison table according to the address information of the slave device to obtain the power switch control circuit electrically connected to the slave device, and cuts off the power of the slave device through the power switch control circuit, so that the slave device is disconnected from the I 2 After the I C bus is isolated for a period of time, power is supplied to the slave device again, so that the slave device can reconnect to the I C bus. 2 C bus is electrically connected, the I 2 The C bus status monitoring and fault recovery and isolation circuit executes the monitoring program again.

4. The method according to claim 1 2 C bus status monitoring and fault recovery and isolation circuit, characterized by: The troubleshooting unit comprises a plurality of reset circuits corresponding to the number of the slave devices, the reset circuits are respectively electrically connected to the respective slave devices to perform a reset operation on the respective slave devices, and a comparison table is stored in the troubleshooting unit, the comparison table records the respective reset circuits corresponding to the addresses of the respective slave devices; the troubleshooting operation is that the troubleshooting unit searches the comparison table according to the address information of the slave device to obtain the reset circuit electrically connected to the corresponding slave device, and sends a reset signal through the reset circuit to reset the slave device and temporarily disconnect it from the I 2 C bus, so that the slave device completes the reset and then reconnects to the I 2 C bus is electrically connected, the I 2 The C bus status monitoring and fault recovery and isolation circuit executes the monitoring program again.

5. The method according to claim 3 or 4 2 C bus status monitoring and fault recovery and isolation circuit, characterized by: TheI 2 After the C bus status monitoring and fault recovery and isolation circuit executes the monitoring program on the slave device for N times, if the slave device is still in a fault state, the fault elimination unit will keep the slave device in a power-off state, record a fault information related to the slave device, and transmit an I 2 The abnormality of the I C bus is notified to a central processor of the electronic system, so that the central processor 2 C bus abnormality notification checks the fault information recorded by the fault troubleshooting unit; where N is greater than or equal to 2.

6. The method according to claim 3 or 4 2 C bus status monitoring and fault recovery and isolation circuit, characterized by: TheI 2 The I C bus status monitoring and fault recovery and isolation circuit also includes a signal on-off circuit corresponding to the number of the slave devices, each of which is arranged on a corresponding circuit connected to the I C bus status monitoring and fault recovery and isolation circuit. 2 The clock line and the data line of the I C bus are electrically connected to control the clock line and the data line of each slave device to communicate with the I C bus. 2 C bus is turned on or off; and the fault elimination unit further comprises a plurality of switch control pins, which are respectively electrically connected to each of the signal on-off circuits to control the operation of each of the signal on-off circuits, and the comparison table also records the switch control pins corresponding to the addresses of each of the slave devices; the I 2 After the C bus status monitoring and fault recovery and isolation circuit executes the monitoring program on the slave device for N times, if the slave device is still in a fault state, the fault elimination unit searches the comparison table according to the address information of the slave device to obtain the switch control pin corresponding to the slave device, and controls the corresponding signal on-off circuit through the switch control pin to connect the clock line and the data line of the slave device to the I2C bus status monitoring and fault recovery and isolation circuit. 2 C bus is disconnected, so that the slave device is 2 C bus is completely isolated; Where N is greater than or equal to 2.

7. The method according to claim 1 2 C bus status monitoring and fault recovery and isolation circuit, characterized by: The fault elimination unit determines that the logical relationship between the data signal and the clock signal does not meet the I 2 C bus transmission protocol and determines that the master device fails according to the bit representing the read / write operation provided by the decoding unit, the fault elimination unit transmits a master device abnormality notification to the central processor of the electronic system, so that the central processor performs the fault elimination action on the master device according to the master device abnormality notification.

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