Semiconductor device and preparation method thereof, storage system and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductors, and aims to solve the problem of electric leakage of the semiconductor device. A semiconductor device has a first region and a second region. The semiconductor device comprises a source electrode layer, a laminated structure and a plurality of channel structures. The laminated structure is arranged on one side of the source electrode layer and comprises gate dielectric layers and gate electrode layers which are alternately arranged in a laminated mode. The plurality of channel structures penetrate through the laminated structure to the source layer. The channel structure comprises a storage function layer and a channel layer. The plurality of channel structures includes a first channel structure and a second channel structure. The first channel structure is located in the first region, and the second channel structure is located in the second region. The channel layer, close to the source electrode layer, in the first channel structure is in direct contact with the source electrode layer, and a storage function is arranged between the channel layer, close to the source electrode layer, in the second channel structure and the source electrode layer. The semiconductor device is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, a storage system, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, the structure of semiconductor devices has gradually transitioned from a simple planar structure to a more complex three-dimensional structure. The integration density is improved by arranging the storage units in the semiconductor devices three-dimensionally on the substrate.

[0003] In the manufacturing process of semiconductor devices, a storage channel structure and a dummy channel structure are usually set. However, the dummy channel structure usually has a leakage problem, and the leakage of the dummy channel structure will affect the performance of the storage channel structure and further affect the product yield. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a storage system, and an electronic device, which are used to improve the leakage phenomenon of the semiconductor device and increase the yield rate of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor device is provided, and the semiconductor device has a first region and a second region. The semiconductor device includes: a source layer, a stacked structure and a plurality of channel structures. The stacked structure is arranged on one side of the source layer. The stacked structure includes a gate dielectric layer and a gate layer that are alternately stacked. A plurality of channel structures penetrate the stacked structure to the source layer. The channel structure includes a storage function layer and a channel layer. The plurality of channel structures include a plurality of first channel structures and at least one second channel structure. The first channel structure is located in the first region, and the second channel structure is located in the second region. Among them, a portion of the channel layer of the first channel structure close to the source layer is in direct contact with the source layer, and a portion of the channel layer of the second channel structure close to the source layer is provided with a storage function between the source layer and the source layer.

[0007] The semiconductor device provided by the embodiments of the present disclosure includes a source layer, a stacked structure and a channel structure, the channel structure includes a first channel structure and a second channel structure, the first channel structure is located in the first area of ​​the semiconductor device, and the second channel structure is located in the second area of ​​the semiconductor device, a portion of the channel layer of the first channel structure close to the source layer is arranged to be in direct contact with the source layer, and a storage function layer is arranged between a portion of the channel layer of the second channel structure close to the source layer and the source layer, thereby, when leakage occurs between the gate layer and the second channel structure, the storage function layer of the second channel structure can be used to separate the channel layer from the source layer, so that the leakage charge between the channel layer and the gate layer of the second channel structure cannot be transmitted to the source layer, so that the storage function of the first channel structure is not affected by the leakage charge, thereby improving the leakage problem of the semiconductor device, ensuring the storage function of the semiconductor device, and improving the yield of the semiconductor device.

[0008] In some embodiments, the semiconductor device further includes: a barrier layer disposed in the second region; the barrier layer is located between the source layer and the stacked structure, and between the source layer and the second channel structure.

[0009] In some embodiments, the material of the barrier layer is the same as that of the source layer.

[0010] In some embodiments, the material of the barrier layer includes polysilicon.

[0011] In some embodiments, the ratio of the thickness of the barrier layer to the thickness of the source layer is in a range of 1:2 to 1:1.

[0012] In some embodiments, the semiconductor device also includes: a stop layer arranged between the stacked structure and the source layer, and an insulating layer arranged between the stop layer and the source layer; the insulating layer is located in the second region, and the stop layer is located in the first region and the second region; the first channel structure also penetrates the stop layer, and the second channel structure also penetrates the stop layer and the insulating layer; the portion of the stop layer located in the first region is in contact with the source layer.

[0013] In some embodiments, the semiconductor device further includes: a plurality of contact structures; the plurality of contact structures are located in the second region and inside the stacked structure; and the contact structures are electrically connected to the gate layer.

[0014] In some embodiments, in a direction parallel to the plane where the gate layer is located, a distance between the contact structure and the first channel structure is greater than or equal to 15 μm.

[0015] In some embodiments, the semiconductor device further includes: a plurality of gate line isolation structures extending through the stacked structure to the source layer; the gate line isolation structures include a first isolation layer and a second isolation layer; the first isolation layer surrounds at least a portion of the second isolation layer; the plurality of gate line isolation structures include a plurality of first gate line isolation structures and at least one second gate line isolation structure; the first gate line isolation structure is located in the first region; the second gate line isolation structure is located in the second region; a portion of the second isolation layer of the first gate line isolation structure close to the source layer is in direct contact with the source layer, and the first isolation layer is disposed between a portion of the second isolation layer of the second gate line isolation structure close to the source layer and the source layer.

[0016] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: providing a three-dimensional array structure; the three-dimensional array structure having a first region and a second region; the three-dimensional array structure comprising a stacked structure, a contact structure and a plurality of channel structures penetrating the stacked structure; the stacked structure comprising a gate dielectric layer and a gate layer alternately stacked; the channel structure comprising a storage function layer and a channel layer; the plurality of channel structures comprising a plurality of first channel structures and at least one second channel structure, the first channel structure being located in the first region and the second channel structure being located in the second region; removing a portion of the storage function layer of the first channel structure protruding from the stacked structure to expose a portion of the channel layer of the first channel structure protruding from the stacked structure; forming the source layer, the source layer being in contact with a portion of the channel layer of the first channel structure extending out of the stacked structure; the storage function layer of the second channel structure separating the channel layer of the second channel structure from the source layer.

[0017] In some embodiments, the preparation method for removing the portion of the storage functional layer of the first channel structure that protrudes from the stacked structure includes: forming a barrier layer in the second region; the barrier layer covers the portion of the second channel structure that protrudes from the stacked structure; and using the barrier layer as a mask to remove the portion of the storage functional layer of the first channel structure that protrudes from the stacked structure.

[0018] In some embodiments, forming a barrier layer in the second area includes: forming a barrier film, the barrier film covering the stacked structure and the portions of the plurality of channel structures protruding from the stacked structure; forming a first mask pattern on the barrier film, the first mask pattern being located in the second area; using the first mask pattern as a mask, removing the portion of the barrier film located in the first area, retaining the portion of the barrier film located in the second area, to form the barrier layer.

[0019] In some embodiments, forming a first mask pattern on the barrier film includes: forming a first sub-mask on the barrier film; forming an anti-reflection film on the first sub-mask; forming a second mask pattern on the anti-reflection film, the second mask pattern being located in the second area; using the second mask pattern as a mask, removing the first sub-mask and the portion of the anti-reflection film located in the first area; removing the anti-reflection film, retaining the portion of the first sub-mask located in the second area, to form the first mask pattern.

[0020] In some embodiments, forming a first sub-mask on the barrier film includes: forming a second sub-mask on the barrier film; the second sub-mask covers the barrier film on the channel structure; forming a third sub-mask on the second sub-mask; the flexibility of the third sub-mask is greater than the flexibility of the second sub-mask; the second sub-mask and the third sub-mask constitute the first sub-mask.

[0021] On the other hand, a storage system is provided, comprising: a controller, and the semiconductor device as described in any one of the above embodiments; wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

[0022] On the other hand, an electronic device is provided, comprising: a storage system as described in any of the above embodiments, and a circuit board electrically connected to the storage system.

[0023] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0025] Figure 1 is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0026] Figure 2 is a structural diagram of a storage system according to some embodiments of the present disclosure;

[0027] Figure 3is a structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 4 is a structural diagram of another semiconductor device in some embodiments of the present disclosure;

[0029] Figure 5 is a structural diagram of another semiconductor device in some embodiments of the present disclosure;

[0030] Figure 6 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 7 to Figure 9 It is a structural diagram corresponding to each step in a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0032] Figure 10-11 It is a structural diagram corresponding to each step in another method for preparing a semiconductor device in some embodiments of the present disclosure;

[0033] Figure 12-13 It is a structural diagram corresponding to each step in another method for preparing a semiconductor device in some embodiments of the present disclosure;

[0034] Figure 14 to Figure 16 It is a structural diagram corresponding to each step in another method for preparing a semiconductor device in some embodiments of the present disclosure;

[0035] Figure 17-18 It is a structural diagram corresponding to each step in another method for preparing a semiconductor device in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0037] In the description of the present disclosure, it is necessary to understand that the terms "upper", "lower", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0041] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0042] like Figure 1As shown, some embodiments of the present disclosure provide an electronic device 3000, which may include any device that can store data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, etc. The electronic device 3000 may include a storage system 1000 configured to implement data storage as described below and a circuit board 2000 electrically connected to the storage system. The circuit board 2000 is used to provide electrical signals, etc. to the storage system 1000.

[0043] like Figure 2 As shown, some embodiments of the present disclosure provide a storage system 1000. The storage system 1000 is used in the above electronic device 3000. The storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 and is configured to control the semiconductor device 100 to store data.

[0044] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other electronic devices with memory.

[0045] In some examples, the storage system 1000 includes a controller 200 and a semiconductor device 100; wherein the storage system 1000 can be integrated into a memory card, for example. The memory card includes one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0046] In other examples, such as Figure 2 As shown, the memory system 1000 includes a controller 200 and a plurality of semiconductor devices 100 .

[0047] Exemplarily, the storage system 1000 includes a controller 200 and four semiconductor devices 100. The storage system 1000 may be integrated into a solid state drive (SSD).

[0048] In some examples, in storage system 1000, controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0049] In other examples, in the storage system 1000, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage of mobile devices such as smart phones, tablet computers, laptop computers, and enterprise storage arrays.

[0050] In some examples, the controller 200 may be configured to manage data stored in the semiconductor device 100 and communicate with an external device (eg, a host).

[0051] In some examples, the controller 200 may also be configured to control operations of the semiconductor device 100 , such as read, erase, and program operations.

[0052] In some examples, controller 200 may also be configured to manage various functions regarding data stored or to be stored in semiconductor device 100 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0053] In some examples, the controller 200 is also configured to process an error correction code regarding data read from or written to the semiconductor device 100 .

[0054] It is easy to understand that the controller 200 may also perform any other suitable functions, such as formatting the semiconductor device 100. For another example, the controller 200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0055] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0056] The controller 200 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0057] like Figure 3 As shown, some embodiments of the present disclosure provide a semiconductor device 100 that can be used in the storage system in the above embodiments.

[0058] The semiconductor device 100 has a first region A1 and a second region A2. For example, the first region A1 may be a core region, and the second region A2 may be a connection region or a step region. Figure 3 The core area is used to implement the storage function, and the connection area is used to implement the interconnection of the core areas.

[0059] The semiconductor device 100 comprises: a source layer 10 , a stacked structure 20 and a channel structure 30 .

[0060] Among them, the stacked structure 20 is arranged on one side of the source layer 10; the stacked structure 20 includes a gate dielectric layer 21 and a gate layer 22 that are alternately stacked. The material of the gate dielectric layer 21 can be an insulating material, and the insulating material can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the gate layer 22 can include a conductive material, for example, the conductive material can include at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, doped single crystal silicon and silicide. A protective layer can also be arranged between the gate layer 22 and the gate dielectric layer 21, and the protective layer covers the gate layer. The material of the protective layer can include a material with a high dielectric constant, such as silicon oxide, silicon nitride, etc.

[0061] The number of channel structures 30 in the semiconductor device 100 may be multiple. Multiple channel structures 30 penetrate the stacked structure 20 and extend into the source layer 10. The channel structure 30 includes a storage function layer 31 and a channel layer 32. The storage function layer 31 includes a barrier layer, a capture layer and a tunnel layer stacked in sequence. The channel layer 32 is stacked on the tunnel layer. The material of the barrier layer may be silicon oxide, the material of the capture layer may be silicon nitride, and the material of the tunnel layer may be silicon oxide or silicon oxynitride. The material of the channel layer 32 may be polysilicon.

[0062] The plurality of channel structures 30 include a plurality of first channel structures 301 and at least one second channel structure 302. The first channel structures 301 are located in the first area A1, and the second channel structures 302 are located in the second area A2. The number of the first channel structures 301 may be greater than the number of the second channel structures 302.

[0063] The first channel structure 301 can be used as a storage channel structure, and the second channel structure 302 can be used as a virtual channel structure. Of course, part of the first channel structure 301 can also be used as a virtual channel structure, and the embodiments of the present disclosure are not limited to this. The virtual channel structure can be the same as the structure of the storage channel structure, or it can be different, and this embodiment is not limited to this. It should be noted that the virtual channel structure is not used as a storage unit, but plays a role in providing mechanical support and / or load balancing for the semiconductor device 100.

[0064] In one implementation, in a semiconductor device, leakage is prone to occur between the gate layer and the second channel structure in the stacked structure, so that the charge in the gate layer is transferred to the source layer through the capture layer and the channel layer of the second channel structure, and then transferred from the source layer to the channel layer of the first channel structure, thereby affecting the threshold voltage between the channel layer and the gate layer of the first channel structure 301, for example, from 26V to between 22.5V and 26V, affecting the storage function of the first channel structure, affecting the function of the semiconductor device, and reducing the yield rate of the semiconductor device.

[0065] Based on this, in some embodiments of the present disclosure, Figure 3 As shown, a portion of the channel layer 32 of the first channel structure 301 close to the source layer 10 is in direct contact with the source layer 10 , and a storage function layer 31 is provided between a portion of the channel layer 32 of the second channel structure 302 close to the source layer 10 and the source layer 10 .

[0066] For example, a portion of the storage function layer 31 of the first channel structure 301 close to the source layer 10 has an opening, and the channel layer 32 directly contacts the source layer 10 through the opening, thereby achieving electrical connection between the channel layer 32 and the source layer 10 .

[0067] For example, a portion of the storage function layer 31 of the second channel structure 302 close to the source layer 10 has no opening, the storage function layer 31 in the second channel structure 302 is in direct contact with the source layer 10 , and the channel layer 32 has no electrical connection with the source layer 10 . Therefore, the storage function layer 31 of the second channel structure 302 is used to separate the channel layer 32 from the source layer 10, so that the leakage charge between the capture layer, the channel layer 32 and the gate layer 22 of the second channel structure 302 cannot be transmitted to the source layer 10, so that the storage function of the first channel structure 301 is not affected by the leakage between the channel layer 32 and the gate layer 22 of the second channel structure 302, thereby ensuring the storage function of the semiconductor device 100 and avoiding the leakage charge between the gate layer 22 and the second channel structure 302 from being transmitted to the channel layer 32 of the first channel structure 301 through the source layer 10, thereby avoiding affecting the threshold voltage of the channel layer 32 and the gate layer 22 of the first channel structure 301 and avoiding affecting the storage function of the semiconductor device 100.

[0068] The semiconductor device 100 provided in the embodiment of the present disclosure includes a source layer 10, a stacked structure 20 and a channel structure 30, wherein the channel structure 30 includes a first channel structure 301 and a second channel structure 302, wherein the first channel structure 301 is located in a first area A1 of the semiconductor device 100, and the second channel structure 302 is located in a second area A2 of the semiconductor device 100, wherein a portion of the channel layer 32 of the first channel structure 301 close to the source layer 10 is in direct contact with the source layer 10, and a portion of the channel layer 32 of the second channel structure 302 close to the source layer 10 is in direct contact with the source layer 10. A storage function layer 31 is arranged between the gate layer 22 and the source layer 10. Therefore, when leakage occurs between the gate layer 22 and the second channel structure 302, the storage function layer 31 of the second channel structure 302 can be used to separate the channel layer 32 from the source layer 10, so that the leakage charge between the channel layer 32 of the second channel structure 302 and the gate layer 22 cannot be transmitted to the source layer 10, so that the storage function of the first channel structure 301 is not affected by the leakage charge, thereby ensuring the storage function of the semiconductor device 100 and improving the yield of the semiconductor device 100.

[0069] In some examples, such as Figure 3 As shown, the semiconductor device 100 further includes: a plurality of gate line isolation structures 40 penetrating the stacked structure 20 to the source layer 10 .

[0070] The gate line isolation structure 40 can separate the semiconductor device 100 into a plurality of memory blocks, and can effectively adjust the warping deformation of the memory blocks and provide good support for the memory blocks.

[0071] The plurality of gate line isolation structures 40 include a plurality of first gate line isolation structures 401 and at least one second gate line isolation structure 402 ; the first gate line isolation structure 401 is located in the first area A1 ; and the second gate line isolation structure 402 is located in the second area A2 .

[0072] There are many specific structures of the gate line isolation structure 40 , which can be selected and set according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0073] In some examples, the gate line isolation structure 40 only includes the first isolation layer 41. The material of the first isolation layer 41 can be an insulating material, such as silicon oxide.

[0074] In other examples, such as Figure 3 As shown, the gate line isolation structure 40 includes a first isolation layer 41 and a second isolation layer 42; the first isolation layer 41 surrounds at least a portion of the second isolation layer 42. The material of the first isolation layer 41 can be an insulating material, such as silicon oxide, and the material of the second isolation layer 42 can be a semiconductor material, such as polysilicon, etc. The second isolation layer 42 composed of polysilicon material can play a good supporting role. For another example, the material of the first isolation layer 41 can be silicon oxide, and the material of the second isolation layer 42 can be carbon, etc.

[0075] In another implementation, in the semiconductor structure, leakage is also prone to occur between the gate layer in the stacked structure and the second gate line isolation structure located in the second area of ​​the semiconductor device, so that the charge in the gate layer is transmitted to the source layer through the second isolation layer of the second gate line isolation structure, and then transmitted from the source layer to the channel layer of the first channel structure, thereby affecting the threshold voltage between the channel layer and the gate layer of the first channel structure, affecting the storage function of the first channel structure, and then affecting the function of the semiconductor device.

[0076] In the example disclosed herein, a second isolation layer 42 close to the source layer 10 in the first gate line isolation structure 401 is arranged to be in direct contact with the source layer 10 , and a first isolation layer 41 is arranged between the isolation layer close to the source layer 10 in the second gate line isolation structure 402 and the source layer 10 .

[0077] For example, in the first gate line isolation structure 401, the first isolation layer 41 near the source layer 10 has an opening, and the second isolation layer 42 passes through the opening and directly contacts the source layer 10. In the second gate line isolation structure 402, the first isolation layer 41 near the source layer 10 has no opening, and the first isolation layer 41 contacts the source layer 10.

[0078] Therefore, by utilizing the first isolation layer 41 of the second gate line isolation structure 402 to separate the second isolation layer 42 from the source layer 10, the storage function of the first channel structure 301 of the first area A1 of the semiconductor device 100 can be ensured to be unaffected by leakage between the second gate line isolation structure 402 and the source layer 10, thereby avoiding leakage charge between the gate layer 22 and the second gate line isolation structure 402 from being sequentially transmitted to the source layer 10 and the channel layer 32 of the first channel structure 301 through the second isolation layer 42 of the second gate line isolation structure 402, thereby avoiding affecting the threshold voltage of the first channel structure 301.

[0079] like Figure 3 As shown, the semiconductor device 100 further includes: a stop layer 50 disposed between the stacked structure 20 and the source layer 10, and an insulating layer 60 disposed between the stop layer 50 and the source layer 10. The stop layer 50 covers the stacked structure 20, and the insulating layer 60 is located on the side of the stop layer 50 away from the stacked structure 20. The insulating layer 60 is located in the second area A2, and the stop layer 50 is located in the first area A1 and the second area A2. The first channel structure 301 also penetrates the stop layer 50, and the second channel structure 302 also penetrates the stop layer 50 and the insulating layer 60. The portion of the stop layer 50 located in the first area A1 contacts the source layer 10. The portion of the stop layer 50 located in the second area A2 contacts the insulating layer 60. The portion of the stop layer 50 close to the channel structure 30 contacts the side of the storage function layer 31 of the channel structure 30 away from the channel layer 32. A portion of the stop layer 50 close to the gate line isolation structure 40 contacts a side of the first isolation layer 41 of the gate line isolation structure 40 away from the second isolation layer 42 .

[0080] It can be understood that the first gate line isolation structure 401 also penetrates the stop layer 50 , and the second gate line isolation structure 402 also penetrates the stop layer 50 and the insulating layer 60 .

[0081] The material of the stop layer 50 may be a conductive material or a semiconductor material.

[0082] For example, the material of the stop layer 50 is the same as that of the source layer 10. Thus, the contact resistance between the stop layer 50 and the source layer 10 can be reduced.

[0083] For example, the materials of the stop layer 50 and the source layer 10 may both be polysilicon.

[0084] For example, the material of the insulating layer 60 may be silicon oxide or the like.

[0085] The portion of the stop layer 50 located in the first area A1 is arranged to contact the source layer 10 , so that the stop layer 50 and the source layer 10 are electrically connected, thereby enhancing the electrical connection between the source layer 10 and the channel layer 32 .

[0086] In some embodiments, Figure 4 As shown, the semiconductor device 100 further includes a barrier layer 80 disposed in the second area A2 . The barrier layer 80 is located between the source layer 10 and the stacked structure 20 , and between the source layer 10 and the second channel structure 302 .

[0087] In the case where the semiconductor device 100 includes the stop layer 50 and the insulating layer 60 , a portion of the barrier layer 80 is located between the insulating layer 60 and the source layer 10 .

[0088] The barrier layer 80 is only located in the second area A2 and covers the surface of the storage function layer 31 of the second channel structure 302, so that when the portion of the storage function layer 31 of the first channel structure 301 protruding from the stacked structure 20 (or the stop layer 50) is removed, the storage function layer 31 of the second channel structure 302 is protected, and the portion of the storage function layer 31 of the second channel structure 302 protruding from the stacked structure 20 (or the stop layer 50) is retained, so as to avoid the channel layer 32 of the second channel structure 302 from being exposed and contacting the source layer 10, thereby avoiding the gate layer 22 from leaking to the channel layer 32 of the second channel structure 302, the source layer 10, and the channel layer 32 of the first channel structure 301 in sequence due to the above-mentioned over-engraving, thereby ensuring that the storage function of the first channel structure 301 is not affected.

[0089] Of course, when the semiconductor device 100 includes the above-mentioned first gate line isolation structure 401 and the second gate line isolation structure 402, the barrier layer 80 also covers the first isolation layer 41 of the second gate line isolation structure 402, so that when the portion of the first isolation layer 41 of the first gate line isolation structure 401 that protrudes out of the stacked structure 20 (or the stop layer 50) is removed, the first isolation layer 41 of the second gate line isolation structure 402 is protected, and the portion of the first isolation layer 41 of the second gate line isolation structure 402 that protrudes out of the stacked structure 20 (or the stop layer 50) is retained, so as to avoid the second isolation layer 42 of the second gate line isolation structure 402 from being exposed and contacting the source layer 10, thereby avoiding the gate layer 22 from leaking to the second isolation layer 42 of the second gate line isolation structure 402, the source layer 10, and the channel layer 32 of the first channel structure 301 in sequence due to the above-mentioned over-engraving, thereby ensuring that the storage function of the first channel structure 301 is not affected.

[0090] Exemplarily, the material of the barrier layer 80 is different from that of the source layer 10. For example, the material of the barrier layer 80 may be an insulating material. For another example, the material of the barrier layer 80 may be a conductive material or a semiconductor material.

[0091] Exemplarily, the material of the barrier layer 80 is the same as that of the source layer 10. Thus, the bonding strength between the barrier layer 80 and the source layer 10 can be improved, and the barrier layer 80 and the source layer 10 can be formed by the same preparation process, which is conducive to simplifying the preparation process.

[0092] For example, the source layer 10 may be made of polysilicon. The barrier layer 80 may also be made of polysilicon.

[0093] The ratio of the thickness of the barrier layer 80 to the thickness of the source layer 10 is in the range of 1:2 to 1:1. Thus, the barrier layer 80 can cover the second channel structure 302, and avoid the barrier layer 80 being too thin to well protect the storage function layer 31 of the second channel structure 302. It can also avoid the difference between the sum of the thickness of the barrier layer 80 and the source layer 10 located in the second area A2 and the thickness of the source layer 10 located in the first area A1 being too large, so that the overall thickness of the second channel structure 302 and the barrier layer 80 and the source layer 10 located thereon are slightly different from or substantially equal to the overall thickness of the first channel structure 301 and the source layer 10 located thereon, thereby avoiding the need to adjust the preparation process of the subsequent back-end process interconnection layer, which is conducive to simplifying the preparation process of the semiconductor device 100.

[0094] For example, the ratio of the thickness of the barrier layer 80 to the thickness of the source layer 10 may range from 1:2 to 3:5, 1:2 to 4:5, 1:2 to 4:7, 4:5 to 1:1, or 6:7 to 1:1.

[0095] For example, the ratio of the thickness of the barrier layer 80 to the thickness of the source layer 10 may be 1:2, 4:7, 3:5, 4:5, 6:7 or 1:1.

[0096] For example, the thickness of the barrier layer 80 may be 21 nm, and the thickness of the source layer 10 may be 40 nm.

[0097] like Figure 3 As shown, the semiconductor device 100 further includes: a plurality of contact structures 70 . The plurality of contact structures 70 are located in the second area A2 and inside the stacked structure 20 ; and the contact structures 70 are electrically connected to the gate layer 22 .

[0098] The plurality of contact structures 70 are located on a side of the second channel structure 302 away from the first channel structure 301. One contact structure 70 is electrically connected to one gate layer 22 and transmits an electrical signal to the gate layer 22.

[0099] It is understood that the process for preparing the contact structure 70 generally includes an etching process and a deposition process. First, an etching process is used to form a groove structure in the second area A2 of the stacked structure 20, and the groove structure extends to the gate layer 22 in the stacked structure 20. Then, a vapor deposition process is used to fill the material in the groove structure to form the contact structure 70. In the process of forming the groove structure, over-etching is likely to occur, and the protective layer outside the gate layer 22 of the second area A2 is etched away, or the storage function layer 31 (or the barrier layer in the storage function layer) between the gate layer 22 and the corresponding channel layer 32 is etched away, or the first isolation layer 41 between the gate layer 22 and the corresponding second isolation layer 42 is etched away. While filling the material in the groove structure, the material is also filled in the etched protective layer or storage function layer 31 or the first isolation layer, so that leakage is likely to occur between the gate layer 22 and the corresponding second channel structure 302 channel layer 32, and the second isolation layer 42 of the second gate line isolation structure 402.

[0100] In the embodiment of the present disclosure, the channel layer 32 of the second channel structure 302 is not in direct contact with the source layer 10, and the channel layer 32 is separated from the source layer 10 by the storage function layer 31 of the second channel structure 302, so that the leakage between the gate layer 22 and the channel layer 32 of the second channel structure 302 will not affect the channel layer 32 of the first channel structure 301, thereby ensuring the storage function of the first channel structure 301 of the first area A1 and the storage function of the semiconductor device 100. The second isolation layer 42 of the second gate line isolation structure 402 is not in direct contact with the source layer 10, and the second isolation layer 41 of the second gate line isolation structure 402 is used to separate the second isolation layer 42 from the source layer, so that the leakage between the gate layer 22 and the second isolation layer 42 of the second gate line isolation structure 402 will not affect the channel layer 32 of the first channel structure 301, thereby further ensuring the storage function of the first channel structure 301 of the first area A1 and the storage function of the semiconductor device 100.

[0101] For example, Figure 3 As shown, in the stacked structure 20 , the portion of the contact structure 70 located on a side away from the second channel structure 302 includes gate dielectric layers 21 and sacrificial layers 23 that are alternately stacked.

[0102] In some examples, in a direction parallel to the plane where the gate layer 22 is located, the distance between the contact structure 70 and the first channel structure 301 is greater than or equal to 15 μm.

[0103] For example, in a direction parallel to the plane where the gate layer 22 is located, the distance between the contact structure 70 and the first channel structure 301 may range from 15 μm to 30 μm, from 15 μm to 40 μm, or from 25 μm to 40 μm.

[0104] For example, in a direction parallel to the plane where the gate layer 22 is located, the distance between the contact structure 70 and the first channel structure 301 is 15 μm, 20 μm, 25 μm, 32 μm or 40 μm.

[0105] It is understandable that the greater the distance between the contact structure 70 and the first channel structure 301 , the less likely the storage function layer 31 of the first channel structure 301 will be over-etched during the preparation of the contact structure 70 , and the less likely the channel layer 32 of the first channel structure 301 will leak electricity.

[0106] The distance between the contact structure 70 and the first channel structure 301 is set within the above range. The first channel structure 301 is far away from the contact structure 70, which improves the yield rate of the semiconductor device 100 and avoids over-etching of the protective layer of the gate layer 22 close to the first channel structure 301 or over-etching of the storage function layer 31 of the first channel structure 301 during the preparation of the contact structure 70. This can prevent the electrical signal of the gate layer 22 from leaking to the channel layer 32 of the first channel structure 301, avoid affecting the threshold voltage of the first channel structure 301, and ensure the storage function of the semiconductor device 100.

[0107] like Figure 4 As shown, the semiconductor device 100 provided in the embodiment of the present disclosure further includes an alignment structure 90 . The alignment structure 90 is located on a side of the contact structure 70 away from the second channel structure 302 , and the alignment structure 90 is located between the stacked structure 20 and the source layer 10 .

[0108] The alignment structure 90 is used to achieve alignment with the back-end process interconnect layer.

[0109] like Figure 5 As shown, the semiconductor device 100 provided by the embodiment of the present disclosure further includes: a peripheral circuit structure 110 and a back-end process interconnection layer 120 .

[0110] The peripheral circuit structure 110 may include a carrier substrate and peripheral devices disposed on the carrier substrate. The peripheral circuit structure 110 may be electrically connected to the gate layer 22 and the first channel structure 301. The peripheral devices may include, for example, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), or any active (or passive) components of a circuit (e.g., transistors, diodes, resistors, capacitors, etc.).

[0111] For example, the peripheral circuit structure 110 may include a plurality of transistors, all or part of which are formed in the carrier substrate (e.g., below the top surface of the carrier substrate) and / or directly on the carrier substrate. Similarly, shallow trench isolation and doped regions (e.g., source and drain regions of the transistors) may also be formed in the carrier substrate.

[0112] It should be noted that the peripheral circuit structure 110 may also include any other circuits compatible with advanced logic processes. Exemplarily, the peripheral circuit structure 110 includes logic circuits (e.g., processors and programmable logic devices (PLDs)), and / or storage circuits (e.g., static random access memories (SRAMs)).

[0113] The back end of line (BEOL) 120 is used to transmit electrical signals to the array device and the peripheral circuit structure 110. The back end of line interconnection layer 120 includes an interconnection conductor layer and a contact layer. The interconnection conductor layer and the contact layer include conductive materials, such as tungsten, copper, aluminum, silicide, and / or other suitable conductive materials. For example, the contact layer includes a source contact electrically connected to the source layer 10, a contact contact electrically connected to the contact structure 70, etc. The interconnection conductor layer includes a lead pad Pad, etc.

[0114] Some embodiments of the present disclosure also provide a method for preparing a semiconductor device 100, which is used to prepare the semiconductor device 100 in some of the above embodiments. Figure 6 As shown, the preparation method includes: S100~S300.

[0115] S100, such as Figure 7 As shown, a three-dimensional array structure 101 is provided; the three-dimensional array structure 101 has a first area A1 and a second area A2; the three-dimensional array structure 101 includes a stacked structure 20 and a plurality of channel structures 30 penetrating the stacked structure 20; the stacked structure 20 includes a gate dielectric layer 21 and a gate layer 22 alternately stacked; the channel structure 30 includes a storage function layer 31 and a channel layer 32; the plurality of channel structures 30 include a plurality of first channel structures 301 and at least one second channel structure 302, the first channel structure 301 is located in the first area A1, and the second channel structure 302 is located in the second area A2.

[0116] It is understandable that if Figure 7 As shown, the three-dimensional array structure 101 further includes: a contact structure 70, a stop layer 50 and an insulating structure layer 60' located on the stacked structure 20, and a plurality of gate line isolation structures 40 penetrating the stop layer 50, the insulating structure layer 60' and the stacked structure 20. For the structures of the contact structure 70, the stop layer 50 and the gate line isolation structure 40, reference may be made to the introduction in some of the above embodiments of the present disclosure, which will not be repeated here.

[0117] S200, such as Figure 8 As shown, a portion of the storage function layer 31 of the first channel structure 301 protruding from the stacked structure 20 is removed, exposing a portion of the channel layer 32 of the first channel structure 301 protruding from the stacked structure 20 .

[0118] For example, an etching process may be used to remove the portion of the storage function layer 31 of the first channel structure 301 that protrudes out of the stacked structure 20. The etching process may be a dry etching process.

[0119] For example, in the case where the three-dimensional array structure 101 includes a first gate line isolation structure 401 and a second gate line isolation structure 402, when removing a portion of the storage function layer 31 of the first channel structure 301 that protrudes from the stacked structure 20, the portion of the first isolation layer 41 of the first gate line isolation structure 401 that protrudes from the stacked structure 20 is also removed at the same time, exposing a portion of the second isolation layer 42 of the first gate line isolation structure 401 that protrudes from the stacked structure 20.

[0120] For example, in the case where the three-dimensional array structure 101 includes a stop layer 50 and an insulating layer 60, when removing the portion of the storage function layer 31 of the first channel structure 301 protruding from the stacked structure 20, the portion of the insulating structure layer 60' located in the first area A1 is removed simultaneously to form the insulating layer 60, so that the portion of the stop layer 50 located in the first area A1 is exposed. The portion of the storage function layer 31 of the first channel structure 301 protruding from the stop layer 50 is removed to expose the portion of the channel layer 32 of the first channel structure 301 protruding from the stop layer 50. Of course, when removing the portion of the storage function layer 31 of the first channel structure 301 protruding from the stop layer 50, the portion of the first isolation layer 41 of the first gate line isolation structure 401 protruding from the stop layer 50 is also removed simultaneously to expose the portion of the second isolation layer 42 of the first gate line isolation structure 401 protruding from the stop layer 50.

[0121] S300, such as Fig. 9 As shown, a source layer 10 is formed, and the source layer 10 contacts the portion of the channel layer 32 of the first channel structure 301 extending out of the stacked structure 20 ; the storage function layer 31 of the second channel structure 302 separates the channel layer 32 of the second channel structure 302 from the source layer 10 .

[0122] Exemplarily, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof can be used to deposit the source layer 10 on the side of the insulating layer 60, the stop layer 50 and the channel structure 30 away from the stacked structure 20.

[0123] The source layer 10 covers the exposed surface of the channel layer 32 of the first channel structure 301, and is in direct contact with the exposed portion of the channel layer 32 to form an electrical connection. The source layer 10 covers the surface of the storage function layer 31 of the second channel structure 302 away from the stacked structure 20, and the source layer 10 has no contact with the channel layer 32 of the second channel structure 302, so that the electrical connection between the channel layer 32 of the second channel structure 302 and the source layer 10 is disconnected by using the storage function layer 31 of the second channel structure 302, thereby preventing the leakage charge between the channel layer 32 of the second channel structure 302 and the gate layer 22 from being transmitted to the channel layer 32 of the first channel structure 301 through the source layer 10, thereby avoiding affecting the storage function of the semiconductor device 100.

[0124] For example, in the case where the three-dimensional array structure 101 includes a first gate line isolation structure 401 and a second gate line isolation structure 402, the source layer 10 also covers the exposed surface of the second isolation layer 42 of the first gate line isolation structure 401, and directly contacts the exposed portion of the second isolation layer 42 to form an electrical connection. The source layer 10 covers the surface of the first isolation layer 41 of the second gate line isolation structure 402 away from the stacked structure 20, and the source layer 10 is not in contact with the second isolation layer 42 of the second gate line isolation structure 402, so that the first isolation layer 41 of the second gate line isolation structure 402 is used to disconnect the electrical connection between the second isolation layer 42 of the second gate line isolation structure 402 and the source layer 10, thereby preventing the leakage charge between the second isolation layer 42 of the second gate line isolation structure 402 and the gate layer 22 from being transmitted to the channel layer 32 of the first channel structure 301 through the source layer 10, thereby avoiding affecting the storage function of the semiconductor device 100.

[0125] In some embodiments, in the above S200 , a portion of the storage function layer 31 of the first channel structure 301 protruding out of the stacked structure 20 is removed, and the preparation method includes: S210 to S220 .

[0126] S210, such as Fig.10 As shown, a barrier layer 80 is formed in the second area A2 ; the barrier layer 80 covers the portion of the second channel structure 302 extending out of the stacked structure 20 .

[0127] For example, the barrier layer 80 also covers the portion of the second gate line isolation structure 402 extending out of the stacked structure 20 .

[0128] S220, such as Fig.11 As shown, the barrier layer 80 is used as a mask to remove the portion of the storage function layer 31 of the first channel structure 301 that protrudes out of the stacked structure 20 .

[0129] For example, while removing the portion of the storage function layer 31 of the first channel structure 301 protruding from the stacked structure 20 , the portion of the insulating layer 60 located in the first area A1 is removed, and the portion of the first isolation layer 41 of the first gate line isolation structure 401 protruding from the stacked structure 20 is removed.

[0130] In some embodiments, in the above S210 , forming the barrier layer 80 in the second area A2 includes: S201 to S203 .

[0131] S201, such as Fig.12 As shown, a barrier film 81 is formed, and the barrier film 81 covers the stacked structure 20 and the portions of the plurality of channel structures 30 protruding out of the stacked structure 20 .

[0132] For example, the barrier film 81 may be formed by a thin film deposition process of CVD, PVD, ALD or any combination thereof.

[0133] The barrier film 81 also covers the portions of the plurality of gate line isolation structures 40 protruding out of the stacked structure 20 .

[0134] S202, such as Fig.13 As shown, a first mask pattern 82 is formed on the barrier film 81 , and the first mask pattern 82 is located in the second area A2 .

[0135] For example, the first mask pattern 82 covers the second channel structure 302 and the second gate line isolation structure 402 .

[0136] S203, such as Fig.13 , Fig.11 and Fig.18 As shown, the first mask pattern 82 is used as a mask to remove a portion of the barrier film 81 located in the first area A1 and retain a portion of the barrier film 81 located in the second area A2 to form a barrier layer 80 .

[0137] By adopting the above-mentioned preparation method, the barrier layer 80 covers and protects the second channel structure 302 and the second gate line isolation structure 402, thereby avoiding the removal of the storage function layer 31 of the second channel structure 302 and the first isolation layer 41 of the second gate line isolation structure 402 in S220. Therefore, when leakage occurs between the gate layer 22 and the second channel structure 302 or the second gate line isolation structure 402, the leakage charge cannot be transmitted to the source layer 10 and the channel layer 32 of the first channel structure 301, thereby ensuring the storage function of the first area A1 of the semiconductor device 100.

[0138] In some embodiments, in the above S202 , forming the first mask pattern 82 on the barrier film 81 includes: S2021 - S2025 .

[0139] S2021, as Fig.14 As shown, a first sub-mask 83 is formed on the barrier film 81 .

[0140] For example, a spin coating process may be used to form the first sub-mask 83. The material of the first sub-mask 83 may be a photosensitive polymer, such as spin coated carbon (SOC).

[0141] S2022, such as Fig.14 As shown, an anti-reflection film 84 is formed on the first sub-mask 83 .

[0142] For example, the anti-reflection film 84 may be formed by a spin coating process.

[0143] For example, the material of the anti-reflection film 84 may include organic siloxane.

[0144] S2023, such as Fig.14 As shown, a second mask pattern 85 is formed on the anti-reflection film 84, and the second mask pattern 85 is located in the second area A2.

[0145] For example, a spin coating process may be used to form the second mask pattern 85. The material of the second mask pattern 85 may be photoresist.

[0146] S2024, such as Fig.14 and Fig.15 As shown, the second mask pattern 85 is used as a mask to remove the first sub-mask 83 and the portion of the anti-reflection film 84 located in the first area A1.

[0147] S2025, such as Fig.16 As shown, the anti-reflection film 84 is removed, and the portion of the first sub-mask 83 located in the second area A2 is retained to form a first mask pattern 82.

[0148] The above preparation method is used to form a first mask pattern 82 , so that the first mask pattern 82 can be used to protect the portion of the barrier film 81 located in the second area A2 , making it easier to remove the portion of the barrier film 81 located in the first area A1 .

[0149] In some embodiments, in the above S2021, forming a first sub-mask 83 on the barrier film 81 includes: Fig.17 As shown, a second sub-mask 86 is formed on the barrier film 81; the second sub-mask 86 covers the barrier film 81 on the channel structure 30; a third sub-mask 87 is formed on the second sub-mask 86; the flexibility of the third sub-mask 87 is greater than the flexibility of the second sub-mask 86; the second sub-mask 86 and the third sub-mask 87 constitute the first sub-mask 83.

[0150] In addition, after forming the first sub-mask 83, as Fig.17 and Fig.18 As shown, using the second mask pattern 85 as a mask, the portion of the anti-reflection film 84 located in the first area A1, the portion of the third sub-mask 87 located in the first area A1, and the portion of the second sub-mask 86 located in the first area A1 are removed in sequence, and then the portion of the anti-reflection film 84 located in the second area A2 is removed. The portion of the second sub-mask 86 located in the second area A2 and the portion of the third sub-mask 87 located in the second area A2 constitute the first mask pattern 82.

[0151] Among them, the above-mentioned third sub-mask 87 has good flexibility, so that it can play a role similar to that of tape. Therefore, the third sub-mask layer 87 can be used to enhance the covering effect of the second sub-mask layer 86, so as to avoid the large surface tension of the second sub-mask layer 86, which causes cracks in the part of the second sub-mask layer 86 located on the channel structure 30 and the part located on the gate line isolation structure 40, thereby affecting its covering effect.

[0152] For example, the second sub-mask 86 and the third sub-mask 87 may be formed by a spin coating process.

[0153] For example, the material of the second sub-mask 86 may be SOC, and the material of the third sub-mask 87 may be amorphous carbon.

[0154] For example, the second sub-mask 86 covers the surface of the trench structure 30 and the gate line isolation structure 40 protruding out of the stacked structure 20 .

[0155] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device has a first region and a second region; The semiconductor device comprises: source layer; A stacked structure arranged on one side of the source layer; the stacked structure includes gate dielectric layers and gate layers alternately stacked; A plurality of channel structures extending from the stacked structure to the source layer; the channel structures include a storage function layer and a channel layer; the plurality of channel structures include a plurality of first channel structures and at least one second channel structure, the first channel structure is located in the first region, and the second channel structure is located in the second region; The portion of the channel layer of the first channel structure close to the source layer is in direct contact with the source layer, and the storage function layer is arranged between the portion of the channel layer of the second channel structure close to the source layer and the source layer.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a barrier layer disposed in the second region; The barrier layer is located between the source layer and the stacked structure, and between the source layer and the second channel structure.

3. The semiconductor device according to claim 2, characterized in that The material of the barrier layer is the same as that of the source layer.

4. The semiconductor device according to claim 2, characterized in that The material of the barrier layer includes polysilicon.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that: The ratio of the thickness of the barrier layer to the thickness of the source layer is in the range of 1:2 to 1:

1.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a stop layer disposed between the stacked structure and the source layer, and an insulating layer disposed between the stop layer and the source layer; The insulating layer is located in the second region, and the stop layer is located in the first region and the second region; the first channel structure also penetrates the stop layer, and the second channel structure also penetrates the stop layer and the insulating layer; a portion of the stop layer located in the first region contacts the source layer.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes: a plurality of contact structures; the plurality of contact structures are located in the second region and inside the stacked structure; and the contact structures are electrically connected to the gate layer.

8. The semiconductor device according to claim 7, characterized in that In a direction parallel to the plane where the gate layer is located, a distance between the contact structure and the first channel structure is greater than or equal to 15 μm.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: The semiconductor device further comprises: a plurality of gate line isolation structures penetrating the stacked structure to the source layer; the gate line isolation structures comprise a first isolation layer and a second isolation layer; the first isolation layer surrounds at least a portion of the second isolation layer; The multiple gate line isolation structures include multiple first gate line isolation structures and at least one second gate line isolation structure; the first gate line isolation structure is located in the first area; the second gate line isolation structure is located in the second area; a portion of the second isolation layer of the first gate line isolation structure close to the source layer is in direct contact with the source layer, and a portion of the second isolation layer of the second gate line isolation structure close to the source layer is provided with the first layer structure between the source layer and the source layer.

10. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: A three-dimensional array structure is provided; the three-dimensional array structure has a first region and a second region; the three-dimensional array structure includes a stacked structure, a contact structure, and a plurality of channel structures penetrating the stacked structure; the stacked structure includes a gate dielectric layer and a gate layer alternately stacked; the channel structure includes a storage function layer and a channel layer; the plurality of channel structures include a plurality of first channel structures and at least one second channel structure, the first channel structure is located in the first region, and the second channel structure is located in the second region; removing a portion of the storage function layer of the first channel structure protruding from the stacked structure, exposing a portion of the channel layer of the first channel structure protruding from the stacked structure; The source layer is formed, and the source layer contacts a portion of the channel layer of the first channel structure extending out of the stacked structure; the storage function layer of the second channel structure separates the channel layer of the second channel structure from the source layer.

11. The preparation method according to claim 10, characterized in that: The removing of the portion of the storage function layer of the first channel structure protruding from the stacked structure, the preparation method comprises: forming a barrier layer in the second region; the barrier layer covers a portion of the second channel structure extending out of the stacked structure; Using the barrier layer as a mask, a portion of the storage function layer of the first channel structure that protrudes out of the stacked structure is removed.

12. The preparation method according to claim 11, characterized in that: The forming of the barrier layer in the second region comprises: forming a barrier film, wherein the barrier film covers the stacked structure and portions of the plurality of channel structures protruding from the stacked structure; forming a first mask pattern on the barrier film, wherein the first mask pattern is located in the second area; The first mask pattern is used as a mask to remove the portion of the barrier film located in the first area and retain the portion of the barrier film located in the second area to form the barrier layer.

13. The preparation method according to claim 12, characterized in that: The forming of a first mask pattern on the barrier film comprises: forming a first sub-mask on the barrier film; forming an anti-reflection film on the first sub-mask; forming a second mask pattern on the anti-reflection film, wherein the second mask pattern is located in the second area; Using the second mask pattern as a mask, removing the first sub-mask and the portion of the anti-reflection film located in the first area; The anti-reflection film is removed, and the portion of the first sub-mask located in the second area is retained to form the first mask pattern.

14. The preparation method according to claim 13, characterized in that: The step of forming a first sub-mask on the barrier film comprises: forming a second sub-mask on the barrier film; the second sub-mask covers the barrier film on the channel structure; A third sub-mask is formed on the second sub-mask; the flexibility of the third sub-mask is greater than the flexibility of the second sub-mask; and the second sub-mask and the third sub-mask constitute the first sub-mask.

15. A storage system, characterized in that: The storage system comprises: a controller, and a semiconductor device according to any one of claims 1 to 9; wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

16. An electronic device, characterized in that: The electronic device comprises the storage system as claimed in claim 15, and a circuit board electrically connected to the storage system.

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