Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same, the semiconductor device may include a capacitor including a first source electrode, a second source electrode to which a plurality of second access lines are commonly connected, and a first channel structure on the first source electrode and penetrating the plurality of second access lines, the second access lines are spaced apart from each other and located on different layers. And at least one cell string between the source line and the first access line, the at least one cell string including a second channel structure penetrating a plurality of second access lines, the plurality of second access lines being electrically separated from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-01000205, filed on August 1, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to an integrated circuit, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, as electronic devices have become smaller, their power consumption has decreased, their performance has increased, and they have become more diverse, there has been a demand for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices.

[0005] In order to reduce the size of a semiconductor device and increase the data storage capacity of the semiconductor device, a semiconductor device is developed in which many memory cells can be integrated in the same area by reducing a metal line width on a two-dimensional plane.

[0006] However, as the metal line width on a two-dimensional plane decreases, there arises a problem of a significant increase in manufacturing equipment, investment cost, and development period. Therefore, a method of manufacturing a semiconductor device with a three-dimensional structure has been studied and developed. Summary of the invention

[0007] In an embodiment, a semiconductor device may include: a capacitor including a first source electrode, a second source electrode commonly connected to a plurality of second access lines, and a first channel structure located on the first source electrode and penetrating the plurality of second access lines, wherein the second access lines are spaced apart from each other and located on different layers; and at least one cell string located between the source line and the first access line, the at least one cell string including a second channel structure penetrating the plurality of second access lines, the plurality of second access lines being electrically separated from each other.

[0008] In an embodiment, a method for manufacturing a semiconductor device may include: forming a source line, a first source electrode, and a second source electrode; forming a stack on the source line, the first source electrode, and the second source electrode, the stack including alternately stacked interlayer insulating layers and gate sacrificial layers; forming a first channel structure on the source line, the first channel structure penetrating the alternately stacked interlayer insulating layers and gate sacrificial layers; forming a second channel structure on the first source electrode, the second channel structure penetrating the alternately stacked interlayer insulating layers and gate sacrificial layers; replacing the gate sacrificial layer with a gate conductive layer; and electrically separating the gate conductive layers of different layers penetrated by the first channel structure from each other.

[0009] In an embodiment, a semiconductor device may include: a plurality of word lines stacked on top of each other, each of the plurality of word lines being spaced apart from each other; a capacitor including a first channel structure electrically connected to a first source electrode and penetrating the plurality of word lines, the plurality of word lines being commonly connected to a second source electrode; and a cell string coupled between a source line and a bit line, the cell string including a second channel structure penetrating the plurality of word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 and Figure 2 is a diagram for describing a semiconductor device according to an embodiment.

[0011] Figure 3 is a diagram for describing a channel structure of a semiconductor device according to an embodiment.

[0012] Figures 4 to 10 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment.

[0013] Fig.11 2 is a diagram for describing an additive manufacturing method of a semiconductor device according to an embodiment.

[0014] Fig.12 is a diagram for describing a semiconductor device according to another embodiment. DETAILED DESCRIPTION

[0015] Various embodiments relate to a semiconductor device having a three-dimensional structure and capable of being operated more stably, and a method of manufacturing the semiconductor device.

[0016] In an embodiment, signal and power stability may be increased by increasing the capacitance of a specific node or line within a semiconductor device.

[0017] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0018] It is understood that when an element or layer, etc. is referred to as being "on", "connected to" or "coupled to" another element or layer, etc., the element may be directly on, connected to or coupled to another element or layer, etc., or there may be an intermediate element or layer, etc. On the contrary, when an element or layer, etc. is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, etc., there is no intermediate element or layer. The same reference numerals refer to the same element throughout the text. It is understood that although the terms "first", "second", "third", etc. are used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not intended to imply the order or quantity of the elements. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments. For ease of description, spatially related terms such as "under", "below", "lower", "above", "upper" and the like may be used in this article to describe the relationship between an element or feature and another element or feature as shown in the figure. It is understood that, in addition to the orientation shown in the figures, spatially related terms are intended to include different orientations of the device when in use or operation. For example, if the device in the figure is flipped, the elements described as "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, examples of the term "below" can include both above and below directions. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptive terms used in this article are also interpreted accordingly.

[0019] Figure 1 and Figure 2 is a diagram for describing a semiconductor device according to an embodiment.

[0020] Reference Figure 1 and Figure 2 , a semiconductor device according to an embodiment may include at least one cell string Cell string and at least one capacitor Cap.

[0021] The cell string may be electrically connected between the bit line BL and the source line SL. The cell string may include a first transistor TR1, a plurality of memory cells MC, and a second transistor TR2. The first transistor TR1, the plurality of memory cells MC, and the second transistor TR2 may be connected in series with each other between the source line SL and the bit line BL. A source select line SSL may be coupled to the gate of the first transistor TR1, a plurality of word lines WL0 to WLn-1 may be coupled to the control gates of the plurality of memory cells MC, and a drain select line DSL may be coupled to the gate of the second transistor TR2.

[0022] The cell string may include a channel structure CH_s formed between a first access line AL_a and a source line SL. In this case, the channel structure CH_s may be formed to penetrate a plurality of second access lines AL_b. In this case, the first access line AL_a may include a bit line BL, and the plurality of second access lines AL_b may include a plurality of word lines WL.

[0023] The capacitor Cap may include a first node Node A and a second node Node B, and may include a dielectric material located between the first node Node A and the second node Node B. In this case, the first node Node A may include a first source electrode SL_eA, and the second node Node B may include a second source electrode SL_eB. The capacitor Cap may be electrically separated from the first access line AL_a. The capacitor Cap may include a second node Node B, and a plurality of second access lines AL_b are commonly connected to the second source electrode SL_eB at the second node Node B. The capacitor Cap may include a channel structure CH_s, which is formed on the first source electrode SL_eA so as to penetrate the plurality of second access lines AL_b and is electrically connected to the first source electrode SL_eA. The channel structure CH_s of the capacitor Cap may include a dielectric material.

[0024] The channel structure CH_s may have a columnar shape extending in a direction perpendicular to an extending direction of the source line SL, and may be a pattern having a high aspect ratio.

[0025] Figure 3 is a diagram for describing a channel structure of a semiconductor device according to an embodiment. Figure 3 is along Figure 2 2 is a cross-sectional view of the channel structure taken along line AA' of FIG. As described above, the channel structure CH_s may have a columnar shape extending in a direction perpendicular to the extending direction of the source line SL.

[0026] Reference Figure 3 The channel structure CH_s may include a core pillar 124 , a channel layer 122 , and a memory layer 120 .

[0027] The stem 124 may be formed to extend in a direction perpendicular to the extending direction of the source line SL. The stem 124 may include any one insulating layer selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer. As an example, the stem 124 may include an oxide layer.

[0028] The channel layer 122 may be formed to surround the stem 124. The channel layer 122 may include a semiconductor layer having a polycrystalline state. As an example, the channel layer 122 may include a polycrystalline silicon layer. The channel layer 122 included in the channel structure CH_s of the cell string Cell string may be electrically connected to the source line SL. On the other hand, the channel layer 122 included in the channel structure CH_s of the capacitor Cap may be electrically connected to the first source electrode SL_eA.

[0029] The memory layer 120 may be formed to surround the channel layer 122. The memory layer 120 may include a blocking layer 120A, a charge trap layer 120B, and a tunneling insulating layer 120C. The tunneling insulating layer 120C may be formed to surround the channel layer 122. The tunneling insulating layer 120C may include an oxide layer. The charge trap layer 120B may be formed to surround the tunneling insulating layer 120C. The charge trap layer 120B may include a nitride layer. The blocking layer 120A may be formed to surround the charge trap layer 120B. The blocking layer 120A may include an oxide layer. In the embodiment of the present disclosure, it has been shown that the memory layer 120 has an oxide-nitride-oxide (ONO) structure including an oxide layer, a nitride layer, and an oxide layer, but the present disclosure is not limited thereto.

[0030] Reference Figure 2 and Figure 3 , the memory layer 120 included in the channel structure CH_s of the cell string Cell string may store charges in the charge trap layer 120B by a voltage level difference between a first access line AL_a corresponding to a bit line BL and a second access line AL_b corresponding to a word line WL.

[0031] On the other hand, the memory layer 120 included in the channel structure CH_s of the capacitor Cap may be formed between the first source electrode SL_eA and the second source electrode SL_eB. Here, the memory layer 120 may have an oxide-nitride-oxide (ONO) structure, and each layer of the oxide-nitride-oxide (ONO) structure between the first source electrode SL_eA and the second source electrode SL_eB may be used as a dielectric material to form polarization between the first source electrode SL_eA and the second source electrode SL_eB. Therefore, the semiconductor device according to the embodiment may include a capacitor Cap using a channel structure CH_s having the same structure as the channel structure CH_s of the cell string Cell string.

[0032] Figures 4 to 10 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment.

[0033] Reference Figure 4, the source line SL, the first source electrode SL_eA and the second source electrode SL_eB may be formed by patterning the source layer (not shown). The source layer may include a doped semiconductor layer. For example, the source layer may include an n-type doped silicon layer. Here, the insulating layer 11 may be formed between the source line SL and the second source electrode SL_eB and between the second source electrode SL_eB and the first source electrode SL_eA. Therefore, the source line SL, the second source electrode SL_eB and the first source electrode SL_eA may be electrically separated from each other.

[0034] Reference Figure 5 , a stack ST may be formed. A stack ST in which interlayer insulating layers 21 and gate sacrificial layers 22 are alternately stacked may be formed on the source line SL, the second source electrode SL_eB, and the first source electrode SL_eA. The gate sacrificial layer 22 may be made of a material having an etching selectivity relative to the interlayer insulating layer 21. Each of the interlayer insulating layer 21 and the gate sacrificial layer 22 may include any one selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer. As an example, the interlayer insulating layer 21 may include an oxide layer, and the gate sacrificial layer 22 may include a nitride layer.

[0035] Reference Figure 6 , a channel structure CH_s can be formed. The channel structure CH_s can be formed on the source line SL and the first source electrode SL_eA. For example, a channel hole (not shown) that penetrates the interlayer insulating layer 21 and the gate sacrificial layer 22 can be formed by forming a mask pattern on the stack ST and then etching the stack ST using the mask pattern as an etching barrier. Thereafter, a memory layer 120 can be formed along the surface of the channel hole. The memory layer 120 can be formed as a stacked layer in which a blocking layer 120A, a charge trapping layer 120B, and a tunneling insulating layer 120C are stacked in sequence. For example, the blocking layer 120A and the tunneling insulating layer 120C can be formed as an oxide layer, and the charge trapping layer 120B can be formed as a nitride layer. Next, a semiconductor layer (not shown) can be formed on the memory layer 120. The semiconductor layer can be formed as a polycrystalline silicon layer. The channel layer 122 can be formed by etching the semiconductor layer. A core column 124 (see Figure 3 ). The core column 124 may include any one insulating layer selected from the group consisting of an oxide layer, a nitride layer, and an oxynitride layer. As an example, the core column 124 may include an oxide layer.

[0036] Reference Figure 7, a first trench T1 and a second trench T2 may be formed. The first trench T1 may be formed by etching the stack ST on the insulating layer 11 between the source line SL and the second source electrode SL_eB. The second trench T2 may be formed by etching the stack ST on the second source electrode SL_eB. On the other hand, according to another embodiment of the present disclosure, a hole (not shown) may be formed by etching the stack ST on the second source electrode SL_eB.

[0037] Reference Figure 8 , a gate conductive layer 23 may be formed. For example, the gate sacrificial layer 22 may be removed through the first trench T1 and the second trench T2. Next, the space where the gate sacrificial layer 22 is removed and the space in the first trench T1 and the second trench T2 may be gap-filled with the gate conductive layer 23. The gate conductive layer 23 may include a conductive layer containing a metal. As an example, the gate conductive layer 23 may be formed as a tungsten layer. As another example, the gate conductive layer 23 may be formed as a stacked layer stacked with a titanium nitride layer and a tungsten layer. Therefore, a gate stack GST in which interlayer insulating layers 21 and gate conductive layers 23 are alternately stacked may be formed.

[0038] Reference Fig. 9 , a plurality of second access lines AL_b may be formed. For example, the gate conductive layers 23 may be separated from each other by etching the gate conductive layers 23 gap-filled in the first trenches T1. The gate conductive layers 23 located between the interlayer insulating layers 21 and separated from each other by the etching process may be used as a plurality of second access lines AL_b. On the other hand, the gate conductive layers 23 gap-filled in the second trenches T2 may be electrically connected in common to the gate conductive layers 23 between the interlayer insulating layers 21, and electrically connected to the second source electrode SL_eB.

[0039] Reference Fig.10 , a first access line AL_a may be formed. For example, the first access line AL_a may be formed on a channel structure CH_s, which is formed on the source line SL and is formed to penetrate a plurality of second access lines AL_bf electrically separated from each other and the interlayer insulating layer 21. The channel structure CH_s and the first access line AL_a may be electrically connected to each other. As described above, the channel structure CH_s may include a memory layer 120, a channel layer 122, and a stem 124. Here, the first access line AL_a may include a bit line, and the plurality of second access lines AL_b may include a plurality of word lines. The channel structure CH_s electrically connected to the first access line AL_a may store charges in the charge trapping layer 120b of the memory layer 120 by a voltage difference between the first access line AL_a and the second access line AL_b. Therefore, the channel structure CH_s electrically connected to the first access line AL_a may include a memory cell MC.

[0040] On the other hand, the capacitor Cap formed with polarization between the plurality of second access lines AL_b and the channel layer 122 connected in common includes a channel structure CH_s, which is electrically separated from the first access line AL_a, connected in common by the second access lines AL_b of different layers, and formed on the first source electrode SL_eA. Here, the second access lines AL_b connected in common may be electrically connected to the second source electrode SL_eB, and the channel layer 122 may be electrically connected to the first source electrode SL_eA. Specifically, the capacitor Cap may use the channel layer 122 of the channel structure CH_s as the semiconductor layer S, may use the second access lines AL_b connected in common as the conductive layer M, and may use the memory layer 120 having an ONO structure in the channel structure CH_s as the dielectric material D.

[0041] Therefore, the capacitor Cap of the semiconductor device according to the embodiment may be formed in the M-ONO-S structure.

[0042] Fig.11 2 is a diagram for describing an additive manufacturing method of a semiconductor device according to an embodiment. Fig.11 1 is a diagram for describing a manufacturing method for improving electrical characteristics of the channel layer 122 constituting the capacitor Cap. Fig.11 Can be used to describe Fig. 9 After the manufacturing method described in Fig.10 Before the manufacturing method, an illustration of the manufacturing method was added.

[0043] Reference Fig.11 , the channel layer of the channel structure CH_s formed on the first source electrode SL_eA can be made conductive. For example, a mask MASK can be formed to cover the channel structure CH_s formed on the source line SL. Thereafter, the channel layer of the channel structure CH_s formed on the first source electrode SL_eA can be made conductive by performing an ion implantation process (IMP) on the channel structure CH_s formed on the first source electrode SL_eA and performing a heat treatment process. Therefore, in an embodiment, the channel layer of the channel structure CH_s formed on the first source electrode SL_eA can have better electrical characteristics than the electrical characteristics of the channel layer of the channel structure CH_s formed on the source line SL. Therefore, in an embodiment, the characteristics of a capacitor using a channel layer of a channel structure CH_s made conductive by an ion implantation process and a heat treatment process can be better than the characteristics of a capacitor using a channel layer of a channel structure that has not undergone an ion implantation process and a heat treatment process.

[0044] Fig.12 is a diagram for describing a semiconductor device according to another embodiment.

[0045] Figures 4 to 10 or Figures 4 to 11 The manufacturing method of the semiconductor device described in the embodiment may include a manufacturing method after forming a circuit (e.g., a peripheral circuit) on a substrate Substrate, that is, a manufacturing method of a periphery under cell (PUC) structure. In addition, at least one of the first source electrode SL_eA and the second source electrode SL_eB may be connected to a specific node Node_i or a specific line Line_i inside the peripheral circuit.

[0046] Therefore, in a semiconductor device according to another embodiment, the capacitance of a specific node Node_i or a specific line Line_i requiring stability of a signal or power may be increased by connecting at least one of the first source electrode SL_eA and the second source electrode SL_eB to the specific node Node_i or the specific line Line_i.

[0047] Although the embodiments according to the technical idea of ​​the present disclosure have been described above with reference to the accompanying drawings, this is only used to explain the embodiments according to the concepts of the present disclosure and the present disclosure is not limited to the above embodiments. Without departing from the technical idea of ​​the present disclosure defined in the claims, technicians in the field to which the present disclosure belongs may make various types of substitutions, modifications and changes to the embodiments, and these substitutions, modifications, and changes should be understood to be included in the scope of the present disclosure.

Claims

1. A semiconductor device comprising: Capacitors, including: a first source electrode; a plurality of second access lines commonly connected to the second source electrode, the second access lines being spaced apart from each other and located on different layers, and a first channel structure located on the first source electrode and penetrating the plurality of second access lines; and At least one cell string is located between the source line and the first access line, the at least one cell string including a second channel structure penetrating the plurality of second access lines, the plurality of second access lines being electrically separated from each other.

2. The semiconductor device according to claim 1, wherein Each of the first channel structure and the second channel structure includes: A core column extending in a direction perpendicular to an extending direction of the source line; a channel layer formed to surround the core column, and A memory layer is formed to surround the channel layer.

3. The semiconductor device according to claim 1, wherein The memory layer comprises: a tunnel insulating layer formed to surround the channel layer; a charge trapping layer formed to surround the tunnel insulating layer, and The blocking layer is formed to surround the charge trapping layer.

4. The semiconductor device according to claim 3, wherein: The tunnel insulating layer and the barrier layer each include an oxide layer, and The charge trapping layer includes a nitride layer.

5. The semiconductor device according to claim 4, wherein: The capacitor forms polarization between the first source electrode and the second source electrode using the memory layer having an oxide-nitride-oxide structure as a dielectric material. 6 . The semiconductor device according to claim 1 , further comprising a peripheral circuit including a specific node or a specific line connected to at least one of the first source electrode and the second source electrode.

7. The semiconductor device according to claim 6, wherein: The peripheral circuit is formed under the source line, the first source electrode, and the second source electrode.

8. A method for manufacturing a semiconductor device, the method comprising: forming a source line, a first source electrode, and a second source electrode; forming a stack on the source line, the first source electrode and the second source electrode, the stack comprising interlayer insulating layers and gate sacrificial layers stacked alternately; forming a first channel structure on the source line, wherein the first channel structure penetrates the alternately stacked interlayer insulating layers and the gate sacrificial layers; forming a second channel structure on the first source electrode, wherein the second channel structure penetrates the alternately stacked interlayer insulating layers and the gate sacrificial layers; replacing the gate sacrificial layer with a gate conductive layer; as well as The gate conductive layers of different layers penetrated by the first channel structure are electrically separated from each other.

9. The manufacturing method according to claim 8, wherein: Replacing the gate sacrificial layer with the gate conductive layer comprises: forming a first trench and a second trench between the first channel structure and the second channel structure, wherein the first trench and the second trench penetrate the interlayer insulating layer and the gate sacrificial layer; removing the gate sacrificial layer through the first trench and the second trench; and The gate conductive layer is used to gap-fill the space where the gate sacrificial layer is removed and the space in the first trench and the second trench.

10. The manufacturing method according to claim 9, in, The first trench is formed between the first channel structure and the second source electrode, and The second trench is formed on the second source electrode.

11. The manufacturing method according to claim 10, wherein: The step of electrically separating the gate conductive layers of different layers penetrated by the first channel structure from each other includes etching and removing the gate conductive layer gap-filled in the first trench.

12. The manufacturing method according to claim 11, wherein: Each of the first channel structure and the second channel structure includes a stem, a channel layer, and a memory layer.

13. The manufacturing method according to claim 12, wherein: The stem is formed to extend in a direction perpendicular to the extending direction of the source line. The channel layer is formed to surround the core column, and The memory layer is formed to surround the channel layer.

14. The manufacturing method according to claim 13, wherein: The memory layer has an oxide-nitride-oxide structure.

15. The manufacturing method according to claim 14, wherein: The memory layer of the second channel structure forms a polarization between the first source electrode and the second source electrode.

16. A semiconductor device comprising: a plurality of word lines stacked on top of each other, each word line in the plurality of word lines being spaced apart from each other; a capacitor including a first channel structure electrically connected to the first source electrode and penetrating the plurality of word lines, the plurality of word lines being commonly connected to the second source electrode; as well as A cell string is coupled between the source line and the bit line, the cell string including a second channel structure penetrating the plurality of word lines.

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