A high threshold voltage stability anti-radiation depletion mode GaN HEMT and a manufacturing method thereof

Abstract

The application provides a high-threshold-voltage stability anti-radiation depletion-mode GaN HEMT and a manufacturing method thereof, and belongs to the technical field of semiconductors. The GaN HEMT comprises a substrate layer and a gallium nitride layer arranged from bottom to top. An active region on the upper surface of the gallium nitride layer is sequentially provided with an active region gallium nitride layer, a barrier layer, a first dielectric layer and a second dielectric layer from bottom to top. A strip-shaped gate metal layer is arranged on the upper surface of the second dielectric layer. A plurality of etching holes with different depths are arranged in the gate metal layer. Different Schottky metal layers are arranged in the etching holes with different depths. The Schottky metal layer in the deeper etching hole is interconnected with the gate metal layer, and the Schottky metal layers in the shallower etching holes are all connected above the gate metal layer. Not only can the interface state charge induced by radiation be extracted from the transistor through the Schottky metal layer in the shallower etching hole, but also the carriers accumulated in the gate can flow out through the Schottky metal layer in the deeper etching hole, thereby improving the anti-radiation capability and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a radiation-resistant depletion-type GaN HEMT with high threshold voltage stability and its manufacturing method. Background Technology

[0002] GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs), by inserting a high-quality insulating dielectric layer between the gate metal and the AlGaN / GaN epitaxial structure, possess advantages such as wide gate swing, low gate leakage current, high output power density, and compatibility with Si-based MOSFET drivers. They are widely used in high-frequency and high-power applications such as mobile phone chargers, portable power supplies, adapters, and data centers. In particular, the excellent material and device properties of GaN HEMT devices give them a certain degree of resistance to radiation displacement damage, making them promising for applications in aerospace and various radiation environments, such as near-Earth orbit satellites for outer space communication and nuclear power plants. However, radiation effects caused by solar activity, high-energy cosmic rays, and high-energy protons, heavy ions, and gamma rays in the Van Allen radiation belts can induce a large number of interface state traps and electron-hole pairs within the device. Interface state traps can trap channel electrons, forming fixed negative charges that severely affect the device's threshold voltage stability; while these induced holes will accumulate in sensitive regions near the device gate, leading to device degradation or even failure, and in severe cases, threatening the safe operation of the entire system. Therefore, in order to ensure the safe and reliable operation of the power system, the device needs to have high threshold voltage stability and radiation resistance. It must not only be able to safely discharge radiation-induced charge carriers, but also be able to extract electrons trapped by the interface state in a timely manner.

[0003] In related technologies, transistors exposed to irradiation generate a large number of charge carriers and interface states. The interface states between the dielectric layer and the barrier layer trap channel electrons, causing threshold voltage drift. Furthermore, the dielectric layer in a metal-in-the-sink (MIS) structure impedes carrier movement, preventing carriers from dissipating through the gate dielectric layer to the outside. This leads to carrier accumulation near the MIS gate, affecting normal transistor operation and, in severe cases, causing irradiation damage or even device burnout. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a radiation-resistant depletion-mode GaN HEMT with high threshold voltage stability and its manufacturing method. This allows trapped negative charges and carriers to be efficiently extracted to the outside of the transistor, preventing the accumulation of more interface state trapped electrons and induced carriers in the gate region after irradiation, thus improving the device's radiation resistance and reliability, making it applicable in irradiated environments. Furthermore, it fully considers the high threshold voltage capability of depletion-mode devices, avoiding the increase in leakage current and power consumption caused by low threshold voltage. Specific technical requirements are as follows:

[0005] In a first aspect, the present invention provides a radiation-depletion resistant GaN HEMT with high threshold voltage stability, comprising a substrate layer and a gallium nitride layer disposed from bottom to top. The active region on the upper surface of the gallium nitride layer is provided with an active region gallium nitride layer, a barrier layer, a first dielectric layer and a second dielectric layer in sequence from bottom to top. The upper surface of the second dielectric layer is provided with a plurality of strip-shaped gate metal layers. The gate metal layers and the first dielectric layer and the second dielectric layer located directly below them form the gate of the MIS-type GaNHEMT.

[0006] The gate metal layer has a plurality of first etched holes arranged along its length, and a Schottky metal layer is disposed in the first etched holes; the Schottky metal layer includes a first Schottky metal layer and a second Schottky metal layer; the bottom of the first Schottky metal layer is in contact with the barrier layer, the sidewalls are in contact with the first dielectric layer and the second dielectric layer, and the top is interconnected with the gate metal layer; the bottom of the second Schottky metal layer is in contact with the top of the first dielectric layer, and the top is in contact with the Schottky metal interconnect layer.

[0007] In the gate structure of a MIS-type GaN HEMT, the gate metal layer has multiple etched holes of different depths spaced apart. Different Schottky metal layers are arranged in the etched holes of different depths. The Schottky metal layers in the deeper etched holes are interconnected with the gate metal layer, while the Schottky metal layers in the shallower etched holes are all connected above the gate metal layer. This not only allows the irradiated interface state charges to be extracted from the transistor through the Schottky metal layer in the shallower etched holes, but also allows the charge carriers accumulated on the gate to flow out through the Schottky metal layer in the deeper etched holes. At the same time, the Schottky metal layer in the deeper etched holes and the barrier layer constitute a Schottky metal gate, which, together with the original MIS gate, forms a composite gate for the device, and works together to regulate the device threshold voltage.

[0008] Since the gate metal layer is uninterrupted with the first dielectric layer and the second dielectric layer along the length of the gate metal layer, the device has normal gate function.

[0009] Optionally, the width of the gate metal layer is 2~5μm and the length is 30~1500μm; the spacing between two adjacent first etched holes on the gate metal layer is 2~15μm, and the length of the first etched hole is 2~150μm; the minimum thickness from the sidewall of the first etched hole to the outer sidewall of the gate metal layer is 0.4~1.2μm, and the minimum distance between the sidewall of the first etched hole located at both ends of the gate metal layer and the corresponding end face of the gate metal layer is 1~10μm.

[0010] Optionally, the first Schottky metal layer and the second Schottky metal layer alternately fill the first etched hole along the length direction of the gate metal layer, and the second Schottky metal layer is located in the middle of the corresponding etched hole, with a length of 1.2~140μm and a width of 0.4~1.4μm; the second Schottky metal layer does not contact the gate metal layer, and the distance between its sidewall and the sidewall of the corresponding etched hole is 0.4~0.6μm.

[0011] Optionally, the top of the second Schottky metal layer is led outward from the active region through a Schottky metal interconnect layer to form a Schottky metal pad area. The Schottky metal interconnect layer is strip-shaped and has a thickness of 0.7~2.5μm.

[0012] Optionally, ohmic metal layers with unequal spacing are provided on both sides of the gate and the ohmic metal layers are in contact with the barrier layer. The ohmic metal layer closer to the gate and the first metal interconnect layer on top of it form the source, and the ohmic metal layer farther from the gate and the second metal interconnect layer on top of it form the drain. The source and drain are respectively led out of the active region through the corresponding metal interconnect layers to form the source pad region and the drain pad region.

[0013] The second Schottky metal layer extends upward through a via on the first metal interconnect layer and connects to the Schottky metal interconnect layer, and there is no contact between the second Schottky metal layer and the first metal interconnect layer; a gap is formed between the second Schottky metal layer and the first metal interconnect layer, and between the first metal interconnect layer and the Schottky metal interconnect layer, and a third dielectric layer is filled between the gaps;

[0014] A third Schottky metal layer and a top metal layer are provided above the interconnect metal layer of the source pad area and the drain pad area, and the top metal layer and the third Schottky metal layer are arranged vertically.

[0015] The gate metal layer extends outward from the active region and converges to form a gate pad region. In the gate pad region, a third Schottky metal layer and a top metal layer are sequentially disposed above the gate metal layer.

[0016] Except for the top surfaces of the drain pad region, source pad region, gate pad region, and Schottky metal pad region, the upper surface of the gallium nitride layer is filled with a third dielectric layer.

[0017] Here, GaN HEMT devices are gallium nitride high electron mobility transistors, which effectively solve the problems of traditional low threshold voltage devices where the trapped electrons of the interface states induced by radiation affect the stability of the threshold voltage and the accumulation of induced carriers at the gate.

[0018] In MIS-type GaN HEMTs, except for the top surfaces of the drain pad region, gate pad region, and Schottky metal pad region, the active region layer and the surrounding area are filled with material to form a third dielectric layer for electrical isolation.

[0019] Optionally, a second etched hole is provided between the ohmic metal layer of the source electrode and the gate metal layer, and a fourth Schottky metal layer is provided in the second etched hole; the bottom of the fourth Schottky metal layer is in contact with the barrier layer, a gap is formed between the sidewall and the corresponding sidewall of the etched hole, and the top extends upward through a via on the first metal interconnect layer and connects to the Schottky metal interconnect layer, and the fourth Schottky metal layer is not in contact with the first metal interconnect layer; a gap is formed between the fourth Schottky metal layer and the first metal interconnect layer, and a third dielectric layer is filled between the gaps.

[0020] Using the above technical solution, the Schottky metal layer between the gate and the source can serve as an electron discharge channel between the gate and the source in the off state, preventing electrons from being injected from the source into the drain and increasing leakage current in the off state.

[0021] Optionally, the spacing between the second etched hole and the ohmic metal layer sidewall of the source electrode and the gate metal layer sidewall is 0.4~0.8μm; the spacing between two adjacent second etched holes is 6μm~200μm; and the spacing between the sidewalls of the two second etched holes located at both ends of the gate metal layer along its length direction and the corresponding edge of the active region is 3μm~100μm.

[0022] The second etched hole has a length of 4μm to 300μm along the length direction of the gate metal layer, a width of 1.6 to 2.5μm along the length direction perpendicular to the gate metal layer, and a distance of 0.3 to 0.5μm between the fourth Schottky metal layer and the sidewall of the second etched hole.

[0023] Optionally, the material of the first dielectric layer is either aluminum oxide or hafnium dioxide, and the thickness is 2-6 nm; the material of the second dielectric layer is either silicon nitride or silicon dioxide, and the thickness is 15-20 nm.

[0024] The term "first dielectric layer" is used here because the first ultrathin high-dielectric-constant dielectric layer below the gate metal layer has the function of extracting interface state charges between the first dielectric layer and the barrier layer, which greatly improves the threshold voltage stability of the device. The term "second dielectric layer" is used because the thicker second dielectric layer below the gate metal layer has the ability to suppress gate leakage and improve the gate voltage swing and threshold voltage. The third dielectric layer is mainly used for electrical isolation, and the second dielectric layer and the third dielectric layer can be made of the same material.

[0025] Locally etched vias of varying depths are fabricated between the gate and source of a GaN HEMT with a dual-dielectric-layer gate-source (MIS) structure, and below the gate, and filled with Schottky metal layers. This not only allows electrons between the gate and source and irradiation-induced interface state charges to flow out of the transistor from the Schottky metal layer in the off-state, but also discharges charge carriers accumulated at the gate, preventing increased leakage current and threshold voltage drift caused by charge carrier accumulation. The lower end of the Schottky metal layer between the gate and source is in contact with the top surface of the barrier layer. Part of the Schottky metal layer in the gate etched vias is in contact with the barrier layer and the gate; the lower end of the remaining Schottky metal layer is in contact with the first ultrathin gate dielectric layer, and the upper end is connected to the Schottky metal layer between the gate and source via strip-shaped Schottky metal interconnect layers, forming an independent pad region outside the active region, used solely for charge carrier discharge.

[0026] Here, the performance of devices with high threshold voltages is also fully considered. A composite structure design of dual dielectric layer MIS gate and Schottky metal gate is proposed, and a device with normal electrical operation capability is realized. The manufacturing method is simple, compatible with existing processes, and improves the overall radiation resistance of the device.

[0027] In a second aspect, the present invention also provides a method for manufacturing a radiation-depletion-resistant GaN HEMT with high threshold voltage stability, for fabricating the aforementioned radiation-depletion-resistant GaN HEMT with high threshold voltage stability, comprising:

[0028] Step 1: The epitaxial wafer is grown sequentially from bottom to top, consisting of the substrate layer, the gallium nitride layer, the barrier layer, the first dielectric layer, and the second dielectric layer. The first dielectric layer, the second dielectric layer, the barrier layer, and part of the gallium nitride layer around the active region are etched away. The thickness of the barrier layer etched away is 5~10nm, and the second dielectric layer contacts the barrier layer to form an ohmic contact with low resistance characteristics.

[0029] Step 2: Grow a third dielectric layer on the entire epitaxial wafer, etch the third dielectric layer, the first dielectric layer, the second dielectric layer and part of the barrier layer in the source and drain regions and deposit an ohmic metal layer.

[0030] Then, a third dielectric layer is grown on the entire epitaxial wafer, the gate region and the gate pad region are etched away to form the third dielectric layer, and a gate metal layer is deposited.

[0031] Step 3: Etch the gate metal layer and the second dielectric layer in the patterned area to form etch holes in the gate metal layer and deposit the second Schottky metal layer;

[0032] The gate metal layer and the first dielectric layer of the etched pattern area are used to form an etch hole in the gate metal layer;

[0033] The third dielectric layer is grown on the whole, the etch holes of the gate metal layer and the already grown third dielectric layer in the Schottky metal pad area are etched, and then the first Schottky metal layer is deposited.

[0034] The second Schottky metal layer is in contact with the first dielectric layer but not with the gate metal layer; the second Schottky metal layer is not in contact with the first metal interconnect layer; when etching the third dielectric layer in the etch hole that fills the second Schottky metal layer, a portion of the edge third dielectric layer is retained to ensure that the space between the second Schottky metal layer and the gate metal layer is filled by the third dielectric layer.

[0035] Step 4: Grow the third dielectric layer on the entire wafer, etch the ohmic metal layer of the drain, the ohmic metal layer of the source, and the third dielectric layer above the gate metal layer, as well as the third dielectric layer above the source pad region, drain pad region, and gate pad region, and deposit the first metal interconnect layer and the second metal interconnect layer.

[0036] The first metal interconnect layer and the third dielectric layer above the gate metal layer pattern area are etched, the third dielectric layer above the source pad area and the drain pad area are etched, and the third dielectric layer in the Schottky metal pad area is etched and strip-shaped Schottky metal interconnect layer and third Schottky metal layer are deposited.

[0037] Step 5: Grow the third dielectric layer on the entire wafer, etch the third dielectric layer above the four pad areas (source pad area, drain pad area, gate pad area, and Schottky metal pad area), deposit the top metal layer, and complete the fabrication of the GaN HEMT device.

[0038] Optionally, after the first Schottky metal layer is deposited in step three, the third dielectric layer, the first dielectric layer, and the second dielectric layer of the patterned region between the gate metal layer and the source ohmic metal layer are etched to form an etch hole in the fourth Schottky metal layer.

[0039] The third dielectric layer is grown on the whole sheet, the etch holes of the fourth Schottky metal layer and the Schottky metal pad area are etched to form the third dielectric layer, and then the fourth Schottky metal layer is deposited.

[0040] The fourth Schottky metal layer is in contact with the barrier layer but not with the surrounding first and second dielectric layers; the fourth Schottky metal layer is not in contact with the first metal interconnect layer; when etching the third dielectric layer in the etch hole that fills the fourth Schottky metal layer, a portion of the edge third dielectric layer is retained to ensure that the third dielectric layer fills the space between the fourth Schottky metal layer and the first and second dielectric layers.

[0041] In step four, when depositing the strip-shaped Schottky metal interconnect layer and the second metal interconnect layer, the first metal interconnect layer and the third dielectric layer above the patterned area of ​​the fourth Schottky metal layer and the gate metal layer are etched, and the third dielectric layer in the Schottky metal pad area is etched while simultaneously depositing the strip-shaped Schottky metal interconnect layer and the third Schottky metal layer.

[0042] The strip-shaped Schottky metal interconnect layer is not in contact with the source interconnect metal layer, but is in contact with the Schottky metal layer and the Schottky metal layer in the gate metal layer; a third dielectric layer is filled between the strip-shaped Schottky metal interconnect layer, the Schottky metal layer, and the interconnect metal.

[0043] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0044] (1) Locally etched holes of different depths are prepared between the gate and source of a GaN HEMT with a dual-dielectric-layer gate MIS structure and below the gate, and Schottky metal layers are filled in. This not only allows electrons between the gate and source and irradiation-induced interface state charges to flow out of the transistor from the Schottky metal layer in the off state, but also discharges the charge carriers accumulated in the gate, avoiding the increase in leakage current and threshold voltage drift caused by the accumulation of charge carriers. The lower end of the Schottky metal layer between the gate and source is in contact with the top surface of the barrier layer, and part of the Schottky metal layer in the gate etched hole is in contact with the barrier layer and the gate; the lower end of the other part of the Schottky metal layer is in contact with the first ultrathin gate dielectric layer, and the upper end is connected to the Schottky metal layer in all the gate metal layer etched holes and the Schottky metal layer between the gate and source through a strip-shaped Schottky metal interconnect layer to form an independent pad area outside the active region, which is used to discharge charge carriers separately.

[0045] (2) A composite dielectric layer with an ultra-thin high dielectric constant first dielectric layer and a second dielectric layer is formed on the gate. At the same time, holes of different depths are etched in the gate metal layer and filled with Schottky metal layers. This not only allows the irradiated interface state charge to be extracted from the transistor through the Schottky metal layer in the shallower etched holes, but also allows the charge carriers accumulated on the gate to flow out through the Schottky metal layer in the deeper etched holes. At the same time, the Schottky metal layer in the deeper etched holes and the barrier layer form a Schottky metal gate, which, together with the original MIS gate, serves as the composite gate of the device and coordinates the control of the device threshold voltage.

[0046] (3) Since the gate metal layer and the first dielectric layer and the second dielectric layer are uninterrupted along the length of the gate metal layer, the device has normal gate function. In addition, the Schottky metal layer between the gate and the source can serve as an electron discharge channel between the gate and the source in the off state, preventing electrons from being injected from the source into the drain and increasing leakage current in the off state. The device is simple to manufacture and compatible with existing processes. Without affecting the normal operation of the transistor, it has the ability to efficiently extract irradiated induced interface state charges and carriers.

[0047] (4) Taking into full account the device performance of high threshold voltage, a composite structure design of dual dielectric layer MIS gate and Schottky metal gate is proposed, and a device with normal electrical operation capability is realized. The manufacturing method is simple, compatible with existing processes, and improves the overall radiation resistance of the device. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the structure of a conventional MIS HEMT device in related technologies;

[0050] Figure 2 This is a three-dimensional structural diagram of the active region of the GaN HEMT device in an embodiment of the present invention;

[0051] Figure 3 This is the three-dimensional structure of the GaN HEMT device in the embodiment of the present invention. Figure 1 ;

[0052] Figure 4 This is the three-dimensional structure of the GaN HEMT device in the embodiment of the present invention. Figure 2 ;

[0053] Figure 5 This is a top view of the GaN HEMT device in an embodiment of the present invention;

[0054] Figure 6 This is a process flow diagram of the GaN HEMT device fabrication process in an embodiment of the present invention;

[0055] Figure 7 This is a schematic diagram of the structure in which the active region has been etched in an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of the structure of etching and depositing an ohmic metal layer in an embodiment of the present invention;

[0057] Figure 9 This is a schematic diagram of the structure of depositing a Schottky metal layer after etching shallow etch holes following the deposition of a gate metal layer in an embodiment of the present invention;

[0058] Figure 10 This is a schematic diagram of the structure in an embodiment of the present invention, showing the etching of a deeper gate metal layer through etching holes and the deposition of a Schottky metal layer;

[0059] Figure 11 This is a schematic diagram of the structure of etching and depositing the Schottky metal layer between the gate and source in an embodiment of the present invention;

[0060] Figure 12 This is a schematic diagram of the structure of etching and depositing the first metal interconnect layer and the second metal interconnect layer in an embodiment of the present invention;

[0061] Figure 13 This is a schematic diagram of the structure of the etched and deposited Schottky metal interconnect layer in an embodiment of the present invention;

[0062] Figure 14 This is a schematic diagram of the structure for etching and depositing the top metal layer in an embodiment of the present invention.

[0063] In the figure: 1-substrate layer; 2-gallium nitride layer; 3-barrier layer; 4-first dielectric layer; 5-second dielectric layer; 6-third dielectric layer; 7-ohmic metal layer; 8-gate metal layer; 9-first Schottky metal layer; 10-second Schottky metal layer; 11-fourth Schottky metal layer; 12-first metal interconnect layer; 13-second metal interconnect layer; 14-third Schottky metal layer; 15-top metal layer; 16-Schottky metal interconnect layer. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0065] Figure 1 This is a schematic diagram of the structure of a conventional MIS HEMT device in the prior art provided by an embodiment of the present invention. In related technologies, existing MIS HEMT devices, such as... Figure 1 As shown, the transistor includes a substrate layer 1 and a gallium nitride layer 2 arranged from bottom to top. The active region on the upper surface of the gallium nitride layer 2, from bottom to top, consists of the active region gallium nitride layer 2, a barrier layer 3, and a first dielectric layer 4. Multiple strip-shaped gate metal layers 8 are disposed on the upper surface of the first dielectric layer. Ohmic metal layers 7 with unequal spacing are disposed on both sides of the gate, and the ohmic metal layers 7 are in contact with the barrier layer 3. The ohmic metal layers 7 closer to the gate form a source with the first metal interconnect layer 12 located on top of them, while the ohmic metal layers 7 farther from the gate form a source with the metal interconnect layer located on top of them. A third dielectric layer 6 is filled above the first dielectric layer 4. Under irradiation conditions, a large number of charge carriers and interface states are generated within the transistor. The interface states between the dielectric layer and the barrier layer trap channel electrons, causing threshold voltage drift. The dielectric layer in the MIS structure can block the movement of charge carriers, preventing them from dissipating to the outside through the gate dielectric layer within the device. This causes charge carriers to accumulate in the region near the MIS gate, affecting the normal operation of the transistor. In severe cases, it can lead to radiation damage to the transistor or even device burnout.

[0066] Therefore, to enable GaN-based MIS HEMT devices to be used in irradiated environments, it is crucial to address the issue of increased interface state trapped electrons and induced carrier accumulation in the gate region after irradiation. This would allow the trapped negative charges and carriers to be efficiently extracted to the outside of the transistor, improving the device's radiation resistance and reliability. Simultaneously, the high threshold voltage capability of depletion-mode devices must be fully considered to avoid increased leakage current and power consumption due to low threshold voltages.

[0067] Figure 2 This is a three-dimensional structural diagram of the active region of the GaN HEMT device in an embodiment of the present invention; Figures 3-5 These are schematic diagrams of the GaN HEMT device from three different perspectives in embodiments of the present invention; Figures 6-13 These are schematic diagrams showing the structure of a GaN HEMT device at different stages during fabrication. Based on the aforementioned shortcomings, this invention provides a radiation-depletion-resistant GaN HEMT with high threshold voltage stability, such as... Figures 2-5 As shown, it includes a substrate layer 1 and a gallium nitride layer 2 arranged from bottom to top. The active region on the upper surface of the gallium nitride layer 2 is provided with an active region gallium nitride layer 2, a barrier layer 3, a first dielectric layer 4 and a second dielectric layer 5 arranged from bottom to top. The upper surface of the second dielectric layer 5 is provided with a plurality of strip-shaped gate metal layers 8. The gate metal layers 8 and the first dielectric layer 4 and the second dielectric layer 5 located directly below them form the gate of the MIS type GaN HEMT.

[0068] The gate metal layer 8 has a plurality of first etched holes arranged along its length, and a Schottky metal layer is disposed in the first etched holes; the Schottky metal layer includes a first Schottky metal layer 9 and a second Schottky metal layer 10; the bottom of the first Schottky metal layer 9 is in contact with the barrier layer 3, the sidewalls are in contact with the first dielectric layer 4 and the second dielectric layer 5, and the top is interconnected with the gate metal layer 8; the bottom of the second Schottky metal layer 10 is in contact with the top of the first dielectric layer 4, and the top is in contact with the Schottky metal interconnect layer 16.

[0069] In the gate structure of a MIS-type GaN HEMT, the gate metal layer has multiple etched holes of different depths spaced apart. Different Schottky metal layers are arranged in the etched holes of different depths. The Schottky metal layers with deeper etched holes (i.e., the first Schottky metal layer 9) are interconnected with the gate metal layer, while the Schottky metal layers with shallower etched holes (i.e., the second Schottky metal layer 10) are all connected above the gate metal layer. This not only allows the irradiated interface state charges to be extracted from the transistor through the Schottky metal layer in the shallower etched holes, but also allows the charge carriers accumulated in the gate to flow out through the Schottky metal layer in the deeper etched holes. At the same time, the Schottky metal layer in the deeper etched holes and the barrier layer constitute a Schottky metal gate, which, together with the original MIS gate, forms a composite gate for the device, and works together to regulate the device threshold voltage.

[0070] Since the gate metal layer is uninterrupted with the first dielectric layer and the second dielectric layer along the length of the gate metal layer, the device has normal gate function.

[0071] For example, the width of the gate metal layer 8 is 2~5μm and the length is 30~1500μm; the distance between two adjacent first etched holes on the gate metal layer 8 is 2~15μm, and the length of the first etched hole is 2~150μm; the minimum thickness from the sidewall of the first etched hole to the outer sidewall of the gate metal layer 8 is 0.4~1.2μm, and the minimum distance from the sidewall of the first etched hole at both ends of the gate metal layer 8 to the corresponding end face of the gate metal layer 8 is 1~10μm.

[0072] More specifically, the shape of the cross-section of the first etched hole is circular, elliptical, polygonal, or other irregularly shaped; in the etched hole, the cross-section of the first Schottky metal layer 9 and the second Schottky metal layer 10 is circular, elliptical, polygonal, or other irregularly shaped.

[0073] Optionally, the first Schottky metal layer 9 and the second Schottky metal layer 10 are alternately filled in the first etched hole along the length direction of the gate metal layer 8, and the second Schottky metal layer 10 is located in the middle of the corresponding etched hole, with a length of 1.2~140μm and a width of 0.4~1.4μm; the second Schottky metal layer 10 is not in contact with the gate metal layer 8, and the distance between its sidewall and the sidewall of the corresponding etched hole is 0.4~0.6μm.

[0074] Optionally, the top of the second Schottky metal layer 10 is led outward from the active region through the Schottky metal interconnect layer 16 to form a Schottky metal pad region. The Schottky metal interconnect layer 16 is strip-shaped and has a thickness of 0.7~2.5μm.

[0075] Optionally, ohmic metal layers 7 with unequal spacing are provided on both sides of the gate, and the ohmic metal layers 7 are in contact with the barrier layer 3. The ohmic metal layer 7 closer to the gate and the first metal interconnect layer 12 on top of it form the source, and the ohmic metal layer 7 farther from the gate and the second metal interconnect layer 13 on top of it form the drain. The source and drain are respectively led out of the active region through the corresponding metal interconnect layers to form the source pad region and the drain pad region.

[0076] The second Schottky metal layer 10 extends upward through a via in the first metal interconnect layer 12 and connects to the Schottky metal interconnect layer 16, without contact between the second Schottky metal layer 10 and the first metal interconnect layer 12; a gap is formed between the second Schottky metal layer 10 and the first metal interconnect layer 12, and between the first metal interconnect layer 12 and the Schottky metal interconnect layer 16, and the gaps are filled with a third dielectric layer 6. For example, the gap between the first metal interconnect layer 12 and the Schottky metal interconnect layer 16 is 0.8~1μm; the fourth Schottky metal layer 11 has a thickness of 2~3μm and a distance of 0.8~1μm from the sidewall of the via in the first metal interconnect layer 12.

[0077] A third Schottky metal layer 14 and a top metal layer 15 are provided above the interconnect metal layer of the source pad area and the drain pad area, and the top metal layer 15 and the third Schottky metal layer 14 are arranged vertically above each other.

[0078] A gate metal layer 8 leads out of the active region and converges to form a gate pad region. In the gate pad region, a third Schottky metal layer 14 and a top metal layer 15 are sequentially disposed above the gate metal layer 8.

[0079] Here, each gate and the adjacent source and drain on both sides form an interdigitated finger. The gates of all interdigitated fingers are led out through the gate metal layer 8 to the active region of the MIS-type GaN HEMT to form a gate pad region. The sources and drains of all interdigitated fingers are led out through the interconnect metal layer to the active region of the HEMT device to form source pad regions and drain pad regions respectively.

[0080] Except for the top surfaces of the drain pad region, source pad region, gate pad region and Schottky metal pad region, the upper surface of the gallium nitride layer 2 is filled with a third dielectric layer 6.

[0081] For example, in the active region, the distance between the gate metal layer 8 and the source ohmic metal layer 7 is 2.4~4.1μm, and the distance between the gate metal layer 8 and the drain ohmic metal layer is 5~20μm; the width of the source ohmic metal layer and the drain ohmic metal layer is 1.5~3.5μm; the first metal interconnect layer 12 extends 1.5~10μm beyond the drain side of the gate metal layer 8; the second metal interconnect layer 13 of the drain extends 1.5~5μm beyond both sides of the drain ohmic metal layer; the spacing between the first metal interconnect layer 12 of the source and the second metal interconnect layer 13 of the drain is 2~5μm.

[0082] Both the source ohmic metal layer 7 and the drain ohmic metal layer 7 are in contact with the top surface of the barrier layer 3, and have a thickness of 0.3~1.2μm; the first metal interconnect layer 12 and the second metal interconnect layer 13 have a thickness of 1.2~2μm; the gate metal layer 8 has a thickness of 0.4~0.8μm; the first Schottky metal layer 9 has a thickness of 0.4~0.8μm; the second Schottky metal layer 10 has a thickness of 1~1.5μm; and the distance between the upper strip-shaped Schottky metal interconnect layer 16 and the gate metal layer 8 is 2~5μm.

[0083] Optionally, a second etched hole is provided between the ohmic metal layer 7 of the source electrode and the gate metal layer 8, and a fourth Schottky metal layer 11 is provided in the second etched hole; the bottom of the fourth Schottky metal layer 11 is in contact with the barrier layer 3, a gap is formed between the sidewall and the corresponding etched hole sidewall, and the top passes through the through hole on the first metal interconnect layer 12 and is connected to the Schottky metal interconnect layer 16, and the fourth Schottky metal layer 11 is not in contact with the first metal interconnect layer 12; a gap is formed between the fourth Schottky metal layer 11 and the first metal interconnect layer 12, and a third dielectric layer 6 is filled between the gap.

[0084] Here, the Schottky metal layer between the gate and the source can serve as an electron discharge channel between the gate and the source in the off state, preventing electrons from being injected from the source into the drain and increasing leakage current in the off state.

[0085] For example, the spacing between the second etched hole and the sidewall of the ohmic metal layer 7 of the source electrode and the sidewall of the gate metal layer 8 is 0.4~0.8μm; the spacing between two adjacent second etched holes is 6μm~200μm; and the spacing between the sidewalls of the two second etched holes located at both ends of the length direction of the gate metal layer 8 and the corresponding edge of the active region is 3μm~100μm.

[0086] The second etched hole has a length of 4μm to 300μm along the length direction of the gate metal layer 8, a width of 1.6 to 2.5μm along the length direction perpendicular to the gate metal layer 8, and a distance of 0.3 to 0.5μm between the fourth Schottky metal layer 11 and the sidewall of the second etched hole.

[0087] Optionally, the shape of the cross-section of the second etched hole is circular, elliptical, polygonal, or other irregularly shaped; in the etched hole, the cross-sectional shape of the fourth Schottky metal layer 11 is circular, elliptical, polygonal, or other irregularly shaped.

[0088] For example, the bottom surface of the fourth Schottky metal layer 11 is located in the middle of the second etch hole and the length of the fourth Schottky metal layer 11 is 3~250μm. It is interconnected with the Schottky metal interconnect layer 16 located above the gate metal layer 8. The thickness of the Schottky metal interconnect layer 16 is 0.7~2.5μm and the width is 4~8.3μm.

[0089] Optionally, the material of the first dielectric layer is either aluminum oxide or hafnium dioxide, and the thickness is 2-6 nm; the material of the second dielectric layer is either silicon nitride or silicon dioxide, and the thickness is 15-20 nm.

[0090] The term "first dielectric layer" is used here because the first ultrathin high-dielectric-constant dielectric layer below the gate metal layer has the function of extracting interface state charges between the first dielectric layer and the barrier layer, greatly improving the threshold voltage stability of the device. The term "second dielectric layer" is used because the thicker second dielectric layer below the gate metal layer has the ability to suppress gate leakage and improve the gate voltage swing and threshold voltage. The third dielectric layer is mainly used for electrical isolation, and its material can be any one or a combination of two or more of silicon dioxide, silicon nitride, or polyimide. The second dielectric layer and the third dielectric layer can be made of the same material.

[0091] It is easy to understand that the sidewalls of the second Schottky metal layer 10 in the etched hole of the gate metal layer 8 are completely and tightly wrapped by the third dielectric layer 6; the second Schottky metal layer 10 and the third dielectric layer 6 are completely and tightly wrapped by the gate metal layer 8 and the second dielectric layer 5; the first Schottky metal layer 9 is completely and tightly wrapped by the gate metal layer 8, the first dielectric layer 4 and the second dielectric layer 5; and the fourth Schottky metal layer 11 and the third dielectric layer 6 are completely and tightly wrapped by the first dielectric layer 4 and the second dielectric layer 5.

[0092] For example, in the active region, the distance between the edges of the first dielectric layer and the second dielectric layer and the ohmic metal layer 7 / gate metal layer 8 is 3~6μm; the cross index in the active region is 1~900; the minimum width of the metal leads of the gate metal layer 8, Schottky metal interconnect layer 16, first metal interconnect layer 12 and second metal interconnect layer 13 outside the active region is 2~8μm; the distance between the gate pad region, source pad region, drain pad region and Schottky metal pad region outside the active region and the active region is 10~20μm; the width of the four pad regions is 100~700μm and the length is 100~2000μm; the thickness of the top metal layer in the four pad regions is 2.5~6μm.

[0093] Locally etched vias of varying depths are fabricated between the gate and source of a GaN HEMT with a dual-dielectric-layer gate-source (MIS) structure, and below the gate, and filled with Schottky metal layers. This not only allows electrons between the gate and source and irradiation-induced interface state charges to flow out of the transistor from the Schottky metal layer in the off-state, but also discharges charge carriers accumulated at the gate, preventing increased leakage current and threshold voltage drift caused by charge carrier accumulation. The lower end of the Schottky metal layer between the gate and source is in contact with the top surface of the barrier layer. Part of the Schottky metal layer in the gate etched vias is in contact with the barrier layer and the gate; the lower end of the remaining Schottky metal layer is in contact with the first ultrathin gate dielectric layer, and the upper end is connected to the Schottky metal layer between the gate and source via strip-shaped Schottky metal interconnect layers, forming an independent pad region outside the active region, used solely for charge carrier discharge.

[0094] This study also fully considers the performance of devices with high threshold voltages, proposes a composite structure design of dual dielectric layer MIS gate and Schottky metal gate, and realizes a device with normal electrical operation capability. The manufacturing method is simple, compatible with existing processes, and improves the overall radiation resistance of the device.

[0095] Secondly, this invention also provides a method for manufacturing a radiation-resistant GaN HEMT with high threshold voltage stability, used to fabricate the aforementioned radiation-resistant GaN HEMT with high threshold voltage stability. See [link to previous document]. Figure 6 ,include:

[0096] Step S1, see Figure 7 The epitaxial wafer is grown sequentially from bottom to top, consisting of the substrate layer 1, the gallium nitride layer 2, the barrier layer 3, the first dielectric layer 4, and the second dielectric layer 5. The first dielectric layer 4, the second dielectric layer 5, the barrier layer 3, and part of the gallium nitride layer 2 around the active region are removed by inductively coupled plasma dry etching. The thickness of the barrier layer 3 etched away is 5~10nm, and the second dielectric layer 5 is in contact with the barrier layer 3 to form an ohmic contact with low resistance characteristics.

[0097] Step S2: A third dielectric layer is grown on the entire epitaxial wafer using plasma-enhanced chemical vapor deposition. The third dielectric layer, the first dielectric layer 4, the second dielectric layer 5, and part of the barrier layer 3 are etched in the source and drain regions using inductively coupled plasma dry etching, and an ohmic metal layer 7 is deposited. (See [link to previous step]). Figure 8 ;

[0098] Then, a third dielectric layer is grown on the entire epitaxial wafer, the gate region and the gate pad region are etched away to form the third dielectric layer, and a gate metal layer is deposited 8.

[0099] Step S3: The gate metal layer 8 and the second dielectric layer 5 of the patterned region are etched using inductively coupled plasma dry etching to form etch holes in the gate metal layer 8 and deposit the second Schottky metal layer 10. See [link to previous step]. Figure 9 ;

[0100] The gate metal layer 8 and the first dielectric layer 4 of the patterned area are etched using inductively coupled plasma dry etching to form etch holes in the gate metal layer 8.

[0101] The third dielectric layer is grown across the entire substrate. The already grown third dielectric layer is etched into the etch holes of the gate metal layer 8 and the Schottky metal pad area. Then, the first Schottky metal layer 9 is deposited. The first Schottky metal layer 9 is in contact with the barrier layer 3 and also with the gate metal layer 8. (See [reference]). Figure 10 ;

[0102] The second Schottky metal layer 10 is in contact with the first dielectric layer 4 but not with the gate metal layer 8; the second Schottky metal layer 10 is not in contact with the first metal interconnect layer 12; when etching the third dielectric layer in the etch hole of the second Schottky metal layer 10, a portion of the edge third dielectric layer is retained to ensure that the space between the second Schottky metal layer 10 and the gate metal layer 8 is filled by the third dielectric layer.

[0103] Step S4: Grow the third dielectric layer over the entire wafer; etch the ohmic metal layer 7 of the drain, the ohmic metal layer 7 of the source, and the third dielectric layer above the gate metal layer 8; and etch the third dielectric layer above the source pad region, drain pad region, and gate pad region. Deposit the first metal interconnect layer 12 and the second metal interconnect layer 13. See below. Figure 12 ;

[0104] The first metal interconnect layer 12 and the third dielectric layer above the patterned area of ​​the gate metal layer 8 are etched using inductively coupled plasma dry etching. The third dielectric layer above the source and drain pad areas is etched, and the third dielectric layer in the Schottky metal pad area is etched, depositing strip-shaped Schottky metal interconnect layers 16 and third Schottky metal layers 14. (See [reference]). Figure 13 ;

[0105] Step S5: Grow the third dielectric layer over the entire substrate; etch the third dielectric layer above the four pad regions (source pad region, drain pad region, gate pad region, and Schottky metal pad region); deposit the top metal layer 15. (See attached diagram) Figure 14 The fabrication of GaN HEMT devices was completed.

[0106] Optionally, after the first Schottky metal layer 9 is deposited in step S3, the third dielectric layer, the first dielectric layer 4 and the second dielectric layer 5 of the patterned region between the gate metal layer 8 and the source ohmic metal layer 7 are etched using inductively coupled plasma dry etching to form an etch hole in the fourth Schottky metal layer 11.

[0107] The third dielectric layer is grown on the entire substrate. The etch holes of the fourth Schottky metal layer 11 and the already grown Schottky metal pad areas are etched to form the third dielectric layer. Then, the fourth Schottky metal layer 11 is deposited. (See [link to previous section]). Figure 11 ;

[0108] The fourth Schottky metal layer 11 is in contact with the barrier layer 3, but not with the surrounding first dielectric layer 4 and second dielectric layer 5; the fourth Schottky metal layer 11 is not in contact with the first metal interconnect layer 12; when etching the third dielectric layer in the etch hole of the fourth Schottky metal layer 11, a portion of the edge third dielectric layer is retained to ensure that the third dielectric layer fills the space between the fourth Schottky metal layer 11 and the first and second dielectric layers.

[0109] In step S4, when depositing the strip-shaped Schottky metal interconnect layer 16, the first metal interconnect layer 12 and the third dielectric layer above the patterned area of ​​the fourth Schottky metal layer 11 and the gate metal layer 8 are etched, and the third dielectric layer of the Schottky metal pad area is etched while simultaneously depositing the strip-shaped Schottky metal interconnect layer 16 and the second metal interconnect layer 13.

[0110] The strip-shaped Schottky metal interconnect layer 16 is not in contact with the first interconnect metal layer 12, but is in contact with the second Schottky metal layer 10 and the fourth Schottky metal layer 11; a third dielectric layer is filled between the strip-shaped Schottky metal interconnect layer 16, the second Schottky metal layer 10, the fourth Schottky metal layer 11 and the first metal interconnect layer 12.

[0111] The high threshold voltage stability, radiation-depleted GaN HEMT fabricated using the above manufacturing method differs from mainstream MIS junction HEMT devices. It constructs a Schottky metal gate by integrating a Schottky metal layer and a barrier layer within a deeper etched hole, which, together with the original dual-dielectric MIS gate, forms a composite gate. This synergistic effect modulates the device's threshold voltage, increasing the gate threshold voltage swing capability. Because the gate metal layer is uninterrupted along the length of the first and second dielectric layers, the device possesses normal gate functionality.

[0112] This invention also fully considers the impact of radiation-induced interface state charges on the device threshold voltage stability, the increase in leakage current due to source carrier injection, the impact of carrier accumulation under the gate on device stability, and the impact of low threshold voltage on power consumption and leakage current. It proposes a radiation-resistant GaN-based HEMT device with high threshold voltage stability featuring a dual dielectric layer gate and a composite gate. The manufacturing method is simple and compatible with existing processes, providing a solution for improving the low threshold voltage stability and radiation resistance of depletion-type devices.

[0113] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, but do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0114] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high threshold voltage stability against irradiation depletion mode GaN HEMT, characterized in that, The high threshold voltage stability anti-radiation depletion type GaN HEMT comprises a substrate layer (1) and a gallium nitride layer (2) arranged from bottom to top, an active region upper surface of the gallium nitride layer (2) is sequentially provided with an active region gallium nitride layer (2), a barrier layer (3), a first dielectric layer (4) and a second dielectric layer (5) from bottom to top, and a plurality of strip-shaped gate metal layers (8) are arranged on the upper surface of the second dielectric layer (5); the gate metal layer (8) and the first dielectric layer (4) and the second dielectric layer (5) located below the gate metal layer (8) form a gate of a MIS type GaN HEMT. A plurality of first etching holes are arranged along the length direction of the gate metal layer (8), and a Schottky metal layer is arranged in the first etching hole; the Schottky metal layer comprises a first Schottky metal layer (9) and a second Schottky metal layer (10); the bottom of the first Schottky metal layer (9) is in contact with the barrier layer (3), the sidewall is in contact with the first dielectric layer (4) and the second dielectric layer (5), and the top is interconnected with the gate metal layer (8); the bottom of the second Schottky metal layer (10) is in contact with the top of the first dielectric layer (4), and the top is in contact with a Schottky metal interconnection layer (16).

2. The high threshold voltage stability anti-radiation depletion type GaN HEMT of claim 1, wherein the width of the gate metal layer (8) is 2-5 μm, and the length is 30-1500 μm; the distance between two adjacent first etching holes on the gate metal layer (8) is 2-15 μm, and the length of the first etching hole is 2-150 μm; the minimum thickness of the sidewall of the first etching hole to the outer sidewall of the gate metal layer (8) is 0.4-1.2 μm, and the minimum distance between the sidewall of the first etching hole at both ends of the gate metal layer (8) and the corresponding end surface of the gate metal layer (8) is 1-10 μm.

3. The high threshold voltage stability anti-radiation depletion type GaN HEMT of claim 1, wherein the first Schottky metal layer (9) and the second Schottky metal layer (10) are alternately filled in the first etching hole along the length direction of the gate metal layer (8), and the second Schottky metal layer (10) is located at the middle position of the corresponding etching hole, the length is 1.2-140 μm, and the width is 0.4-1.4 μm; the second Schottky metal layer (10) is not in contact with the gate metal layer (8), and the distance between the sidewall of the second Schottky metal layer (10) and the sidewall of the corresponding etching hole is 0.4-0.6 μm. The top of the second Schottky metal layer (10) is led out to form a Schottky metal pad area outside the active region through a Schottky metal interconnection layer (16), the Schottky metal interconnection layer (16) is strip-shaped, and the thickness is 0.7-2.5 μm. ​ 4. The high threshold voltage stability, radiation-hardened depletion mode GaN HEMT of claim 1, wherein, ​ 5. The high threshold voltage stability anti-radiation depletion mode GaN HEMT of claim 4, wherein, The gate is provided with ohmic metal layers (7) with different intervals on both sides, and the ohmic metal layers (7) are in contact with the barrier layer (3), wherein the ohmic metal layer (7) closer to the gate forms a source with the first metal interconnection layer (12) on the top, and the ohmic metal layer (7) farther from the gate forms a drain with the second metal interconnection layer (13) on the top; the source and the drain are respectively led out of the active area through the corresponding metal interconnection layers to form a source pad area and a drain pad area; The second Schottky metal layer (10) is connected with the Schottky metal interconnection layer (16) by passing through the through hole on the first metal interconnection layer (12) upwards, and the second Schottky metal layer (10) is not in contact with the first metal interconnection layer (12); intervals are formed between the second Schottky metal layer (10) and the first metal interconnection layer (12) and between the first metal interconnection layer (12) and the Schottky metal interconnection layer (16), and the intervals are filled with the third dielectric layer (6); The third Schottky metal layer (14) and the top metal layer (15) are arranged above the interconnection metal layer of the source pad area and the drain pad area, and the top metal layer (15) is arranged above and below the third Schottky metal layer (14); The gate metal layer (8) is led out of the active area to form a gate pad area, and the third Schottky metal layer (14) and the top metal layer (15) are sequentially arranged above the gate metal layer (8) in the gate pad area; The top surface of the gallium nitride layer (2) is filled with the third dielectric layer (6) except the top surface of the drain pad area, the source pad area, the gate pad area and the Schottky metal pad area.

6. The high threshold voltage stability anti-radiation depletion mode GaN HEMT of claim 5, wherein, The second etching hole is arranged between the ohmic metal layer (7) of the source and the gate metal layer (8) and is spaced along the length direction of the gate metal layer (8), and the fourth Schottky metal layer (11) is arranged in the second etching hole; the bottom of the fourth Schottky metal layer (11) is in contact with the barrier layer (3), an interval is formed between the sidewall of the fourth Schottky metal layer (11) and the sidewall of the corresponding etching hole, the top of the fourth Schottky metal layer (11) is connected with the Schottky metal interconnection layer (16) by passing through the through hole on the first metal interconnection layer (12) upwards, and the fourth Schottky metal layer (11) is not in contact with the first metal interconnection layer (12); an interval is formed between the fourth Schottky metal layer (11) and the first metal interconnection layer (12), and the interval is filled with the third dielectric layer (6).

7. The high threshold voltage stability anti-radiation depletion mode GaN HEMT of claim 6, wherein, The interval between the second etching hole and the sidewall of the ohmic metal layer (7) of the source and the sidewall of the gate metal layer (8) is 0.4-0.8 μm; the interval between two adjacent second etching holes is 6-200 μm, and the interval between the sidewall of the two second etching holes at the two ends of the length direction of the gate metal layer (8) and the corresponding edge of the active area is 3-100 μm. The length of the second etching hole along the length direction of the gate metal layer (8) is 4-300 μm, the width along the direction perpendicular to the length direction of the gate metal layer (8) is 1.6-2.5 μm, and the distance between the fourth Schottky metal layer (11) and the sidewall of the second etching hole is 0.3-0.5 μm.

8. The high threshold voltage stability anti-fusion GaN HEMT according to any one of claims 1-7, characterized in that, The material of the first dielectric layer is any one of aluminum oxide and hafnium dioxide, and the thickness is 2-6 nm; the material of the second dielectric layer is any one of silicon nitride and silicon dioxide, and the thickness is 15-20 nm.

9. A method for manufacturing a high threshold voltage stability radiation-hardened depletion mode GaN HEMT for making a high threshold voltage stability radiation-hardened depletion mode GaN HEMT according to any one of claims 1 to 7, characterized in that, The method comprises the following steps: Step one, growing the substrate layer (1), the gallium nitride layer (2), the barrier layer (3), the first dielectric layer (4) and the second dielectric layer (5) on the epitaxial wafer from bottom to top, and etching to remove the first dielectric layer (4), the second dielectric layer (5), the barrier layer (3) and part of the gallium nitride layer (2) around the active region; Step two, growing the third dielectric layer on the whole epitaxial wafer, etching the third dielectric layer, the first dielectric layer (4), the second dielectric layer (5) and part of the barrier layer (3) in the source and drain regions, and depositing the ohmic metal layer (7); Then growing the third dielectric layer on the whole epitaxial wafer, etching to remove the third dielectric layer formed in the gate region and the gate pad region, and depositing the gate metal layer (8); Step three, etching the gate metal layer (8) and the second dielectric layer (5) in the patterned region to form the etching hole of the gate metal layer (8) and depositing the second Schottky metal layer (10); Etching the gate metal layer (8) and the first dielectric layer (4) in the patterned region to form the etching hole of the gate metal layer (8); Growing the third dielectric layer on the whole wafer, etching the third dielectric layer formed in the etching hole of the gate metal layer (8) and the Schottky metal pad region, and then depositing the first Schottky metal layer (9); Step four, growing the third dielectric layer on the whole wafer, etching the ohmic metal layer (7) of the drain, the ohmic metal layer (7) of the source and the third dielectric layer formed above the gate metal layer (8), and etching the third dielectric layer formed above the source pad region, the drain pad region and the gate pad region, and depositing the first metal interconnection layer (12) and the second metal interconnection layer (13); Etching the first metal interconnection layer (12) and the third dielectric layer above the patterned region of the gate metal layer (8), etching the third dielectric layer above the source pad region and the drain pad region, and etching the third dielectric layer in the Schottky metal pad region to deposit the strip-shaped Schottky metal interconnection layer (16) and the third Schottky metal layer (14); Step five, growing the third dielectric layer on the whole wafer, etching the third dielectric layer above the source pad region, the drain pad region, the gate pad region and the Schottky metal pad region, and depositing the top metal layer (15) to complete the fabrication of the GaN HEMT device.

10. The method according to claim 9, wherein the GaN HEMT device is a depletion-mode GaN HEMT device. After the first Schottky metal layer (9) is deposited in step three, the third dielectric layer, the first dielectric layer (4) and the second dielectric layer (5) between the pattern area of the gate metal layer (8) and the ohmic metal layer (7) of the source are etched to form the etching hole of the fourth Schottky metal layer (11); The third dielectric layer is grown in whole, the etching hole of the fourth Schottky metal layer (11) and the third dielectric layer of the Schottky metal pad area are etched, and then the fourth Schottky metal layer (11) is deposited; In step four, when the strip-shaped Schottky metal interconnection layer (16) and the third Schottky metal layer (14) are deposited, the first metal interconnection layer (12) and the third dielectric layer above the pattern area of the fourth Schottky metal layer (11) and the gate metal layer (8) are etched, the third dielectric layer of the Schottky metal pad area is etched, and the strip-shaped Schottky metal interconnection layer (16) and the third Schottky metal layer (14) are deposited at the same time.

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