Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, in the manufacturing method of the semiconductor device, a first emitter contact layer, a first collector contact layer, a second base contact layer and a depletion layer are firstly formed, the first emitter contact layer is formed in a device layer of a first emitter region, and the second collector contact layer is formed in a device layer of a second emitter region; the first collector contact layer is formed in the device layer of the first collector region, the second base contact layer is formed in the device layer of the second base region, the depletion layer is formed in the device layer of the first base region, and the depletion layer is in contact with the first collector contact layer and is spaced from the first emitter contact layer; a first collector, a first emitter, and a second base are formed. Therefore, the NPN bipolar transistor and the PNP bipolar transistor can be integrated on the same substrate, and the depletion layer is formed in the device layer of the first base region, so that the breakdown voltage between the first base region and the first collector region can be improved, and the voltage resistance between the first base and the first collector is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Among semiconductor devices, bipolar devices have the characteristics of high current handling capability, high current gain, and high power density, which are essential for realizing oscillators and various amplifiers (such as power amplifiers, low noise amplifiers, and current feedback operational amplifiers). However, in the integrated manufacturing method of NPN bipolar transistors and PNP bipolar transistors, the monolithic integration of NPN bipolar transistors and PNP bipolar transistors (integrated on the same GaN epitaxial substrate, especially the Si-based GaN epitaxial substrate commonly used in enhancement mode devices at this stage) is difficult, and limits the withstand voltage performance between the collector and the base of the PNP bipolar transistor, which is not conducive to realizing the high withstand voltage between the collector and the base of the PNP bipolar transistor. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to integrate an NPN bipolar transistor and a PNP bipolar transistor on the same substrate and to improve the withstand voltage between the collector and the base of the PNP bipolar transistor.

[0004] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0005] Providing a substrate, on which a device layer is formed, the substrate defining a first emitter region, a first base region, and a first collector region of a PNP bipolar transistor, wherein the first base region is located between the first emitter region and the first collector region, and the substrate defining a second base region of an NPN bipolar transistor, wherein the second base region is spaced apart from the first collector region;

[0006] Forming a first emitter contact layer, a first collector contact layer, a second base contact layer and a depletion layer, wherein the first emitter contact layer is formed in a device layer in the first emitter region, the first collector contact layer is formed in a device layer in the first collector region, the second base contact layer is formed in a device layer in the second base region, the depletion layer is formed in a device layer in the first base region, and the depletion layer is in contact with the first collector contact layer and spaced apart from the first emitter contact layer, wherein the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions;

[0007] A first emitter, a first collector and a second base are formed, wherein the first emitter is formed on the top surface of the first emitter contact layer and is electrically connected to the first emitter contact layer, the first collector is formed on the top surface of the first collector contact layer and is electrically connected to the first collector contact layer, and the second base is formed on the top surface of the second base contact layer and is electrically connected to the second base contact layer.

[0008] Optionally, the method for forming the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer includes:

[0009] By a first ion implantation process, ion implantation is performed on the device layer in the first emitter region to form the first emitter contact layer, ion implantation is performed on the device layer in the first collector region to form the first collector contact layer, and ion implantation is performed on the device layer in the second base region to form the second base contact layer;

[0010] By performing at least one second ion implantation process, ion implantation is performed in a device layer of a portion of the first base region to form the depletion layer, and the ion implantation depth of the second ion implantation process is less than the ion implantation depth of the first ion implantation process.

[0011] Optionally, the method for forming the first collector, the first emitter and the second base includes:

[0012] forming a metal material layer, wherein the metal material layer covers the device layer, the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer;

[0013] The metal material layer is etched using a dry etching process to remove the metal material layer on the device layer and the depletion layer, and the metal material layer on the first emitter contact layer is retained to form the first emitter, and the metal material layer on the first collector contact layer is retained to form the first collector, and the metal material layer on the second base contact layer is retained to form the second base.

[0014] Optionally, the device layer includes a channel layer, a barrier layer and a P-type epitaxial layer stacked in sequence from bottom to top, and after forming the first collector, the first emitter and the second base, further includes:

[0015] The P-type epitaxial layer is etched by a dry etching process to remove the P-type epitaxial layer between the first emitter contact layer and the first collector contact layer, and to remove the P-type epitaxial layer on both sides of the second base contact layer, wherein the channel layer and the barrier layer between the first emitter contact layer and the first collector contact layer constitute the first base contact layer of the PNP bipolar transistor, the channel layer and the barrier layer of the second base contact layer close to the first collector contact layer constitute the second emitter contact layer of the NPN bipolar transistor, and the channel layer and the barrier layer of the second base contact layer away from the first collector constitute the second collector contact layer of the NPN bipolar transistor.

[0016] Optionally, the material of the channel layer is gallium nitride, the material of the barrier layer is aluminum gallium nitride, and the material of the P-type epitaxial layer is P-type doped gallium nitride.

[0017] Optionally, after forming the first base contact layer, the second emitter contact layer and the second collector contact layer, the method further includes:

[0018] forming a passivation layer and a dielectric layer in sequence, the passivation layer covering the first collector, the first emitter, the second base, the first base contact layer, the second collector contact layer, the second emitter contact layer and the depletion layer, and the dielectric layer covering the passivation layer; and,

[0019] A first base of the PNP bipolar transistor is formed, and a second collector and a second emitter of the NPN bipolar transistor are formed, wherein the first base penetrates the passivation layer and the dielectric layer and is electrically connected to the first base contact layer, the second collector penetrates the passivation layer and the dielectric layer and is electrically connected to the second collector contact layer, and the second emitter penetrates the passivation layer and the dielectric layer and is electrically connected to the second emitter contact layer.

[0020] Optionally, the method for forming the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer includes:

[0021] Etching the device layer in the first emitter region to form a first opening, etching the device layer in the first collector region to form a second opening, and etching the device layer in the second base region to form a third opening;

[0022] Etching the device layer in the first base region to form a fourth opening, wherein the fourth opening is connected to the second opening, and a depth of the fourth opening is less than a depth of the second opening;

[0023] A selective epitaxial growth process is performed to form the first emitter contact layer in the first opening, the first collector contact layer in the second opening, the second base contact layer in the third opening, and the depletion layer in the fourth opening.

[0024] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:

[0025] A substrate having a device layer formed thereon, the substrate defining a first emitter region, a first base region, and a first collector region of a PNP bipolar transistor, the first base region being located between the first emitter region and the first collector region, and the substrate defining a second base region of an NPN bipolar transistor, the second base region being spaced apart from the first collector region;

[0026] a first emitter contact layer formed in the device layer in the first emitter region;

[0027] a first collector contact layer formed in the device layer in the first collector region;

[0028] a second base contact layer formed in the device layer in the second base region;

[0029] A depletion layer is formed in the device layer of the first base region, and the depletion layer is in contact with the first collector contact layer and is separated from the first emitter contact layer, and the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions;

[0030] a first collector electrode formed on a top surface of the first collector contact layer and electrically connected to the first collector contact layer;

[0031] a first emitter formed on a top surface of the first emitter contact layer and electrically connected to the first emitter contact layer;

[0032] A second base is formed on a top surface of the second base contact layer and is electrically connected to the second base contact layer.

[0033] Optionally, the device layer includes a channel layer and a barrier layer formed on the channel layer, the channel layer and the barrier layer between the first emitter contact layer and the first collector contact layer constitute the first base contact layer of the PNP bipolar transistor, the channel layer and the barrier layer on the side of the second base contact layer close to the first collector contact layer constitute the second emitter contact layer of the NPN bipolar transistor, and the channel layer and the barrier layer on the side of the second base contact layer away from the first collector contact layer constitute the second collector contact layer of the NPN bipolar transistor.

[0034] Optionally, the semiconductor device further includes:

[0035] a passivation layer and a dielectric layer, wherein the passivation layer covers the first collector, the first emitter, the second base, the first base contact layer, the second collector contact layer, the second emitter contact layer and the depletion layer;

[0036] A first base, a second collector and a second emitter, the first base penetrates the passivation layer and the dielectric layer and is electrically connected to the first base contact layer, the second collector penetrates the passivation layer and the dielectric layer and is electrically connected to the second collector contact layer, and the second emitter penetrates the passivation layer and the dielectric layer and is electrically connected to the second emitter contact layer.

[0037] In the manufacturing method of the semiconductor device provided by the present invention, a first emitter contact layer, a first collector contact layer, a second base contact layer and a depletion layer are first formed, the first emitter contact layer is formed in the device layer of the first emitter region, the first collector contact layer is formed in the device layer of the first collector region, the second base contact layer is formed in the device layer of the second base region, the depletion layer is formed in the device layer of the first base region, and the depletion layer is in contact with the first collector contact layer and is spaced apart from the first emitter contact layer, wherein the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions; then, a first collector, a first emitter and a second base are formed, the first collector is formed on the top surface of the first collector contact layer and is electrically connected to the first collector contact layer, the first emitter is formed on the top surface of the first emitter contact layer and is electrically connected to the emitter contact layer, and the second base is formed on the top surface of the second base contact layer and is electrically connected to the second base contact layer. In this way, the NPN bipolar transistor and the PNP bipolar transistor can be integrated on the same substrate, and since a depletion layer is formed in the device layer of the first base region, the electric field distribution between the first base region and the first collector region can be made more uniform, which is beneficial to increase the breakdown voltage between the first base region and the first collector region, thereby improving the voltage resistance between the first base region and the first collector region, and further improving the voltage resistance between the first base and the first collector of the PNP bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0039] Figures 2 to 15 is a schematic diagram of a structure formed in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0040] The reference numerals are described as follows:

[0041] 100-substrate;

[0042] 101a - first emitter region; 101b - first base region; 101c - first collector region;

[0043] 102a - second emitter region; 102b - second base region; 102c - second collector region;

[0044] 110- buffer layer;

[0045] 120-device layer; 120a-first opening; 120b-second opening; 120c-third opening; 120d-fourth opening; 121a-first emitter contact layer; 121b-first base contact layer; 121c-first collector contact layer;

[0046] 122a - second emitter contact layer; 122b - second base contact layer; 122c - second collector contact layer;

[0047] 1201-channel layer; 1202-barrier layer; 1203-P-type epitaxial layer;

[0048] 130 - a patterned first photoresist layer; 131 - a patterned second photoresist layer; 132 - a depletion layer;

[0049] 140 - metal material layer; 140a - first emitter; 140b - first collector; 140c - second base;

[0050] 150-passivation layer;

[0051] 160- dielectric layer;

[0052] 170a - first base; 170b - second emitter; 170c - second collector. DETAILED DESCRIPTION

[0053] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0054] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 As shown, the method for manufacturing a semiconductor device provided in this embodiment includes:

[0055] Step S1: providing a substrate, on which a device layer is formed, the substrate defining a first emitter region, a first base region and a first collector region of a PNP bipolar transistor, wherein the first base region is located between the first emitter region and the first collector region, and the substrate defining a second base region of an NPN bipolar transistor, wherein the second base region is spaced apart from the first collector region;

[0056] Step S2: forming a first emitter contact layer, a first collector contact layer, a second base contact layer and a depletion layer, wherein the first emitter contact layer is formed in a device layer in the first emitter region, the first collector contact layer is formed in a device layer in the first collector region, the second base contact layer is formed in a device layer in the second base region, the depletion layer is formed in a device layer in the first base region, and the depletion layer is in contact with the first collector contact layer and spaced apart from the first emitter contact layer, wherein the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions;

[0057] Step S3: Form a first emitter, a first collector and a second base, wherein the first emitter is formed on the top surface of the first emitter contact layer and is electrically connected to the first emitter contact layer, the first collector is formed on the top surface of the first collector contact layer and is electrically connected to the first collector contact layer, and the second base is formed on the top surface of the second base contact layer and is electrically connected to the second base contact layer.

[0058] Figures 2 to 15 is a schematic diagram of a structure formed in a method for manufacturing a semiconductor device provided by an embodiment of the present invention; Figures 2 to 15 A more detailed description is provided for the method for manufacturing the semiconductor device provided in this embodiment.

[0059] First, refer to Figure 2 As shown, step S1 is performed to provide a substrate 100, on which a device layer 120 is formed, and the substrate 100 defines a first emitter region 101a, a first base region 101b and a first collector region 101c of a PNP bipolar transistor, wherein the first base region 101b is located between the first emitter region 101a and the first collector region 101c, and the substrate 100 defines a second base region 102b of an NPN bipolar transistor, wherein the second base region 102b is spaced apart from the first collector region 101c, i.e., the second base region 102b is located on one side of the first collector region 101c and the two are spaced apart.

[0060] In this embodiment, Figure 2As shown, the substrate 100 may also define a second collector region 102c and a second emitter region 102a of the NPN bipolar transistor, and the second collector region 102c and the second emitter region 102a are respectively located on both sides of the second base region 102b. In other words, the substrate 100 includes a first emitter region 101a, a first base region 101b, and a first collector region 101c for forming a PNP bipolar transistor, and a second emitter region 102a, a second base region 102b, and a second collector region 102c for forming an NPN bipolar transistor. The first collector region 101c and the second emitter region 102a may be isolated by a shallow trench isolation structure.

[0061] Exemplarily, the material of the substrate 100 may be silicon (Si), gallium nitride (GaN) or sapphire. The device layer 120 covers the substrate 100, and the device layer 120 includes a channel layer 1201, a barrier layer 1202 and a P-type epitaxial layer 1203 stacked in sequence from bottom to top, wherein the material of the channel layer 1201 is gallium nitride, the material of the P-type epitaxial layer 1203 is P-doped gallium nitride, and the material of the barrier layer 1202 is aluminum gallium nitride.

[0062] In this embodiment, a buffer layer 110 is formed between the substrate 100 and the device layer 120. The material of the buffer layer 110 is gallium nitride. The buffer layer 110 is used to reduce the lattice mismatch generated when the channel layer 1201 is directly epitaxially grown on the substrate 100, reduce the density of dislocation crystal defects, and improve the quality of the channel layer 1201.

[0063] Next, refer to Figure 6 As shown, step S2 is performed to form a first emitter contact layer 121a, a first collector contact layer 121c, a second base contact layer 122b and a depletion layer 132, wherein the first emitter contact layer 121a is formed in the device layer 120 of the first emitter region 101a, the first collector contact layer 121c is formed in the device layer 120 of the first collector region 101c, and the second base contact layer 122b is formed in the device layer 120 of the second base region 102b, wherein the first emitter contact layer 121a, the first collector contact layer 121c, the second base contact layer 122b and the depletion layer 132 all have P-type ions.

[0064] In this embodiment, since a depletion layer 132 is formed in the device layer 120 of the first base region 101b, the electric field distribution between the first base region 101b and the first collector region 101c can be made more uniform, which is conducive to improving the breakdown voltage between the first base region 101b and the first collector region 101c, thereby improving the withstand voltage between the first base region 101b and the first collector region 101c, and further improving the withstand voltage between the first base and the first collector of the PNP bipolar transistor. Specifically, when the PN junction between the first base (N type) and the first collector (P type) of the subsequently formed PNP bipolar transistor is reverse biased, the direction of the electric field points from the first base to the first collector, and the reverse electric field prevents the electrons in the first base from diffusing to the first collector, and forms a depletion region in the depletion layer, so that the charge in the depletion region is depleted, and almost no free carriers exist. The width of the depletion region increases with the increase of the reverse bias voltage, thereby improving the withstand voltage between the first base and the first collector.

[0065] In one embodiment, the method for forming the first emitter contact layer 121a, the first collector contact layer 121c, the second base contact layer 122b and the depletion layer 132 comprises the following steps 1 and 2:

[0066] Step 1, such as Figure 4 As shown, through a first ion implantation process, ion implantation is performed on the device layer 120 of the first emitter region 101a to form the first emitter contact layer 121a, and ion implantation is performed on the device layer 120 of the first collector region 101c to form the first collector contact layer 121c, and ion implantation is performed on the device layer 120 of the second base region 102b to form the second base contact layer 122b.

[0067] Specifically, the method of the first ion implantation process includes: first, Figure 3 As shown, a patterned first photoresist layer 130 is formed on the device layer 120, and the patterned first photoresist layer 130 exposes the device layer 120 in the first collector region, the device layer 120 in the first emitter region, and the device layer 120 in the second base region; then, as shown Figure 4 As shown, using the patterned first photoresist layer 130 as a mask, ion implantation is performed on the exposed device layer 120 to form a first collector contact layer 121c, a first emitter contact layer 121a and a second base contact layer 122b.

[0068] In this embodiment, the first ion implantation process may be a vertical ion implantation process to accurately control the depth of the implanted ions so that the ions are implanted into the P-type epitaxial layer 1203, the barrier layer 1202, and the channel layer 1201 in the device layer 120. The ions in the first ion implantation process are magnesium (Mg) ions, that is, the P-type ions in the first emitter contact layer 121a, the first collector contact layer 121c, and the second base contact layer 122b are magnesium (Mg) ions.

[0069] In a further solution, the first ion implantation process can also implant ions into a partially thick buffer layer 110, that is, the ion implantation depth of the first ion implantation process reaches a partially thick buffer layer 110, that is, the bottoms of the first emitter contact layer 121a, the first collector contact layer 121c, and the second base contact layer 122b extend into the buffer layer 110. In this way, it is helpful to ensure the withstand voltage between the electrodes in the PNP bipolar transistor and the withstand voltage between the electrodes in the NPN bipolar transistor.

[0070] Then, if Figure 5 As shown, the patterned first photoresist layer 130 is removed to expose the device layer 120 .

[0071] In this embodiment, at the interface between the barrier layer 1202 and the channel layer 1201 in the first emitter contact layer 121a and the first collector contact layer 121c, due to the difference in the conduction band bottom energy of the two materials, a potential well is formed at the interface between the barrier layer 1202 and the channel layer 1201, thereby accumulating electrons to form a two-dimensional electron gas (2DEG), thereby enabling efficient current conduction.

[0072] Step 2, such as Figure 6 As shown, by performing at least one second ion implantation process to form a depletion layer 132 in the device layer 120 of a portion of the first base region 101b, the ion implantation depth of the second ion implantation process is less than the ion implantation depth of the first ion implantation process, so that the depth of the depletion layer 132 is less than the depth of the first collector contact layer 121c, which is beneficial to improving the current amplification capability of the PNP bipolar transistor.

[0073] Specifically, the method of performing at least one second ion implantation process includes: first, Figure 6As shown, a patterned second photoresist layer 131 is formed on the device layer 120, and the patterned second photoresist layer 131 exposes a portion of the first base region 101b, that is, exposes a portion of the first base region 101b close to the first collector contact layer 121c. In other words, the patterned second photoresist layer 131 covers the first emitter contact layer 121a, the first collector contact layer 121c, the second base contact layer 122b, the device layer 120 of the second collector region 102c, the device layer 120 of the second emitter region 102a, and covers a portion of the device layer 120 of the first base region 101b close to the first emitter contact layer 121a.

[0074] Then, the patterned second photoresist layer 131 is used as a mask to perform at least one second ion implantation process to form a depletion layer 132. By forming the depletion layer 132, the electric field distribution between the first base region 101b and the first collector region 101c can be made more uniform, and the breakdown voltage between the first base region 101b and the first collector region 101c can be increased, thereby increasing the withstand voltage between the first base region 101b and the first collector region 101c, and further increasing the withstand voltage between the first base and the first collector of the PNP bipolar transistor.

[0075] Optionally, the total number of times the second ion implantation process is performed may be two times, but is not limited thereto, and the number of times the second ion implantation process is performed may be selected according to process requirements, such as three times, four times, five times, or six times. In this way, the doping concentration of the depletion layer 132 may be adjusted and the gradient of the depletion layer 132 may be optimized, which is beneficial to improving the withstand voltage between the first collector region 101c and the first base region 101b of the PNP bipolar transistor. In addition, the leakage current in the PNP bipolar transistor may also be reduced.

[0076] In this embodiment, the ions in the second ion implantation process include magnesium (Mg) ions, that is, the P-type doped ions in the depletion layer 132 are magnesium ions.

[0077] In this embodiment, the second ion implantation process may be a vertical ion implantation process to accurately control the depth of the implanted ions so that the ions are implanted into the P-type epitaxial layer 1203 , the barrier layer 1202 and a partial thickness of the channel layer 1201 in the device layer 120 .

[0078] In another embodiment, the method for forming the first emitter contact layer 121a, the first collector contact layer 121c, the second base contact layer 122b and the depletion layer 132 comprises: first, Figure 8As shown, the device layer 120 of the first emitter region 101a is etched to form a first opening 120a, the device layer 120 of the first collector region 101c is etched to form a second opening 120b, and the device layer of the second base region 102b is etched to form a third opening 120c.

[0079] The first opening 120a, the second opening 120b and the third opening 120c all penetrate the device layer 120. In a further embodiment, after etching the device layer 120, the buffer layer 110 below the device layer is also etched so that the first opening 120a, the second opening 120b and the third opening 120c extend into the buffer layer 110. Figure 8 As shown, a patterned first photoresist layer 130 can be first formed on the device layer 120, and then the patterned first photoresist layer 130 is used as a mask to adopt a dry etching process to etch the device layer 120 of the first emitter region 101a, the device layer 120 of the first collector region 101c, and the device layer 120 of the second base region 102b to form the first opening 120a, the second opening 120b and the third opening 120c; then, the patterned first photoresist layer 130 is removed.

[0080] Then, if Fig. 9 As shown, the device layer 120 of the first base region 101b is etched to form a fourth opening 120d, and the fourth opening 120d is connected to the second opening 120b, and the depth of the fourth opening 120d is less than the depth of the second opening 120b; wherein, a patterned second photoresist layer (not shown) can be first formed to cover the inner surfaces of the first opening 120a, the second opening 120b and the third opening 120c, and then the patterned second photoresist layer is used as a mask to sequentially etch the P-type epitaxial layer 1203, the barrier layer 1202 and the partial thickness of the channel layer 1201 of the first base region by a dry etching process to form the fourth opening 120d; thereafter, the patterned second photoresist layer is removed.

[0081] Then, if Fig.10As shown, a selective epitaxial growth process is performed to form the first emitter contact layer 121a in the first opening 120a, to form the first collector contact layer 121c in the second opening 120b, to form the second base contact layer 122b in the third opening 120c, and to form the depletion layer in the fourth opening. The material of the first emitter contact layer 121a, the material of the first collector contact layer 121c, the material of the second base contact layer 122b, and the material of the depletion layer 132 may be gallium nitride (GaN) doped with P-type ions. The selective epitaxial growth process gas includes a nitrogen source gas, a gallium source gas, and a magnesium source gas, wherein the magnesium source gas is used to provide P-type doping ions.

[0082] Afterwards, if Fig.12 As shown, step S3 is performed to form a first emitter 140a, a first collector 140b and a second base 140c. The first emitter 140a is located on the top surface of the first emitter contact layer 121a and is electrically connected to the first emitter contact layer 121a, the first collector 140b is located on the top surface of the first collector contact layer 121c and is electrically connected to the first collector contact layer 121c, and the second base 140c is located on the top surface of the second base contact layer 122b and is electrically connected to the second base contact layer 122b. In this way, the NPN bipolar transistor and the PNP bipolar transistor can be integrated on the same substrate, that is, the monolithic integration of the NPN bipolar transistor and the PNP bipolar transistor is realized.

[0083] In this embodiment, the method for forming the first collector 140b, the first emitter 140a and the second base 140c includes: first, Fig.11 As shown, a metal material layer 140 is formed, and the metal material layer 140 covers the device layer 120, the first emitter contact layer 121a, the first collector contact layer 121c, the second base contact layer 122b and the depletion layer 132. The material of the metal material layer 140 includes palladium, titanium, titanium nitride, aluminum, nickel, gold or tungsten, but is not limited thereto.

[0084] Then, if Fig.12 As shown, the metal material layer 140 is etched by a dry etching process to remove the metal material layer 140 on the device layer 120 and the depletion layer 132, and retain the metal material layer 140 on the first emitter contact layer 121a to form the first emitter 140a, and retain the metal material layer 140 on the first collector contact layer 121c to form the first collector 140b, and retain the metal material layer 140 on the second base contact layer 122b to form the second base 140c.

[0085] Then, if Fig.13 As shown, the P-type epitaxial layer is etched by a dry etching process to remove the P-type epitaxial layer between the first emitter and the first collector, and to remove the P-type epitaxial layer on both sides of the second base, that is, to remove the P-type epitaxial layer 1203 in the first base region 101b, the second collector region 102c and the second emitter region 102a. In addition, the P-type epitaxial layer 1203 in the depletion layer 132 is also removed. The channel layer 1201 and the barrier layer 1202 between the first emitter contact layer 121a and the first collector contact layer 121c (i.e., the first base region 101b) constitute the first base contact layer 121b of the PNP bipolar transistor, the channel layer 1201 and the barrier layer 1202 of the second base contact layer 122b close to the first collector contact layer 121c side (i.e., the second emitter region 102a) constitute the second emitter contact layer 122a of the NPN bipolar transistor, and the channel layer 1201 and the barrier layer 1202 of the second base contact layer 122b away from the first collector contact layer 121c side (i.e., the second collector region 102c) constitute the second collector contact layer 122c of the NPN bipolar transistor.

[0086] Then, if Fig.13 As shown, a passivation layer 150 and a dielectric layer 160 are sequentially formed, the passivation layer 150 covers the first collector 140b, the first emitter 140a, the second base 140c, the first base contact layer 121b, the second collector contact layer 122c and the second emitter contact layer 122a, and the dielectric layer 160 covers the passivation layer 150. The passivation layer 150 and the dielectric layer 160 may be made of silicon oxide.

[0087] Afterwards, if Fig.15As shown, the first base 170a of the PNP bipolar transistor is formed, and the second collector 170c and the second emitter 170b of the NPN bipolar transistor are formed, the first base 170a penetrates the passivation layer 150 and the dielectric layer 160 and is electrically connected to the first base contact layer 121b, the second collector 170c penetrates the passivation layer 150 and the dielectric layer 160 and is electrically connected to the second collector contact layer 122c, and the second emitter 170b penetrates the passivation layer 150 and the dielectric layer 160 and is electrically connected to the second emitter contact layer 122a. The top surface of the first base 170a is higher than the top surface of the dielectric layer 160 on the first base contact layer 121b. The top surface of the second collector 170c is higher than the top surface of the dielectric layer 160 on the second collector contact layer 122c. The top surface of the second emitter 170 b is higher than the top surface of the dielectric layer 160 on the second emitter contact layer 122 a .

[0088] In further schemes, such as Fig.15 As shown, the first base 170a, the second collector 170c and the second emitter 170b can all penetrate the barrier layer 1202 and extend into the channel layer 1201 to reduce contact resistance.

[0089] In this embodiment, the method for forming the first base 170a, the second collector 170c and the second emitter 170b includes: using a dry etching process to sequentially etch the dielectric layer 160 and the passivation layer 150 to form a first groove, a second groove and a third groove, wherein the first groove is aligned with the first base contact layer 121b, the second groove is aligned with the second emitter contact layer 122a, and the third groove is aligned with the second collector contact layer 122c. In a further solution, after the passivation layer 150, the barrier layer 1202 and the channel layer 1201 under the passivation layer 150 are also etched so that the first groove, the second groove and the third groove penetrate the barrier layer 1202 and extend into the channel layer 1201; then, fill the first groove with metal material to form the first base 170a, fill the second groove with metal material to form the second emitter 170b, and fill the third groove with metal material to form the second collector 170c.

[0090] In addition, the manufacturing method of the semiconductor device provided in this embodiment can be compatible with the process of preparing high-voltage enhancement power devices, that is, the PNP bipolar transistor and NPN bipolar transistor in this embodiment can be integrated with traditional power devices on the same substrate, that is, the PNP bipolar transistor, NPN bipolar transistor and power device can be monolithically integrated.

[0091] Continue to refer Fig.14As shown, this embodiment further provides a semiconductor device, which is manufactured using the above-mentioned method for manufacturing a semiconductor device, and the semiconductor device includes:

[0092] A substrate 100, on which a device layer is formed, wherein the substrate 100 defines a first emitter region 101a, a first base region 101b, and a first collector region 101c of a PNP bipolar transistor, wherein the first base region 101b is located between the first emitter region 101a and the first collector region 101c, and wherein the substrate 100 defines a second base region 102b of an NPN bipolar transistor, wherein the second base region 102b is spaced apart from the first collector region 101c;

[0093] a first emitter contact layer 121a, a first collector contact layer 121c, and a second base contact layer 122b, wherein the first emitter contact layer 121a is formed in the device layer of the first emitter region 101a, the first collector contact layer 121c is formed in the device layer of the first collector region 101c, and the second base contact layer 122b is formed in the device layer of the second base region 102b;

[0094] A depletion layer 132 is formed in the device layer of the first base region 101b, and the depletion layer 132 is in contact with the first collector contact layer 121c and is spaced apart from the first emitter contact layer 121a; wherein the first emitter contact layer 121a, the first collector contact layer 121c, the second base contact layer 122b and the depletion layer 132 all contain P-type ions. By providing the depletion layer 132, the electric field distribution between the first base region 101b and the first collector region 101c can be made more uniform, which is beneficial to improving the breakdown voltage between the first base region 101b and the first collector region 101c, thereby improving the withstand voltage between the first base region 101b and the first collector region 101c, and further improving the withstand voltage between the first base region 101b and the first collector of the PNP bipolar transistor.

[0095] A first collector 140b, a first emitter 140a and a second base 140c, wherein the first collector 140b is formed on the top surface of the first collector contact layer 121c and is electrically connected to the first collector contact layer 121c, the first emitter 140a is formed on the top surface of the first emitter contact layer 121a and is electrically connected to the first emitter contact layer 121a, and the second base 140c is formed on the top surface of the second base contact layer 122b and is electrically connected to the second base contact layer 122b.

[0096] In this embodiment, the device layer includes a channel layer 1201 and a barrier layer 1202 located on the channel layer 1201, the channel layer 1201 and the barrier layer 1202 between the first emitter contact layer 121a and the first collector contact layer 121c constitute the first base contact layer 121b of the PNP bipolar transistor, the channel layer 1201 and the barrier layer 1202 of the second base contact layer 122b close to the first collector contact layer 121c constitute the second emitter contact layer 122a of the NPN bipolar transistor, and the channel layer 1201 and the barrier layer 1202 of the second base contact layer 122b away from the first collector 140b constitute the second collector contact layer 122c of the NPN bipolar transistor.

[0097] In this embodiment, the semiconductor device further includes a passivation layer 150 and a dielectric layer 160, wherein the passivation layer 150 covers the first collector 140b, the first emitter 140a, the second base 140c, the first base contact layer 121b, the second collector contact layer 122c and the second emitter contact layer 122a;

[0098] In this embodiment, the semiconductor device also includes a first base 170a, a second collector 170c and a second emitter 170b, the first base 170a penetrates the passivation layer 150 and the dielectric layer 160 and is electrically connected to the first base contact layer 121b, the second collector 170c penetrates the passivation layer 150 and the dielectric layer 160 and is electrically connected to the second collector contact layer 122c, and the second emitter 170b penetrates the passivation layer 150 and the dielectric layer 160 and is electrically connected to the second emitter contact layer 122a.

[0099] In summary, in the manufacturing method of the semiconductor device provided by the present invention, a first emitter contact layer, a first collector contact layer, a second base contact layer and a depletion layer are first formed, the first emitter contact layer is formed in the device layer of the first emitter region, the first collector contact layer is formed in the device layer of the first collector region, the second base contact layer is formed in the second base region, the depletion layer is formed in the device layer of the first base region, and the depletion layer is in contact with the first collector contact layer and is separated from the first emitter contact layer, wherein the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions; then, a first collector, a first emitter and a second base are formed, the first collector is located on the top surface of the first collector contact layer and is electrically connected to the first collector contact layer, the first emitter is located on the top surface of the first emitter contact layer and is electrically connected to the emitter contact layer, and the second base is located on the top surface of the second base contact layer and is electrically connected to the second base contact layer. In this way, the NPN bipolar transistor and the PNP bipolar transistor can be integrated on the same substrate, and since a depletion layer is formed in the device layer of part of the first base region, the electric field distribution between the first base and the first collector can be made more uniform, which is beneficial to increase the breakdown voltage between the first base region and the first collector region, thereby improving the voltage resistance between the first base region and the first collector region, and further improving the voltage resistance between the first base and the first collector of the PNP bipolar transistor.

[0100] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a device layer is formed, the substrate defining a first emitter region, a first base region, and a first collector region of a PNP bipolar transistor, wherein the first base region is located between the first emitter region and the first collector region, and the substrate defining a second base region of an NPN bipolar transistor, wherein the second base region is spaced apart from the first collector region; Forming a first emitter contact layer, a first collector contact layer, a second base contact layer and a depletion layer, wherein the first emitter contact layer is formed in a device layer in the first emitter region, the first collector contact layer is formed in a device layer in the first collector region, the second base contact layer is formed in a device layer in the second base region, the depletion layer is formed in a device layer in the first base region, and the depletion layer is in contact with the first collector contact layer and spaced apart from the first emitter contact layer, wherein the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions; A first emitter, a first collector and a second base are formed, wherein the first emitter is formed on the top surface of the first emitter contact layer and is electrically connected to the first emitter contact layer, the first collector is formed on the top surface of the first collector contact layer and is electrically connected to the first collector contact layer, and the second base is formed on the top surface of the second base contact layer and is electrically connected to the second base contact layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer comprises: By a first ion implantation process, ion implantation is performed on the device layer in the first emitter region to form the first emitter contact layer, ion implantation is performed on the device layer in the first collector region to form the first collector contact layer, and ion implantation is performed on the device layer in the second base region to form the second base contact layer; By performing at least one second ion implantation process, ion implantation is performed in a device layer of a portion of the first base region to form the depletion layer, and the ion implantation depth of the second ion implantation process is less than the ion implantation depth of the first ion implantation process.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming the first collector, the first emitter and the second base includes: forming a metal material layer, wherein the metal material layer covers the device layer, the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer; The metal material layer is etched using a dry etching process to remove the metal material layer on the device layer and the depletion layer, and the metal material layer on the first emitter contact layer is retained to form the first emitter, and the metal material layer on the first collector contact layer is retained to form the first collector, and the metal material layer on the second base contact layer is retained to form the second base.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The device layer includes a channel layer, a barrier layer and a P-type epitaxial layer stacked in sequence from bottom to top, and after forming the first collector, the first emitter and the second base, further includes: The P-type epitaxial layer is etched by a dry etching process to remove the P-type epitaxial layer between the first emitter contact layer and the first collector contact layer, and to remove the P-type epitaxial layer on both sides of the second base contact layer, wherein the channel layer and the barrier layer between the first emitter contact layer and the first collector contact layer constitute the first base contact layer of the PNP bipolar transistor, the channel layer and the barrier layer of the second base contact layer close to the first collector contact layer constitute the second emitter contact layer of the NPN bipolar transistor, and the channel layer and the barrier layer of the second base contact layer away from the first collector constitute the second collector contact layer of the NPN bipolar transistor.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The material of the channel layer is gallium nitride, the material of the barrier layer is aluminum gallium nitride, and the material of the P-type epitaxial layer is P-type doped gallium nitride.

6. The method for manufacturing a semiconductor device according to claim 4, wherein: After forming the first base contact layer, the second emitter contact layer and the second collector contact layer, the method further includes: forming a passivation layer and a dielectric layer in sequence, the passivation layer covering the first collector, the first emitter, the second base, the first base contact layer, the second collector contact layer, the second emitter contact layer and the depletion layer, and the dielectric layer covering the passivation layer; and, A first base of the PNP bipolar transistor is formed, and a second collector and a second emitter of the NPN bipolar transistor are formed, wherein the first base penetrates the passivation layer and the dielectric layer and is electrically connected to the first base contact layer, the second collector penetrates the passivation layer and the dielectric layer and is electrically connected to the second collector contact layer, and the second emitter penetrates the passivation layer and the dielectric layer and is electrically connected to the second emitter contact layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer comprises: Etching the device layer in the first emitter region to form a first opening, etching the device layer in the first collector region to form a second opening, and etching the device layer in the second base region to form a third opening; Etching the device layer in the first base region to form a fourth opening, wherein the fourth opening is connected to the second opening, and a depth of the fourth opening is less than a depth of the second opening; A selective epitaxial growth process is performed to form the first emitter contact layer in the first opening, the first collector contact layer in the second opening, the second base contact layer in the third opening, and the depletion layer in the fourth opening.

8. A semiconductor device, characterized in that: include: A substrate having a device layer formed thereon, the substrate defining a first emitter region, a first base region, and a first collector region of a PNP bipolar transistor, the first base region being located between the first emitter region and the first collector region, and the substrate defining a second base region of an NPN bipolar transistor, the second base region being spaced apart from the first collector region; a first emitter contact layer formed in the device layer in the first emitter region; a first collector contact layer formed in the device layer in the first collector region; a second base contact layer formed in the device layer in the second base region; A depletion layer is formed in the device layer of the first base region, and the depletion layer is in contact with the first collector contact layer and is separated from the first emitter contact layer, and the first emitter contact layer, the first collector contact layer, the second base contact layer and the depletion layer all have P-type ions; a first collector electrode formed on a top surface of the first collector contact layer and electrically connected to the first collector contact layer; a first emitter formed on a top surface of the first emitter contact layer and electrically connected to the first emitter contact layer; A second base is formed on a top surface of the second base contact layer and is electrically connected to the second base contact layer.

9. The semiconductor device according to claim 8, characterized in that The device layer includes a channel layer and a barrier layer formed on the channel layer, the channel layer and the barrier layer between the first emitter contact layer and the first collector contact layer constitute the first base contact layer of the PNP bipolar transistor, the channel layer and the barrier layer on the side of the second base contact layer close to the first collector contact layer constitute the second emitter contact layer of the NPN bipolar transistor, and the channel layer and the barrier layer on the side of the second base contact layer away from the first collector contact layer constitute the second collector contact layer of the NPN bipolar transistor.

10. The semiconductor device according to claim 9, wherein: The semiconductor device further comprises: a passivation layer and a dielectric layer, wherein the passivation layer covers the first collector, the first emitter, the second base, the first base contact layer, the second collector contact layer, the second emitter contact layer and the depletion layer; A first base, a second collector and a second emitter, the first base penetrates the passivation layer and the dielectric layer and is electrically connected to the first base contact layer, the second collector penetrates the passivation layer and the dielectric layer and is electrically connected to the second collector contact layer, and the second emitter penetrates the passivation layer and the dielectric layer and is electrically connected to the second emitter contact layer.

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