Electrode structure of semiconductor quantum chip and test method

Abstract

The invention discloses an electrode structure of a semiconductor quantum chip and a test method, the electrode structure of the semiconductor quantum chip comprises a source electrode and a drain electrode which are located at two opposite sides of a substrate, and a plurality of grid electrodes, the grid electrodes comprise a first grid electrode and a second grid electrode, the first electrode is used for applying a first direct-current voltage signal to enable a channel below the first grid electrode to form two-dimensional electron gas; the second grid electrode is used for applying a second direct-current voltage signal to adjust the charge density of two-dimensional electron gas in a channel below the second grid electrode so as to form induction quantum dots; the third grid electrode is positioned between the first grid electrode and the second grid electrode and is used for applying a radio frequency signal to read the state of the sensing quantum dot; wherein the first grid electrode and the third grid electrode are provided with overlapped end parts in the vertical direction of the substrate, and an insulating medium layer is formed between the overlapped end parts. According to the invention, the leakage of the measurement signal along the electrode structure of the semiconductor quantum chip is avoided, and the measurement compatibility of the semiconductor quantum chip is improved.

Description

Technical Field

[0001] The present application relates to the field of quantum computer technology, and in particular to an electrode structure and a testing method for a semiconductor quantum chip. Background Art

[0002] Silicon-based spin qubits have been regarded as quantum physical systems that are expected to realize large-scale general-purpose quantum computers in the future due to their advantages such as ultra-long coherence time, nanoscale structural size, solid-state physical system characteristics of all-electrical control, and good compatibility with traditional CMOS manufacturing processes.

[0003] The spin state information of silicon-based spin qubits is indirectly read by using the charge-spin conversion mechanism, with the help of the charge state change in the adjacent single-electron transistor. There are currently two mainstream measurement schemes that are more popular internationally: (1) Traditional transport measurement, which uses the transport current to detect the change of weak resistance signals in the single-electron transistor; (2) RF reflection reading technology, which introduces an "impedance converter" circuit between the single-electron transistor and the measurement reading link, thereby constructing an impedance matching network that can provide real-time feedback on the change of the conductivity state in the single-electron transistor.

[0004] The integration time required for traditional transport measurement of DC resistance is in the millisecond level. In addition, due to the constraints of the DC measurement circuit and the RC circuit composed of the single-electron transistor, the measurement bandwidth is limited to the order of ~10kHz, and the overall reading speed is relatively slow. It will also be affected by the low-frequency 1 / f noise on the measurement system link. The initialization and manipulation waveform scale of silicon-based spin qubits is in the nanosecond or microsecond level, and the technical solutions of traditional transport measurements greatly limit the efficient readout of qubits. The RF reflection reading technology uses an RF signal source as the input carrier signal, and with the help of the resonant circuit of the impedance matching network, it modulates the signal with the impedance or conductance change of the single-electron transistor, and amplifies the signal through a low-noise amplifier and demodulates the room temperature signal, thereby achieving effective signal readout. The evaluation of the initial working state of quantum dots in quantum chips by RF reflection reading technology is far less intuitive and accurate than the traditional transport measurement method.

[0005] Therefore, in actual testing, the above two measurement methods are often required to be used in combination. From the perspective of quantum chip structure design, how to achieve the compatibility of the two has always been a bottleneck problem that is difficult to solve. Summary of the invention

[0006] The present application provides an electrode structure and a testing method for a semiconductor quantum chip, which are used to solve the problem that the electrode structure of the semiconductor quantum chip in the prior art cannot achieve compatibility with two measurement methods of traditional transport measurement and radio frequency reflection reading measurement of quantum dots, thereby avoiding leakage of radio frequency signals along the electrode structure of the semiconductor quantum chip and improving the measurement compatibility of the semiconductor quantum chip.

[0007] In a first aspect, the present application provides an electrode structure of a semiconductor quantum chip, comprising a source electrode and a drain electrode located on opposite sides of a substrate, and a plurality of gate electrodes, wherein the gate electrodes include:

[0008] A first gate, used for applying a first DC voltage signal to form a two-dimensional electron gas in a channel below the first gate;

[0009] A second gate, used for applying a second DC voltage signal to adjust the charge density of the two-dimensional electron gas in the channel below the second gate to form an induction quantum dot;

[0010] A third gate located between the first gate and the second gate, used for applying a radio frequency signal to read the state of the sensing quantum dot;

[0011] The first gate and the third gate extend in opposite directions to form a first extension member and a second extension member. In a vertical extension direction, an end of the first extension member overlaps with an end of the second extension member, and an insulating dielectric layer is formed between the overlapping ends.

[0012] In the electrode structure of the semiconductor quantum chip as described above, preferably, the first gate is formed with the first extension member extending on the substrate in a direction toward the third gate, and the third gate is formed with the second extension member extending on the substrate in a direction toward the first gate;

[0013] Wherein, the first extension piece is above the second extension piece.

[0014] In the electrode structure of the semiconductor quantum chip as described above, preferably, the first gate is formed with the first extension member extending on the substrate in a direction toward the third gate, and the third gate is formed with the second extension member extending on the substrate in a direction toward the first gate;

[0015] Wherein, the first extension piece is below the second extension piece.

[0016] In the electrode structure of the semiconductor quantum chip as described above, preferably, the first gate and the third gate each include a pad located on the substrate and a signal transmission line connected to the pad at one end, and the other end of the signal transmission line extends to the sensing quantum dot region;

[0017] The overlapping end is located at an end of the signal transmission line close to the sensing quantum dot area.

[0018] In the electrode structure of the semiconductor quantum chip as described above, preferably, the area of ​​the overlapping end is not less than 10 square nanometers and not more than 100 square nanometers.

[0019] For the electrode structure of the semiconductor quantum chip as described above, preferably, when the first DC voltage signal applied to the first gate is zero, the resistance of the overlapping end is not less than 10 megohms.

[0020] In the electrode structure of the semiconductor quantum chip as described above, preferably, the impedance of the third gate is smaller than the impedance of the sensing quantum dot.

[0021] In the electrode structure of the semiconductor quantum chip as described above, preferably, the third gate is further used to apply a third DC voltage signal to enable the channel below the third gate to form the two-dimensional electron gas.

[0022] A second aspect of the present application provides a method for testing a semiconductor quantum chip, wherein the semiconductor quantum chip comprises an electrode structure of any of the semiconductor quantum chips described above, and the method comprises:

[0023] Applying the third DC voltage signal through the third gate to form a two-dimensional electron gas in the channel below the third gate;

[0024] Applying the first DC voltage signal through the first gate to form a two-dimensional electron gas in the channel below the first gate;

[0025] Applying the second DC voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induction quantum dot;

[0026] Applying an excitation signal through the drain electrode to form a transport current in the channel and transmit the transport current to the sensing quantum dot;

[0027] The current output by the source is measured to obtain the state of the sensing quantum dot.

[0028] A third aspect of the present application provides a method for testing a semiconductor quantum chip, wherein the semiconductor quantum chip comprises any electrode structure of the semiconductor quantum chip described above, and the method comprises:

[0029] Turn off the signal source electrically connecting the drain and the first gate;

[0030] Applying the second DC voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induction quantum dot;

[0031] Applying the third DC voltage signal through the third gate to form a two-dimensional electron gas in the channel below the third gate;

[0032] The state of the sensing quantum dot is read by applying a radio frequency signal through the third gate. Compared with the prior art, after the electrode of the present application is split into the first gate and the third gate, not only can the traditional transport measurement method be used to read the sensing quantum dot by applying an excitation signal through the drain, at this time, the excitation signal applied to the drain is a voltage signal, and electrons are introduced into the sensing quantum dot region through the two-dimensional electron gas under the first gate and the third gate to form a transport current for reading; it is also possible to read the sensing quantum dot by applying a radio frequency signal through the third gate, at this time, the voltage signal of the drain and the first gate is zero, and the electrode is suspended. An overlapping end separated by an insulating dielectric layer is formed between the first gate and the third gate, so that the first gate and the third gate are in a high-resistance state, and the radio frequency signal cannot leak from the first gate; no matter which reading method is used, there will be no signal leakage, and the compatibility of traditional transport measurement and radio frequency reflection reading technology is achieved.

[0033] The semiconductor quantum chip testing method provided in the present application adopts the electrode structure of the semiconductor quantum chip mentioned above, and therefore has the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of the gate of a semiconductor quantum chip in the prior art;

[0035] Figure 2 A schematic diagram of a gate structure of a semiconductor quantum chip provided in an embodiment of the present application;

[0036] Figure 3 A schematic diagram of the structure of an overlapping end portion provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of another structure of overlapping ends provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the position of an overlapping end portion on a substrate provided in an embodiment of the present application;

[0039] Figure 6 A flow chart of a method for testing a semiconductor quantum chip provided in an embodiment of the present application;

[0040] Figure 7 A flow chart of another method for testing a semiconductor quantum chip provided in an embodiment of the present application.

[0041] In the reference numerals:

[0042] 1-substrate, 2-gate, 3-ohmic electrode, 4-gate, 5-two-dimensional electron gas;

[0043] 11-sensing quantum dot region, 21-first gate, 22-third gate, 23-overlapping end, 31-drain, 32-source, 41-second gate;

[0044] 212 - soldering pad, 213 - signal transmission line, 231 - first extension piece, 232 - second extension piece, 233 - insulating medium layer. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.

[0046] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0048] As attached Figure 1The schematic diagram of reading the gated silicon-based spin quantum bit of the prior art shown in the figure, 1 is the substrate of the semiconductor quantum chip, electrodes 2 and 4 are both gates, electrode 31 represents the drain, electrode 32 represents the source, and 5 represents the two-dimensional electron gas. Specifically, electrode 2 can be used to apply a DC voltage signal to form a two-dimensional electron gas in the channel, and can also be used to apply a radio frequency signal to read the charge state of the quantum dot Q1; electrode 4 is used to apply a DC voltage signal to form the quantum dot Q1 for reading. In addition, an ion injection region is formed under the drain 31 and the source 32, which can be used to apply a DC voltage signal. The charge flows from the drain 31 into the ion injection region, and flows into the sensing quantum dot through the two-dimensional electron gas, and then is output by the source 32 to form a transport current signal to test the sensing quantum dot Q1.

[0049] In addition, in the attached figure, R1 is the equivalent resistance of the ion implantation region, R2 is the equivalent resistance of the two-dimensional electron gas, and C2 is the equivalent parasitic capacitance of the two-dimensional electron gas. Among them, R1, R2, and C2 are all equivalent resistances and capacitors, which are used to characterize the impedance characteristics in the RF signal transmission link.

[0050] The quantum dot Q1 can be read using conventional transport measurement technology, that is, a DC voltage signal is applied to the electrode 4 to form an inductive quantum dot underneath it; a DC voltage signal is applied to the electrode 2 to form a two-dimensional electron gas in the channel, and an excitation signal is applied to the drain 31, and the inductive quantum dot is measured by measuring the change in the current output by the source 32.

[0051] The quantum dot Q1 can also be read using radio frequency reflection reading technology, that is, a DC voltage signal is applied to electrode 4 to form an inductive quantum dot underneath it; a DC voltage signal is applied to electrode 2 to form a two-dimensional electron gas in the channel below electrode 2, and a radio frequency signal is applied to electrode 2 at the same time to read the state of the inductive quantum dot.

[0052] It is conceivable that when performing conventional transport measurement technology, the channel of the single electron transistor needs to be opened to form a transport current; then RF reflection reading is performed, and when an RF signal is applied to the drain 31, the RF signal leaks along the transport channel. A semiconductor quantum chip structure that can achieve compatibility between conventional transport measurement and RF reflection reading is urgently needed.

[0053] Based on this, combined with the Figure 2 and attached Figure 3As shown, the present application proposes an electrode structure of a semiconductor quantum chip, including a drain 31 and a source 32 located on opposite sides of a substrate, and a plurality of gates located between the drain 31 and the source 32, wherein the gates include: a first gate 21, used to apply a first DC voltage signal to form a two-dimensional electron gas in a channel below the first gate 21; a second gate 41, used to apply a second DC voltage signal to adjust the charge density of the two-dimensional electron gas in the channel below the second gate 41 to form an induction quantum dot; a third gate 22 located between the first gate 21 and the second gate 41 is used to apply a radio frequency signal to read the state of the induction quantum dot; wherein the first gate 21 and the third gate 22 extend in relative directions to form a first extension member 231 and a second extension member 232, and in a vertical extension direction, an end of the first extension member 231 overlaps an end of the second extension member 232, and an insulating dielectric layer 233 is formed between the overlapping ends 23.

[0054] In this embodiment, the Figure 1 The electrode 2 used for forming a two-dimensional electron gas in the channel and for applying a radio frequency signal is divided into a first gate 21 and a third gate 22. Specifically, the first gate 21 is used to apply a first DC voltage signal to form a two-dimensional electron gas 5 in the channel below the first gate 21, and the third gate 22 is located between the first gate 21 and the second gate 41, and is used to apply a radio frequency signal to read the state of the sensing quantum dot. The first gate 21 and the third gate 22 are respectively used to apply different types of signals for forming a two-dimensional electron gas 5 in the channel and reading the sensing quantum dot.

[0055] In this embodiment, the drain 31 and the source 32 are located on opposite sides of the substrate, and the first gate 21, the second gate 41, and the third gate 22 are located between the drain 31 and the source 32. Since the second gate 41 is used to apply a voltage signal to form a sensing quantum dot, it is located adjacent to the Figure 2 The combined gate structure is shown in FIG. Figure 1 and attached Figure 2 The gate structure shown in the example only illustrates the reading of one sensing quantum dot; when more sensing quantum dots are integrated on the semiconductor quantum chip and need to be read, the gate structure needs to be set accordingly, which will not be repeated in this embodiment.

[0056] Combined with Figure 2As shown, when the conventional transport measurement method is adopted, a second DC voltage signal is applied to the second gate 41 to form an induction quantum dot in the channel below it; a first DC voltage signal is applied to the first gate 21 to form a two-dimensional electron gas in the channel below it, and an excitation signal is applied to the drain 31, and the measurement of the induction quantum dot is achieved by measuring the change in the current output by the source 32. At this time, the excitation signal applied to the drain 31 is a voltage signal, which cannot leak through the equivalent capacitance C2 channel of the two-dimensional electron gas below the first gate 21 and the third gate 22.

[0057] Combined with Figure 3 As shown, when the RF reflection reading technology is adopted, the first gate 21 and the third gate 22 extend in opposite directions on the substrate 1 to form a first extension piece 231 and a second extension piece 232, and the end of the first extension piece 231 and the end of the second extension piece 232 have overlapping ends 23 in the vertical direction of the extension, and an insulating dielectric layer 233 is formed between the overlapping ends 23, and the insulating dielectric layer 233 makes the first gate 21 and the third gate 22 present a high resistance state and avoids short circuit connection. When the RF signal is applied to the third gate 22 to read the sensing quantum dot, the RF signal cannot leak from the first gate 21; in addition, the resistance value between the third gate 22 and the drain 31 is much greater than the resistance value between the third gate 22 and the first gate 21, and the RF signal will not leak along the path of the drain 31, ensuring that the RF signal can be fully transmitted to the sensing quantum dot, and dissipation is formed in the quantum dot area to achieve measurement of the sensing quantum dot, thereby improving the measurement sensitivity and accuracy.

[0058] Continue as attached Figure 2 As shown, the overlapping end 23 provided between the first gate 21 and the third gate 22 can ensure the continuity of the two-dimensional electron gas in the channel below the first gate 21 and the third gate 22, so that electrons can move from the drain 31 to the source 32 to ensure the flow of transport current.

[0059] In addition, combined with Figure 1 and attached Figure 2 As shown, when using traditional transport measurement, the output channel of the signal source can be electrically connected to the drain 31 of the semiconductor quantum chip to provide an excitation signal, and the measuring device can be electrically connected to the source 32 of the semiconductor quantum chip to measure the output current signal. When using radio frequency reflection reading, the output channel of the microwave source is electrically connected to the third gate 22 of the semiconductor quantum chip to provide a radio frequency signal. In addition, the reflection signal representing the state of the induction quantum dot is also output to the measuring device through the third gate 22; at this time, one port of the coupler can be electrically connected to the third gate 22, and the other ports of the coupler are electrically connected to the microwave source and the measuring device respectively.

[0060] To sum up, after the electrode 2 is split into the first gate 21 and the third gate 22, not only can the excitation signal be applied through the drain 31 to realize the traditional transport measurement method to read the sensing quantum dots, but the radio frequency signal can also be applied through the third gate 22 to realize the reading of the sensing quantum dots. Regardless of which reading method is used, there will be no signal leakage, thus achieving the compatibility of traditional transport measurement and radio frequency reflection reading technology.

[0061] As attached Figure 3 As shown, as an implementation of an embodiment of the present application, the first gate 21 is extended on the substrate 1 in the direction toward the third gate 22 to form the first extension piece 231, and the third gate 22 is extended on the substrate 1 in the direction toward the first gate 21 to form the second extension piece 232; wherein the first extension piece 231 is above the second extension piece 232.

[0062] As attached Figure 4 As shown, as another implementation of the embodiment of the present application, the first gate 21 is extended on the substrate 1 in the direction toward the third gate 22 to form the first extension piece 231, and the third gate 22 is extended on the substrate 1 in the direction toward the first gate 21 to form the second extension piece 232; wherein the first extension piece 231 is below the second extension piece 232.

[0063] When preparing the first gate 21 and the third gate 22 on the substrate 1, it is sufficient that there is an overlapping end 23 between the first extension 231 and the second extension 232, wherein the extension located at the bottom is first prepared, and then the insulating dielectric layer 233 is formed on the surface of the lower extension, and finally the extension located at the top is formed on the surface of the insulating dielectric layer 233. The overlapping end 23 ensures the continuity of the two-dimensional electron gas below, and realizes the flow of the transport current in the channel; and the insulating dielectric layer 233 realizes the high impedance between the first gate 21 and the third gate 22, and realizes the blocking of the leakage of the radio frequency signal.

[0064] As attached Figure 5 As shown, the first gate and the third gate each include a pad 212 located on the substrate and a signal transmission line 213 connected to the pad at one end, and the other end of the signal transmission line 213 extends to the sensing quantum dot region 11; the overlapping end 23 is located at one end of the signal transmission line 213 close to the sensing quantum dot region.

[0065] Attached Figure 5, 1 represents the substrate, 31 represents the drain, 32 represents the source, 11 represents the sensing quantum dot region, which is generally the central region of the substrate 1; 212 represents the pad, and 213 represents the signal transmission line connected to the pad. The first gate and the third gate both include a pad 212 and a signal transmission line 213 connected to the pad 212, and the other end of the signal transmission line 213 is connected to the sensing quantum dot region 11. In addition, the pad of the second gate is also connected to the central region of the substrate 1 through a section of the signal transmission line 213, so as to form a sensing quantum dot in the central region.

[0066] Among them, Figure 5 The overlapping end 23 is located at one end of the signal transmission line 213 close to the sensing quantum dot region 11; the radio frequency signal is applied to the pad 212 of the third gate 22, and is transmitted to the sensing quantum dot region 11 at the center of the substrate 1 through the signal transmission line 213. The high-resistance overlapping end 23 is arranged at one end close to the sensing quantum dot region 11, which can maximize the avoidance of radio frequency signal leakage.

[0067] It is conceivable that if the overlapping end 23 is set on the side close to the pad 212, the radio frequency signal will be transmitted along one end of the signal transmission line 213 in the central area of ​​the substrate 1 toward the pad 212. Even if it is blocked by the overlapping end 23 with a high resistance value on the side close to the pad 212, it will be dissipated when transmitted on the signal transmission line 213, so that the accuracy of the radio frequency signal transmitted to the sensing quantum dot area 11 becomes low, affecting the measurement effect of the sensing quantum dots.

[0068] It should be added that Figure 5 In the schematic diagram of the semiconductor quantum chip, the illustrated pad 212 is generally formed on the outer periphery of the substrate 1 for electrical connection with a signal source or a test circuit. In addition, the drain 31 and the source 32 also have corresponding pads, and the size of the pads is usually in the micron level; the sensing quantum dot region 11 is usually in the central area of ​​the substrate 1, and the pads 212 located on the periphery of the substrate 1 are usually introduced to the vicinity of the sensing quantum dot region 11 through nanoscale signal transmission lines 213.

[0069] In the embodiment of the present application, the area of ​​the overlapping end 23 is not less than 10 square nanometers, and the area of ​​the overlapping end 23 is not greater than 100 square nanometers. The overlapping end 23 is used to realize the connection between the two-dimensional electron gas in the channel below the first gate 21 and the two-dimensional electron gas in the channel below the third gate 22. When the first DC voltage signal and the third DC voltage signal need to be applied to the first gate 21 and the third gate 22 respectively, the two-dimensional electron gas can be formed in the channel below the overlapping end 23. The size of the overlapping end 23 is not easy to be set too large. When the size of the overlapping end 23 is too large, the risk of leakage of the radio frequency signal will increase; in addition, the size of the overlapping end 23 should not be set too small. If it is too small, the two-dimensional electron gas cannot be formed under the overlapping end, so that the two-dimensional electron gas in the channel below the first gate 21 and the third gate 22 is discontinuous and cannot form a transport current. The area used in this embodiment is not less than 10 square nanometers and not greater than 100 square nanometers. After testing and verification, on the one hand, the structure is easy to prepare on the substrate, and on the other hand, high impedance can be ensured.

[0070] Specifically, when the first DC voltage signal applied to the first gate is zero, the resistance of the overlapping end is not less than 10 megohms. The resistance value of 10 megohms is very large, and the radio frequency signal cannot pass through. Compared with the open circuit, the radio frequency signal cannot leak along the overlapping end to the first gate.

[0071] In addition, when the third gate is formed on the substrate, the impedance of the third gate is less than the impedance of the sensing quantum dot. When the RF signal is transmitted, the greater the impedance in the transmission path, the greater the dissipation of the RF signal. The impedance of the third gate is limited to ensure that the RF signal applied by the third gate can be transmitted to the sensing quantum dot as much as possible for measurement.

[0072] In this embodiment, the third gate is not only used to apply a radio frequency signal for reading the sensing quantum dot, but also used to apply a third DC voltage signal to form the two-dimensional electron gas in the channel below the third gate. The two-dimensional electron gas in the channel below the third gate is connected with the two-dimensional electrons in the channel below the first gate, so that the electrons can move from the drain to the source to ensure the flow of the transport current; thus, the radio frequency signal tests the sensing quantum dot through the transport current.

[0073] As attached Figure 6 As shown, based on the same application concept, the embodiment of the present application further provides a method for testing a semiconductor quantum chip, wherein the semiconductor quantum chip includes any electrode structure of the semiconductor quantum chip described above, and the method includes the following steps:

[0074] Step S10: applying a third DC voltage signal through the third gate to form a two-dimensional electron gas in the channel below the third gate.

[0075] Step S11: applying a first DC voltage signal through the first gate to form a two-dimensional electron gas in a channel below the first gate.

[0076] Step S12: applying the second DC voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induction quantum dot.

[0077] Step S13: applying an excitation signal through the drain electrode to form a transport current in the channel and transmit the transport current to the sensing quantum dot.

[0078] Step S14: measuring the current output by the source to obtain the state of the sensing quantum dot.

[0079] By applying the first DC voltage signal and the third DC voltage signal to the first gate and the third gate respectively, a continuous two-dimensional electron gas is formed in the channel below the first gate and the third gate; and a second DC voltage signal is applied to the second gate to form an induction quantum dot; finally, an excitation signal is applied to the drain, wherein the excitation signal is generally also a voltage signal, and the voltage signal causes the electrons in the channel to move from the drain to the source to form a transport current. The state of the induction quantum dot will cause a change in the transport current, and the state of the induction quantum dot can be obtained by testing the current output by the source.

[0080] The electrode of the semiconductor chip to be tested adopts the electrode structure in the embodiment of the present application. The conventional transport measurement method is used for the semiconductor quantum chip with the electrode structure, and the test of the sensing quantum dot can be completed without applying a radio frequency signal to the third gate.

[0081] As attached Figure 7 As shown, based on the same application concept, the embodiment of the present application also provides another method for testing a semiconductor quantum chip, wherein the semiconductor quantum chip includes any electrode structure of the semiconductor quantum chip described above, and the method includes the following steps:

[0082] Step S20: turning off the voltage signal output to the drain and the first gate.

[0083] Step S21: applying the second DC voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induction quantum dot.

[0084] Step S22: applying a third DC voltage signal through the third gate to form a two-dimensional electron gas in the channel below the third gate.

[0085] Step S23: applying a radio frequency signal through the third gate to read the state of the sensing quantum dot.

[0086] The electrode of the semiconductor chip to be tested adopts the electrode structure in the embodiment of the present application. When the semiconductor quantum chip with this electrode structure is read using radio frequency reflection, there is no need to apply a voltage signal to the drain and the first gate. Only a second DC voltage signal is applied to the second gate to form an inductive quantum dot, and a third DC voltage signal is applied to the third gate to ensure that a two-dimensional electron gas is formed at the corresponding position below, thereby ensuring that the applied radio frequency signal can be transmitted to the inductive quantum dot.

[0087] By adopting the electrode structure of the semiconductor quantum chip in this embodiment, the sensing quantum dots can be read by applying an excitation signal through the drain using the traditional transport measurement method, or by applying a radio frequency signal through the third gate to read the sensing quantum dots. Regardless of which reading method is used, there will be no signal leakage, thus achieving compatibility between traditional transport measurement and radio frequency reflection reading technology.

[0088] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0089] The above are only preferred embodiments of the present application and do not have any limiting effect on the present application. Any technical personnel in the relevant technical field, without departing from the scope of the technical solution of the present application, may make any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present application, which shall be deemed as the content of the technical solution of the present application and still fall within the protection scope of the present application.

Claims

1. An electrode structure of a semiconductor quantum chip, characterized in that: The invention comprises a source electrode and a drain electrode located on opposite sides of the substrate, and a plurality of gate electrodes, wherein the gate electrodes include: A first gate, used for applying a first DC voltage signal to form a two-dimensional electron gas in a channel below the first gate; A second gate, used for applying a second DC voltage signal to adjust the charge density of the two-dimensional electron gas in the channel below the second gate to form an induction quantum dot; A third gate located between the first gate and the second gate, used for applying a radio frequency signal to read the state of the sensing quantum dot; The first gate and the third gate extend in opposite directions to form a first extension member and a second extension member. In a vertical extension direction, an end of the first extension member overlaps with an end of the second extension member, and an insulating dielectric layer is formed between the overlapping ends.

2. The electrode structure of the semiconductor quantum chip according to claim 1, characterized in that: The first gate is formed with the first extension member extending on the substrate in a direction toward the third gate, and the third gate is formed with the second extension member extending on the substrate in a direction toward the first gate; Wherein, the first extension piece is above the second extension piece.

3. The electrode structure of the semiconductor quantum chip according to claim 1, characterized in that: The first gate is formed with the first extension member extending on the substrate in a direction toward the third gate, and the third gate is formed with the second extension member extending on the substrate in a direction toward the first gate; Wherein, the first extension piece is below the second extension piece.

4. The electrode structure of the semiconductor quantum chip according to claim 2 or 3, characterized in that: The first gate and the third gate each include a pad located on the substrate and a signal transmission line connected to the pad at one end, and the other end of the signal transmission line extends to the region where the sensing quantum dot is located; The overlapping end is located at one end of the signal transmission line close to the area where the sensing quantum dot is located.

5. The electrode structure of the semiconductor quantum chip according to claim 4, characterized in that: The area of ​​the overlapping end portion is not less than 10 square nanometers and not more than 100 square nanometers.

6. The electrode structure of the semiconductor quantum chip according to claim 1, characterized in that: When the first DC voltage signal applied to the first gate is zero, the resistance of the overlapping end is not less than 10 megohms.

7. The electrode structure of the semiconductor quantum chip according to claim 1, characterized in that: The impedance of the third gate is smaller than the impedance of the sensing quantum dot.

8. The electrode structure of the semiconductor quantum chip according to claim 1, characterized in that: The third gate is further used to apply a third DC voltage signal to enable the channel below the third gate to form the two-dimensional electron gas.

9. A method for testing a semiconductor quantum chip, characterized in that: The semiconductor quantum chip comprises an electrode structure of a semiconductor quantum chip according to any one of claims 1 to 8, and the method comprises: Applying a third DC voltage signal through the third gate to form a two-dimensional electron gas in the channel below the third gate; Applying the first DC voltage signal through the first gate to form a two-dimensional electron gas in the channel below the first gate; Applying the second DC voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induction quantum dot; Applying an excitation signal through the drain electrode to form a transport current in the channel and transmit the transport current to the sensing quantum dot; The current output by the source is measured to obtain the state of the sensing quantum dot.

10. A method for testing a semiconductor quantum chip, characterized in that: The semiconductor quantum chip comprises an electrode structure of a semiconductor quantum chip according to any one of claims 1 to 8, and the method comprises: Turn off the signal source electrically connecting the drain and the first gate; Applying the second DC voltage signal through the second gate to adjust the charge density of the two-dimensional electron gas in the channel to form an induction quantum dot; Applying a third DC voltage signal through the third gate to form a two-dimensional electron gas in the channel below the third gate; A radio frequency signal is applied through the third gate to read the state of the sensing quantum dot.

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