Planar gate power device and method of manufacturing the same

Abstract

The application discloses a planar gate power device, and the device unit comprises a drift region, a planar gate, a channel region, a source region and an anti-JFET region. The anti-JFET region is divided into at least an anti-JFET top layer region and an anti-JFET bottom layer region, and the anti-JFET top layer region is located between the channel regions on both sides of the planar gate. The doping concentration of the anti-JFET top layer region is less than that of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used to reduce the step of the device. The higher doping concentration of the bottom region is used to reduce the specific on-resistance of the device. A first doping layer passes through the source region and the channel region, and the top region of the first doping layer is used to contact the channel region and serve as a channel lead-out region for leading out the channel region; and the bottom region of the first doping layer is used to deplete the anti-JFET bottom layer region, thereby improving the breakdown voltage of the device. The application further discloses a manufacturing method of the planar gate power device. The application can reduce the step of the device, reduce the on-resistance of the device and increase the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a planar gate power device; the present invention also relates to a manufacturing method of the planar gate power device. Background Art

[0002] The most common gate structures for power devices are planar gate and trench gate. Trench gate has a higher channel density and lower on-resistance, but the trench etching process is complex and the etching depth is difficult to control. In addition, the electric field strength at the bottom of the trench is strong. This problem becomes particularly prominent, especially for SiC trench gate MOSFETs, which brings great difficulty to the design. Planar gate MOSFETs have better reliability, but the device has a large pitch. The pitch is the size of a device unit along the arrangement direction of the periodically arranged device units in the active area, for example, the sum of the width of the gate structure of the device unit and the spacing between the gate structures. Therefore, based on the planar gate MOSFET structure, if the pitch can be reduced, the channel density will be increased.

[0003] like Figure 1 FIG. 1 is a schematic diagram of the structure of an existing planar gate MOSFET. Taking an N-type device as an example, the device unit structure of an existing planar gate MOSFET includes:

[0004] A heavily doped N-type substrate 1 is connected to the drain electrode on the back side, which is composed of a backside metal layer. To reduce back diffusion, an arsenic-doped substrate 1 is typically selected. To reduce the resistance of the substrate 1, the doping concentration of the substrate 1 is preferably as high as possible, and the thickness of the substrate 1 is preferably as thin as possible.

[0005] The drift region 2 is composed of a semiconductor epitaxial layer formed on the substrate 1. The doping concentration and thickness of the drift region 2 determine the breakdown voltage of the device. The drift region 2 can be uniformly doped or variably doped.

[0006] The gate conductive material layer 6 is usually composed of N-type heavily doped polysilicon; a gate oxide layer 5 is separated from the gate conductive material layer and the bottom semiconductor epitaxial layer, and the gate oxide layer 5 is usually SiO2; the thickness of the gate oxide layer 5 depends on the breakdown voltage of the device; the thicker the gate oxide layer 5, the higher the breakdown voltage.

[0007] A P-type channel region 3 is formed in the top region of the semiconductor epitaxial layer on both sides of the planar gate, and an N-type heavily doped source region 4 is formed in the surface region of the channel region 3.

[0008] The source region 4 is connected to the source metal, which is composed of the front metal layer 8, through the contact hole 9, i.e., the via (CT). The contact hole corresponding to the source region 4 also contacts the source region 4 and the channel region 3. The position of the contact hole is in the middle of the mesa between the gate structures. In order to ensure that the contact hole and the channel region 3 can form a good ohmic contact, a via implant is usually added below the contact hole to form a heavily doped P-type layer 10. The via implant is usually BF2, the implantation energy is between 10 keV and 50 keV, and the implantation dose is usually between 1e14 cm -2 and 5e15 cm -2 The contact hole 9 penetrates the interlayer film 7.

[0009] In the bottom region of the planar gate, the channel region 3 and the N-type drift region 2 form a depletion region, which makes the conductive region between the channel regions 3 in the bottom region of the planar gate more narrow. In order to reduce the width of the depletion region, an Anti-JFET region 11 is usually added between the channel regions 3. The Anti-JFET region 11 is part of the drift region 2 and serves to increase the doping concentration of the surface of the drift region 2. The Anti-JFET region 11 is formed by increasing the surface doping concentration of the drift region 2 during growth. The typical condition is that the surface doping concentration of the Anti-JFET region 11 is increased by 2 to 6 times compared with the drift region 2 at the bottom of the Anti-JFET region 11, but this brings difficulty to the design of the terminal.

[0010] The Anti-JFET region 11 can also be formed by ion implantation, which is the mainstream process at present. The impurity of the Anti-JFET region 11 is usually phosphorus, and the implantation dose is usually between 1e12 cm -2 and 1e13 cm -2 The ion implantation corresponding to the Anti-JFET region 11 is also called Anti-JFET Implant.

[0011] Compared with the trench gate MOSFET, the pitch of the planar gate MOSFET is larger and the on-resistance is higher, mainly due to the following reasons:

[0012] A. The width of the channel region 3 of the planar gate MOSFET is affected by process fluctuations. The width of the channel region 3 covered by the planar gate is the conductive channel length. We need to ensure that the width of the channel region 3 is still sufficient in the worst case of process, so that the source and the drain do not directly conduct, i.e., the source region 4 and the drift region 2 do not punch through. Therefore, the width of the channel region 3 is determined by the corresponding width in the worst case of process, so the design width of the channel region 3 must be larger, which increases the pitch.

[0013] B.It is generally desirable to have a higher doping concentration of the anti-JFET region 11 to reduce the specific on-resistance. The higher doping concentration of the anti-JFET region 11 results in a stronger depletion of the channel region 3, which affects the width of the channel region 3 and eventually increases the pitch. Therefore, the doping concentration of the anti-JFET region 11 is set to meet the requirements of reducing the pitch and reducing the specific on-resistance. In addition, the high doping concentration of the anti-JFET region 11 reduces the breakdown voltage of the device. SUMMARY

[0014] The technical problem to be solved by the present application is to provide a planar gate power device that can reduce the pitch of the device, reduce the on-resistance of the device, and increase the breakdown voltage of the device. To this end, the present application also provides a manufacturing method of a planar gate power device.

[0015] To solve the above technical problem, the device unit of the planar gate power device provided by the present application comprises:

[0016] a first-conductivity-type doped semiconductor epitaxial layer.

[0017] a planar gate formed on the top surface of the semiconductor epitaxial layer.

[0018] a channel region of a second-conductivity-type doped formed in the semiconductor epitaxial layer on both sides of the planar gate, the channel region also extending into the semiconductor epitaxial layer covered by the planar gate, and the surface of the channel region covered by the planar gate being used to form a conductive channel.

[0019] a first-conductivity-type heavily doped source region formed in the surface region of the channel region on both sides of the planar gate and self-aligned with the side surface of the planar gate.

[0020] a side wall formed on the side surface of the planar gate.

[0021] a first doped layer of a second-conductivity-type heavily doped also formed in the semiconductor epitaxial layer on both sides of the planar gate, the first doped layer being self-aligned with the side surface of the side wall.

[0022] an anti-JFET region of a first-conductivity-type doped formed in the surface region of the semiconductor epitaxial layer, the semiconductor epitaxial layer at the bottom of the anti-JFET region serving as a drift region, and the doping concentration of the anti-JFET region being greater than the doping concentration of the drift region.

[0023] The anti-JFET region is at least divided into an anti-JFET top layer region and an anti-JFET bottom layer region, the anti-JFET top layer region being located between the channel regions on both sides of the planar gate, and the anti-JFET bottom layer region extending below the bottom surface of the channel region.

[0024] The doping concentration of the anti-JFET top layer region is less than that of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used to reduce the depletion of the channel region to increase the effective length of the conductive channel and thereby reduce the step of the device.

[0025] The higher doping concentration of the bottom region is used to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device.

[0026] The first doped layer passes through the source region and the channel region, and the top region of the first doped layer is used to contact the channel region and serve as a channel extraction region for extracting the channel region; the bottom region of the first doped layer is used to deplete the anti-JFET bottom layer region, thereby increasing the breakdown voltage of the device.

[0027] A further improvement is that the channel region and the side surface of the planar gate are self-aligned, and the channel region is formed by angled ion implantation.

[0028] A further improvement is that the planar gate power device includes an active region and a termination region, and the device unit is located in the active region.

[0029] The anti-JFET region is composed of ion implantation regions formed in the active region.

[0030] The ion implantation of the anti-JFET region includes at least two times, and the implantation energy of each ion implantation of the anti-JFET region is different, and the implantation dose of the ion implantation with low implantation energy is lower than that of the ion implantation with high implantation energy.

[0031] A further improvement is that the process conditions of the ion implantation of the anti-JFET region include:

[0032] The implantation energy of the first ion implantation of the anti-JFET region is 40keV-100keV, and the implantation dose is 5e11cm -2 -2e12cm -2 .

[0033] The implantation energy of the second ion implantation of the anti-JFET region is 200keV-600keV, and the implantation dose is 1e12cm -2 -3e12cm -2 .

[0034] A further improvement is that the width of the side wall is 0.2μm-0.6μm.

[0035] A further improvement is that the number of ion implantations of the first doped layer is single or more than twice.

[0036] Further improvement is that the ion implantation of the first doped layer is single time, the ion implantation energy of the first doped layer is 50keV-200keV, the implantation dose is 1e14cm -2 -5e15cm -2 .

[0037] The ion implantation of the first doped layer is two times, the ion implantation energy of the first doped layer is 30keV-80keV, the implantation dose is 5e14cm -2 -5e15cm -2 , the ion implantation energy of the second ion implantation of the first doped layer is 100keV-400keV, the implantation dose is 1e12cm -2 -1e14cm -2 .

[0038] Further improvement is that the ion implantation angle of the channel region is 30-60 degrees.

[0039] The ion implantation of the source region is vertical implantation or angle implantation with an angle less than or equal to 7 degrees.

[0040] Further improvement is that the planar gate power device includes a planar gate power MOSFET, and a first-conductivity-type heavily doped drain region is formed on the back surface of the drift region.

[0041] Further improvement is that the material of the semiconductor epitaxial layer includes Si and SiC.

[0042] To solve the above technical problems, the manufacturing method of the planar gate power device provided by the application includes the following steps:

[0043] A first-conductivity-type doped semiconductor epitaxial layer is provided.

[0044] A first-conductivity-type doped anti-JFET region is formed in the surface region of the semiconductor epitaxial layer of the active region, the semiconductor epitaxial layer at the bottom of the anti-JFET region is used as a drift region, and the doping concentration of the anti-JFET region is greater than that of the drift region; the active region is the formation region of a device unit.

[0045] A planar gate and a second-conductivity-type doped channel region are formed on the top surface of the semiconductor epitaxial layer; the channel region is formed in the semiconductor epitaxial layer on both sides of the planar gate, and the channel region also extends into the semiconductor epitaxial layer in the region covered by the planar gate, and the surface of the channel region covered by the planar gate is used for forming a conductive channel.

[0046] A first conductive type heavily doped source region is formed in the surface region of the channel region on both sides of the planar gate with the side surface of the planar gate as a self-alignment condition.

[0047] The source region and the side surface of the planar gate are self-aligned.

[0048] A side wall is formed on the side surface of the planar gate.

[0049] A second conductive type heavily doped first doped layer is formed in the semiconductor epitaxial layer on both sides of the planar gate with the side surface of the side wall on both sides of the planar gate as a self-alignment condition.

[0050] The anti-JFET region is at least divided into an anti-JFET top layer region and an anti-JFET bottom layer region, the anti-JFET top layer region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom layer region extends below the bottom surface of the channel region.

[0051] The doping concentration of the anti-JFET top layer region is less than the doping concentration of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used to reduce the depletion of the channel region to increase the effective length of the conductive channel and thereby reduce the step of the device.

[0052] The higher doping concentration of the bottom region is used to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device.

[0053] The first doped layer passes through the source region and the channel region, the top region of the first doped layer is used to contact the channel region and serve as a channel extraction region for extracting the channel region, and the bottom region of the first doped layer is used to deplete the anti-JFET bottom layer region, thereby increasing the breakdown voltage of the device.

[0054] A further improvement is that the channel region is formed before or after the formation of the planar gate.

[0055] When the channel region is formed after the formation of the planar gate, it is formed by angled ion implantation with the side surface of the planar gate as a self-alignment condition.

[0056] A further improvement is that the anti-JFET region is formed by ion implantation, and the ion implantation of the anti-JFET region includes at least two times, the implantation energy of each ion implantation of the anti-JFET region is different, and the implantation dose of the ion implantation with low implantation energy is lower than that of the ion implantation with high implantation energy.

[0057] A further improvement is that the process conditions of the ion implantation of the anti-JFET region include:

[0058] The first ion implantation of the anti-JFET region has an implantation energy of 40keV-100keV and an implantation dose of 5e11cm -2 -2e12cm -2 .

[0059] The second ion implantation of the anti-JFET region has an implantation energy of 200keV-600keV and an implantation dose of 1e12cm -2 -3e12cm -2 .

[0060] Further improvement is that the width of the side wall is 0.2-0.6μm.

[0061] Further improvement is that the ion implantation of the first doped layer is single or more than twice.

[0062] Further improvement is that when the ion implantation of the first doped layer is single, the implantation energy of the ion implantation of the first doped layer is 50keV-200keV and the implantation dose is 1e14cm -2 -5e15cm -2 .

[0063] When the ion implantation of the first doped layer is twice, the implantation energy of the first ion implantation of the first doped layer is 30keV-80keV and the implantation dose is 5e14cm -2 -5e15cm -2 , the implantation energy of the second ion implantation of the first doped layer is 100keV-400keV and the implantation dose is 1e12cm -2 -1e14cm -2 .

[0064] Further improvement is that the implantation angle of the ion implantation of the channel region is 30-60 degrees.

[0065] The ion implantation of the source region is vertical implantation or angle implantation with an angle less than or equal to 7 degrees.

[0066] The present application sets the anti-JFET region in layers, and the doping concentration of the top layer of the anti-JFET region is lower than that of the bottom layer of the anti-JFET region. Thus, the anti-JFET effect can be realized through the top layer of the anti-JFET region while avoiding the adverse effect of excessive doping of the top layer of the JFET region on the channel region. Thus, the depletion of the channel region by the anti-JFET region can be reduced, thereby increasing the effective length of the conductive channel, i.e. under the condition that the step of the device remains unchanged, the effective length of the conductive channel is increased, and under the condition that the effective length of the conductive channel remains unchanged, the step of the device is reduced.

[0067] Meanwhile, the doping concentration of the anti-JFET bottom layer region can be increased, since the anti-JFET bottom layer region is located at the bottom region of the channel region, increasing the doping concentration of the anti-JFET bottom layer region will not adversely affect the channel region, so that the specific on-resistance of the device can be reduced by increasing the doping concentration of the anti-JFET bottom layer region, so that the present application overcomes the contradiction in the prior art that the doping concentration of the anti-JFET region is too high to adversely affect the channel region and the doping concentration of the anti-JFET region is too low to adversely affect the specific on-resistance of the device, while achieving the beneficial effects of reducing the step of the device and reducing the specific on-resistance of the device.

[0068] Meanwhile, since the anti-JFET region also belongs to part of the drift region, the increase of the doping concentration of the anti-JFET bottom layer region will affect the voltage resistance of the device, the present application sets the first doping layer, which can deplete the anti-JFET bottom layer region, so that the breakdown voltage of the device remains unchanged or is further increased; at the same time, the first doping layer also serves as a channel lead-out region, which can directly realize Ohmic contact through the contact hole at the top of the back source region, so that it is not necessary to increase the ion implantation of the second conductivity type heavy doping at the bottom of the opening of the contact hole to form a contact hole implantation region. BRIEF DESCRIPTION OF DRAWINGS

[0069] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0070] Figure 1 is a structural schematic diagram of a prior planar gate MOSFET;

[0071] Figure 2 is a structural schematic diagram of a planar gate power device according to an embodiment of the present application;

[0072] Figures 3A-3D is a structural schematic diagram of a planar gate power device according to an embodiment of the present application. DETAILED DESCRIPTION

[0073] As shown in Figure 2 is a structural schematic diagram of a planar gate power device according to an embodiment of the present application; the device unit of the planar gate power device according to the embodiment of the present application includes:

[0074] a first conductivity type doped semiconductor epitaxial layer 32.

[0075] A planar gate is formed on the top surface of the semiconductor epitaxial layer 32. In the embodiment of the present application, the planar gate includes a gate dielectric layer 35 and a gate conductive material layer 36 which are sequentially stacked. In some embodiments, the gate dielectric layer 35 adopts a gate oxide layer, and the gate conductive material layer 36 adopts a polysilicon gate.

[0076] A channel region 33 of the second conductivity type is formed in the semiconductor epitaxial layer 32 on both sides of the planar gate, the channel region 33 also extends into the semiconductor epitaxial layer 32 under the area covered by the planar gate, the surface of the channel region 33 covered by the planar gate is used to form a conductive channel.

[0077] A source region 34 of the first conductivity type is heavily doped in the surface region of the channel region 33 on both sides of the planar gate, the source region 34 and the side surface of the planar gate are self-aligned.

[0078] A side wall 42 is formed on the side surface of the planar gate. In some embodiments, the material of the side wall 42 includes silicon oxide, silicon nitride or silicon oxynitride.

[0079] A first doped layer 40 of the second conductivity type is also formed in the semiconductor epitaxial layer 32 on both sides of the planar gate, the first doped layer 40 and the side surface of the side wall 42 are self-aligned.

[0080] A JFET- resistant region 41 of the first conductivity type is formed in the surface region of the semiconductor epitaxial layer 32, the semiconductor epitaxial layer 32 at the bottom of the JFET- resistant region 41 is used as a drift region, the doping concentration of the JFET- resistant region 41 is greater than that of the drift region.

[0081] The JFET- resistant region 41 is at least divided into a JFET- resistant top layer and a JFET- resistant bottom layer, the JFET- resistant top layer is located between the channel regions 33 on both sides of the planar gate, and the JFET- resistant bottom layer extends below the bottom surface of the channel region 33.

[0082] The doping concentration of the JFET- resistant top layer is less than that of the JFET- resistant bottom layer, the lower doping concentration of the JFET- resistant top layer is used to reduce the depletion of the channel region 33, so as to increase the effective length of the conductive channel and thereby reduce the step of the device.

[0083] The higher doping concentration of the bottom region is used to increase the doping concentration of the entire JFET- resistant region 41 and thereby reduce the specific on-resistance of the device.

[0084] The top region of the first doped layer 40 is used to contact the channel region 33 and serve as a channel lead-out region leading out the channel region 33; the bottom region of the first doped layer 40 is used to deplete the JFET- resistant bottom layer, thereby increasing the breakdown voltage of the device.

[0085] In the embodiment of the present application, the channel region 33 and the side surface of the planar gate are self-aligned, the channel region 33 is formed by ion implantation with an angle, and in this structure, the channel region 33 is formed after the planar gate. In other embodiments, the ion implantation region of the channel region 33 can also be defined by photolithography, and in this case, the channel region 33 is formed before the formation process of the planar gate, and in this structure, the implanted impurities of the channel region 33 will undergo more heat processes, such as the heat process of the formation process of the gate dielectric layer 35 of the planar gate, such as the thermal oxidation process, and this structure is more suitable for the case where the material of the semiconductor epitaxial layer 32 is SiC, because the ion activation temperature of the SiC device is high, and the channel region 33 is formed before the planar gate, which is beneficial to fully activate the channel region 33 by the formation process of the planar gate.

[0086] In the embodiment of the present application, the planar gate power device includes an active region and a terminal region, and the device unit is located in the active region. Generally, the terminal region is surrounded on the peripheral side of the active region, and a guard ring dielectric layer is formed on the surface of the terminal region, and the guard ring dielectric layer is generally field oxide.

[0087] The anti-JFET region 41 is composed of an ion implantation region formed in the active region.

[0088] The ion implantation of the anti-JFET region 41 includes at least two times, the implantation energy of each ion implantation of the anti-JFET region 41 is different, and the implantation dose of the ion implantation with low implantation energy is lower than that of the ion implantation with high implantation energy.

[0089] As an example, the process conditions of the ion implantation of the anti-JFET region 41 include:

[0090] The implantation energy of the first ion implantation of the anti-JFET region 41 is 40keV-100keV, and the implantation dose is 5e11cm -2 -2e12cm -2 .

[0091] The implantation energy of the second ion implantation of the anti-JFET region 41 is 200keV-600keV, and the implantation dose is 1e12cm -2 -3e12cm -2 .

[0092] As an example, the width of the side wall 42 is 0.2μm-0.6μm.

[0093] The number of ion implantations of the first doped layer 40 is single or more than two times.

[0094] When the number of ion implantations of the first doped layer 40 is single, the implantation energy of the ion implantation of the first doped layer 40 is 50keV-200keV, and the implantation dose is 1e14cm -2 -5e15cm-2 .

[0095] When the number of ion implantation of the first doped layer 40 is twice, the first ion implantation of the first doped layer 40 has an implantation energy of 30keV-80keV and an implantation dose of 5e14cm -2 -5e15cm -2 The second ion implantation of the first doped layer 40 has an implantation energy of 100keV-400keV and an implantation dose of 1e12cm -2 -1e14cm -2 .

[0096] As an example, the ion implantation of the channel region 33 has an implantation angle of 30-60 degrees.

[0097] As an example, the ion implantation of the source region 34 is vertical implantation or angled implantation with an angle less than or equal to 7 degrees.

[0098] In the embodiment of the present application, the planar gate power device includes a planar gate power MOSFET, and a first-conductivity-type heavily doped drain region is formed on the back surface of the drift region.

[0099] The semiconductor epitaxial layer 32 is formed on the surface of the semiconductor substrate 31. In some embodiments, the semiconductor substrate 31 is heavily doped with the first conductivity type, and the drain region is directly composed of the thinned semiconductor substrate 31; or the drain region is formed by back surface ion implantation of the thinned semiconductor substrate 31 with the first conductivity type.

[0100] In the embodiment of the present application, the materials of the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are Si. In other embodiments, the materials of the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are SiC.

[0101] In the embodiment of the present application, the top of the source region 34 is also connected to the source electrode composed of the front metal layer 38 through the contact hole, i.e., the via (CT) 39 passing through the interlayer film 37. The via 39 at the top of the source region 34 also passes through the source region 34, and the channel region 33 forms an ohmic contact through the channel lead-out region of the first doped layer 40 and the via 39, and finally connects the channel region 33 and the source region 34 to the source electrode. Figure 1 As shown in the figure, in the embodiment of the present application, the channel lead-out region is directly composed of the first doped layer 40, and does not need to be formed by ion implantation at the bottom of the via 39 additionally.

[0102] The embodiment of the present application sets the anti-JFET region 41 in layers, and the doping concentration of the top layer of the anti-JFET region is lower than that of the bottom layer of the anti-JFET region, so that the anti-JFET effect can be achieved through the top layer of the anti-JFET region while avoiding the adverse effect of excessive doping of the top layer of the anti-JFET region on the channel region 33, so that the depletion of the channel region 33 by the anti-JFET region 41 can be reduced, thereby increasing the effective length of the conductive channel, that is, under the condition that the step of the device remains unchanged, the effective length of the conductive channel is increased, and under the condition that the effective length of the conductive channel remains unchanged, the step of the device is reduced.

[0103] Meanwhile, the doping concentration of the bottom layer of the anti-JFET region of the embodiment of the present application can be increased, and since the bottom layer of the anti-JFET region is located at the bottom region of the channel region 33, increasing the doping concentration of the bottom layer of the anti-JFET region will not adversely affect the channel region 33, so that the specific on-resistance of the device can be reduced by increasing the doping concentration of the bottom layer of the anti-JFET region. Therefore, the embodiment of the present application overcomes the contradiction in the prior art that the high doping concentration of the anti-JFET region 41 adversely affects the channel region 33 and affects the step of the device, and the low doping concentration of the anti-JFET region 41 adversely affects the specific on-resistance of the device, while achieving the beneficial effects of reducing the step of the device and reducing the specific on-resistance of the device.

[0104] Meanwhile, since the anti-JFET region 41 also belongs to part of the drift region, increasing the doping concentration of the bottom layer of the anti-JFET region will affect the voltage resistance of the device, and the embodiment of the present application sets the first doping layer 40, which can deplete the bottom layer of the anti-JFET region, so that the breakdown voltage of the device remains unchanged or is further increased; at the same time, the first doping layer 40 also serves as a channel lead-out region, and the channel lead-out region can directly achieve ohmic contact through the contact hole at the top of the back source region 34, so that it is not necessary to increase the ion implantation of the second conductive type heavy doping at the bottom of the opening of the contact hole to form a contact hole implantation region.

[0105] As shown in Figures 3A to 3D , it is a device structure schematic diagram in each step of the manufacturing method of the planar gate power device of the embodiment of the present application; the manufacturing method of the planar gate power device of the embodiment of the present application comprises the following steps:

[0106] Step S101, as shown in Figure 3A , a first conductive type doped semiconductor epitaxial layer 32 is provided.

[0107] In the method of the embodiment of the present application, the semiconductor epitaxial layer 32 is formed on the top surface of the semiconductor substrate 31.

[0108] In the method of the embodiment, the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are both made of Si. In other embodiments, the semiconductor substrate 31 and the semiconductor epitaxial layer 32 are both made of SiC.

[0109] In step S102, as shown in the figure, an anti-JFET region 41 of the first conductive type is formed in the surface region of the semiconductor epitaxial layer 32 of the active region, the semiconductor epitaxial layer 32 at the bottom of the anti-JFET region 41 serves as a drift region, and the doping concentration of the anti-JFET region 41 is greater than that of the drift region; the active region is the formation region of the device unit. Figure 3A

[0110] In the method of the embodiment, the anti-JFET region 41 is at least divided into an anti-JFET top layer region and an anti-JFET bottom layer region, the anti-JFET top layer region is located between the channel regions 33 on both sides of the planar gate, and the anti-JFET bottom layer region extends below the bottom surface of the channel region 33.

[0111] The doping concentration of the anti-JFET top layer region is less than that of the anti-JFET bottom layer region, and the lower doping concentration of the anti-JFET top layer region is used to reduce the depletion of the channel region 33 to increase the effective length of the conductive channel and thereby reduce the step of the device.

[0112] The higher doping concentration of the bottom region is used to increase the doping concentration of the entire anti-JFET region 41 and thereby reduce the specific on-resistance of the device.

[0113] In the method of the embodiment, the anti-JFET region 41 is formed by ion implantation, and the ion implantation of the anti-JFET region 41 is shown by the arrow line corresponding to the mark 101. The ion implantation of the anti-JFET region 41 includes at least twice, and the implantation energy of each ion implantation of the anti-JFET region 41 is different, and the implantation dose of the ion implantation with low implantation energy is lower than that of the ion implantation with high implantation energy.

[0114] As an example, the process conditions of the ion implantation of the anti-JFET region 41 include:

[0115] The implantation energy of the first ion implantation of the anti-JFET region 41 is 40keV-100keV, and the implantation dose is 5e11cm -2 -2e12cm -2 .

[0116] The implantation energy of the second ion implantation of the anti-JFET region 41 is 200keV-600keV, and the implantation dose is 1e12cm -2 -3e12cm -2 .

[0117] ​As an example, in the case of an N-type device, the implanting impurity of the ion implantation of the JFET region 41 is phosphorus.

[0118] In step S103, as shown in the figure, a planar gate and a channel region 33 of the second conductivity type are formed on the top surface of the semiconductor epitaxial layer 32; the channel region 33 is formed in the semiconductor epitaxial layer 32 on both sides of the planar gate, and the channel region 33 also extends into the semiconductor epitaxial layer 32 covered by the planar gate; the surface of the channel region 33 covered by the planar gate is used to form a conductive channel. Figure 3B

[0119] In the method of the embodiment of the present application, the channel region 33 is formed after the formation of the planar gate, that is, the channel region 33 is formed after the formation of the gate dielectric layer 35 such as a gate oxide layer and the etching of the gate conductive material layer 36; at this time, the formation region of the channel region 33 is directly defined by self-alignment of the side surface of the planar gate. In other embodiment methods, the channel region 33 can also be formed before the formation of the planar gate; for SiC devices, the ion activation temperature is high, and the channel region 33 needs to be formed before the planar gate, which is beneficial to the impurity activation of the channel region 33, but at this time, the implanting region of the channel region 33 needs to be defined by photolithography separately.

[0120] When the channel region 33 is formed after the formation of the planar gate, the channel region 33 is formed by ion implantation with an angle under the condition of self-alignment of the side surface of the planar gate. The ion implantation of the channel region 33 is indicated by the inclined arrow line corresponding to the mark 102.

[0121] The planar gate includes sequentially forming the gate dielectric layer 35 and the gate conductive material layer 36, then forming the hard mask layer 103, performing patterned etching on the hard mask layer 103, and then etching the gate conductive material layer 36 and the gate dielectric layer 35 with the hard mask layer 103 as a mask to form the planar gate.

[0122] As an example, the implanting angle of the ion implantation of the channel region 33 is 30 degrees to 60 degrees. In order to ensure the consistency of the doping concentration of the channel region 33 in different directions, the corresponding wafer of the semiconductor substrate 31 also needs to be rotated; usually, the wafer is rotated 4 times, each time by 90 degrees. As an example of an N-type device, the typical conditions of the ion implantation of the channel region 33 are as follows: the implanting impurity is boron, the implanting energy is between 60 keV and 150 keV, and the implanting dose is between 5e12 cm -2 and 2e13 cm -2 ; the implanting can be performed once or multiple times; if the implanting is performed multiple times, it is more preferred that the implanting energy is low and the dose is low, and the implanting energy is high and the dose is high.

[0123] ​The length of the conductive channel formed in the channel region 33, ie, the channel length, is controlled by the injection angle and the injection energy. This is a self-aligned process that does not require photolithography, thus avoiding the influence of photolithography precision changes on the channel length.

[0124] Step S104: Figure 3C As shown, source regions 34 heavily doped with the first conductivity type are formed in the surface areas of the channel region 33 on both sides of the planar gate under the self-alignment condition of the side surfaces of the planar gate.

[0125] The source region 34 is formed in the surface area of ​​the channel region 33 on both sides of the planar gate and is self-aligned with the side surfaces of the planar gate.

[0126] In the embodiment of the present invention, the ion implantation in the source region 34 is vertical implantation or angled implantation with an implantation angle of less than or equal to 7 degrees. Using an angled implantation of less than or equal to 7 degrees can avoid the channeling effect during the implantation process. Taking an N-type device as an example, the typical conditions for the ion implantation in the source region 34 are that the implanted impurity is Arsenic, the implantation energy is between 30keV and 80keV, and the implantation dose is 1e15 cm -2 ~1e16 cm -2 between.

[0127] Step S105: Figure 3D As shown, sidewalls 42 are formed on the sides of the planar grid.

[0128] In the method of the embodiment of the present invention, the sidewall spacer 42 is formed by first depositing a sidewall material layer and then fully etching the sidewall material layer. The sidewall material layer retained on the side of the planar gate serves as the sidewall spacer 42, and the sidewall spacer 42 is self-aligned and formed on the side of the planar gate.

[0129] As an example, the width of the spacer 42 is 0.2 μm to 0.6 μm.

[0130] Step S106: Figure 3D As shown, a first doped layer 40 heavily doped with the second conductivity type is formed in the semiconductor epitaxial layer 32 on both sides of the planar gate using the sidewalls 42 on both sides of the planar gate as a self-aligned condition. The ion implantation of the first doped layer 40 is marked with arrows corresponding to marker 105.

[0131] The first doped layer 40 passes through the source region 34 and the channel region 33. The top area of ​​the first doped layer 40 is used to contact the channel region 33 and serve as a channel lead-out region for leading out the channel region 33. The bottom area of ​​the first doped layer 40 is used to deplete the bottom area of ​​the JFET, thereby increasing the breakdown voltage of the device.

[0132] In the method of the embodiment of the present invention, the number of ion implantations in the first doping layer 40 is one or more than two times.

[0133] As an example, when the number of ion implantation of the first doping layer 40 is single, the implantation energy of the ion implantation of the first doping layer 40 is 50keV-200keV, the implantation dose is 1e14cm -2 -5e15cm -2 .

[0134] As an example, when the number of ion implantation of the first doping layer 40 is two, the implantation energy of the first ion implantation of the first doping layer 40 is 30keV-80keV, the implantation dose is 5e14cm -2 -5e15cm -2 , the implantation energy of the second ion implantation of the first doping layer 40 is 100keV-400keV, the implantation dose is 1e12cm -2 -1e14cm -2 . In order to make the first doping layer 40 better with the depletion of the JFET region 41, reduce the electric field intensity of the surface of the gate dielectric layer 35, the high-energy implant of the first doping layer 40 can use angle implantation.

[0135] As an example, taking N-type device as an example, the implanting impurity of the ion implantation of the first doping layer 40 is Boron.

[0136] The above has carried out the detailed description to the present application through specific embodiments, but these do not constitute the limitation to the present application. In the case of not departing from the principle of the present application, the person skilled in the art can also make many deformation and improvement, these also should be regarded as the protection scope of the present application.

Claims

1. A planar gate power device, characterized in that: The device unit includes: a semiconductor epitaxial layer doped with a first conductivity type; A planar gate is formed on the top surface of the semiconductor epitaxial layer; A channel region doped with a second conductivity type is formed in the semiconductor epitaxial layer on both sides of the planar gate, and the channel region further extends into the semiconductor epitaxial layer in the area covered by the planar gate, and the surface of the channel region covered by the planar gate is used to form a conductive channel; A source region heavily doped with a first conductivity type is formed in the surface area of ​​the channel region on both sides of the planar gate, and the source region and the side surface of the planar gate are self-aligned; A side wall is formed on the side of the planar grid; A first doped layer heavily doped with a second conductivity type is further formed in the semiconductor epitaxial layer on both sides of the planar gate, and the first doped layer is self-aligned with the side surface of the spacer; An anti-JFET region doped with a first conductive type is formed in a surface region of the semiconductor epitaxial layer, the semiconductor epitaxial layer at the bottom of the anti-JFET region serves as a drift region, and the doping concentration of the anti-JFET region is greater than the doping concentration of the drift region; The anti-JFET region is divided into at least an anti-JFET top region and an anti-JFET bottom region, wherein the anti-JFET top region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region; The doping concentration of the anti-JFET top region is lower than the doping concentration of the anti-JFET bottom region, and the lower doping concentration of the anti-JFET top region is used to reduce depletion of the channel region, so as to increase the effective length of the conductive channel and thereby reduce the stepping of the device; The higher doping concentration of the anti-JFET bottom region is used to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device; The first doped layer passes through the source region and the channel region, the top region of the first doped layer is used to contact the channel region and serve as a channel lead-out region for leading out of the channel region; the bottom region of the first doped layer is used to deplete the bottom region of the anti-JFET, thereby increasing the breakdown voltage of the device; The anti-JFET region is composed of an ion implantation region; The ion implantation in the anti-JFET region includes at least two times, the implantation energies of the ion implantations in the anti-JFET region are different, and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy.

2. The planar gate power device according to claim 1, wherein: The channel region and the side surface of the planar gate are self-aligned, and the channel region is formed by angled ion implantation.

3. The planar gate power device according to claim 2, wherein: The planar gate power device comprises an active region and a terminal region, wherein the device unit is located in the active region; The anti-JFET region is an ion implantation region formed in the active region.

4. The planar gate power device according to claim 3, wherein: The process conditions for ion implantation in the anti-JFET region include: The first ion implantation in the anti-JFET region has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 ; The second ion implantation in the anti-JFET region has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

5. The planar gate power device according to claim 1, wherein: The width of the sidewall is 0.2 μm to 0.6 μm.

6. The planar gate power device according to claim 1, wherein: The number of times of ion implantation into the first doping layer is one time or two times or more.

7. The planar gate power device according to claim 6, wherein: When the number of ion implantations of the first doping layer is single, the implantation energy of the ion implantations of the first doping layer is 50keV to 200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 ; When the number of ion implantations of the first doping layer is 2, the implantation energy of the first ion implantation of the first doping layer is 30keV to 80keV, and the implantation dose is 5e14cm -2 ~5e15cm -2 The second ion implantation energy of the first doping layer is 100keV to 400keV, and the implantation dose is 1e12cm -2 ~1e14cm -2 .

8. The planar gate power device according to claim 1, wherein: The ion implantation angle of the channel region is 30 to 60 degrees; The ion implantation in the source region is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

9. The planar gate power device according to claim 1, wherein: The planar gate power device comprises a planar gate power MOSFET, wherein a drain region heavily doped with a first conductive type is formed on the back side of the drift region.

10. The planar gate power device according to claim 1, wherein: The material of the semiconductor epitaxial layer includes Si and SiC.

11. A method for manufacturing a planar gate power device, characterized in that: The steps include: providing a semiconductor epitaxial layer doped with a first conductivity type; An anti-JFET region doped with a first conductive type is formed in a surface region of the semiconductor epitaxial layer in the active region, the semiconductor epitaxial layer at the bottom of the anti-JFET region serves as a drift region, and the doping concentration of the anti-JFET region is greater than the doping concentration of the drift region; the active region is a formation region of a device unit; the anti-JFET region is formed by ion implantation, the ion implantation of the anti-JFET region includes at least two times, the implantation energies of the ion implantations of the anti-JFET region are different, and the implantation dose of the ion implantation with low implantation energy is lower than the implantation dose of the ion implantation with high implantation energy; A planar gate and a second conductive type doped channel region are formed on the top surface of the semiconductor epitaxial layer; the channel region is formed in the semiconductor epitaxial layer on both sides of the planar gate, and the channel region also extends into the semiconductor epitaxial layer in the area covered by the planar gate, and the surface of the channel region covered by the planar gate is used to form a conductive channel; forming a heavily doped source region of the first conductivity type in the surface area of ​​the channel region on both sides of the planar gate using the side surfaces of both sides of the planar gate as a self-alignment condition; The source region is formed in the surface area of ​​the channel region on both sides of the planar gate and the side surfaces of the source region and the planar gate are self-aligned; A side wall is formed on the side of the planar grid; forming a heavily doped first layer of the second conductivity type in the semiconductor epitaxial layer on both sides of the planar gate using the side surfaces of the spacers on both sides of the planar gate as a self-alignment condition; The anti-JFET region is divided into at least an anti-JFET top region and an anti-JFET bottom region, wherein the anti-JFET top region is located between the channel regions on both sides of the planar gate, and the anti-JFET bottom region extends below the bottom surface of the channel region; The doping concentration of the anti-JFET top region is lower than the doping concentration of the anti-JFET bottom region, and the lower doping concentration of the anti-JFET top region is used to reduce depletion of the channel region, so as to increase the effective length of the conductive channel and thereby reduce the stepping of the device; The higher doping concentration of the anti-JFET bottom region is used to increase the doping concentration of the entire anti-JFET region and thereby reduce the specific on-resistance of the device; The first doped layer passes through the source region and the channel region, and the top area of ​​the first doped layer is used to contact the channel region and serve as a channel lead-out area for leading out the channel region; the bottom area of ​​the first doped layer is used to deplete the anti-JFET bottom area, thereby increasing the breakdown voltage of the device.

12. The method for manufacturing a planar gate power device according to claim 11, wherein: The channel region is formed before or after the planar gate is formed; When the channel region is formed after the planar gate is formed, angled ion implantation is performed with the side of the planar gate as a self-aligned condition.

13. The method for manufacturing a planar gate power device according to claim 12, wherein: The process conditions for ion implantation in the anti-JFET region include: The first ion implantation in the anti-JFET region has an implantation energy of 40keV to 100keV and an implantation dose of 5e11cm -2 ~2e12cm -2 ; The second ion implantation in the anti-JFET region has an implantation energy of 200keV to 600keV and an implantation dose of 1e12cm -2 ~3e12cm -2 .

14. The method for manufacturing a planar gate power device according to claim 11, wherein: The width of the sidewall is 0.2 μm to 0.6 μm.

15. The method for manufacturing a planar gate power device according to claim 11, wherein: The number of times of ion implantation into the first doping layer is one time or two times or more.

16. The method for manufacturing a planar gate power device according to claim 15, wherein: When the number of ion implantations of the first doping layer is single, the implantation energy of the ion implantations of the first doping layer is 50keV to 200keV, and the implantation dose is 1e14cm -2 ~5e15cm -2 ; When the number of ion implantations of the first doping layer is 2, the implantation energy of the first ion implantation of the first doping layer is 30keV to 80keV, and the implantation dose is 5e14cm -2 ~5e15cm -2 The second ion implantation energy of the first doping layer is 100keV to 400keV, and the implantation dose is 1e12cm -2 ~1e14cm -2 .

17. The method for manufacturing a planar gate power device according to claim 11, wherein: The ion implantation angle of the channel region is 30 to 60 degrees; The ion implantation in the source region is vertical implantation or angled implantation with an implantation angle less than or equal to 7 degrees.

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