Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes: a semiconductor body, including a well region, a first region and a second region; the first region is located on the first surface, and the well region is located on the side of the first region away from the first surface; the first surface is also provided with a gate groove and a source groove; the second region surrounds the bottom surface and sidewall of the source groove; the trench gate is located on the side of the insulating layer in the gate groove away from the semiconductor body; the source groove structure includes a filling layer located in the source groove; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is less than the ohmic contact resistance when the metal titanium forms an ohmic contact with the semiconductor body; and at the annealing temperature of the ohmic contact layer, there is no chemical reaction intermediate product between the filling layer and the ohmic contact layer. The technical solution provided by the embodiment of the present invention improves the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a third-generation wide-bandgap semiconductor represented by silicon carbide, has excellent characteristics such as wide bandgap, high critical breakdown electric field, high electron saturation mobility and high thermal conductivity, and has become a research hotspot for power semiconductor devices.

[0003] like Figure 1 As shown, Figure 1 It is a structural schematic diagram of a dual-trench MOSFET semiconductor device provided by the prior art. In the current dual-trench MOSFET semiconductor device, in the source trench structure 300, the filling layer 302 located in the source trench T2 and in contact with the ohmic contact layer 303 and the trench gate 202 located in the gate trench T1 are made of the same material, and the trench gate 202 usually includes semiconductor material polysilicon. In order to form a good ohmic contact between the ohmic contact layer 303 and the second region 105, the semiconductor device is usually annealed. During the annealing process, the semiconductor device needs to be heated to a certain temperature, maintained for a sufficient time, and then cooled at an appropriate speed. During the annealing process, the ohmic contact layer 303 and the trench gate 202 are separated by an interlayer insulating layer 203, while the filling layer 302 and the ohmic contact layer 303 are in direct contact. When the filling layer 302 and the trench gate 202 are made of the same material, the trench gate 202 usually includes semiconductor material polysilicon, and the ohmic contact layer 303 usually includes metal titanium or titanium compounds. The ohmic contact resistance is relatively large, resulting in poor electrical performance of the semiconductor device. Figure 1 The figure marks in the figure are explained as follows: 100-semiconductor body; 101-first surface; 102-second surface; 103-well region; 104-first region; 105-second region; T1-gate trench; T2-source trench; 201-insulating layer; 202-trench gate; 203-interlayer insulating layer; 300-source trench structure; 301-source insulating layer; 302-filling layer; 303-ohmic contact layer; 304-source; 400-drain. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to improve the electrical performance of the semiconductor device.

[0005] In a first aspect, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first area and a second area; the first area is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first area away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench extends from the first surface into the semiconductor body, and the source trench extends from the first surface into the semiconductor body; the second area is set to a second conductivity type and surrounds the bottom surface and side walls of the source trench; the semiconductor body further comprises an insulating layer, the insulating layer is located on the bottom surface and side walls of the gate trench;

[0007] A trench gate, wherein the trench gate is located in the gate trench on a side of the insulating layer away from the semiconductor body; the insulating layer is used to insulate the semiconductor body and the trench gate;

[0008] A source trench structure, the source trench structure comprising a filling layer, the filling layer being located in the source trench;

[0009] An ohmic contact layer, the ohmic contact layer is located on the first surface; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is less than the ohmic contact resistance when metal titanium forms an ohmic contact with the semiconductor body; and at the annealing temperature of the ohmic contact layer, there is no chemical reaction intermediate product between the filling layer and the ohmic contact layer;

[0010] a source electrode, the source electrode being located at a side of the ohmic contact layer away from the first surface;

[0011] A drain electrode is located on the second surface.

[0012] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0013] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first area and a second area; the first area is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first area away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench extends from the first surface into the semiconductor body, and the source trench extends from the first surface into the semiconductor body; the second area is set to a second conductivity type and surrounds the bottom surface and side walls of the source trench; the semiconductor body further comprises an insulating layer, the insulating layer is located on the bottom surface and side walls of the gate trench;

[0014] A trench gate is formed in the gate trench on a side of the insulating layer away from the semiconductor body; the insulating layer is used to insulate the semiconductor body and the trench gate;

[0015] forming a source trench structure in the source trench, wherein the source trench structure comprises a filling layer;

[0016] An ohmic contact layer is formed on the first surface; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is less than the ohmic contact resistance when metal titanium forms ohmic contact with the semiconductor body; and at the annealing temperature of the ohmic contact layer, there is no chemical reaction intermediate product between the filling layer and the ohmic contact layer;

[0017] forming a source electrode on a side of the ohmic contact layer away from the first surface;

[0018] A drain electrode is formed on the second surface.

[0019] In a third aspect, the present invention provides a power module, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is used to carry the semiconductor device.

[0020] In a fourth aspect, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0021] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0022] In a fifth aspect, the present invention provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0023] The semiconductor device and manufacturing method, power module, power conversion circuit and vehicle provided by the embodiment of the present invention have an ohmic contact resistance between the ohmic contact layer and the semiconductor body that is less than the ohmic contact resistance when metal titanium forms an ohmic contact with the semiconductor body, thereby reducing the contact resistance and the on-resistance of the semiconductor device. Moreover, at the annealing temperature of the ohmic contact layer, the chemical stability between the filling layer and the ohmic contact layer is higher than the chemical stability between metal nickel and polysilicon, that is, at the annealing temperature of the ohmic contact layer, it is more difficult for the filling layer and the ohmic contact layer to react chemically than metal nickel and polysilicon, thereby avoiding the ohmic contact layer from consuming the filling layer during its annealing process, and avoiding the problem of the filling layer being consumed too quickly by the ohmic contact layer, thereby improving the performance of the semiconductor device. There is no need to set the ohmic contact layer to a material with stable chemical properties but large ohmic contact resistance, such as metal titanium or titanium compound, and a material that can form a good ohmic contact with the second region can be selected as the ohmic contact layer, thereby helping to improve the performance of the semiconductor device.

[0024] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0027] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0028] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0029] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0030] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0031] Figure 6 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0032] Figure 7-Figure 15 It is a structural schematic diagram corresponding to each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of "including" and "having" are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or structures that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] In order to improve the electrical performance of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0036] like Figure 2 As shown, Figure 21 is a schematic diagram of a structure of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further comprises a well region 103, a first region 104 and a second region 105; the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is further provided with a gate trench T1 and a source trench T2, the gate trench T1 extends from the first surface 101 into the semiconductor body 100, and the source trench T2 extends from the first surface 101 into the semiconductor body 100; the second region 105 is set to a second conductivity type and surrounds the bottom surface and sidewalls of the source trench T2; the semiconductor body 100 further comprises an insulating layer 201, the insulating layer 201 Located on the bottom surface and sidewall of the gate trench T1; a trench gate 202, the trench gate 202 is located on the side of the insulating layer 201 in the gate trench T1 away from the semiconductor body 100; the insulating layer 201 is used to insulate the semiconductor body 100 and the trench gate 202; a source trench structure 300, the source trench structure 300 includes a filling layer 302, and the filling layer 302 is located in the source trench T2; an ohmic contact layer 303, located on the first surface 101; the ohmic contact resistance between the ohmic contact layer 303 and the semiconductor body 100 is less than the ohmic contact resistance when the metal titanium forms an ohmic contact with the semiconductor body 100; and at the annealing temperature of the ohmic contact layer 303, there is no chemical reaction intermediate product between the filling layer 302 and the ohmic contact layer 303; a source 304, located on the side of the ohmic contact layer 303 away from the first surface 101; a drain 400, the drain 400 is located on the second surface 102.

[0037] In an embodiment of the present invention, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0038] The MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking the N-type MOSFET semiconductor device as an example, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the second region 105 is a P+ doped region, and the well region 103 is a P-well region.

[0039] Among them, the interlayer insulating layer 203 is used to insulate the gate trench T1 and the ohmic contact layer 303. After careful research, the inventor found that when polysilicon is selected as the filling layer 302, a material that can form a good ohmic contact with the semiconductor material, such as metal Ni, is selected as the ohmic contact layer 303. Metal Ni will react with the silicon in the filling layer 302 at high temperature to generate a chemical reaction intermediate with low thermal stability, causing the filling layer 302 to be consumed too quickly, resulting in poor electrical performance of the semiconductor device. If a material with stable chemical properties, such as metal titanium or titanium compounds, is selected as the ohmic contact layer 303, the chemical reaction intermediate formed by the ohmic contact layer 303 and the silicon in the filling layer 302 has high thermal stability, but the contact resistance is too large.

[0040] In the semiconductor device provided by the embodiment of the present invention, the ohmic contact resistance between the ohmic contact layer 303 and the semiconductor body 100 is less than the ohmic contact resistance when the metal titanium forms an ohmic contact with the semiconductor body 100, thereby reducing the contact resistance and the on-resistance of the semiconductor device. Moreover, at the annealing temperature of the ohmic contact layer 303, there is no chemical reaction intermediate product between the filling layer 302 and the ohmic contact layer 303, thereby avoiding the ohmic contact layer 303 from consuming the filling layer 302 during its annealing process, avoiding the problem of the filling layer 302 being consumed too quickly by the ohmic contact layer 303, thereby improving the performance of the semiconductor device. Moreover, there is no need to set the ohmic contact layer 303 to a material with stable chemical properties but large ohmic contact resistance, such as metal titanium or titanium compound, and a material that can form a good ohmic contact with the second region 105 can be selected as the ohmic contact layer 303, thereby helping to improve the performance of the semiconductor device.

[0041] Optionally, based on the above technical solution, Figure 2 As shown, the ohmic contact layer 303 includes any one or a combination of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al.

[0042] Specifically, any one of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al, or a combination thereof, can form a good ohmic contact with the second region 105, and the ohmic contact resistance is relatively small, thereby improving the performance of the semiconductor device.

[0043] Optionally, based on the above technical solution, Figure 2 As shown, the filling layer 302 includes any one of silicon nitride, silicon oxide, carbon and silicon oxynitride or a combination thereof.

[0044] like Figure 2 As shown, the filling layer 302 includes silicon nitride. Figure 3 As shown, Figure 3 3 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, wherein the filling layer 302 includes silicon oxynitride. Figure 4 As shown, Figure 4 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, wherein the filling layer 302 includes silicon oxide.

[0045] Specifically, any one of silicon nitride, silicon oxide, carbon and silicon oxynitride or a combination thereof is an insulating material, and unlike polysilicon, it is not a semiconductor material. This can ensure that during the annealing process of the ohmic contact layer 303, there are no chemical reaction intermediates between the filling layer 302 and the ohmic contact layer 303, and the ohmic contact layer 303 can be prevented from consuming the filling layer 302 during its annealing process, thereby avoiding the problem of the filling layer 302 being consumed too quickly by the ohmic contact layer 303, thereby further improving the performance of the semiconductor device.

[0046] Optionally, based on the above technical solution, Figure 2 As shown, the width W1 of the source trench T2 is smaller than the width W2 of the gate trench T1 .

[0047] Specifically, the width W1 of the source trench T2 is smaller than the width W2 of the gate trench T1, and the width W1 of the source trench T2 is greater than or equal to the width W2 of the gate trench T1, so that the source trench structure 300 can reduce the on-resistance of the semiconductor device while reducing the peak electric field effect of the bottom insulating layer of the trench gate 202.

[0048] Optionally, based on the above technical solution, Figure 2-Figure 4 As shown, an air gap 305 is provided in the filling layer 302 .

[0049] Specifically, when the aspect ratio of the source trench T2 is larger, during the formation of the source trench T2, before the inside of the source trench T2 is filled with the filling layer 302, the opening of the source trench T2 has been sealed by the filling layer 302, thereby forming an air gap 305 in the filling layer 302.

[0050] Optionally, based on the above technical solution, Figure 2-Figure 4 As shown, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0051] Specifically, the semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0052] Optionally, on the basis of the above technical solution, a plurality of source trenches T2 are arranged on one side of the gate trench T1, and the source trench structure 300 and the source trenches T2 are arranged in one-to-one correspondence.

[0053] For example, Figure 5 As shown, Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, in which two source trenches T2 are arranged on one side of the gate trench T1.

[0054] Specifically, the more source trenches T2 are set on one side of the gate trench T1, the larger the area of ​​the semiconductor body 100 occupied by the source trench structure 300 in a unit cell of a MOSFET semiconductor device, and the more significant the effect of the source trench structure 300 on reducing the peak electric field of the bottom insulating layer of the trench gate 202.

[0055] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 6 As shown, Figure 6 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figure 2 Taking the semiconductor device shown in FIG. 1 as an example, the manufacturing method of the semiconductor device includes the following steps:

[0056] S110, providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first region, and a second region; the first region is set to be of a first conductivity type and is located on the first surface, and the well region is set to be of a second conductivity type and is located on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench extends from the first surface into the semiconductor body, and the source trench extends from the first surface into the semiconductor body; the second region is set to be of a second conductivity type and surrounds the bottom surface and sidewalls of the source trench. The semiconductor body further comprises an insulating layer, and the insulating layer is located on the bottom surface and sidewalls of the gate trench.

[0057] like Figure 7As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 that are oppositely arranged; the semiconductor body 100 also includes a well region 103 and a first region 104; the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101.

[0058] like Figure 8 As shown, a gate trench T1 and a source trench T2 are formed on the first surface by photolithography and etching processes. The gate trench T1 extends from the first surface 101 into the semiconductor body 100, and the source trench T2 extends from the first surface 101 into the semiconductor body 100. A second region 105 is formed on the bottom surface and sidewall of the source trench T2, and the second region 105 is set to the second conductivity type.

[0059] In an embodiment of the present invention, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0060] The MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking the N-type MOSFET semiconductor device as an example, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the second region 105 is a P+ doped region, and the well region 103 is a P-well region.

[0061] S120, forming a trench gate on a side of the insulating layer in the gate trench away from the semiconductor body; the insulating layer is used to insulate the semiconductor body and the trench gate.

[0062] S130 , forming a source trench structure in the source trench, wherein the source trench structure includes a filling layer.

[0063] S140, forming an ohmic contact layer on the first surface; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is less than the ohmic contact resistance when metal titanium forms ohmic contact with the semiconductor body; and at the annealing temperature of the ohmic contact layer, there is no chemical reaction intermediate product between the filling layer and the ohmic contact layer.

[0064] S150 , forming a source electrode on a side of the ohmic contact layer away from the first surface.

[0065] S160, forming a drain on the second surface.

[0066] Figure 9-Figure 15 The schematic diagram of the structure of S120 - S150 and the schematic diagram of the structure of forming the insulating layer 201 on the bottom surface and the side wall of the gate trench T1 are shown.

[0067] like Fig. 9 As shown, a filling layer 302 is formed in the gate trench T1 , the source trench T2 and the first surface 101 by a deposition process.

[0068] like Fig.10 As shown, the first surface 101 and the filling layer 302 of the gate trench T1 may be removed by a wet etching process.

[0069] like Fig.11 As shown, an insulating layer 201 is formed on the bottom surface and sidewalls of the gate trench T1 and the first surface 101 .

[0070] like Fig.12 As shown, in the gate trench T1 , a trench gate 202 is formed on the surface of the insulating layer 201 , and the insulating layer 201 is used to insulate the semiconductor body 100 and the trench gate 202 .

[0071] like Fig.13 As shown, the insulating layer 201 on the first surface 101 is removed, and an interlayer insulating layer 203 is formed. The interlayer insulating layer 203 is used to insulate the trench gate 202 and the subsequently formed ohmic contact layer 303 .

[0072] like Fig.14 As shown, an ohmic contact layer 303 is formed on the first surface 101. At the annealing temperature of the ohmic contact layer 303, there is no chemical reaction intermediate product between the filling layer 302 and the ohmic contact layer 303.

[0073] like Fig.15 As shown, a source electrode 304 is formed on a side of the ohmic contact layer 303 away from the first surface 101 .

[0074] like Figure 2 As shown, a drain electrode 400 is formed on the second surface 102. The drain electrode 400 may include a stack of metal Ti, metal Ni, and metal Ag.

[0075] In the semiconductor device provided by the embodiment of the present invention, the ohmic contact resistance between the ohmic contact layer 303 and the semiconductor body 100 is less than the ohmic contact resistance when the metal titanium forms an ohmic contact with the semiconductor body 100, thereby reducing the contact resistance and the on-resistance of the semiconductor device. Moreover, at the annealing temperature of the ohmic contact layer 303, there is no chemical reaction intermediate between the filling layer 302 and the ohmic contact layer 303, thereby avoiding the consumption of the filling layer 302 by the ohmic contact layer 303 during its annealing process, avoiding the problem of the filling layer 302 being consumed too quickly by the ohmic contact layer 303, thereby improving the performance of the semiconductor device. There is no need to set the ohmic contact layer 303 to a material with stable chemical properties but large ohmic contact resistance, such as metal titanium or titanium compound, and a material that can form a good ohmic contact with the second region 105 can be selected as the ohmic contact layer 303, thereby helping to improve the performance of the semiconductor device.

[0076] Optionally, based on the above technical solution, S140 forming an ohmic contact layer on the first surface includes:

[0077] An ohmic contact layer including any one of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al or a combination thereof is formed on the first surface.

[0078] like Fig.14 As shown, an ohmic contact layer 303 including any one of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al or a combination thereof is formed on the first surface 101 .

[0079] Specifically, any one of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al, or a combination thereof, can form a good ohmic contact with the second region 105, and the ohmic contact resistance is relatively small, thereby improving the performance of the semiconductor device.

[0080] Optionally, based on the above technical solution, S130 filling the source trench with a layer includes:

[0081] A filling layer including any one of silicon nitride, silicon oxide, carbon and silicon oxynitride or a combination thereof is formed in the source trench.

[0082] like Fig.10 As shown, a filling layer 302 including any one or a combination of silicon nitride, silicon oxide, carbon and silicon oxynitride is formed in the source trench T2. Exemplarily, Fig.10 In the embodiment, the filling layer 302 includes silicon nitride. Figure 3As shown, the filling layer 302 includes silicon oxynitride. Figure 4 As shown, fill layer 302 includes silicon oxide.

[0083] Specifically, any one of silicon nitride, silicon oxide, carbon and silicon oxynitride or a combination thereof is an insulating material, and unlike polysilicon, it is not a semiconductor material. This can ensure that during the annealing process of the ohmic contact layer 303, there are no chemical reaction intermediates between the filling layer 302 and the ohmic contact layer 303, and the ohmic contact layer 303 can be prevented from consuming the filling layer 302 during its annealing process, thereby avoiding the problem of the filling layer 302 being consumed too quickly by the ohmic contact layer 303, thereby further improving the performance of the semiconductor device.

[0084] Optionally, based on the above technical solution, S110 provides a semiconductor body including:

[0085] A semiconductor body is provided including a source trench having a width smaller than a width of a gate trench.

[0086] like Figure 8 As shown, a semiconductor body 100 is provided, including a source trench T2 whose width W1 is smaller than a gate trench T1 whose width W2 is smaller.

[0087] Specifically, the width W1 of the source trench T2 is smaller than the width W2 of the gate trench T1, achieving different filling effects of the trenches, so that in the subsequent removal process, the filling layer 302 located in the gate trench T1 is removed, while the filling layer 302 located in the source trench T2 can be retained. And the width W1 of the source trench T2 is smaller than the width W2 of the gate trench T1, relative to the solution that the width W1 of the source trench T2 is greater than or equal to the width W2 of the gate trench T1, so that the source trench structure 300 can reduce the on-resistance of the semiconductor device while reducing the peak electric field effect of the bottom insulating layer of the trench gate 202.

[0088] Optionally, based on the above technical solution, S130 forming a filling layer in the source trench includes:

[0089] A filling layer including an air gap is formed in the source trench.

[0090] like Fig. 9 As shown, a filling layer 302 including an air gap 305 is formed in the source trench T2.

[0091] Specifically, when the aspect ratio of the source trench T2 is larger, during the formation of the source trench T2, before the inside of the source trench T2 is filled with the filling layer 302, the opening of the source trench T2 has been sealed by the filling layer 302, thereby forming an air gap 305 in the filling layer 302.

[0092] Optionally, based on the above technical solution, S110 provides a semiconductor body including:

[0093] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0094] like Figure 7 As shown, a semiconductor body 100 including a silicon carbide semiconductor body or a gallium nitride semiconductor body is provided.

[0095] Specifically, the semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0096] Optionally, based on the above technical solution, S110 provides a semiconductor body including:

[0097] A semiconductor body is provided with a plurality of source trenches on one side of a gate trench, and the source trench structures and the source trenches are arranged in a one-to-one correspondence.

[0098] For example, Figure 5 As shown, Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, in which two source trenches T2 are arranged on one side of the gate trench T1.

[0099] Specifically, the more source trenches T2 are set on one side of the gate trench T1, the larger the area of ​​the semiconductor body 100 occupied by the source trench structure 300 in a unit cell of a MOSFET semiconductor device, and the more significant the effect of the source trench structure 300 on reducing the peak electric field of the bottom insulating layer of the trench gate 202.

[0100] The embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device described in any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device described in any embodiment of the present invention are not described in detail here.

[0101] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0102] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiments of the present invention will not be repeated here.

[0103] The embodiment of the present invention further provides a vehicle, comprising a load and any power conversion circuit as in the embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0104] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0105] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first region and a second region; the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench extends from the first surface into the semiconductor body, and the source trench extends from the first surface into the semiconductor body; The second region is set to be of a second conductivity type and surrounds the bottom surface and side walls of the source trench; the semiconductor body further includes an insulating layer, and the insulating layer is located on the bottom surface and side walls of the gate trench; A trench gate, wherein the trench gate is located in the gate trench on a side of the insulating layer away from the semiconductor body; The insulating layer is used to insulate the semiconductor body and the trench gate; A source trench structure, the source trench structure comprising a filling layer, the filling layer being located in the source trench; An ohmic contact layer, wherein the ohmic contact layer is located on the first surface; The ohmic contact resistance between the ohmic contact layer and the semiconductor body is less than the ohmic contact resistance when metal titanium forms an ohmic contact with the semiconductor body; and at the annealing temperature of the ohmic contact layer, there is no chemical reaction intermediate product between the filling layer and the ohmic contact layer; a source electrode, the source electrode being located at a side of the ohmic contact layer away from the first surface; a drain electrode, the drain electrode being located on the second surface; The ohmic contact layer comprises any one or a combination of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al; The filling layer includes any one of silicon nitride, silicon oxide, carbon and silicon oxynitride or a combination thereof; The semiconductor body comprises a silicon carbide semiconductor body or a gallium nitride semiconductor body; An air gap is provided in the filling layer; A plurality of source trenches are arranged on one side of the gate trench, the source trench structure and the source trenches are arranged in one-to-one correspondence, and the ohmic contact layer is in contact with the source trench structure.

2. The semiconductor device according to claim 1, wherein: The width of the source trench is smaller than the width of the gate trench.

3. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first region and a second region; the first region is set to be of a first conductivity type and is located on the first surface, the well region is set to be of a second conductivity type and is located on a side of the first region away from the first surface; the first surface is further provided with a gate trench and a source trench, the gate trench extends from the first surface into the semiconductor body, and the source trench extends from the first surface into the semiconductor body; The second region is set to be of a second conductivity type and surrounds the bottom surface and side walls of the source trench; the semiconductor body further includes an insulating layer, and the insulating layer is located on the bottom surface and side walls of the gate trench; Forming a trench gate on a side of the insulating layer away from the semiconductor body in the gate trench; The insulating layer is used to insulate the semiconductor body and the trench gate; forming a source trench structure in the source trench, wherein the source trench structure comprises a filling layer; An ohmic contact layer is formed on the first surface; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is less than the ohmic contact resistance when metal titanium forms ohmic contact with the semiconductor body; and at the annealing temperature of the ohmic contact layer, there is no chemical reaction intermediate product between the filling layer and the ohmic contact layer; forming a source electrode on a side of the ohmic contact layer away from the first surface; forming a drain electrode on the second surface; Forming an ohmic contact layer on the first surface comprises: forming an ohmic contact layer comprising any one of Ni, TiNi alloy, a stack of Ti and Ni, NiPt alloy, a stack of Ni and Pt, Co, TiAl alloy, and a stack of Ti and Al, or a combination thereof, on the first surface; Forming a filling layer in the source trench comprises: forming a filling layer including at least one of silicon nitride, silicon oxide, carbon and silicon oxynitride or a combination thereof in the source trench; The semiconductor body provided includes: Providing a semiconductor body comprising a silicon carbide semiconductor body or a gallium nitride semiconductor body; An air gap is provided in the filling layer; The semiconductor body provided includes: A semiconductor body is provided with a plurality of source trenches on one side of the gate trench, the source trench structure and the source trenches are arranged in one-to-one correspondence, and the ohmic contact layer is in contact with the source trench structure.

4. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to claim 1 or 2, wherein the substrate is used for carrying the semiconductor device.

5. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in claim 1 or 2, wherein the semiconductor device is electrically connected to the circuit board.

6. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 5, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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