Fabrication methods and vertically stacked semiconductor devices

Abstract

This disclosure provides a method for fabricating a vertically stacked semiconductor device and the vertically stacked semiconductor device itself. The method includes: sequentially forming a lower stacked structure, an intermediate layer, and an upper stacked structure on a substrate; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure together with the upper portion of the substrate; forming a sacrificial gate on the substrate extending along a second direction intersecting a first direction and thus intersecting with a fin; forming a gate sidewall on the sidewall of the sacrificial gate; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure; selectively etching the sacrificial layer and the intermediate layer; filling the space released in the fin due to the selective etching of the sacrificial layer and the intermediate layer with a dielectric material; forming a lower source / drain layer that contacts the exposed side surface of the channel layer in the lower stacked structure and an upper source / drain layer that contacts the exposed side surface of the channel layer in the upper stacked structure; and replacing the sacrificial gate and the sacrificial layer with a gate stack.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a method for fabricating a vertically stacked semiconductor device and the vertically stacked semiconductor device itself. Background Technology

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FETs (Nano-SheetGate-All-Around Field-Effect Transistors) will replace existing Fin FET (Fin Field-Effect Transistor) technology at 3nm and below. Furthermore, three-dimensional stacked transistors will become the main technology route after the 1nm node. Three-dimensional stacked transistors include three-dimensional stacked integrated transistors and VFETs (Vertical Field-Effect Transistors). The three-dimensional stacked integrated transistor is also known as 3DS FET, or CFET (Complementary Field-Effect Transistor).

[0003] The main process methods for realizing 3DS FETs fall into two categories: sequential integration and self-aligned in-line (or single-line) integration. The former is simpler but is limited by performance and resources; the latter offers high integration density and superior performance, but it is complex and faces various technological challenges. Summary of the Invention

[0004] In view of this, the present disclosure provides a method for fabricating a vertically stacked semiconductor device and a vertically stacked semiconductor device.

[0005] According to a first aspect of this disclosure, a method for fabricating a vertically stacked semiconductor device is provided, comprising: sequentially disposing a lower stacked structure, an intermediate layer, and an upper stacked structure on a substrate, wherein the lower stacked structure and the upper stacked structure each include an alternately disposed channel layer and a sacrificial layer, wherein the sacrificial layer and the intermediate layer have etch selectivity relative to the substrate and the channel layer; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure together with the upper part of the substrate to form a fin extending along a first direction; forming a sacrificial gate extending along a second direction intersecting the first direction and thus intersecting the fin on the substrate; forming a gate sidewall on the sidewall of the sacrificial gate; and patterning the lower stacked structure, the intermediate layer, and the upper stacked structure using the sacrificial gate and the gate sidewall as a mask, such that the patterned lower stacked structure, the intermediate layer, and the upper stacked structure have side surfaces exposed in the first direction; The sacrificial layer and intermediate layer are selectively etched via the exposed side surface, wherein the etching rate of the intermediate layer is higher than that of the sacrificial layer during selective etching, such that the intermediate layer is removed and the sacrificial layer is retained upon completion of selective etching, with the retained sacrificial layer recessed at its end relative to the channel layer in the first direction; a dielectric material is filled in the space in the fin released by the selective etching of the sacrificial layer and intermediate layer, wherein the portion of the dielectric material filled at the end of the sacrificial layer serves as an inner sidewall, and the portion of the dielectric material filled between the lower stack and the upper stack serves as an inter-device isolation layer; a lower source / drain layer is formed in contact with the exposed side surface of the channel layer in the lower stack and an upper source / drain layer is formed in contact with the exposed side surface of the channel layer in the upper stack; and the sacrificial gate and sacrificial layer are replaced with a gate stack.

[0006] According to embodiments of this disclosure, the intermediate layer and the sacrificial layer are made of the same material, but the doping ratios of the intermediate layer and the sacrificial layer are different, so that the etching rate of the intermediate layer is higher than that of the sacrificial layer.

[0007] According to embodiments of this disclosure, the above-described preparation method further includes: forming an intermediary dielectric layer covering the upper stacked structure, the upper source / drain layer, and the lower source / drain layer; etching the intermediary dielectric layer to form an opening in the dielectric layer exposing the upper source / drain layer and the lower source / drain layer; and disposing of a conductive material within the opening in the dielectric layer to form a contact hole, wherein the contact hole in the intermediary dielectric layer allows the upper drain layer and the lower drain layer to be electrically connected to a data output terminal through the contact hole, and allows: the lower source layer that is not electrically connected to a power source and is not powered to a ground terminal, and the upper source layer located directly above the lower source layer that is not powered to a power source and is powered to a ground terminal; or, the upper source layer located directly above the lower source layer that is powered to a power source and is powered to a bit line terminal.

[0008] According to an embodiment of this disclosure, a shallow trench isolator is provided next to the upper part of the substrate; a power rail for electrical connection to a power source is pre-embedded in the shallow trench isolator; the above preparation method further includes: etching the shallow trench isolator according to the position of the lower source layer and the position of the power rail to form an isolator opening that exposes the lower source layer and the power rail; filling the isolator opening with a conductive material, and sealing the isolator opening with a dielectric material after filling with the conductive material, thereby forming a contact hole that electrically connects the lower source layer and the power rail.

[0009] According to embodiments of this disclosure, forming a lower source / drain layer that is in contact with the exposed side surface of the channel layer in the lower stacked structure and an upper source / drain layer that is in contact with the exposed side surface of the channel layer in the upper stacked structure includes: forming a protective sidewall on a substrate for protecting the upper stacked structure; forming a first electrode material layer in contact with the lower stacked structure in an unprotected region between the protective sidewall and the substrate; in-situ doping the first electrode material layer to obtain the lower source / drain layer; depositing a dielectric material over the lower source / drain layer to form an inter-device isolation layer that isolates the lower source / drain layer and the upper source / drain layer; removing the protective sidewall exposed outside the inter-device isolation layer; forming a second electrode material layer in contact with the upper stacked structure on the inter-device isolation layer; in-situ doping the second electrode material layer to form the upper source / drain layer; and activating the lower source / drain layer and the upper source / drain layer.

[0010] According to a second aspect of this disclosure, a vertically stacked semiconductor device is provided, comprising: a first field-effect transistor and a second field-effect transistor stacked on a substrate in a vertical direction; and an inter-device isolation layer between the first field-effect transistor and the second field-effect transistor, wherein each of the first and second field-effect transistors comprises: a plurality of channel layers stacked at intervals from each other in a vertical direction; source / drain layers adjoining the channel layers on both sides in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; and an inner sidewall between the gate stack and the source / drain layers, wherein the inner sidewalls of each of the first and second field-effect transistors have substantially aligned outer surfaces.

[0011] According to embodiments of this disclosure, the inter-device isolation layer is integrated with the adjacent inner wall.

[0012] According to embodiments of the present disclosure, in a first field-effect transistor, the gate stack includes a portion of the upper surface of the uppermost channel layer among a plurality of channel layers in the first field-effect transistor, and in a second field-effect transistor, the gate stack includes a portion of the lower surface of the lowermost channel layer among a plurality of channel layers in the second field-effect transistor.

[0013] According to embodiments of this disclosure, there are multiple sets of vertically stacked first and second field-effect transistors. Two sets of vertically stacked field-effect transistors in the multiple sets of vertically stacked field-effect transistors are configured as inverter structures. In the vertically stacked semiconductor device, the multiple inverter structures are cross-coupled to each other to form an SRAM structure.

[0014] According to embodiments of this disclosure, for two sets of vertically stacked field-effect transistors used to form an inverter structure, the drain layers of the two sets of vertically stacked field-effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal; in the two sets of vertically stacked field-effect transistors, the two source layers of one set of vertically stacked field-effect transistors are both electrically connected to the ground terminal, and the two source layers of the other set of vertically stacked field-effect transistors are respectively electrically connected to the bit line terminal and the power rail.

[0015] According to embodiments of this disclosure, an intermediate layer and a sacrificial layer with etch selectivity relative to the substrate and channel layer are provided in the fin, and the etch rate of the intermediate layer is set higher than that of the sacrificial layer. Based on this, the intermediate layer and the sacrificial layer are selectively etched simultaneously until the selective etching is completed. At this point, the intermediate layer is removed, while the sacrificial layer is retained, and the end of the retained sacrificial layer in the first direction is recessed relative to the channel layer. The space released in the fin due to the selective etching of the sacrificial layer and the intermediate layer is filled with a dielectric material, thereby forming an inter-device isolation layer and an inner sidewall. This achieves simultaneous fabrication of the inter-device isolation layer and the inner sidewall, reducing process steps and avoiding the need for multiple-step formation of the inter-device isolation layer and the inner sidewall. Based on this, in the vertically stacked semiconductor device fabricated based on the simultaneous fabrication method of the inter-device isolation layer and the inner sidewall, the upper source / drain layer of the upper field-effect transistor and the lower source / drain layer of the lower field-effect transistor are symmetrical, avoiding the unfavorable result that the volume of the upper field-effect transistor structure is larger than that of the lower field-effect transistor structure in step-by-step fabrication. Attached Figure Description

[0016] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 The diagram illustrates a schematic representation of the development process of integrated circuits according to embodiments of the present disclosure.

[0018] Figure 2 The diagram illustrates the evolution path of the core transistor structure of an integrated circuit according to embodiments of the present disclosure.

[0019] Figure 3 A schematic diagram of a sequential integration process according to an embodiment of the present disclosure is shown.

[0020] Figure 4 A schematic diagram of a self-aligned simultaneous integration process according to an embodiment of the present disclosure is shown.

[0021] Figure 5 A flowchart illustrating a method for fabricating a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0022] Figure 6 A schematic diagram of an SRAM integrated circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 7 A schematic diagram of a single-layer SRAM structure according to an embodiment of the present disclosure is shown.

[0024] Figure 8A A schematic diagram of the layer structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0025] Figure 8B A schematic diagram of the top layer structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0026] Figure 8C A schematic diagram of the underlying structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0027] Figure 9A A schematic diagram of a vertically stacked semiconductor device extending along a first direction according to an embodiment of the present disclosure is shown.

[0028] Figure 9B A schematic diagram of a vertically stacked semiconductor device extending along a second direction according to an embodiment of the present disclosure is shown.

[0029] Figures 10A-10E The schematic diagram illustrates various axes of the layer structure of a vertically stacked semiconductor device according to embodiments of the present disclosure.

[0030] Figures 11A to 48A , Figures 11B to 48B , Figure 32C , Figure 32D , Figure 48C and Figure 48D A schematic cross-sectional view of a vertically stacked semiconductor device along the axial direction is shown according to an embodiment of the present disclosure.

[0031] Figure 18B' , Figures 22A'~24A' , Figures 22B'~24B' , Figure 26A' , Figure 32A' , Figure 32B' , Figure 32C' , Figure 32D' , Figure 34A' , Figure 35A' , Figure 45A' , Figure 48A' , Figure 48B' , Figure 48C' and Figure 48D' The diagram schematically illustrates a cross-sectional view of a semiconductor device along the axial direction in the related art.

[0032] Figure 49 A schematic diagram of the structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0033] Figure 50 A schematic diagram of an SRAM structure based on vertically stacked semiconductor devices according to an embodiment of the present disclosure is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0036] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0037] When using expressions such as "at least one of A, B, and C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C. Similarly, when using expressions such as "at least one of A, B, or C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C.

[0038] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0039] In this embodiment of the disclosure, Figure 1 The illustrated technology development roadmap serves as an example to demonstrate the progress of integrated circuit development. It should be noted that... Figure 1 In this context, "Tech Node" refers to a semiconductor process node, which can be used to represent the critical dimensions achievable in the manufacturing process of integrated circuits. Based on this, refer to... Figure 1 As shown in the technology development roadmap, the integrated circuit fabrication processes are ordered from high to low according to the size represented by the semiconductor process nodes, namely Planar 11A (i.e., planar transistor structure), Fin FET 11B, NS-GAA FET 11C, VFET 11D, and StackedFET 11E. Specifically, the dimensions represented by Tech Node 12A of Planar 11A, from highest to lowest, are 90, 65, 45, 32, 28, and 20, in nm; the dimensions represented by Tech Node 12B of Fin FET 11B, from highest to lowest, are 14, 10, 7, 5, and 4, in nm; the dimensions represented by Tech Node 12C of NS-GAA FET 11C, from highest to lowest, are 3 and 2, in nm; and the dimensions represented by Tech Node 12D of VFET 11D and Stacked FET 11E, from highest to lowest, are 1 and 0.7, in nm.

[0040] Furthermore, such as Figure 2 As shown, in the evolution path of the core transistor structure of integrated circuits, it will evolve from Fin FET201 to NS-GAA FET202, Forksheet FET203, and further to three-dimensional stacked integrated transistors in a single chip, namely 3DS FET or CFET (Complementary Field Effect Transistor)204, in order to obtain higher integration density and overall performance.

[0041] like Figure 3 and Figure 4As shown, the main process methods for realizing 3DS FETs fall into two categories: sequential 3D and monolithic 3D. Taking two stacked transistors as an example, when these two transistors are fabricated using sequential integration, their channel materials can be different; when they are fabricated using monolithic 3D, their channel materials can be the same. For example, the sequential integration process may include: bonding a substrate 301 to the upper part of the bottom device 302 to obtain an intermediate device 303; and fabricating a top device based on the substrate bonded in the intermediate device to obtain an integrated circuit 304. The monolithic 3D process may include directly growing a polysilicon layer 402 surrounding multiple channel layers on the fin structure 401, followed by processing, to obtain the integrated circuit 403.

[0042] Therefore, sequential integration is simple, but it is limited by performance and resources; the latter self-aligned sequential integration method has high integration and superior performance, but it is complex and faces various process technology challenges.

[0043] Specifically, the advantages of sequential integration technology include: flexible architecture design, adjustable channel materials, and flexible interconnection methods between transistors. The main disadvantages of sequential integration technology are: higher resource consumption, limitations in the fabrication process, bonding, isolation space between NPs, thermal budget, and photolithography alignment.

[0044] The advantages of self-aligned in-line integration include: low resource consumption, precise process control (e.g., self-aligned top and bottom devices), and narrow isolation space between NPs. The main disadvantages are: high process complexity, such as processes with high aspect ratios and complex interconnections between devices.

[0045] In view of this, the present disclosure provides a method for fabricating a vertically stacked semiconductor device, comprising: sequentially forming a lower stacked structure, an intermediate layer, and an upper stacked structure on a substrate, wherein the lower stacked structure and the upper stacked structure each include an alternately arranged channel layer and a sacrificial layer, wherein the sacrificial layer and the intermediate layer have etching selectivity relative to the substrate and the channel layer; patterning the lower stacked structure, the intermediate layer, and the upper stacked structure together with the upper part of the substrate to form fins extending along a first direction; forming a sacrificial gate on the substrate extending along a second direction intersecting the first direction and thus intersecting the fins; forming gate sidewalls on the sidewalls of the sacrificial gate; and patterning the lower stacked structure, the intermediate layer, and the upper stacked structure using the sacrificial gate and the gate sidewalls as masks, such that the patterned lower stacked structure, the intermediate layer, and the upper stacked structure have side surfaces exposed in the first direction. The sacrificial layer and intermediate layer are selectively etched via the exposed side surfaces, wherein the etching rate of the intermediate layer is higher than that of the sacrificial layer during selective etching, such that upon completion of the selective etching, the intermediate layer is removed while the sacrificial layer is retained, with the retained sacrificial layer recessed relative to the channel layer at its end in the first direction. The space freed in the fin due to the selective etching of the sacrificial and intermediate layers is filled with a dielectric material, wherein the portion of the dielectric material filling at the end of the sacrificial layer serves as an inner sidewall, and the portion of the dielectric material filling between the lower and upper stacked structures serves as an inter-device isolation layer. A lower source / drain layer is formed that contacts the exposed side surface of the channel layer in the lower stacked structure, and an upper source / drain layer is formed that contacts the exposed side surface of the channel layer in the upper stacked structure. The sacrificial gate and sacrificial layer are replaced with a gate stack.

[0046] Figure 5 A flowchart illustrating a method for fabricating a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0047] like Figure 5 As shown, the fabrication method of the vertical semiconductor device in this embodiment includes operations S501 to S509.

[0048] In operation S501, a lower stacked structure, an intermediate layer, and an upper stacked structure are sequentially disposed on the substrate. The lower stacked structure and the upper stacked structure each include an alternately disposed channel layer and a sacrificial layer, wherein the sacrificial layer and the intermediate layer have etching selectivity relative to the substrate and the channel layer.

[0049] In operation S502, the lower stacked structure, the intermediate layer and the upper stacked structure together with the upper part of the substrate are patterned to form fins extending along a first direction.

[0050] In operation S503, a sacrificial gate is formed on the substrate extending along a second direction that intersects the first direction and thus crosses the fin.

[0051] In operation S504, a gate sidewall is formed on the sidewall of the sacrificial gate.

[0052] In operation S505, using the sacrificial gate and gate sidewall as a mask, the lower stacked structure, the intermediate layer and the upper stacked structure are patterned, so that the patterned lower stacked structure, the intermediate layer and the upper stacked structure have side surfaces exposed in the first direction.

[0053] In operation S506, the sacrificial layer and the intermediate layer are selectively etched via the exposed side surface, wherein the etching rate of the intermediate layer is higher than that of the sacrificial layer during the selective etching, such that when the selective etching is completed, the intermediate layer is removed while the sacrificial layer is retained, and the end of the retained sacrificial layer in the first direction is recessed relative to the channel layer.

[0054] In operation S507, the space freed up in the fin due to the selective etching of the sacrificial layer and the intermediate layer is filled with dielectric material, wherein the portion of the dielectric material filled at the end of the sacrificial layer serves as an inner sidewall, and the portion of the dielectric material filled between the lower stacked structure and the upper stacked structure serves as an inter-device isolation layer.

[0055] In operation S508, a lower source / drain layer is formed that is in contact with the exposed side surface of the channel layer in the lower stacked structure, and an upper source / drain layer is formed that is in contact with the exposed side surface of the channel layer in the upper stacked structure.

[0056] In operation S509, the sacrificial gate and sacrificial layer are replaced with a gate stack.

[0057] According to embodiments of this disclosure, the vertical semiconductor device fabricated by the method of this disclosure can be used to implement an SRAM structure (Static Random-Access Memory). For example, a first group of field-effect transistors and a second group of field-effect transistors can be provided, arranged along a second direction and spaced apart from each other. Each of the first group of field-effect transistors and the second group of field-effect transistors includes two vertically stacked semiconductor devices. Each vertically stacked semiconductor device may include vertically stacked field-effect transistors. Based on this, the above-described SRAM structure can be implemented using the two stacked field-effect transistors in the first group of field-effect transistors and the two stacked field-effect transistors in the second group of field-effect transistors.

[0058] The following describes the fabrication method of the vertical semiconductor device according to an embodiment of this disclosure, using an SRAM structure as an example. It should be understood that the SRAM described here is merely an example, and those skilled in the art can implement other integrated circuit structures based on the vertical semiconductor device in this disclosure as needed.

[0059] like Figure 6As shown, SRAM is the core unit circuit of integrated circuits, and continuously reducing the SRAM cell area is the main trend in integrated circuit development. Utilizing a three-dimensional stacked transistor structure (3DS-FET or CFET) can significantly reduce the SRAM cell area, by more than 30%. (Reference) Figure 7 and Figure 8A ,contrast Figure 7 Single-layer SRAM structure and Figure 8A As can be seen from the dual-layer SRAM structure, Figure 8A The area of ​​the realized three-dimensional stacked structure is smaller than Figure 7 The area of ​​the two-dimensional structure. Furthermore, Figure 8A The three-dimensional stacked structure in [the system] can be divided into a top-level structure and a bottom-level structure. The top-level structure can be implemented based on NMOS, and the bottom-level structure can be implemented based on PMOS. Based on this, Figure 8B and Figure 8C They are shown respectively Figure 8A The top and bottom layers of the three-dimensional stacked structure are shown. It should be noted that the dimensions shown in the accompanying drawings are illustrative and not intended to limit the actual dimensions of the staggered units in this disclosure.

[0060] Taking SRAM as an example, combined with Figure 10A and Figure 10B The various axes of the vertically stacked semiconductor device as defined in embodiments of this disclosure are shown. Figures 10A-10E An example is shown Figure 8A The image shows the various axes of the layer structure used to implement the vertically stacked semiconductor device SRAM. The X-X' axis extends along a first direction. The Y1-Y1', Y2-Y2', Y3-Y3', and Y4-Y4' axes extend along a second direction.

[0061] The following are cross-sectional views along various axes during the fabrication of vertical semiconductor devices, i.e. Figures 11A to 48A , Figures 11B to 48B , Figure 32C , Figure 32D , Figure 48C and Figure 48D The following will describe the content of the embodiments of this disclosure. It should be noted that in the various figures shown in this disclosure, when the numbers in the titles of multiple figures are the same, the manufacturing processes corresponding to those multiple figures are the same. When the numbers in the titles of multiple figures are the same but the letters are different, the manufacturing processes corresponding to those multiple figures are the same, but the axial directions corresponding to those multiple figures are different. For example, Figure 11A and Figure 11B These are cross-sectional views along two axes, representing the same preparation process.

[0062] Taking a set of stacked field-effect transistors as an example, Figures 11A-12A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 11B-12B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of a vertical semiconductor device. (Reference) Figures 11A-12A ,as well as Figures 11B-12B The substrate SUB can be made of materials such as silicon. Pre-treatment operations such as trap lithography, ion implantation, annealing, and cleaning can be performed sequentially on the substrate SUB. Then, an epitaxial growth process is used to sequentially form a lower stacked structure, an intermediate layer 103, and an upper stacked structure on the pre-treated substrate SUB. Both the lower and upper stacked structures include alternating channel layers 101 and sacrificial layers 102. The sacrificial layer 102 and the intermediate layer 103 can be made of the same material, such as SiGe or Si. The channel layer 101 can be made of doped silicon. The channel layer 101 above the intermediate layer 103 and the channel layer 101 below the intermediate layer 103 can have the same or different doping elements.

[0063] In a first embodiment of this disclosure, the channel layer 101 above the intermediate layer 103 is made of p-type doped silicon; the channel layer 101 below the intermediate layer 103 is made of n-type doped silicon. In a second embodiment of this disclosure, the channel layer 101 above the intermediate layer 103 is made of n-type doped silicon; the channel layer 101 below the intermediate layer 103 is made of p-type doped silicon. In a third embodiment of this disclosure, the channel layer 101 above the intermediate layer 103 and the channel layer 101 below the intermediate layer 103 can each be made of either n-type doped silicon or both of p-type doped silicon.

[0064] Figures 13A to 19A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 13B to 19B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of a vertical semiconductor device. (Reference) Figures 13A to 19A ,as well as Figures 13B to 19BThe sidewall 104 can be formed using a sidewall transfer (SIT) process. The material of the sidewall 104 can be silicon nitride, etc. In this embodiment, a core mold 105 can be formed on the upper stacked structure, and the core mold 105 can be patterned using a photolithography process to obtain a linear pattern extending along the X direction. The material of the core mold 105 can be polycrystalline silicon or amorphous silicon, etc. The sidewall 104 is formed in the above-mentioned area, and the patterned core mold 105 is removed after the sidewall 104 is formed, so that only the sidewall 104 is retained on the stacked structure, thereby completing the fabrication of the sidewall 104. Based on this, the upper stacked structure, the intermediate layer 103, the lower stacked structure, and the substrate SUB can be etched using an anisotropic etching process according to the pattern of the sidewall 104 to form fins extending along a first direction on the substrate SUB and substrate etching regions distributed on both sides of the fins along the first direction.

[0065] Within the etched area of ​​the substrate, a dielectric material 106 is deposited. Then, following a BPR (Buried Power Rail) pattern, the dielectric material 106 is etched to obtain a deep hole whose lower surface is lower than the upper surface of the lower fin formed by the substrate SUB. A conductive material with an upper surface no higher than the upper surface of the lower fin is placed in the deep hole to form a power rail VDD. Based on this, the deep hole filled with the conductive material is sealed using the dielectric material, and after sealing, the dielectric material 106 is etched to be lower than or equal to the upper surface of the lower fin, resulting in a shallow trench isolation device. The dielectric material in this embodiment may include silicon dioxide or silicon nitride, etc. Based on this, refer to... Figure 18B' As can be seen from the schematic illustration of the related art in which power rails are embedded, in this embodiment, power rails are embedded in the shallow trench isolation members on both sides of the fin. Compared with this art, the above-described fabrication method of this disclosure reduces the number of embedded power rails, thereby reducing the area of ​​the horizontal cross-section of the vertically stacked semiconductor device obtained by this disclosure.

[0066] Figures 20A-24A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 20B-24B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of a vertical semiconductor device. (Reference) Figures 20A-24A ,as well as Figures 20B-24BA sacrificial gate spanning the fins can be formed on the dielectric material 106 using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The sacrificial gate, from bottom to top, comprises a gate oxide layer 107, a silicon layer 108, and a mask layer 109. The gate oxide layer 107 can be made of materials such as SiO2. The silicon layer 108 is made of amorphous silicon or polycrystalline silicon. The hard mask layer 109 can be made of materials such as oxides, carbides, or organic materials. Based on this, a gate sidewall 110 can be formed on the sidewalls of the sacrificial gate using a sidewall formation process. The gate sidewall can be made of materials such as SiCNO. The upper stacked structure, intermediate layer, and lower stacked structure can be etched according to the pattern of the sacrificial gate and the gate sidewall 110, so that the patterned lower stacked structure, intermediate layer, and upper stacked structure have side surfaces exposed in a first direction.

[0067] Since the sacrificial layer 102 and the intermediate layer 103 have etch selectivity relative to the substrate SUB and the channel layer 101, they can be selectively etched via the exposed side surfaces. During selective etching, the etching rate of the intermediate layer 103 is higher than that of the sacrificial layer 102, such that upon completion of selective etching, the intermediate layer 103 is removed while the sacrificial layer 102 is retained, with its end in the first direction recessed relative to the channel layer 101. In one embodiment of this disclosure, the intermediate layer and the sacrificial layer are made of the same material, but the doping ratios between them are different, resulting in a higher etching rate for the intermediate layer than for the sacrificial layer. Based on this, simultaneous etching of the intermediate layer 103 and the sacrificial layer 102 can be achieved. For example, the etch selectivity ratio between the intermediate layer 103 and the sacrificial layer 102 is greater than 5:1. For example, both the sacrificial layer 102 and the intermediate layer 103 are made of Ge doped with SiGe. By setting the Ge doping content in the sacrificial layer 102 to be different from that in the intermediate layer 103, the aforementioned selective etching can be achieved, and the etching rate of the intermediate layer can be higher than that of the sacrificial layer. For example, the Ge doping content in the intermediate layer 103 can be set to be higher than that in the sacrificial layer 102.

[0068] Based on this, after the intermediate layer 103 is etched, an opening 112 is formed, and the recess of the end of the sacrificial layer 102 in the first horizontal direction relative to the channel layer 101 serves as an opening 111. The space released in the fin due to the selective etching of the sacrificial layer 102 and the intermediate layer 103 is filled with a dielectric material. The portion of the dielectric material filling at the end of the sacrificial layer 102 serves as an inner sidewall 113, and the portion of the dielectric material filling between the lower and upper stacked structures serves as an inter-device isolation layer 114. The inner sidewall 113 in the upper stacked structure is symmetrical to the inner sidewall 113 in the lower stacked structure. Based on this, refer to... Figures 22A'~24A' ,as well as Figures 22B'~24B' As illustrated in the related art, the etching method of the channel layer 101 is such that, in this embodiment, the intermediate layer 103 is first completely etched away to form the opening 112, and then the upper stacked structure is etched, while the lower stacked structure is not etched in this step. That is, in the related art, the upper and lower stacked structures are etched in different steps. Compared with this art, the above-described fabrication method achieves the simultaneous fabrication of the inner sidewall 113 and the inter-device isolation layer 114, reducing the number of fabrication steps and avoiding the unfavorable result of misalignment of the upper and lower field-effect transistors in the vertically stacked semiconductor device due to the separate fabrication of the inner sidewall 113 and the inter-device isolation layer 114.

[0069] Figures 25A-28A ,as well as Figures 33A-35A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 25B to 28B ,as well as Figures 33B to 35B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of a vertical semiconductor device. (Reference) Figures 25A-28A , Figures 33A-35A , Figures 25B to 28B ,as well as Figures 33B to 35B The process involves forming a lower source / drain layer 117 that is in contact with the exposed side surface of the channel layer 101 in the lower stacked structure, and an upper source / drain layer 119 that is in contact with the exposed side surface of the channel layer 101 in the upper stacked structure. This includes: forming a protective sidewall 116 on a substrate SUB to protect the upper stacked structure; forming a first electrode material layer in contact with the lower stacked structure in an unprotected region between the protective sidewall 116 and the substrate SUB; in-situ doping the first electrode material layer to obtain the lower source / drain layer 117; depositing a dielectric material over the lower source / drain layer to form an inter-device isolation layer 114 that isolates the lower and upper source / drain layers; removing the protective sidewall 116 exposed outside the inter-device isolation layer 114; forming a second electrode material layer in contact with the upper stacked structure on the inter-device isolation layer 114; and in-situ doping the second electrode material layer to form the upper source / drain layer 119. The lower source / drain layer 117 and the upper source / drain layer 119 are activated. Based on this, refer to... Figure 26A'As can be seen from the schematic illustration of the arrangement of the inner wall 113 in the related art, in the case of setting the inner wall 113 of the lower stacked structure, the inner wall 113 of the upper stacked structure has not yet been formed. That is, in this embodiment, the inner wall 113 of the lower stacked structure and the inner wall 113 of the upper stacked structure are formed in different steps. Compared with this embodiment, the above-described fabrication method achieves the simultaneous fabrication of the inner wall 113 and the inter-device isolation layer 114, reduces the number of manufacturing process steps, and avoids the adverse result of misalignment of the outer surfaces of the upper and lower field-effect transistors in the vertically stacked semiconductor device in the vertical direction, which would be caused by separately fabricating the inner wall 113 and the inter-device isolation layer 114. Based on this, further reference is made to... Figure 34A' and Figure 35A' As can be seen in related technologies, since the inner wall 113 in the upper stacked structure and the inner wall 113 in the lower stacked structure are formed in different steps, the outer surfaces of the inner wall 113 in the upper stacked structure and the inner wall 113 in the lower stacked structure of this embodiment are not aligned in the vertical direction. This results in the horizontal area of ​​the upper source / drain layer 119 being larger than the horizontal area of ​​the lower source / drain layer 117. However, in the vertically stacked semiconductor device of this disclosure, since the outer surfaces of the inner wall 113 in the upper stacked structure and the inner wall 113 in the lower stacked structure are substantially aligned in the vertical direction, the horizontal cross-sectional area of ​​the upper source / drain layer 119 of the vertically stacked semiconductor device of this disclosure is equal to the horizontal cross-sectional area of ​​the lower source / drain layer 117.

[0070] Specifically, lower source / drain location defining layers 115 are formed on both sides of the channel layer 101 located below the inter-device isolation layer 114, contacting the channel layer 101. Protective sidewalls 116 are formed on the lower source / drain location defining layers 115 using a sidewall forming process. The material of the lower source / drain location defining layers 115 may include, but is not limited to, aC (amorphous carbon). The formation method of the lower source / drain location defining layers 115 includes, but is not limited to, spin coating. For example, after depositing aC, the deposited aC can be planarized, and aC can be etched back to a position no higher than the middle of the inter-device isolation layer 114. The material of the protective sidewalls 116 includes, but is not limited to, SiNx, etc. The protective sidewalls 116 are used to protect the channel layer 101 located above the inter-device isolation layer, preventing source / drain growth at both ends of the channel layer 101 of the upper device during the growth of the source / drain of the lower device. When the types of upper and lower devices are different, the source / drain materials of the upper and lower devices can be different.

[0071] After forming the protective sidewall 116, the lower source / drain location defining layer 115 is removed to expose the sidewalls of the channel layer 101 located below the inter-device isolation layer 114. On the exposed sidewalls of the channel layer 101, a source / drain material layer is epitaxially grown and in-situ doped to form a lower source / drain layer 117 that is connected to the lower stacked structure. The source / drain material can be SiGe or Si. A dielectric material 118 can be deposited on the lower source / drain layer 117, and the dielectric material 118 can be etched to a position no higher than the inter-device isolation layer 114 to electrically isolate the source / drain layers of the upper and lower devices. The protective sidewall 116 can be selectively etched to expose the sidewalls of the channel layer 101 above the inter-device isolation layer 114. On the exposed sidewalls of the channel layer 101, a source / drain material is epitaxially grown and in-situ doped to form a source / drain layer 119 that is connected to the upper stacked structure. Based on this, source / drain layers 117 and 119 are activated to obtain activated source / drain layers 117 and 119.

[0072] In this embodiment, a shallow trench isolator is provided next to the upper part of the substrate SUB. A power rail VDD for electrical connection to a power source is pre-embedded in the shallow trench isolator. After depositing the dielectric material 118, the above-described fabrication method further includes: etching the shallow trench isolator according to the position of the lower source layer and the position of the power rail VDD to form an isolator opening exposing the lower source layer and the power rail VDD. A conductive material is filled into the isolator opening, and after filling with the conductive material, the isolator opening is sealed with a dielectric material, thereby forming a contact hole for electrical connection between the lower source layer and the power rail.

[0073] For example, taking the four field-effect transistors in the first group of field-effect transistors and the four field-effect transistors in the second group of field-effect transistors as examples, Figures 29A to 32A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 29B to 32B It is a cross-sectional view along the Y2-Y2' axis during the fabrication of a vertical semiconductor device. Figure 32C It is a cross-sectional view along the Y1-Y1' axis during the fabrication of a vertical semiconductor device. Figure 32D It is a cross-sectional view along the Y3-Y3' axis during the fabrication of a vertical semiconductor device.

[0074] Based on this, Figures 29A to 32A , Figures 29B to 32B , Figure 32C and Figure 32D A cross-sectional schematic diagram of the structure integrating the above eight field-effect transistors is shown.

[0075] Refer to the above Figures 29A to 32A , Figures 29B to 32B , Figure 32C and Figure 32D After depositing dielectric material 118 on the lower source / drain layer 117 and etching the dielectric material 118 to a position no higher than the inter-device isolation layer 114, the fabrication method further includes: etching the dielectric material 118 and dielectric material 106 according to the position of the lower source / drain layer 117 to form isolation openings 128_1, 128_2, and 128_3. Each of the isolation openings 128_1, 128_2, and 128_3 simultaneously exposes the power rail and the lower source / drain layer. Conductive material is deposited within the isolation openings 128_1, 128_2, and 128_3. Based on this, contact holes are formed using the conductive material within the isolation openings 128_1 and 128_3 to electrically connect the lower source layer to the power rail. Based on the conductive material within the isolation opening 128_2, a contact hole is formed that connects to the lower drain layer of either the first group of field-effect transistors or the lower drain layer of the second group of field-effect transistors. Based on this, refer to... Figure 32A' , Figure 32B' , Figure 32C' and Figure 32D' As can be seen from the schematic illustration of the power rails VDD in the related art, the number of power rails VDD in this embodiment is greater than that in the present disclosure. Therefore, the fabrication method of the present disclosure reduces the area of ​​the semiconductor device in the horizontal cross-section, making the area of ​​the horizontal cross-section of the vertically stacked semiconductor device of the present disclosure smaller than the area of ​​the horizontal cross-section of the semiconductor device in the related art.

[0076] Figures 36A to 44A ,as well as Figures 36A to 44A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 36B to 44B ,as well as Figures 36B to 44B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of a vertical semiconductor device. (Reference) Figures 36A to 44A , Figures 36A to 44A , Figures 36B to 44B ,as well as Figures 36B to 44B A dielectric material 120 is formed on a substrate SUB and planarized. Planarization removes the mask layer 109 in the sacrificial gate, exposing the silicon layer 108. The dielectric material 120, gate sidewall 110, and silicon layer 108 are etched to the same height. Then, using an etch-back process, the silicon layer 108 and sacrificial layer 102 are etched, thereby forming cavities 121_1 exposed by etching at the original location of the silicon layer 108 and cavities 121_2 exposed by etching at the original location of the sacrificial layer 102, inside the gate sidewall 110 and inner sidewall 113.

[0077] A gate stack surrounding the channel layer 101 is sequentially formed on the inner walls of cavities 121_1 and 121_2. This gate stack includes a gate dielectric layer 122 and a P-type work function layer 123. The gate dielectric layer 122 can be made of a high-k dielectric material, where K represents the dielectric constant. High-k dielectric materials include HfO2 and HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x The material of the P-type work function layer 123 may be one or a combination of Ta2O5 or La2O3. The material of the P-type work function layer 123 may be titanium nitride, etc. A protective layer 124 is formed on the substrate SUB, and the protective layer 124 is etched to the top surface located between the top and bottom surfaces of the inter-device isolation layer 114 to shield the cavity for the underlying device. The protective layer 124 protects the P-type work function layer 123 located in the cavity below the inter-device isolation layer 114, while exposing the P-type work function layer 123 located in the cavity above the inter-device isolation layer 114.

[0078] The P-type work function layer 123 above the inter-device isolation layer 114 is etched using a selective etching process, while retaining the gate dielectric layer 122 above the inter-device isolation layer 114. Then, an N-type work function layer 125 is formed surrounding the gate dielectric layer 122 above the inter-device isolation layer 114. Thus, different gate stacks surrounding the channel layer 101 are formed above and below the inter-device isolation layer 114. Therefore, the channel layer 101, gate stack, and source / drain layer 119 above the inter-device isolation layer 114 constitute an N-type field-effect transistor, and the channel layer 101, gate stack, and source / drain layer 117 above the inter-device isolation layer 114 constitute a P-type field-effect transistor, thereby obtaining a stacked field-effect transistor.

[0079] It should be understood that the above is only one embodiment of this disclosure. In the preparation process of other embodiments of this disclosure, N-type field-effect transistors or P-type field-effect transistors can be formed as needed by changing the doping type of the source / drain layers and forming corresponding work function layers. For example, the upper N-type field-effect transistor can be formed as a P-type field-effect transistor, and / or the lower P-type field-effect transistor can be formed as an N-type field-effect transistor.

[0080] After fabricating the aforementioned N-type and P-type field-effect transistors, the protective layer 124 is removed, thereby releasing the cavity located below the inter-device isolation layer 114. Then, conductive material is deposited in all cavities 121_1 and all cavities 121_2 to form a conductive layer 126, thus completing the fabrication of the gate structure. The conductive material in this embodiment may include tungsten or the like. After forming the conductive layer 126, it can be planarized, and a dielectric material can be deposited on the planarized conductive layer 126.

[0081] Figure 45A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figure 45B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of a vertical semiconductor device. (Reference) Figure 45A and Figure 45B A contact hole 127 can be formed in the dielectric material 120 to connect with the source / drain layer 119. Based on this, refer to... Figure 45A' As is known in related technologies, the inter-device isolation layer 114 and the adjacent channel layer 101 are in close contact. Therefore, the gate stack is not disposed between the inter-device isolation layer 114 and the adjacent channel layer 101. However, in the vertical semiconductor device of this disclosure, the gate stack includes a portion located below the lower surface of the lowermost channel layer 101 in the upper stacked structure and a portion located below the uppermost channel layer 101 in the lower stacked structure. Therefore, the fabrication method of this disclosure allows the gate stack to more comprehensively surround the channel layer 101, improving the performance of the fabricated semiconductor device.

[0082] Specifically, taking the four field-effect transistors in the first group of field-effect transistors and the four field-effect transistors in the second group of field-effect transistors as examples, Figures 46A-48A It is a cross-sectional view along the X-X' axis during the fabrication of a vertical semiconductor device. Figures 46B-48B It is a cross-sectional view along the Y3-Y3' axis during the fabrication of a vertical semiconductor device. Figure 48C It is a cross-sectional view along the Y1-Y1' axis during the fabrication of a vertical semiconductor device. Figure 48D It is a cross-sectional view along the Y2-Y2' axis during the fabrication of a vertical semiconductor device.

[0083] Based on this, Figures 46A-48A , Figures 46B-48B , Figure 48C and Figure 48D A cross-sectional schematic diagram of a structure integrating the aforementioned eight field-effect transistors is shown. (Reference) Figures 46A-48A , Figures 46B-48B , Figure 48C and Figure 48DThe above-described preparation method further includes: forming an intermediary dielectric layer covering the upper stacked structure, the upper source / drain layer, and the lower source / drain layer. The intermediary dielectric layer may be based on the aforementioned dielectric material 120, dielectric material 118, and dielectric material 120. The intermediary dielectric layer is etched to form openings exposing the upper and lower source / drain layers. A conductive material is disposed within the dielectric layer openings to form contact holes. These contact holes in the intermediary dielectric layer allow the upper and lower drain layers to be electrically connected to a data output terminal, and also allow the lower source layer (not electrically connected to a power source) to be electrically connected to a ground terminal, and the upper source layer located directly above the lower source layer (not electrically connected to a power source) to also be electrically connected to a ground terminal. Alternatively, the upper source layer located directly above the lower source layer (electrically connected to a power source) is electrically connected to a bit line terminal.

[0084] Specifically, the upper surface of the dielectric material 120 is etched until the source / drain layer 119 is exposed, thereby forming dielectric layer openings 129_1, 129_2, and 129_3 in the dielectric material 120. Specifically, the Y3-Y3' dielectric layer opening 129_21 exposes conductive material in contact with the lower drain layer of the first group of field-effect transistors, and the dielectric layer opening 129_22 exposes conductive material in contact with the lower drain layer of the second group of field-effect transistors. Further etching of the dielectric layer opening 129_21 exposes both the conductive material in contact with the lower drain layer of the first group of field-effect transistors and the upper drain layer located on top of that lower drain layer. Furthermore, the dielectric layer opening 129_22 is further etched, exposing both the conductive material in contact with the lower drain layer of the second group of field-effect transistors and the upper drain layer located on the lower drain layer. Based on this, conductive material is filled into the dielectric layer opening 129_21 to form a contact hole 127_21 that simultaneously contacts the lower and upper drain layers of the first group of field-effect transistors. Conductive material is also filled into the dielectric layer opening 129_22 to form a contact hole 127_22 that simultaneously contacts the lower and upper drain layers of the second group of field-effect transistors. The contact hole 127_21 can be electrically connected to a first data output terminal; the contact hole 127_22 can be electrically connected to a second data output terminal.

[0085] Similarly, the dielectric layer opening 129_1 includes dielectric layer opening 129_11 and dielectric layer opening 129_12. The dielectric layer opening 129_11 along the Y2-Y2' axis exposes conductive material in contact with the lower source layer of the second group of field-effect transistors, while the dielectric layer opening 129_12 along the Y2-Y2' axis exposes the lower and upper source layers of the first group of field-effect transistors. Based on this, conductive material is filled into the dielectric layer opening 129_11 to form a contact hole 127_11; and conductive material is filled into the dielectric layer opening 129_12 to form a contact hole 127_12. Contact hole 127_11 can be electrically connected to the first line terminal, and contact hole 127_12 can be electrically connected to the ground terminal.

[0086] Similarly, the dielectric layer opening 129_3 includes dielectric layer opening 129_31 and dielectric layer opening 129_32. The dielectric layer opening 129_31 along the Y1-Y1' axis exposes the lower and upper source layers of the first group of field-effect transistors, while the dielectric layer opening 129_32 along the Y1-Y1' axis exposes conductive material connected to the lower source layer of the second group of field-effect transistors. Based on this, conductive material is filled into the dielectric layer opening 129_31 to form a contact hole 127_31; conductive material is filled into the dielectric layer opening 129_32 to form a contact hole 127_32. Contact hole 127_31 can be electrically connected to a ground terminal, and contact hole 127_32 can be electrically connected to a second bit line terminal complementary to the first bit line terminal. This allows the vertically stacked semiconductor device of this disclosure to be fabricated. Based on this, refer to... Figure 48A' , Figure 48B' , Figure 48C' and Figure 48D' It is known that the number of power rails VDD in the semiconductor devices of the related art is greater than the number of power rails VDD in the vertically stacked semiconductor device of this disclosure, and the number of contact holes connecting to the power rails VDD in the related art is greater than the number of contact holes connecting to the power rails in the vertically stacked semiconductor device of this disclosure. Therefore, the fabrication method of this disclosure reduces the horizontal cross-sectional area of ​​the vertically stacked semiconductor device, making the horizontal cross-sectional area of ​​the vertically stacked semiconductor device of this disclosure smaller than the horizontal cross-sectional area of ​​the semiconductor device in the related art.

[0087] Based on this, the present disclosure provides an intermediate layer 103 and a sacrificial layer 102 in the fin, which have etch selectivity relative to the substrate SUB and the channel layer 101, and sets the etching rate of the intermediate layer 103 to be higher than that of the sacrificial layer 102. Based on this, the intermediate layer 103 and the sacrificial layer 102 are selectively etched simultaneously until the selective etching is complete. At this point, the intermediate layer 103 is removed, while the sacrificial layer 102 is retained, with its end in the first direction recessed relative to the channel layer 101. The space released in the fin due to the selective etching of the sacrificial layer 102 and the intermediate layer 103 is filled with a dielectric material, thereby fabricating an inter-device isolation layer 114 and an inner sidewall 113. This achieves simultaneous fabrication of the inter-device isolation layer 114 and the inner sidewall 113, reducing process steps and avoiding the need for multiple step-by-step formation of the inter-device isolation layer 114 and the inner sidewall 113. Based on this, in the vertically stacked semiconductor device fabricated using the same manufacturing method for the inter-device isolation layer 114 and the inner sidewall 113, the upper source / drain layer 119 of the upper field-effect transistor and the lower source / drain layer 117 of the lower field-effect transistor are symmetrical, avoiding the unfavorable result that the volume of the upper field-effect transistor structure is larger than that of the lower field-effect transistor structure in the step-by-step manufacturing process. It should be understood that in the embodiments of this disclosure, the dielectric material includes, but is not limited to, SiO2 and SiN. x The dielectric materials include SiNO, SiCO, SiCNO, SiCN, as well as polymers, aC, and combinations thereof. Methods for filling the dielectric include, but are not limited to, ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), Spin, etc. Etching methods include, but are not limited to, wet etching, RIE (Reactive Ion Etching), RPS (Remote Plasma Source) etching, Chemical Dry Etch, ALE (Atomic Layer Etching), etc. This disclosure does not limit the scope of the invention; any method that implements the above-described preparation methods is acceptable.

[0088] Figure 49 A schematic diagram of a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown.

[0089] like Figure 49As shown, the vertically stacked semiconductor device 4900 of this embodiment includes: a first field-effect transistor 4901 and a second field-effect transistor 4902 stacked on a substrate SUB in a vertical direction. An inter-device isolation layer 114 is provided between the first and second field-effect transistors, wherein each of the first and second field-effect transistors includes: a plurality of channel layers 101 stacked at intervals in a vertical direction; source / drain layers adjoining the channel layers 101 on both sides in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers 101; and an inner wall 113 between the gate stack and the source / drain layers, wherein the inner wall 113 of each of the first and second field-effect transistors has substantially aligned outer surfaces. In this embodiment, the first field-effect transistor 4901 and the second field-effect transistor 4902 correspond to a field-effect transistor formed by the above-described upper stacked structure and a field-effect transistor formed by the above-described lower stacked structure, respectively. The source / drain layer of the first field-effect transistor 4901 is the source / drain layer 119 connected to the upper stacked structure described above. The source / drain layer of the second field-effect transistor 4902 is the source / drain layer 117 connected to the lower stacked structure described above. The gate stack surrounding the channel layer 101 corresponds to... Figure 49 The gate structure G (channel layer 101 is surrounded by gate structure G) in the middle Figure 49 (Not shown in the perspective view).

[0090] According to the embodiments of this disclosure, since the inter-device isolation layer 114 and the adjacent inner wall 113 are manufactured in the same batch, the inter-device isolation layer 114 and the adjacent inner wall 113 are integral in the vertically stacked semiconductor device of the embodiments of this disclosure.

[0091] According to embodiments of the present disclosure, in a first field-effect transistor, the gate stack includes a portion of the uppermost channel layer 101 among the plurality of channel layers 101 in the first field-effect transistor; and in a second field-effect transistor, the gate stack includes a portion of the lowermost channel layer 101 among the plurality of channel layers 101 in the second field-effect transistor. Therefore, the fabrication method of the present disclosure allows the gate stack to more comprehensively surround the channel layer 101, improving the performance of the fabricated semiconductor device.

[0092] According to embodiments of this disclosure, there are multiple sets of vertically stacked first and second field-effect transistors. Two sets of vertically stacked field-effect transistors in the multiple sets of vertically stacked field-effect transistors are configured as inverter structures. In the vertically stacked semiconductor device, the multiple inverter structures are cross-coupled to each other to form an SRAM structure.

[0093] According to embodiments of this disclosure, for two sets of vertically stacked field-effect transistors used to form an inverter structure, the drain layers of the two sets of vertically stacked field-effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal. In the two sets of vertically stacked field-effect transistors, the two source layers of one set of vertically stacked field-effect transistors are both electrically connected to the ground terminal, and the two source layers of the other set of vertically stacked field-effect transistors are respectively electrically connected to the bit line terminal and the power rail.

[0094] Specifically, the following are... Figure 50 The structure of the vertically stacked semiconductor device described above in this disclosure will be illustrated as an example. Figure 50 A schematic diagram of an SRAM structure implemented based on vertically stacked semiconductor devices according to an embodiment of the present disclosure is shown. It should be noted that... Figure 50 In this specification, the extension direction of the X-axis is defined as a first direction, the extension direction of the Y-axis is defined as a second direction intersecting the first direction, and the extension direction of the Z-axis is defined as a vertical direction. In one embodiment of this disclosure, the first direction and the second direction may be perpendicular to each other within the same horizontal plane. The vertical direction may be a direction perpendicular to the horizontal plane.

[0095] like Figure 50 As shown, the SRAM structure 5000 of this embodiment includes: the first group of field-effect transistors and the second group of field-effect transistors respectively arranged on the upper surface of the substrate SUB along a first direction, and an intermediary dielectric layer surrounding the substrate SUB, the first group of field-effect transistors and the second group of field-effect transistors.

[0096] exist Figure 50 Each field-effect transistor shown can be used as a transfer transistor or a pull-up transistor, etc., depending on actual needs. A transfer transistor can be used to transfer write data from a bit line. A pull-up transistor can include pull-up transistors and pull-down transistors. A pull-up transistor can be used to pull up node levels. A pull-down transistor can be used to pull down node levels. Furthermore, in... Figure 50 In order to avoid obscuring the SRAM structure 5000, Figure 50 The schematic diagram of the intermediary medium layer is omitted. It should be understood that the intermediary medium layer in the embodiments of this disclosure can be configured in the SRAM structure 5000 as needed.

[0097] Continue to refer to Figure 50 ,exist Figure 50 Two substrate sub-subs are shown arranged along a second horizontal direction. Multiple field-effect transistors integrated into a single structure are disposed on each of these two substrate sub-subs. Therefore, for ease of description, the structures located in this disclosure will be referred to as... Figure 50The multiple field-effect transistors on the substrate SUB at the lower left are defined as the first group of field-effect transistors mentioned above, and their... Figure 50 The space shown is located in front; and, will be located in Figure 50 The transistor on the upper right substrate is defined as the second group of field-effect transistors mentioned above, and its... Figure 50 The space shown is located at the rear.

[0098] The following will Figure 50 The field-effect transistors shown are defined as pull-out transistors or transport transistors to facilitate understanding of the SRAM structure 5000 of this disclosure embodiment. It should be understood that the following are merely examples, and those skilled in the art can configure the function of the field-effect transistors in the SRAM structure 5000 according to their needs.

[0099] For example, the transistor located at the upper left of the first group of field-effect transistors is defined as the transfer transistor AC1; the transistor located at the lower left of the first group of field-effect transistors is defined as the pull-down transistor PU1; and the transistor located at the upper right of the first group of field-effect transistors is defined as the pull-down transistor PD1. (See reference) Figure 50 It is known that the transfer transistor AC1 and the pull-down transistor PD1 are coupled through a common layer. Furthermore, based on the above, it is known that the upper and lower common layers of the first group of field-effect transistors are coupled through a connection structure. Based on this, electrical connections can be achieved between the transfer transistor AC1, the pull-up transistor PU1, and the pull-down transistor PD1. The common layer used for electrical connections between the transfer transistor AC1, the pull-up transistor PU1, and the pull-down transistor PD1 corresponds to the first source / drain layer of each of the transfer transistor AC1, the pull-up transistor PU1, and the pull-down transistor PD1. Specifically, the transfer transistor AC1 can be electrically connected to the bit line terminal through a source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the transfer transistor AC1, and the transfer transistor AC1 can be electrically connected to the word line terminal through a gate contact hole connected to its gate structure G. Pull-up transistor PU1 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of pull-up transistor PU1; pull-down transistor PD1 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of pull-down transistor PD1. Based on this, the pull-up transistors stacked in the first group of field-effect transistors can be configured as an inverter, with pull-up transistor PU1 implementing the level of the common layer and pull-down transistor PD1 implementing the level of the common layer.

[0100] Correspondingly, the transistor located at the upper right of the second group of field-effect transistors is defined as the transfer transistor AC2; the transistor located at the lower right of the second group of field-effect transistors is defined as the pull-up transistor PU2; and the transistor located at the upper left of the first group of field-effect transistors is defined as the pull-down transistor PD2. (Reference) Figure 50 It is known that the transfer transistor AC2 and the pull-down transistor PU2 are coupled through a common layer. Furthermore, based on the above, it is known that the upper and lower common layers of the second group of field-effect transistors are coupled through a connection structure. Based on this, electrical connections can be achieved between the transfer transistor AC2, the pull-up transistor PU2, and the pull-down transistor PD2. The common layer used for electrical connections between the transfer transistor AC2, the pull-up transistor PU2, and the pull-down transistor PD2 corresponds to the first source / drain layer of each of the transfer transistor AC2, the pull-up transistor PU2, and the pull-down transistor PD2. Specifically, the transfer transistor AC2 can be electrically connected to the bit line terminal through a source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the transfer transistor AC2, and the transfer transistor AC2 can be electrically connected to the word line terminal through a gate contact hole connected to its gate structure G. Pull-up transistor PU2 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of pull-up transistor PU2; pull-down transistor PD2 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of pull-down transistor PD2. Based on this, the stacked pull-up transistors in the second group of field-effect transistors can be configured as an inverter, with pull-up transistor PU2 achieving the level of the common layer and pull-down transistor PD2 achieving the level of the common layer.

[0101] In this embodiment, the gate structures of pull-up transistor PU1 and pull-down transistor PD1 are electrically connected to the common drain layer of the second group of field-effect transistors via contact holes, thereby connecting them to the second data output terminal. Similarly, the gate structures of pull-up transistor PU2 and pull-down transistor PD2 are electrically connected to the common drain layer of the first group of field-effect transistors via contact holes, thereby connecting them to the first data output terminal. The gate structures of transfer transistors AC1 and AC2 are electrically connected to the word line terminal via contact holes, thus realizing the SRAM structure of this disclosure.

[0102] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating a vertically stacked semiconductor device, comprising: A lower stacked structure, an intermediate layer, and an upper stacked structure are sequentially disposed on a substrate. The lower stacked structure and the upper stacked structure each include an alternately disposed channel layer and a sacrificial layer, wherein the sacrificial layer and the intermediate layer have etching selectivity relative to the substrate and the channel layer. The lower stacked structure, the intermediate layer, and the upper stacked structure, together with the upper part of the substrate, are patterned to form fins extending along a first direction; A sacrificial gate is formed on the substrate, extending along a second direction intersecting the first direction and thus intersecting the fin; A gate sidewall is formed on the sidewall of the sacrificial gate; Using the sacrificial gate and the gate sidewall as a mask, the lower stacked structure, the intermediate layer and the upper stacked structure are patterned, so that the patterned lower stacked structure, the intermediate layer and the upper stacked structure have side surfaces exposed in the first direction; The sacrificial layer and the intermediate layer are selectively etched via the exposed side surface, wherein the etching rate of the intermediate layer is higher than that of the sacrificial layer during the selective etching, such that when the selective etching is completed, the intermediate layer is removed while the sacrificial layer is retained, and the retained sacrificial layer is recessed at its end in the first direction relative to the channel layer. The space released in the fin due to the selective etching of the sacrificial layer and the intermediate layer is filled with a dielectric material, wherein the portion of the dielectric material filled at the end of the sacrificial layer serves as an inner sidewall, and the portion of the dielectric material filled between the lower stack and the upper stack serves as an inter-device isolation layer. A lower source / drain layer is formed that contacts the exposed side surface of the channel layer in the lower stacked structure, and an upper source / drain layer is formed that contacts the exposed side surface of the channel layer in the upper stacked structure; and Replace the sacrificial gate and the sacrificial layer with a gate stack.

2. The method according to claim 1, wherein, The intermediate layer and the sacrificial layer are made of the same material, but the doping ratios of the intermediate layer and the sacrificial layer are different, so that the etching rate of the intermediate layer is higher than that of the sacrificial layer.

3. The method according to claim 1, wherein, The method further includes: An intermediate dielectric layer is formed that covers the upper stacked structure, the upper source / drain layer, and the lower source / drain layer; The intervening dielectric layer is etched to form an opening in the dielectric layer that exposes the upper source / drain layer and the lower source / drain layer; Conductive material is disposed within the opening of the dielectric layer to form a contact hole, wherein the contact hole in the intervening dielectric layer enables the upper drain layer and the lower drain layer to be electrically connected to the data output terminal through the contact hole, and enables: the unpowered lower source layer not electrically connected to the power supply to be electrically connected to the ground terminal, and the upper source layer located directly above the unpowered lower source layer to be electrically connected to the ground terminal; or, the upper source layer located directly above the powered lower source layer electrically connected to the power supply to be electrically connected to the bit line terminal.

4. The method according to claim 3, wherein, A shallow trench isolation element is provided next to the upper part of the substrate; a power rail for electrical connection to the power source is pre-embedded in the shallow trench isolation element. The method further includes: The shallow trench isolator is etched according to the position of the lower source layer and the position of the power rail to form an opening in the isolator that exposes the lower source layer and the power rail; A conductive material is filled into the opening of the isolator, and after filling the conductive material, a dielectric material is used to seal the opening of the isolator, thereby forming a contact hole that electrically connects the lower source layer to the power rail.

5. The method according to claim 1, wherein, The formation of a lower source / drain layer that contacts the exposed side surface of the channel layer in the lower stacked structure and an upper source / drain layer that contacts the exposed side surface of the channel layer in the upper stacked structure includes: A protective sidewall for protecting the upper laminate structure is formed on the substrate; In the unprotected area between the protective sidewall and the substrate, a first electrode material layer is formed that is in contact with the lower stacked structure; The first electrode material layer is in-situ doped to obtain the lower source / drain layer; A dielectric material is deposited above the lower source / drain layer to form an inter-device isolation layer that isolates the lower source / drain layer and the upper source / drain layer; Remove the protective sidewalls exposed outside the inter-device isolation layer; A second electrode material layer is formed on the inter-device isolation layer, which is in contact with the upper stacked structure; The second electrode material layer is in-situ doped to form the upper source / drain layer; The lower source / drain layer and the upper source / drain layer are activated.

6. A vertically stacked semiconductor device, comprising: A first field-effect transistor and a second field-effect transistor are stacked on a substrate in a vertical direction; as well as The inter-device isolation layer between the first field-effect transistor and the second field-effect transistor, Wherein, the first field-effect transistor and the second field-effect transistor each include: Multiple channel layers stacked at intervals in the vertical direction; Source / drain layers that are in contact with the channel layers on both sides in the first direction; A gate stack extending in a second direction intersecting the first direction and surrounding the channel layer; and The inner wall between the gate stack and the source / drain layer, The inner walls of the first field-effect transistor and the second field-effect transistor each have substantially aligned outer surfaces.

7. The vertically stacked semiconductor device according to claim 6, wherein, The device isolation layer is integrated with the adjacent inner wall.

8. The vertically stacked semiconductor device according to claim 6, wherein, In the first field-effect transistor, the gate stack includes a portion of the upper surface of the uppermost channel layer among the plurality of channel layers in the first field-effect transistor. In the second field-effect transistor, the gate stack includes a portion of the lower surface of the lowermost channel layer among the plurality of channel layers in the second field-effect transistor.

9. The vertically stacked semiconductor device according to claim 6, wherein, The first and second field-effect transistors are stacked vertically in multiple groups. Two of the stacked field-effect transistors form an inverter structure. In the vertically stacked semiconductor device, the multiple inverter structures are cross-coupled to each other to form an SRAM structure.

10. The vertical complementary field-effect transistor according to claim 9, wherein, For the two sets of vertically stacked field-effect transistors used to form the inverter structure, the drain layers of the two sets of vertically stacked field-effect transistors are shared, and the shared drain layer is electrically connected to the signal output terminal; in the two sets of vertically stacked field-effect transistors, the two source layers of one set of vertically stacked field-effect transistors are electrically connected to the ground terminal, and the two source layers of the other set of vertically stacked field-effect transistors are electrically connected to the bit line terminal and the power rail, respectively.

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