Semiconductor device

Abstract

The invention discloses a semiconductor device, and belongs to the technical field of semiconductors. The semiconductor device includes: a substrate; the drift region is positioned on one longitudinal side of the substrate; the resistance voltage divider comprises a resistor, a first electrode, a second electrode and a third electrode; the resistor is located on the side, away from the substrate, of the drift region, is insulated from the drift region and comprises a first end, a second end and a voltage dividing end located between the first end and the second end; the first electrode, the second electrode and the third electrode are located on the side, away from the substrate, of the resistor and are correspondingly connected with the first end, the second end and the voltage dividing end of the resistor respectively. The first well region is located in the drift region at the bottom of the resistor and is opposite to the drift region in doping type, the first well region corresponds to the resistor in position, and the cross section of the first well region is matched with the cross section of the resistor in shape. According to the invention, the uniformity of charge electric field distribution in the resistor can be improved, so that the stability of the output voltage of the resistance voltage divider and the overall stability and reliability of the device are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a semiconductor device. Background Art

[0002] As one of the most basic components of electronic circuits, the development of integrated resistor dividers is inseparable from the progress of semiconductor technology. With the popularization of electronic devices and the development of integrated circuit technology, resistor dividers have begun to be widely used in various electronic devices. It can effectively generate the required reference voltage or adjust the level during signal processing. In power integrated circuits, resistor dividers still play an important role. Its simple and easy-to-use characteristics make it an indispensable part of the design. The resistor divider consists of two or more resistors in series. It is very simple to design and build, without complex circuit configuration, and can obtain different output voltages by adjusting the resistance value as needed, with high adjustability. The resistor divider can be easily integrated into existing circuits and is suitable for various application scenarios, such as signal conditioning, measurement, and sensor interface.

[0003] Resistor voltage dividers are widely used in power integrated circuits due to their simplicity and low cost. However, the resistor voltage dividers in related technologies are easily affected by external loads, which makes the electric field distribution of charges in the resistors uneven, causing the output voltage of the resistor voltage divider to change with the load, affecting the stability of the output voltage of the resistor voltage divider and the stability and reliability of the device as a whole. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a semiconductor device that can improve the uniformity of the electric field distribution of the charge in the resistor, thereby improving the output voltage stability of the resistor divider, and further optimizing the overall stability and reliability of the device.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] substrate;

[0007] A drift region, located on one side of the substrate in the longitudinal direction;

[0008] A resistor voltage divider, comprising a resistor, a first electrode, a second electrode and a third electrode; the resistor is located at a side of the drift region away from the substrate and is insulated from the drift region, the resistor comprises a first end, a second end and a voltage divider end located between the first end and the second end; the first electrode, the second electrode and the third electrode are located at a side of the resistor away from the substrate and are respectively connected to the first end, the second end and the voltage divider end of the resistor;

[0009] The first well region is located in the drift region at the bottom of the resistor and has a doping type opposite to that of the drift region. The first well region corresponds to the position of the resistor, and a cross section of the first well region matches the shape of a cross section of the resistor.

[0010] According to the semiconductor device of the present application, a first well region corresponding to the position of the resistor is set in the drift region at the bottom of the resistor, the cross-section of the first well region matches the shape of the cross-section of the resistor, and the doping type of the first well region is opposite to that of the drift region, so as to expand the width of the depletion region in the drift region, and a PN junction is formed between the first well region and the drift region, so that the surface electric field of the drift region introduces more electric field peaks, thereby making the surface electric field distribution more uniform, and then the electric field distribution in the resistor is balanced by the silicon surface electric field of the device, thereby improving the uniformity of the charge electric field distribution in the resistor divider, stabilizing the resistor voltage divider, and thus improving the overall stability of the device.

[0011] According to one embodiment of the present application, an orthographic projection of the resistor on the substrate is located within an orthographic projection of the first well region on the substrate.

[0012] According to an embodiment of the present application, the first well region is a floating well region.

[0013] According to one embodiment of the present application, the semiconductor device further includes:

[0014] The fourth electrode is located at a side of the resistor away from the substrate and is connected to the first well region.

[0015] According to one embodiment of the present application, the fourth electrode is connected to the second electrode.

[0016] According to an embodiment of the present application, the first well region is located on a side of the drift region close to the resistor, or the first well region is located inside the drift region.

[0017] According to one embodiment of the present application, the cross-section of the resistor is spiral-shaped, the first end is the inner end of the resistor, the second end is the outer end of the resistor, the cross-section of the first well region is spiral-shaped, and the number of spiral turns of the first well region is the same as the number of spiral turns of the resistor.

[0018] According to an embodiment of the present application, a cross section of the resistor is in a folded spiral shape, and a cross section of the first well region is in a folded spiral shape.

[0019] According to one embodiment of the present application, the semiconductor device further includes:

[0020] The second well region, the first well region has a plurality of spiral turns, the second well region is located in the drift region between adjacent spiral turns of the first well region, the second well region has the same doping type as the drift region, and the doping concentration of the second well region is greater than the doping concentration of the drift region.

[0021] According to an embodiment of the present application, a cross section of the second well region is spiral-shaped.

[0022] According to an embodiment of the present application, the resistor is a positive temperature coefficient resistor.

[0023] According to an embodiment of the present application, the resistor includes a polysilicon layer and a metal silicide layer located on a side of the polysilicon layer facing away from the substrate.

[0024] According to one embodiment of the present application, the semiconductor device further includes:

[0025] The transistor comprises a source, a drain and a gate, and is located on a side of the drift region away from the substrate. The resistor is arranged around the drain, and the drain is connected to the first electrode. The gate is arranged around the resistor, and the source is arranged around the gate.

[0026] According to one embodiment of the present application, the transistor further includes:

[0027] A first body region, located on one side of the substrate in the longitudinal direction and laterally adjacent to the drift region;

[0028] a second body region, located on the first body region;

[0029] A drain region, located on the drift region at the bottom of the drain, and the drain is in ohmic contact with the drain region;

[0030] A source region, located at the bottom of the source electrode, and the source electrode is in ohmic contact with the source region;

[0031] Wherein, the source region is located on the drift region at the bottom of the source, and the transistor also includes a body electrode located on the side of the second body region away from the first body region, the body electrode is arranged around the source, and the body electrode is in ohmic contact with the second body region; or, the source region is located on the first body region at the bottom of the source and is laterally adjacent to the second body region, and the source is also in ohmic contact with the second body region.

[0032] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0033] A first well region corresponding to the position of the resistor is arranged in the drift region at the bottom of the resistor, the cross section of the first well region matches the shape of the cross section of the resistor, and the doping type of the first well region is opposite to that of the drift region, so as to expand the width of the depletion region in the drift region, and a PN junction is formed between the first well region and the drift region, so that the surface electric field of the drift region introduces more electric field peaks, thereby making the surface electric field distribution more uniform, and then balancing the electric field distribution in the resistor through the device silicon surface electric field, improving the uniformity of the electric field distribution of the charge in the resistor voltage divider, stabilizing the resistor voltage division, and thus improving the circuit stability;

[0034] Furthermore, a positive temperature coefficient resistor is integrated in the drift region, and the resistor with a positive temperature effect becomes larger after absorbing heat, thereby reducing power loss.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 It is one of the structural schematic diagrams of the semiconductor device provided in the embodiment of the present application;

[0038] Figure 2 is one of the cross-sectional views of the semiconductor device provided in the embodiment of the present application;

[0039] Figure 3 This is the second cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0040] Figure 4 This is the second structural schematic diagram of the semiconductor device provided in the embodiment of the present application;

[0041] Figure 5 This is the third cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0042] Figure 6 This is the fourth cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0043] Figure 7 This is the fifth cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0044] Figure 8 This is the third structural schematic diagram of the semiconductor device provided in the embodiment of the present application;

[0045] Fig. 9 This is the sixth cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0046] Fig.10 This is the seventh cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0047] Fig.11 This is the fourth structural schematic diagram of the semiconductor device provided in the embodiment of the present application;

[0048] Fig.12 This is the eighth cross-sectional view of the semiconductor device provided in the embodiment of the present application;

[0049] Fig.13 is a ninth cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0050] Fig.14 It is a circuit diagram of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0052] The semiconductor device provided by the embodiments of the present application is described below with reference to the accompanying drawings.

[0053] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application, Figure 2 for Figure 1 Schematic diagram of the cross section at the dotted line AA', Figure 3 for Figure 1 The cross-sectional view at the dotted line BB' is shown in FIG.

[0054] Combination Figures 1 to 3 As shown, the semiconductor device provided in the embodiment of the present application includes a substrate 14, a drift region 13, a resistor divider and a first well region 15. Among them, the substrate 1 can be a silicon substrate (such as bulk silicon) or a germanium substrate, or a semiconductor substrate including other elements. The substrate 1 can be a first doping type substrate, and the first doping type can be P-type or N-type. For example, a trace amount of trivalent elements, such as boron, indium, gallium, aluminum, etc., can be doped into the substrate 1 to form a P-type semiconductor substrate; a trace amount of pentavalent elements, such as phosphorus, antimony, arsenic, etc., can also be doped into the substrate to form an N-type semiconductor substrate.

[0055] The drift region 13 is located on one side of the longitudinal direction Y of the substrate 14, and the longitudinal direction Y is perpendicular to the upper surface of the substrate 14. An epitaxial layer is formed by depositing on the substrate 14, and ion implantation is performed in the top area of ​​the epitaxial layer to form the drift region 13. The drift region 13 has a second doping type, and the second doping type can be P type or N type. The second doping type is opposite to the first doping type, that is, the doping type of the drift region 13 is opposite to that of the substrate 14. In some embodiments, the semiconductor device also includes a dielectric layer 8, which is located on the side of the drift region 13 away from the substrate 14 and covers the epitaxial layer. The dielectric layer 8 may include silicon oxide, silicon nitride, such as SiO2, Si3N4, etc.

[0056] The resistor divider includes a resistor 4, a first electrode 17, a second electrode 5, and a third electrode 6. The resistor 4 is located on the side of the drift region 13 facing away from the substrate 14, and the resistor 4 is insulated from the drift region 13. In some embodiments, the resistor 4 is located inside the dielectric layer 8, and the dielectric layer 8 is disposed between the resistor 4 and the drift region 13.

[0057] The resistor 4 can be linear, such as spiral, and extend in a plane parallel to the upper surface of the substrate 14. The resistor 4 includes a first end, a second end and a voltage divider end, and the first end and the second end are two ends of the resistor 4 respectively. The voltage divider end is located between the first end and the second end, and is used to divide the resistor 4 into two resistors connected in series. For example, the resistor 4 between the first end and the voltage divider end can constitute a resistor R1, and the resistor 4 between the voltage divider end and the second end can constitute a resistor R2, and the resistor R1 and the resistor R2 are connected in series. By adjusting the position of the voltage divider end on the resistor 4, the size of the resistor R1 and the resistor R2 can be adjusted, thereby adjusting the voltage division of the resistor divider.

[0058] The first electrode 17 is located on the side of the resistor 4 facing away from the substrate 13, and the first electrode 17 is connected to the first end of the resistor 4. In some embodiments, the first electrode 17 is located on the side of the dielectric layer 8 facing away from the substrate 14, and extends into the dielectric layer 8 along the longitudinal direction Y to connect to the first end of the resistor 4. The first electrode 17 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel, and titanium.

[0059] The second electrode 5 is located on the side of the resistor 4 facing away from the substrate 13, and the second electrode 5 is connected to the second end of the resistor 4. In some embodiments, the second electrode 5 is located on the side of the dielectric layer 8 facing away from the substrate 14, and extends into the dielectric layer 8 along the longitudinal direction Y to connect to the second end of the resistor 4. The second electrode 5 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel, and titanium.

[0060] The third electrode 6 is located on the side of the resistor 4 facing away from the substrate 13, and the third electrode 6 is connected to the voltage divider end of the resistor 4. In some embodiments, the third electrode 6 is located on the side of the dielectric layer 8 facing away from the substrate 14, and extends into the dielectric layer 8 along the longitudinal direction Y to be connected to the voltage divider end of the resistor 4. The third electrode 6 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel, and titanium.

[0061] Wherein, the first electrode 17 can be the positive electrode of the resistor divider, connected to the high voltage input port, so that the first end of the resistor 4 is connected to the high voltage input port through the first electrode 17. In the case where the semiconductor device is applied to a power integrated device, the first electrode 17 can be connected to a transistor (such as a drain of a transistor). The second electrode 5 can be the negative electrode of the resistor divider, grounded, so that the second end of the resistor 4 is grounded through the second electrode 5. The third electrode 6 can be the output electrode of the resistor divider, connected to the voltage dividing port, so that the voltage dividing end of the resistor 4 is connected to the voltage dividing port through the third electrode 6.

[0062] The first well region 15 is located in the drift region 13, and the first well region 15 has a first doping type, that is, the doping type of the first well region 15 is opposite to that of the drift region 13, so that a PN junction is formed between the first well region 15 and the drift region 13. The first well region 15 is located at the bottom of the resistor 4, and the first well region 15 corresponds to the position of the resistor 4. The transverse X-section of the first well region 15 matches the shape of the transverse X-section of the resistor 4, and the transverse X-section of the first well region 15 is the same as the shape of the transverse X-section of the resistor 4, and the area size can be the same or different. For example, when the transverse X-section of the resistor 4 is spiral, the transverse X-section of the first well region 15 is spiral.

[0063] The width, spacing, height and doping concentration of the first well region 15 can be set according to actual needs and are not specifically limited here. By adjusting the width and spacing of the first well region 15, for example, adjusting the width and spacing of the first well region 15 to be consistent, the position of the PN junction formed between the first well region 15 and the drift region 13 can be adjusted to balance the device surface electric field.

[0064] The related art does not set the first well region, and the resistor voltage division is greatly affected by the load, which is not conducive to the stability and reliability of the device as a whole. In this embodiment, the first well region 15 is set in the drift region 13 at the bottom of the resistor 4 to assist the substrate 14 in depleting the drift region 13, expand the width of the device depletion region, and then optimize the device silicon surface electric field distribution. In addition, multiple PN junctions are formed between the first well region 15 and the drift region 13 (both sides of the first well region 15 are drift regions 13, so that the first well region 15 and the drift regions 13 on both sides constitute multiple PN junctions), so that the surface electric field introduces more electric field peaks, so that the surface electric field distribution is more uniform and all are high electric fields, and the transistor withstand voltage is improved. In addition, the uniformly distributed silicon surface electric field of the device will act on the resistor 4, so that the electric field distribution in the resistor 4 is stable, thereby stabilizing the voltage division of the resistor divider, so that the output voltage of the third electrode 6 is stable and does not change significantly with the load change. In addition, the introduction of the first well region 15 will increase the withstand voltage of the transistor connected to the resistor divider. By increasing the doping concentration of the drift region 13, the saturation current of the transistor can be increased without reducing the withstand voltage of the transistor, thereby accelerating the charging speed of the transistor.

[0065] In some embodiments, Figure 1 As shown, the transverse X-section of the resistor 4 is spiral, and the transverse X is perpendicular to the longitudinal Y and parallel to the upper surface of the substrate 14. The first end of the resistor 4 is the inner end of the resistor 4, and the second end of the resistor 4 is the outer end of the resistor 4. The resistor 4 can extend in a spiral shape with the first end as the spiral center. The transverse X-section of the first well region 15 is spiral. The number of spiral turns of the first well region 15 and the number of spiral turns of the resistor 4 can be the same.

[0066] In this embodiment, the resistor 4 extends in a spiral shape, which can reduce the occupied area of ​​the resistor 4 and increase the length of the resistor 4, thereby increasing the resistance value of the resistor 4, improving the device integration, and reducing static power consumption.

[0067] In some embodiments, the helical shape comprises a folded helical shape. Figure 4 As shown, the transverse X-section of the resistor 4 is in a folded spiral shape, and the transverse X-section of the first well region 15 is in a folded spiral shape. Specifically, the resistor 4 extends in a circular shape along the first direction (such as the clockwise direction) from the first end (the end connected to the first electrode 17), turns back and extends in a circular shape along the second direction (such as the counterclockwise direction) near the first end, and then turns back and extends in a circular shape along the first direction near the first end, and so on, until the resistor 4 cannot extend in its occupied area.

[0068] In this embodiment, the occupied area of ​​the resistor 4 remains unchanged. Figure 1 The spiral structure in Figure 4The folded spiral structure can further increase the length of the resistor 4, further increase the resistance value of the resistor 4, improve the device integration, and reduce static power consumption.

[0069] In some embodiments, the resistor 4 is a positive temperature coefficient resistor, which is a resistor whose resistance value increases significantly as the temperature increases.

[0070] In some embodiments, the resistor 4 includes a polysilicon layer and a metal silicide layer, and the metal silicide layer is located on a side of the polysilicon layer facing away from the substrate 14 , so that the resistor 4 is a positive temperature coefficient resistor.

[0071] In this embodiment, a positive temperature coefficient resistor is integrated on the drift region 13. The heat generated when the device is turned on is absorbed by the positive temperature coefficient resistor, which increases the resistance value of the resistor and reduces the current on the resistor, thereby reducing the power loss of the device.

[0072] In some embodiments, the orthographic projection of the resistor 4 on the substrate 14 is located within the orthographic projection of the first well region 15 on the substrate 14. The first well region 15 corresponds to the position of the resistor 4, and the width of the first well region 15 can be greater than or equal to the width of the resistor 4, so as to further optimize the surface electric field, adjust the electric field inside the resistor 4, and stabilize the resistor voltage division.

[0073] In some embodiments, the first well region 15 is a floating well region, and the first well region 15 is not connected to any electrode.

[0074] In some embodiments, Figure 2 and Figure 3 As shown, the first well region 15 is located on the side of the drift region 13 close to the resistor 4. In the longitudinal direction Y, the upper surface of the first well region 15 (i.e., the surface of the first well region 15 close to the resistor 4) can be flush with the upper surface of the drift region 13 (i.e., the surface of the drift region 13 close to the resistor 4), and the lower surface of the first well region 15 (i.e., the surface of the first well region 15 away from the resistor 4) can be spaced from the lower surface of the drift region 13 (i.e., the surface of the back side of the drift region 13 on the resistor 4 side).

[0075] In some embodiments, Figure 5 As shown, the first well region 15 is located inside the drift region 13. In the longitudinal direction Y, the upper surface of the first well region 15 is spaced apart from the upper surface of the drift region 13, and the lower surface of the first well region 15 is spaced apart from the lower surface of the drift region 13. For example, the first well region 15 can be disposed near the middle of the longitudinal direction Y of the drift region 13.

[0076] In this embodiment, the first well region 15 is located inside the drift region 13, so that the depletion region of the surrounding drift region 13 is expanded, the withstand voltage is increased and the on-resistance of the transistor connected to the resistor divider is reduced, the device surface electric field distribution is further optimized, and the output voltage of the resistor divider is stabilized.

[0077] In some embodiments, Figure 6 and Figure 7 As shown, the semiconductor device further includes a second well region 16, and the second well region 16 is located in the drift region 13 between the first well regions 15. The transverse X-section of the first well region 15 is spiral-shaped, and the first well region 15 has a plurality of spiral turns, and there is a gap between adjacent spiral turns. The second well region 16 is located in the drift region 13 between adjacent spiral turns of the first well region 15. The gap between the first well regions 15 is small, and the second well region 16 can be adjacent to the first well regions 15. The second well region 16 has a second doping type, that is, the second well region 16 has the same doping type as the drift region 13, and is opposite to the doping type of the first well region 15. The doping concentration of the second well region 16 is greater than the doping concentration of the drift region 13.

[0078] In this embodiment, the second well region 16 is arranged between the first well regions 15, so as to prevent the first well regions 15 from diffusing into one piece during the thermal process due to the reduced spacing. Moreover, the doping concentration of the second well region 16 is greater than the doping concentration of the drift region 13, so that the depletion region forming the PN junction between the second well region 16 and the first well region 15 is less likely to be penetrated than the depletion region forming the PN junction between the first well region 15 and the drift region 13, thereby further reducing the width and spacing between the resistor 4 and the first well region 15, and increasing the length of the resistor 4 while keeping the occupied area of ​​the resistor 4 unchanged, further increasing the resistance value of the resistor 4, improving the device integration, and reducing the static power consumption.

[0079] The second well region 16 may have the same height as the first well region 15 , the upper surface of the second well region 16 may be flush with the upper surface of the first well region 15 , and the lower surface of the second well region 16 may be flush with the lower surface of the first well region 15 .

[0080] like Figure 6 As shown, the first well region 15 can be located at the top of the drift region 13 (i.e., the side of the drift region 13 close to the resistor 4), the second well region 16 is located at the top of the drift region 13 (i.e., the side of the drift region 13 close to the resistor 4), and the second well region 16 is flush with the upper and lower surfaces of the first well region 15. Figure 7 As shown, the first well region 15 may also be located inside the drift region 13 , and the second well region 16 is located inside the drift region 13 , and the upper and lower surfaces of the second well region 16 and the first well region 15 are flush with each other.

[0081] The first well region 15 extracts minority carriers from the surface of the drift region 13, and the second well region 16 extracts majority carriers from the surface of the drift region 13, further optimizing the surface charge distribution, thereby stabilizing the electric field balance of the charges in the resistor and stabilizing the resistor voltage division.

[0082] In some embodiments, the cross section of the resistor 4 is spiral, the cross section of the first well region 15 is spiral, and the gaps between adjacent spiral turns of the first well region 15 are all provided with the second well region 16, so that the cross section of the second well region 16 is spiral.

[0083] In some embodiments, Figures 8 to 10 As shown, Fig. 9 for Figure 8 Schematic diagram of the cross section at the dotted line CC', Fig.10 for Figure 8 The semiconductor device further comprises a fourth electrode 19, which is located on the side of the resistor 4 away from the substrate 14 and connected to the first well region 15, that is, the first well region 15 is not floating but connected to a fixed potential.

[0084] The first well region 15 may be located on the side of the drift region 13 close to the resistor 4, and the first well region 15 is also located inside the drift region 13. In the case where the first well region 15 is located on the side of the drift region 13 close to the resistor 4, the fourth electrode 19 may be located on the side of the dielectric layer 8 away from the substrate 14, and the longitudinal direction Y penetrates the dielectric layer 8 and is connected to the first well region 15. In the case where the first well region 15 is located inside the drift region 13, the fourth electrode 19 may be located on the side of the dielectric layer 8 away from the substrate 14, and the longitudinal direction Y penetrates the dielectric layer 8 and extends into the drift region 13 to connect to the first well region 15. A spacer layer may be provided around the fourth electrode 19 extending into the drift region 13 to isolate the fourth electrode 19 from the drift region 13.

[0085] This embodiment can adjust the device surface electric field by controlling the fixed potential, and further adjust the internal electric field of the resistor 4, so that the internal electric field distribution of the resistor 4 is more stable and uniform, thereby maintaining a linear relationship between the voltage drop on the resistor 4 and the length of the resistor 4.

[0086] In some embodiments, the fourth electrode 19 is spaced apart from other electrodes (including the second electrode 5), that is, the fourth electrode 19 can be connected to a potential alone. By controlling the potential of the fourth electrode 19, the internal electric field of the resistor is adjusted to improve the stability of the output voltage of the resistor divider.

[0087] In some embodiments, Figure 8 As shown, the fourth electrode 19 is connected to the second electrode 5, that is, the fourth electrode 19 is not connected to a potential alone. By controlling the potential of the second electrode 5 and the potential of the fourth electrode 19 at the same time, the internal electric field of the resistor is adjusted to improve the stability of the output voltage of the resistor divider.

[0088] In some embodiments, the semiconductor device further comprises a transistor, such as Figures 1 to 3As shown, the transistor includes a source 2, a drain 7 and a gate 3, and the source 2, the drain 7 and the gate 3 are located on the side of the drift region 13 away from the substrate 14. The resistor 4 is arranged around the drain 7, and the drain 7 is connected to the first electrode 17, the gate 3 is arranged around the resistor 4, and the source 2 is arranged around the gate 3. In some embodiments, the source 2 and the drain 7 are located on the side of the dielectric layer 8 away from the substrate 14, and the source 2, the drain 7, the first electrode 17, the second electrode 5 and the third electrode 6 can be arranged in the same layer. The gate 3 can be located inside the dielectric layer 8, and the dielectric layer 8 is arranged between the gate 3 and the drift region 13, and the gate 3 and the resistor 4 can be arranged in the same layer.

[0089] The drain electrode 7 may be located at the center of the resistor 4 and connected to the first electrode 17 to be connected to the high voltage input port. The cross section of the drain electrode 7 may be circular. The cross section of the gate 3 may be in a closed shape, such as a ring, and the resistor 4 is located inside the gate 3. The cross section of the source electrode 2 may be in a closed shape, such as a ring, and the gate 3 is located inside the source electrode 2. The source electrode 2 and the drain electrode 7 may include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel and titanium. The gate 3 may include polysilicon, etc.

[0090] The transistor may include a JFET, an LDMOS, an IGBT or a super junction (SJ) transistor, etc. The transistor may also be other types of transistors, which are not specifically limited here.

[0091] In some embodiments, the transistor further includes a drain region 11 and a source region 10. The drain region 11 is located on the drift region 13 at the bottom of the drain 7, and the drain region 11 has a second doping type, that is, the drain region 11 has the same doping type as the drift region 13. The drain region 11 corresponds to the position of the drain 7, and the drain 7 is in ohmic contact with the drain region 11. In some embodiments, the dielectric layer 8 covers the drain region 11 and is arranged around the drain region 11 to isolate the drain region 11. The drain is located on the side of the dielectric layer 8 away from the substrate 14, and penetrates the dielectric layer 8 in the longitudinal direction Y to connect with the drain region 11.

[0092] The source region 10 is located at the bottom of the source 2, and the source region 10 has the second doping type, that is, the source region 10 has the same doping type as the drift region 13. The source region 10 corresponds to the position of the source 2, and the source 2 is in ohmic contact with the source region 10. In some embodiments, the dielectric layer 8 covers the source region 10 and is arranged around the source region 10 to isolate the source region 10, and the source 2 is located on the side of the dielectric layer 8 away from the substrate 14, and penetrates the dielectric layer 8 in the longitudinal direction Y to connect with the source region 10.

[0093] The specific position of the source region 10 is related to the type of transistor, that is, the specific position of the source region 10 may be different for different types of transistors.

[0094] In the case where the transistor comprises a JFET transistor, such as Figure 2 and Figure 3 As shown, the source region 10 is located on the drift region 13 at the bottom of the source 2 (that is, the source 2 is located above the drift region 13). The transistor also includes a first body region 12, a second body region 9 and a body electrode 1. The body electrode 1 is arranged around the source 2, and the cross-section of the body electrode 1 can be a closed shape, such as a ring, and the source 2 is located on the inner side of the body electrode 1. Among them, the body electrode 1 can include one or more combinations of metals such as copper, aluminum, tungsten, platinum, nickel and titanium.

[0095] The first body region 12 is located on one side of the substrate 14 in the longitudinal direction Y and is adjacent to the drift region 13 in the lateral direction X, that is, the first body region 12 is arranged close to the upper surface of the substrate 14. The first body region 12 has a first doping type, that is, the first body region 12 and the substrate 14 have the same doping type.

[0096] The second body region 9 is located on the first body region 12 at the bottom of the body electrode 1, and the body electrode 1 is in ohmic contact with the first body region 12. The second body region 9 has a first doping type, that is, the second body region 9 has the same doping type as the first body region 12. In some embodiments, the dielectric layer 8 covers the first body region 12 and the second body region 9, and is disposed around the second body region 9 to isolate the second body region 9. The body electrode 1 is located on the side of the dielectric layer 8 facing away from the substrate 14, and penetrates the dielectric layer 8 in the longitudinal direction Y to connect with the second body region 9.

[0097] like Figures 11 to 13 As shown, Fig.12 for Fig.11 Schematic diagram of the cross section at the dashed line EE', Fig.13 for Fig.11 Schematic cross-sectional view at the dotted line FF' in the middle. In the case where the transistor includes an LDMOS transistor, the transistor also includes a first body region 12 and a second body region 9. The first body region 12 is located on one side of the substrate 14 in the longitudinal direction Y, and is adjacent to the drift region 13 in the transverse direction X. The second body region 9 is located on the first body region 12, and the source region 10 is located on the first body region 12 at the bottom of the source 2 (that is, the source 2 is located above the first body region 12), and the source region 10 is adjacent to the second body region 9 in the transverse direction X. The source 2 is in ohmic contact with the source region 10 and the second body region 9. In some embodiments, the dielectric layer 8 covers the source region 10 and the second body region 9, and is arranged around the source region 10 and the second body region 9 to isolate the source region 10 and the second body region 9. The source 2 is located on the side of the dielectric layer 8 away from the substrate 14, and penetrates the dielectric layer 8 in the longitudinal direction Y to connect with the source region 10 and the second body region 9.

[0098] In the LDMOS transistor, the source region 10 and the second body region 9 are short-circuited, and the resistance has a certain optimization effect on the carrier distribution on the device surface, making the saturation current of the LDMOS larger, while reducing the power loss of the device, improving the overall efficiency and reliability of the device, and making the device less prone to thermal burnout.

[0099] The equivalent circuit diagram of a semiconductor device can be shown as Fig.14 As shown. The semiconductor device includes a resistor divider 100 and a transistor 200. The partial resistance between the first end and the voltage dividing end of the resistor 4 in the resistor divider 100 constitutes a resistor R1, and the partial resistance between the voltage dividing end and the second end of the resistor 4 can constitute a resistor R2, and the resistor R1 and the resistor R2 are connected in series. The first end of the resistor 4 (i.e., the end of the resistor R1 away from the resistor R2) is connected to the high-voltage input port HV through the first electrode 17, the second end of the resistor 4 (i.e., the end of the resistor R2 away from the resistor R1) is grounded through the second electrode 5, and the voltage dividing end of the resistor 4 (i.e., the connection point of the resistor R1 and the resistor R2) is connected to the voltage dividing port HV_DIV through the third electrode 6. The drain 7 of the transistor 200 is connected to the high-voltage input port HV through the drain terminal D, the gate 3 of the transistor 200 is grounded through the gate terminal G, and the source 2 of the transistor 200 is connected to the voltage port HV_S through the source terminal S.

[0100] The output voltage of the voltage divider port HV_DIV is make K is a voltage division ratio coefficient. In this embodiment, the voltage division ratio coefficient K can be stabilized at 0.005-0.01, meeting the requirement of output voltage stability of the voltage division port HV_DIV.

[0101] In summary, according to the semiconductor device provided by the embodiment of the present application, a first well region 15 corresponding to the position of the resistor 4 is set in the drift region 13 at the bottom of the resistor 4, the cross section of the first well region 15 matches the shape of the cross section of the resistor 4, and the doping type of the first well region 15 is opposite to that of the drift region 13, so as to expand the width of the depletion region in the drift region, and a PN junction is formed between the first well region 15 and the drift region 13, so that the surface electric field of the drift region 13 introduces more electric field peaks, so that the surface electric field distribution is more uniform, and then the electric field distribution in the resistor is balanced by the silicon surface electric field of the device, the uniformity of the electric field distribution of the charge in the resistor divider is improved, and the stability of the output voltage of the resistor divider is improved, thereby improving the overall stability and reliability of the device. Moreover, a positive temperature coefficient resistor is integrated in the drift region 13, and the heat generated when the device is turned on is absorbed by the positive temperature coefficient resistor, so that the resistance value of the resistor is increased, and the current on the resistor is reduced, thereby reducing the power loss of the device.

[0102] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0103] In the description of the present application, “plurality” means two or more.

[0104] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0105] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: substrate; A drift region, located on one side of the substrate in the longitudinal direction; A resistor divider comprising a resistor, a first electrode, a second electrode and a third electrode; The resistor is located at a side of the drift region away from the substrate and is insulated from the drift region, and the resistor includes a first end, a second end, and a voltage divider end located between the first end and the second end; the first electrode, the second electrode, and the third electrode are located at a side of the resistor away from the substrate and are respectively connected to the first end, the second end, and the voltage divider end of the resistor; The first well region is located in the drift region at the bottom of the resistor and has a doping type opposite to that of the drift region. The first well region corresponds to the position of the resistor, and a cross section of the first well region matches the shape of a cross section of the resistor.

2. The semiconductor device according to claim 1, wherein: An orthographic projection of the resistor on the substrate is located within an orthographic projection of the first well region on the substrate.

3. The semiconductor device according to claim 1, wherein: The first well region is a floating well region.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The fourth electrode is located at a side of the resistor away from the substrate and is connected to the first well region.

5. The semiconductor device according to claim 4, characterized in that The fourth electrode is connected to the second electrode.

6. The semiconductor device according to claim 1, wherein: The first well region is located on a side of the drift region close to the resistor, or the first well region is located inside the drift region.

7. The semiconductor device according to claim 1, wherein: The cross section of the resistor is spiral-shaped, the first end is the inner end of the resistor, the second end is the outer end of the resistor, the cross section of the first well region is spiral-shaped, and the number of spiral turns of the first well region is the same as the number of spiral turns of the resistor; The spiral shape includes a folded spiral shape.

8. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises: a second well region, wherein the first well region has a plurality of spiral turns, the second well region is located in the drift region between adjacent spiral turns of the first well region, the second well region has the same doping type as the drift region, and the doping concentration of the second well region is greater than the doping concentration of the drift region; The cross section of the second well region is spiral-shaped.

9. The semiconductor device according to claim 1, wherein: The resistor is a positive temperature coefficient resistor; and / or, The resistor includes a polysilicon layer and a metal silicide layer located on a side of the polysilicon layer facing away from the substrate.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The semiconductor device further comprises: A transistor, comprising a source, a drain and a gate, located on a side of the drift region away from the substrate, the resistor is arranged around the drain, and the drain is connected to the first electrode, the gate is arranged around the resistor, and the source is arranged around the gate; The transistor further comprises: A first body region, located on one side of the substrate in the longitudinal direction and laterally adjacent to the drift region; a second body region, located on the first body region; A drain region, located on the drift region at the bottom of the drain, and the drain is in ohmic contact with the drain region; A source region, located at the bottom of the source electrode, and the source electrode is in ohmic contact with the source region; Wherein, the source region is located on the drift region at the bottom of the source, and the transistor also includes a body electrode located on the side of the second body region away from the first body region, the body electrode is arranged around the source, and the body electrode is in ohmic contact with the second body region; or, the source region is located on the first body region at the bottom of the source and is laterally adjacent to the second body region, and the source is also in ohmic contact with the second body region.

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