Integrated circuit including back contact and method of designing same

Abstract

An integrated circuit includes: a standard cell including a first transistor and a second transistor, each of the first transistor and the second transistor disposed on a front surface of a substrate; a back via hole passing through the substrate in a vertical direction relative to the substrate; a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected to a first source / drain of the first transistor through a backside via; and a back contact extending in the first direction between the standard cell and the back wiring layer and electrically connecting the second source / drain of the first transistor and the first source / drain of the second transistor, in which a bottom level of the back contact is different from a top level of the back power rail, and the back contact is electrically insulated from the back power rail.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0054978 filed on April 26, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0125003 filed on September 19, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit including a back side contact and a method of designing the integrated circuit. Background Art

[0004] As the demand for increased integration in the semiconductor industry grows, the width, spacing, and / or height of wiring included in an integrated circuit may decrease, and the adverse effects of parasitic elements of the wiring may increase. In addition, the power supply voltage of the integrated circuit may be reduced to reduce power consumption and operating speed, and due to this, the adverse effects of parasitic elements of the wiring on the integrated circuit may become more significant. Therefore, a method of designing an integrated circuit is needed for effectively routing wiring and vias while avoiding these adverse effects. Summary of the invention

[0005] The present disclosure provides an integrated circuit and a method of designing the same, in which power performance area (PPA) can be improved by using a back side contact or a back side wiring as a signal line.

[0006] Generally speaking, aspects of the subject matter described in this specification can be embodied in an integrated circuit comprising: a standard cell including a first transistor and a second transistor, each of the first transistor and the second transistor being disposed on a front side of a substrate; a back side via penetrating a substrate in a vertical direction relative to the substrate; a back side wiring layer including a back side power rail, the back side power rail being disposed on a back side of the substrate and connected to a first source / drain of the first transistor through the back side via; and a back side contact extending in a first direction between the standard cell and the back side wiring layer and electrically connecting the second source / drain of the first transistor to the first source / drain of the second transistor, wherein a bottom level of the back side contact is different from a top level of the back side power rail and the back side contact is electrically insulated from the back side power rail.

[0007] Another general aspect may be embodied in an integrated circuit comprising: a standard cell including a first transistor and a second transistor, each of the first transistor and the second transistor being disposed on a front side of a substrate; a back side via penetrating the substrate in a vertical direction relative to the substrate; a back side wiring layer including a back side power rail, the back side power rail being disposed on a back side of the substrate and connected to a source of the first transistor through the back side via; and a back side contact portion being disposed between the standard cell and the back side wiring layer to correspond to an output node of the standard cell and electrically connected to a drain of the second transistor, wherein a bottom level of the back side contact portion is different from a top level of the back side power rail, and the back side contact portion is electrically insulated from the back side power rail.

[0008] Another general aspect can be embodied in an integrated circuit, which includes: a standard cell, including a first transistor arranged on a front side of a substrate; a back side via, which passes through the substrate in a vertical direction relative to the substrate; a back side wiring layer, including a back side power rail, which is arranged on the back side of the substrate and connected to the source of the first transistor through the back side via; a first back side gate contact, which is connected to the gate of the first transistor to pass through the substrate in a vertical direction; and a first back side contact, which is arranged to extend in a first direction between the standard cell and the back side wiring layer, and is connected to the gate of the first transistor through the first back side gate contact, wherein a bottom level of the first back side contact is different from a top level of the back side power rail, and the first back side contact is electrically insulated from the back side power rail.

[0009] In some embodiments, the integrated circuit further includes: a front wiring layer disposed above the front side of the substrate. The front wiring layer may include: a first front wiring line electrically connected to the gate of the first transistor; and a second front wiring line electrically connected to the second source / drain of the second transistor. The first front wiring line and the second front wiring line extend along the first direction and are arranged in a row along the first direction.

[0010] In some embodiments, the front wiring layer further includes: a third front wiring line spaced apart from the first front wiring line or the second front wiring line in the second direction; and a fourth front wiring line spaced apart from the third front wiring line in the second direction. The second direction is perpendicular to the first direction.

[0011] In some embodiments, the back contact at least partially overlaps the first front side wiring line in the vertical direction, and at least partially overlaps the second front side wiring line in the vertical direction.

[0012] In some embodiments, the back contact does not overlap with the first front wiring line in the vertical direction and does not overlap with the second front wiring line in the vertical direction.

[0013] In some embodiments, the back contact at least partially overlaps the back power rail in a vertical direction.

[0014] In some embodiments, the back contact does not overlap the back power rail in the vertical direction.

[0015] In some embodiments, the back contact portion includes: a first pattern connected to the second source / drain of the first transistor and extending in a second direction perpendicular to the first direction; a second pattern connected to the first source / drain of the second transistor and extending in the second direction; and a third pattern electrically connecting the first pattern to the second pattern and extending in the first direction.

[0016] In some embodiments, the standard cell includes: a first active region extending along a first direction; and a second active region arranged to be separated from the first active region in a second direction perpendicular to the first direction to extend along the first direction; and the back contact portion includes: a first pattern overlapping with the first active region in a vertical direction and extending along the first direction; and a second pattern contacting the first pattern and extending along the second direction.

[0017] In some embodiments, the back contact further includes a third pattern that contacts the second pattern, overlaps the second active region in a vertical direction, and extends in the first direction.

[0018] In some embodiments, the first transistor and the second transistor are disposed in a first active region, the standard cell further includes a third transistor disposed in a second active region, the first pattern is connected to the drain of the second transistor, and the second pattern connects the drain of the third transistor to the drain of the second transistor.

[0019] In some embodiments, the integrated circuit includes: a front wiring layer disposed above the front side of the substrate. The front wiring layer may include: a first front wiring line extending along a first direction at an upper portion of the first active region; and a second front wiring line extending along the first direction at an upper portion of the second active region.

[0020] In some embodiments, the front side wiring layer further includes: a third front side wiring line extending from the first front side wiring line and the second front side wiring line along the first direction.

[0021] In some embodiments, the first front-side wiring line is connected to a gate of the second transistor.

[0022] In some embodiments, the standard cell further includes: a first active region and a second active region, the first active region and the second active region extending along a first direction and spaced apart from each other in a second direction perpendicular to the first direction, and the first back contact portion is disposed between the first active region and the second active region.

[0023] In some embodiments, the standard cell further includes: a first active region and a second active region, the first active region and the second active region extending along a first direction and spaced apart from each other in a second direction perpendicular to the first direction, and the first back contact portion at least partially overlaps with the first active region or the second active region along a vertical direction.

[0024] In some embodiments, the standard cell also includes a second transistor, and the integrated circuit also includes: a second back gate contact connected to the gate of the second transistor to pass through the substrate in a vertical direction; and a second back contact extending along the first direction between the standard cell and the back wiring layer and connected to the gate of the second transistor through the second back gate contact, and the first back contact and the second back contact are arranged in a row along the first direction.

[0025] In some embodiments, the standard cell further includes: a first active region and a second active region, the first active region and the second active region extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction. The integrated circuit may further include: a front wiring layer disposed above the front surface of the substrate. The front wiring layer may further include: a first front wiring line extending in the first direction at an upper portion of the first active region; a second front wiring line extending in the first direction at an upper portion of the second active region; and a third front wiring line extending from the first front wiring line and the second front wiring line in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 An example of a layout of an integrated circuit is shown.

[0027] Figure 2 Depicted with Figure 1 The circuit diagram corresponding to the integrated circuit.

[0028] Figure 3A It shows Figure 1 A plan view of an example of the front side of an integrated circuit, and Figure 3B It shows Figure 1 A plan view of an example of the back side of an integrated circuit.

[0029] Figure 4A is along Figure 1 An example of a cross-sectional view taken along line X1-X1', and Figure 4B is along Figure 1 An example of a cross-sectional view taken along line X2-X2'.

[0030] Figure 5 An example of a layout of an integrated circuit is shown.

[0031] Fig. 6A It shows Figure 5A plan view of an example of the front side of an integrated circuit, and Figure 6B It shows Figure 5 A plan view of an example of the back side of an integrated circuit.

[0032] Fig. 7A is along Figure 5 An example of a cross-sectional view taken along line X3-X3', and Figure 7B is along Figure 5 An example of a cross-sectional view taken along line X4-X4'.

[0033] Figure 8 An example of a layout of an integrated circuit is shown.

[0034] Fig. 9A is along Figure 8 An example of a cross-sectional view taken along line X5-X5', and Fig. 9B is along Figure 8 An example of a cross-sectional view taken along line X5a-X5a'.

[0035] Fig. 10A An example of a layout of an integrated circuit is shown, and Fig. 10B is along Fig. 10A An example of a cross-sectional view taken along line X5b-X5b'.

[0036] FIG. 11A to FIG. 11C An example of a layout of an integrated circuit is shown.

[0037] Fig.12 An example of a layout of an integrated circuit is shown.

[0038] Fig.13A is along Fig.12 An example of a cross-sectional view taken along line X6-X6', Fig. 13B is along Fig.12 An example of a cross-sectional view taken along line X7-X7', and Fig. 13C is along Fig.12 An example of a cross-sectional view taken along line Y1-Y1'.

[0039] Fig.14 An example of a layout of an integrated circuit is shown.

[0040] Fig.15 An example of a layout of an integrated circuit is shown.

[0041] Fig.16 is along Fig.15 An example of a cross-sectional view taken along line X8-X8'.

[0042] Fig.17 An example of a layout of an integrated circuit is shown.

[0043] Fig.18 An example of a layout of an integrated circuit is shown.

[0044] Fig.19 is along Fig.18 An example of a cross-sectional view taken along line X9-X9'.

[0045] Fig. 20 An example of a layout of an integrated circuit is shown.

[0046] Fig.21A is along Fig. 20 An example of a cross-sectional view taken along line X10-X10', and Fig. 21B is along Fig. 20 An example of a cross-sectional view taken along line X11-X11'.

[0047] FIG. 22A to FIG. 22D An example of a device is shown.

[0048] Fig.23 is a flow chart illustrating an example of a method of manufacturing an integrated circuit.

[0049] Fig.24 is an example of a block diagram showing a system on chip.

[0050] Fig.25 is an example of a block diagram illustrating a computing system including a memory storing programs.

[0051] The same reference numerals in the drawings refer to the same elements, and their repeated descriptions are omitted.

[0052] Here, the X-axis direction may be referred to as a first horizontal direction or a first direction, the Y-axis direction may be referred to as a second horizontal direction or a second direction, and the Z-axis direction may be referred to as a vertical direction. A plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, an element arranged along the +Z-axis direction relative to another element may be referred to as being on the other element, and an element arranged along the -Z-axis direction relative to another element may be referred to as being below the other element. DETAILED DESCRIPTION

[0053] An integrated circuit can be designed by arranging a plurality of standard cells. A standard cell can be a unit of a layout included in an integrated circuit, and in some embodiments, can be referred to as a cell. A standard cell can be designed to include a plurality of transistors in order to perform a predefined function. Such a standard cell scheme can be a method of pre-preparing standard cells and combining standard cells to design a dedicated large-scale integrated circuit customized to the specifications of a customer or user. Standard cells can be pre-designed and verified, and can be registered in a standard cell library, and integrated circuits can be designed by performing a logic design in which standard cells are combined, placed, and routed using computer-aided design (CAD). In the design of an integrated circuit, the length and routing complexity of wiring and / or vias can be reduced, and thus the performance of the integrated circuit can be further enhanced.

[0054] Figure 1 An example of a layout of integrated circuit 10 is shown.

[0055] Reference Figure 1 , the integrated circuit 10 includes a first active area RX1 and a second active area RX2, a gate line GT, a source / drain contact CA, a via VA, a front wiring layer M1, a back wiring layer BM, a back via BVA and a back gate contact BCB. In some embodiments, the integrated circuit 10 may be referred to as an integrated circuit device or a semiconductor device. For example, the gate line GT, the source / drain contact CA and the back gate contact BCB may constitute a standard cell SC, and the standard cell SC may be defined by a cell boundary BD. The front wiring layer M1 may be arranged above the standard cell SC in a vertical direction Z (e.g., perpendicular to a horizontal plane parallel to the XY plane). In the embodiments shown herein, the phrase "source / drain contact" may be understood to mean a contact to a source terminal region of a transistor and / or a contact to a drain terminal region. In addition, the phrase "source / drain region" may be understood to mean a source terminal region and / or a drain terminal region of a transistor.

[0056] The integrated circuit 10 may include a front wiring layer M1 and a back wiring layer BM, and a power distribution network (PDN) may be implemented by using the front wiring layer M1 and the back wiring layer BM. In this case, the front wiring layer M1 may be arranged above the standard cell SC in the vertical direction Z, and the back wiring layer BM may be arranged below the standard cell SC in the vertical direction Z. Therefore, some of each signal and / or power applied to the integrated circuit 10 may be transmitted through the front wiring layer M1, and other signals and / or power may be transmitted through the back wiring layer BM. Therefore, in some embodiments, compared with a structure in which wiring is only arranged above the front side of the substrate, the complexity of routing can be significantly reduced, and the length of each wiring or each via can also be reduced, thereby improving the performance of the integrated circuit 10.

[0057] Figure 2 is with Figure 1 A circuit diagram corresponding to the integrated circuit 10.

[0058] Combination Figure 1 Reference Figure 2 , the integrated circuit 10 includes P-type transistors PM1 and PM2 and N-type transistors NM1 and NM2. The P-type transistors PM1 and PM2 may be connected in parallel to each other, and the N-type transistors NM1 and NM2 may be connected in series to each other. As described above, the integrated circuit 10 may include a NAND gate cell, and the standard cell SC may correspond to the NAND gate cell.

[0059] The P-type transistor PM1 may include a source receiving the power supply voltage VDD, a gate receiving the first input signal A, and a drain connected to the output node OUT. The P-type transistor PM2 may include a source receiving the power supply voltage VDD, a gate receiving the second input signal B, and a drain connected to the output node OUT. The N-type transistor NM1 may include a source receiving the ground voltage VSS and a gate receiving the first input signal A. The N-type transistor NM2 may include a gate receiving the second input signal B and a drain connected to the output node OUT.

[0060] Figure 3A It shows Figure 1 FIG. 1 is a plan view of the front side of the integrated circuit 10 .

[0061] Reference Figure 1 , Figure 2 and Figure 3A , the integrated circuit 10 is implemented as a semiconductor device, and the substrate forming the semiconductor device may include a first surface and a second surface. The first surface may be, for example, a surface on which a circuit device such as a transistor is provided, and here, the first surface may be referred to as a front surface. The second surface may be, for example, a surface opposite to the first surface, and here, the second surface may be referred to as a back surface.

[0062] The first active region RX1 and the second active region RX2 may each extend along the first direction X on the front side of the substrate and may be separated from each other in the second direction Y. For example, each of the first active region RX1 and the second active region RX2 may be a diffusion region doped with impurities that change the electrical properties of the substrate material. For example, the length of each of the first active region RX1 and the second active region RX2 in the second direction Y may correspond to the length of the nanosheet stack (e.g., Figure 4AIn some embodiments, the P-type transistors PM1 and PM2 may be disposed in the first active region RX1, and the N-type transistors NM1 and NM2 may be disposed in the second active region RX2. However, the inventive concept is not limited thereto, and in other examples, the N-type transistors NM1 and NM2 may be disposed in the first active region RX1, and the P-type transistors PM1 and PM2 may be disposed in the second active region RX2.

[0063] The gate line GT may include a first gate line GT1 and a second gate line GT2, each of which extends in the second direction Y and is separated from each other in the first direction X. The gate line GT may be defined as a conductive segment including a conductive material such as one or more metals or polysilicon. The source / drain contact CA may be disposed on the first active region RX1 or the second active region RX2, and each may extend in the second direction Y.

[0064] The front wiring layers M1 and M2 may each be used as a signal wiring for transmitting a signal for the integrated circuit 10, and the back wiring layer BM may be used as a signal wiring for transmitting power for the integrated circuit 10 and a signal wiring for transmitting a signal for the integrated circuit 10. For example, the front wiring layers M1 and M2 may transmit an output signal for the standard cell SC. In addition, for example, the back wiring layer BM may provide power such as a positive power supply voltage (e.g., a power supply voltage VDD) and / or a negative power supply voltage (e.g., a ground voltage VSS) to the standard cell SC, and further, an input signal may be transmitted for the standard cell SC.

[0065] In some embodiments, the front wiring layer M1 may have a 2-track structure including a 2-track signal line above the standard cell SC. Specifically, the front wiring layer M1 may include front wiring lines 11a and 11b, each of which extends along the first direction X and is separated from each other in the second direction Y. For example, the front wiring line 11a may be disposed above the first active region RX1 and may be electrically connected to the source / drain contact CA through the via VA. For example, the front wiring line 11b may be disposed above the second active region RX2 and may be electrically connected to the source / drain contact CA through the via VA.

[0066] The front wiring layer M2 may be arranged above the front wiring layer M1 in the vertical direction Z. The front wiring layer M2 may extend along the second direction Y and may intersect the first active region RX1 and the second active region RX2. For example, the front wiring layer M2 may be connected to the front wiring lines 11a and 11b through the vias V1. The front wiring lines 11a and 11b and the front wiring layer M2 may correspond to the output terminal or output node OUT of the standard cell SC.

[0067] Figure 3B It shows Figure 1 FIG. 1 is a plan view of the back side of the integrated circuit 10 .

[0068] Reference Figure 1 , Figure 2 and Figure 3B , the gate line GT and the source / drain contact CA may be shown to describe the location of the elements disposed on the back side of the integrated circuit 10. In some embodiments, the back wiring layer BM may have a 4-track structure including a 2-track power rail and a 2-track signal line. Specifically, the back wiring layer BM may include first to fourth back wiring lines 12a to 12d, each of which extends along the first direction X and is separated from each other in the second direction Y.

[0069] In some embodiments, the first backside wiring line 12a and the second backside wiring line 12b may be used as backside power rails that supply a power supply voltage to the standard cell SC. For example, the first backside wiring line 12a may be a first backside power rail that supplies a positive power supply voltage (e.g., a power supply voltage VDD), and the second backside wiring line 12b may be a second backside power rail that supplies a negative power supply voltage (e.g., a ground voltage VSS). Backside vias BVA may be provided on the first backside wiring line 12a and the second backside wiring line 12b, respectively.

[0070] The first backside wiring line 12a may be connected to the source / drain region of the first active region RX1 through the backside via BVA, and, for example, may provide the power supply voltage VDD to the source of the P-type transistor PM1 and the source of the P-type transistor PM2. The second backside wiring line 12b may be connected to the source / drain region of the second active region RX2 through the backside via BVA, and, for example, may provide the ground voltage VSS to the source of the N-type transistor NM1.

[0071] The back side via BVA may connect the layers and elements disposed on the back side with the elements (e.g., the diffusion region) in the substrate. Specifically, the back side via BVA may be connected to each of the source / drain region of the first active region RX1 and the source / drain region of the second active region RX2. Therefore, the back side via BVA may be referred to as a back side source / drain contact. As described above, the structure connecting the contact portion to the lower portion of the epitaxial region (e.g., the source / drain region) may be referred to as a direct back side contact (DBC). In some embodiments, the DBC may include a back side contact and / or a back side via.

[0072] In some embodiments, the third back side wiring line 12c and the fourth back side wiring line 12d may be used as back side signal lines that provide input signals to the standard cell SC. For example, the third back side wiring line 12c may be a first back side signal line that provides a first input signal A, and the fourth back side wiring line 12d may be a second back side signal line that provides a second input signal B. The back side gate contacts BCB may be disposed on the third back side wiring line 12c and the fourth back side wiring line 12d, respectively.

[0073] The third back side wiring line 12c may be connected to the first gate line GT1 through the back side gate contact BCB, and, for example, may provide the first input signal A to the gate of the P-type transistor PM1, and may provide the first input signal A to the gate of the N-type transistor NM1. The fourth back side wiring line 12d may be connected to the second gate line GT2 through the back side gate contact BCB, and, for example, may provide the second input signal B to the gate of the P-type transistor PM2, and may provide the second input signal B to the gate of the N-type transistor NM2.

[0074] Figure 4A is along Figure 1 A cross-sectional view taken along line X1-X1', and Figure 4B is along Figure 1 A cross-sectional view taken along line X2-X2'.

[0075] Figure 4A and Figure 4B An example of forming a nanosheet on an active region is shown. For example, a plurality of nanosheets may be stacked on the active region, and a multi-bridge channel (MBC) field effect transistor (FET) in which a gate line surrounds the plurality of nanosheets may be formed on the active region. However, the integrated circuit 10 is not limited to Figure 4A and Figure 4B For example, a FinFET may be formed, which includes a fin formed on an active area and a gate line. As another example, a gate-all-around (GAA) FET may be formed, in which a nanowire formed on an active area is surrounded by a gate line. As another example, a vertical GAA FET may be formed, in which a plurality of nanowires are vertically stacked on an active area and surrounded by a gate line. FIG. 22A to FIG. 22D Describe this.

[0076] Reference Figures 1 to 4B, the first layer L1 may include a substrate or a semiconductor substrate. In this case, the upper region of the first layer L1 may correspond to the first active region RX1. For example, the first layer L1 or the upper region of the first layer L1 may correspond to, for example, an N well formed in a P-type substrate. For example, the semiconductor substrate may include one of silicon on insulator (SOI), silicon on sapphire, germanium, silicon-germanium, and gallium arsenide. The interlayer insulating layer ILD may be disposed at an upper portion relative to the first layer L1 in the vertical direction Z. The interlayer insulating layer ILD may include an insulating material. For example, the insulating material may include one of an oxide, a nitride, and an oxynitride.

[0077] In some embodiments, the first layer L1 may correspond to a bulkless substrate. When the manufacturing process of the integrated circuit 10 is performed, gate lines, source / drain regions, contacts, vias, and / or wiring layers may be formed on the front side of the substrate, thereby forming a device wafer. Subsequently, the device wafer may be temporarily bonded to a carrier wafer, and at least a portion of the substrate may be removed by performing a back grinding process on the device wafer. As described above, a wafer on which a back grinding process has been performed so that the height of the substrate is less than or equal to a reference height may be referred to as a bulkless wafer or a bulkless substrate.

[0078] A nanosheet stack NS extending along a first direction X may be disposed above the first layer L1. The nanosheet stack NS may include a plurality of nanosheets (e.g., a first nanosheet NS1 to a third nanosheet NS3) overlapping each other in a vertical direction Z. For example, the nanosheet stack NS may be doped with N-type impurities and may configure a P-type transistor. As another example, the nanosheet stack NS may be doped with P-type impurities and may constitute an N-type transistor. In some embodiments, the nanosheet stack NS may include silicon (Si), germanium (Ge), or SiGe. In some embodiments, the nanosheet stack NS may include InGaAs, InAs, GaSb, InSb, or a combination thereof.

[0079] Each of the first gate line GT1 and the second gate line GT2 may cover the nanosheet stack NS and may surround each of the first to third nanosheets NS1 to NS3. Therefore, the first to third nanosheets NS1 to NS3 may have a GAA structure. A gate insulating layer may be provided between each of the first and second gate lines GT1 and GT2 and the first to third nanosheets NS1 to NS3. The first source / drain region SD1 and the second source / drain region SD2 may include an epitaxial region of a semiconductor material such as silicon, boron, phosphorus, germanium, carbon, SiGe, and / or SiC.

[0080] The back via BVA may be disposed on the first back wiring line 12a, and further, the back via BVA may pass through the first layer L1 and may extend in the vertical direction Z. The back via BVA may electrically connect the first back wiring line 12a to the first source / drain region SD1. The back gate contact BCB may be disposed on the third back wiring line 12c, and further, the back gate contact BCB may pass through the first layer L1 and may extend in the vertical direction Z. The back gate contact BCB may electrically connect the third back wiring line 12c to the first gate line GT1. The source / drain contact CA may be disposed on the second source / drain region SD1, and the via VA may be disposed on the source / drain contact CA. The front wiring line 11a may extend in the first direction X at the upper portion of the via VA. The via V1 may be disposed on the front wiring line 11a, and the front wiring layer M2 may extend in the second direction Y at the upper portion of the via V1.

[0081] For example, the first source / drain region SD1 may correspond to the source of the P-type transistor PM1, the second source / drain region SD2 may correspond to the drain of the P-type transistor PM1, and the second gate line GT2 may correspond to the gate of the P-type transistor PM1. In this case, the first back wiring line 12a may provide the power supply voltage VDD to the source of the P-type transistor PM1 through the back via BVA. The front wiring line 11a may be connected to the drain of the P-type transistor PM1 through the via VA and the source / drain contact CA.

[0082] As described above, in some embodiments, the back wiring layer BM may include first to fourth back wiring lines 12a to 12d, each of which extends along the first direction X and is separated from each other in the second direction Y. In this case, the first to fourth back wiring lines 12a to 12d may be arranged at the same level. Specifically, the top levels of the first to fourth back wiring lines 12a to 12d may have the same height as each other. In addition, the bottom levels of the first to fourth back wiring lines 12a to 12d may have the same height as each other.

[0083] However, the present disclosure is not limited thereto, and the first to fourth back wiring lines 12a to 12d may be arranged at different levels. Specifically, the bottom level of at least one of the first to fourth back wiring lines 12a to 12d may be different from the top level of another of the first to fourth back wiring lines 12a to 12d. For example, in the vertical direction Z, the bottom level of at least one of the first to fourth back wiring lines 12a to 12d may be at the top level of another of the first to fourth back wiring lines 12a to 12d, and the at least one back wiring line may be electrically insulated from the other back wiring line.

[0084] Figure 5 The layout of integrated circuit 20 is shown. Fig. 6A It shows Figure 5 A plan view of the front side of the integrated circuit 20, and Figure 6B It shows Figure 5 A plan view of the back side of the integrated circuit 20 is shown. Fig. 7A is along Figure 5 A cross-sectional view taken along line X3-X3', and Figure 7B is along Figure 5 A cross-sectional view taken along line X4-X4'.

[0085] Reference Figures 5 to 7B , the integrated circuit 20 includes a first active region RX1 and a second active region RX2, a gate line GT, a source / drain contact CA, a via VA, front wiring layers M1 and M2, a back wiring layer BM, a back via BVA, and a back gate contact BCB. For example, the gate line GT, the source / drain contact CA, and the back gate contact BCB may constitute a standard cell SCa, and the standard cell SCa may be defined by a cell boundary BD. For example, the standard cell SCa may correspond to Figure 2 The integrated circuit 20 may correspond to Figure 1 A modified version of the integrated circuit 10 and referenced above Figures 1 to 4B The description given can be applied to other examples. Figures 1 to 4B The differences between the integrated circuit 10 are shown.

[0086] In some embodiments, the front wiring layer M1 may have a 2-track structure including a 2-track signal line above the standard cell SCa. Specifically, the front wiring layer M1 may include front wiring lines 21a and 21b, each of which extends along the first direction X and is separated from each other in the second direction Y. For example, the front wiring line 21a may be disposed above the first active region RX1 and may be electrically connected to the source / drain contact CA through the via VA. For example, the front wiring line 21b may be disposed above the second active region RX2 and may be electrically connected to the source / drain contact CA through the via VA.

[0087] In some embodiments, the back wiring layer BM may have a 3-track structure including a 2-track power rail and a 1-track signal line. Specifically, the back wiring layer BM may include a first back wiring line 22a to a fourth back wiring line 22d, each of which extends along the first direction X. The first back wiring line 22a and the second back wiring line 22b may be used as back power rails to supply a power supply voltage to the standard cell SCa. For example, the first back wiring line 22a may be a first back power rail supplying a positive power supply voltage (e.g., a power supply voltage VDD), and the second back wiring line 22b may be a second back power rail supplying a negative power supply voltage (e.g., a ground voltage VSS). The back vias BVA may be disposed on the first back wiring line 22a and the second back wiring line 22b, respectively.

[0088] The first backside wiring line 22a may be connected to the source / drain region of the first active region RX1 through the backside via BVA, and, for example, may provide the power supply voltage VDD to the source of the P-type transistor PM1 and the source of the P-type transistor PM2. The second backside wiring line 22b may be connected to the source / drain region of the second active region RX2 through the backside via BVA, and, for example, may provide the ground voltage VSS to the source of the N-type transistor NM1. The backside via BVA may be provided on the first backside wiring line 22a and the second backside wiring line 22b, and further, the backside via BVA may pass through the first layer L1 and may extend in the vertical direction Z. The backside via BVA may be connected to each of the source / drain region of the first active region RX1 and the source / drain region of the second active region RX2.

[0089] The third back wiring line 22c and the fourth back wiring line 22d can be used as back signal lines for providing input signals to the standard cell SCa. The third back wiring line 22c and the fourth back wiring line 22d can be separated from each other in the first direction X, and can be arranged in a row along the first direction X. As described above, the third back wiring line 22c and the fourth back wiring line 22d can occupy one track. For example, the third back wiring line 22c can be a first back signal line providing a first input signal A, and the fourth back wiring line 22d can be a second back signal line providing a second input signal B.

[0090] The third back side wiring line 22c may be connected to the first gate line GT1 through the back side gate contact BCB, and, for example, may provide the first input signal A to the gate of the P-type transistor PM1, and may provide the first input signal A to the gate of the N-type transistor NM1. The fourth back side wiring line 22d may be connected to the second gate line GT2 through the back side gate contact BCB, and, for example, may provide the second input signal B to the gate of the P-type transistor PM2, and may provide the second input signal B to the gate of the N-type transistor NM2.

[0091] The back gate contact BCB1 may be disposed on the third back wiring line 22c, and further, the back gate contact BCB1 may pass through the first layer L1 and may extend in the vertical direction Z. Therefore, the back gate contact BCB1 may electrically connect the third back wiring line 22c to the first gate line GT1. The back gate contact BCB2 may be disposed on the fourth back wiring line 22d, and further, the back gate contact BCB2 may pass through the first layer L1 and may extend in the vertical direction Z. Therefore, the back gate contact BCB2 may electrically connect the fourth back wiring line 22d to the second gate line GT2.

[0092] As described above, in some embodiments, the back wiring layer BM may include first to fourth back wiring lines 22a to 22d, each of which extends along the first direction X. In this case, the first to fourth back wiring lines 22a to 22d may be arranged at the same level. Specifically, the top levels of the first to fourth back wiring lines 22a to 22d may have an equal height. In addition, the bottom levels of the first to fourth back wiring lines 22a to 22d may have the same height.

[0093] However, the present disclosure is not limited thereto, and the first to fourth back wiring lines 22a to 22d may be arranged at different levels. Specifically, the bottom level of at least one of the first to fourth back wiring lines 22a to 22d may be different from the top level of another of the first to fourth back wiring lines 22a to 22d. For example, in the vertical direction Z, the bottom level of at least one of the first to fourth back wiring lines 22a to 22d may be at the top level of another of the first to fourth back wiring lines 22a to 22d, and the at least one back wiring line may be electrically insulated from the other back wiring line.

[0094] Figure 8 The layout of integrated circuit 30 is shown. Fig. 9A is along Figure 8 A cross-sectional view taken along line X5-X5', and Fig. 9B is along Figure 8 A cross-sectional view taken along line X5a-X5a'.

[0095] Reference Figure 8 , Fig. 9A and Fig. 9B , the integrated circuit 30 includes a first active area RX1 and a second active area RX2, a gate line GT, a source / drain contact CA, a gate contact CB, vias VA and V1, front wiring layers M1 and M2, a back wiring layer BM, a back via BVA, and a back contact BSCA. In this case, the back wiring layer BM and the back contact BSCA may be arranged at different levels. Specifically, the bottom level of the back contact BSCA may be different from the top level of the back wiring layer BM. For example, the gate line GT, the source / drain contact CA, and the gate contact CB may constitute a standard cell SCb, and the standard cell SCb may be defined by a cell boundary BD. For example, the standard cell SCb may correspond to the AOI22 cell and may include a plurality of transistors including a first transistor TR11 to a fifth transistor TR15.

[0096] In some embodiments, the front wiring layer M1 may have a 3-track structure including a 3-track signal line (e.g., front wiring lines 31a to 31f) above the standard cell SCb. In some embodiments, the back wiring layer BM may have a 2-track structure including a 2-track power rail (e.g., a first back power rail 32a and a second back power rail 32b) below the standard cell SCb. In some embodiments, the back contact BSCA may include a back contact 33 extending along the first direction X between the standard cell SCb and the back wiring layer BM, and may correspond to a local interconnection of the standard cell SCb. In this case, the back contact 33 may be electrically insulated from the first back power rail 32a and the second back power rail 32b. For example, the gate line GT may include gate lines 34a to 34e.

[0097] For example, the front wiring lines 31a and 31b may be arranged in the upper part of the first active region RX1. In this case, the front wiring lines 31a and 31b may be arranged in a row along the first direction X, and thus may occupy the first track. The front wiring line 31a may be electrically connected to the gate line 34a through the gate contact CB. For example, the front wiring line 31a may transmit the first input signal to the gate line 34a corresponding to the gate of the first transistor TR11. The front wiring line 31b may be electrically connected to the source / drain region 35d of the second transistor TR12 through the via VA. In addition, the front wiring line 31b may be electrically connected to the front wiring layer M2 through the via V1. In this case, the front wiring layer M2 may correspond to the output node of the standard cell SCb.

[0098] For example, the front wiring lines 31c and 31d may be separated from each other in the second direction Y relative to the front wiring lines 31a and 31b. In this case, the front wiring lines 31c and 31d may be arranged in a row along the first direction X, and thus may occupy the second track. In some embodiments, the front wiring lines 31c and 31d may be disposed in the upper portion of the dummy area between the first active area RX1 and the second active area RX2. In some embodiments, the front wiring lines 31c and 31d may at least partially overlap the first active area RX1 and / or the first back power rail 32a. In some embodiments, the front wiring lines 31c and 31d may at least partially overlap the second active area RX2 and / or the second back power rail 32b. The front wiring line 31c may be electrically connected to the gate line 34b through the gate contact CB. For example, the front wiring line 31c may transmit the second input signal to the gate line 34b corresponding to the gate of the third transistor TR13. The front wiring line 31d may be electrically connected to the gate line 34d through the gate contact CB. For example, the front-side wiring line 31d may transmit the third input signal to the gate line 34d corresponding to the gate of the fourth transistor TR14.

[0099] For example, the front wiring lines 31e and 31f may be arranged in the upper portion of the second active region RX2. In this case, the front wiring lines 31e and 31f may be arranged in a row along the first direction X, and thus may occupy the third track. The front wiring line 31e may be electrically connected to the source / drain contact CA of the second active region RX2 through the via VA. The front wiring line 31f may be electrically connected to the gate line 34e through the gate contact CB. For example, the front wiring line 31f may transmit the fourth input signal to the gate line 34e corresponding to the gate of the second transistor TR12.

[0100] For example, the first back power rail 32a may overlap the first active region RX1 and may be electrically connected to the source / drain regions 35a and 35c of the first active region RX1 through the back via BVA. For example, the second back power rail 32b may overlap the second active region RX2 and may be electrically connected to the source / drain regions of the second active region RX2 through the back via BVA. For example, the back contact 33 may overlap the first active region RX1 and may be electrically connected to the source / drain regions 35b and 35d of the first active region RX1 through the back via BVA0.

[0101] For example, the source / drain region 35a may correspond to the source of the first transistor TR11, the source / drain region 35b may correspond to the drain of the first transistor TR11, and the gate line 34a may correspond to the gate of the first transistor TR11. In this case, the first back power rail 32a may provide the power supply voltage VDD to the source of the first transistor TR11 through the back via BVA. The interlayer insulating layer ILD may be disposed on the first layer L1, and the interlayer insulating layer ILD1 may be disposed on the interlayer insulating layer ILD.

[0102] For example, the source / drain region 35b may be electrically connected to the source / drain region 35d through the back contact 33 and the back via BVA0. In this case, the source / drain region 35d may correspond to the source of the second transistor TR12, and the source / drain region 35e may correspond to the drain of the second transistor TR12. The source / drain region 35e may be connected to the front wiring line 31b through the source / drain contact CA and the via VA. The front wiring line 31b may be connected to the front wiring layer M2 through the via V1. In this case, the front wiring layer M2 may correspond to the output node of the standard cell SCb.

[0103] Fig. 10A The layout of integrated circuit 30a is shown. Fig. 10B is along Fig. 10A A cross-sectional view taken along line X5b-X5b'.

[0104] Reference Fig. 10A and Fig. 10B , the integrated circuit 30a includes a standard cell SCb' and may correspond to Figure 8 In some embodiments, the back contact BSCA may include a back contact 33a, and the back contact 33a may not overlap with the first back power rail 32a' and the second back power rail 32b'. For example, the length of each of the first back power rail 32a' and the second back power rail 32b' in the second direction Y may be less than Figure 8 The length of each of the first back power rail 32a and the second back power rail 32b in the second direction Y is short. For example, the back contact 33a may at least partially overlap with the front wiring lines 31c and 31d. For example, the back contact 33a may not overlap with the first active area RX1 and the second active area RX2. In this example, because the edge of the back contact 33a is spaced apart from the edge of each of the first active area RX1 and the second active area RX2 in the Y direction (horizontal direction), the back contact 33a does not overlap with the first active area RX1 or the second active area RX2 along the Z axis (vertical direction).

[0105] Fig.11A The layout of integrated circuit 30b is shown.

[0106] Reference Fig.11A , the integrated circuit 30b may include a standard cell SCb", and may correspond to Figure 8 A modified version of the integrated circuit 30 of . In some embodiments, the back contact BSCA may include a back contact 33b, and the back contact 33b may not overlap with the front wiring lines 31a and 31b. For example, the back contact 33b may include patterns PT1, PT2a, and PT2b. The patterns PT2a and PT2b may each extend along the second direction Y, and the pattern PT1 may extend along the first direction X. The pattern PT1 may be connected to the patterns PT2a and PT2b. As described above, the back contact 33b may include a bidirectional pattern. For example, the pattern PT2a may be connected to the drain of the first transistor TR11, the pattern PT2b may be connected to the source of the second transistor TR12, and the pattern PT1 may connect the drain of the first transistor TR11 to the source of the second transistor TR12.

[0107] Fig. 11B The layout of integrated circuit 30c is shown.

[0108] Reference Fig. 11B , the integrated circuit 30c includes a first active region RX1 and a second active region RX2, a gate line GT, a source / drain contact CA, a gate contact CB, vias VA and V1, front wiring layers M1 and M2, a back wiring layer BM, a back via BVA, and a back contact BSCA. In this case, the back wiring layer BM and the back contact BSCA may be arranged at different levels. Specifically, the bottom level of the back contact BSCA may be different from the top level of the back wiring layer BM. The integrated circuit 30c may correspond to Figure 8 A modified version of the integrated circuit 30.

[0109] The back wiring layer BM may include a first back power rail 32a″ and a second back power rail 32b″, each of which extends in the first direction X. For example, the first back power rail 32a″ and the second back power rail 32b″ may be disposed at a boundary of the standard cell. For example, the first back power rail 32a″ and the second back power rail 32b″ may at least partially overlap with the cell boundary of the standard cell. For example, the length of each of the first back power rail 32a″ and the second back power rail 32b″ in the second direction Y may be greater than Figure 8 The length of each of the first back power rail 32a and the second back power rail 32b in the second direction Y is short.

[0110] In some embodiments, the back contact BSCA may include a back contact 33c extending along the first direction X, and the back contact 33c may correspond to a local interconnect. In this case, the back contact 33c may be electrically insulated from the first back power rail 32a'' and the second back power rail 32b''. For example, the back contact 33c may at least partially overlap the first front wiring line 31a and the second front wiring line 31b.

[0111] Fig. 11C The layout of integrated circuit 30d is shown.

[0112] Reference Fig. 11C , the integrated circuit 30d includes a first active region RX1 and a second active region RX2, a gate line GT, a source / drain contact CA, a gate contact CB, vias VA and V1, front wiring layers M1 and M2, a back wiring layer BM, and a back via BVA. The integrated circuit 30d may correspond to Fig. 11B A modified version of integrated circuit 30c.

[0113] The back wiring layer BM may include a first back power rail 32a″ and a second back power rail 32b″ each extending in the first direction X, and a back wiring pattern 32c. In some embodiments, the back wiring pattern 32c may extend in the first direction X and may correspond to a local interconnect. In this case, the back wiring pattern 32c may be connected to the source / drain region of the first active region RX1 through the back via BVA. For example, the back wiring pattern 32c may at least partially overlap the third front wiring line 31c and the fourth front wiring line 31d.

[0114] Fig.12 The layout of integrated circuit 40 is shown. Fig.13A is along Fig.12 A cross-sectional view taken along line X6-X6', Fig. 13B is along Fig.12 A cross-sectional view taken along line X7-X7', and Fig. 13C is along Fig.12 A cross-sectional view taken along line Y1-Y1'.

[0115] Reference Figures 12 to 13B, the integrated circuit 40 includes a first active area RX1 and a second active area RX2, a gate line GT, a source / drain contact CA, a gate contact CB, a via VA, front wiring layers M1 and M2, a back wiring layer BM, a back via BVA, and a back contact BSCA. In this case, the back wiring layer BM and the back contact BSCA may be arranged at different levels. Specifically, the bottom level of the back contact BSCA may be different from the top level of the back wiring layer BM. For example, the gate line GT, the source / drain contact CA, and the gate contact CB may constitute a standard cell SCc, and the standard cell SCc may be defined by a cell boundary BD. For example, the standard cell SCc may correspond to the AOI22 cell and may include a plurality of transistors including a first transistor TR21 to a fifth transistor TR25.

[0116] In some embodiments, the front wiring layer M1 may have a 3-track structure including a 3-track signal line (e.g., front wiring lines 41a to 41e) on the standard cell SCc. In some embodiments, the back wiring layer BM may have a 2-track structure including a 2-track power rail (e.g., a first back power rail 42a and a second back power rail 42b) on the standard cell SCc. In some embodiments, the back contact BSCA may include a back contact 43 implemented in two directions between the standard cell SCc and the back wiring layer BM, and the back contact 43 may correspond to an output node of the standard cell SCc. In this case, the back contact 43 may be electrically insulated from the first back power rail 42a and the second back power rail 42b. For example, the gate line GT may include gate lines 44a to 44e.

[0117] For example, the front wiring lines 41a and 41b may be arranged in the upper part of the first active region RX1. In this case, the front wiring lines 41a and 41b may be arranged in a row along the first direction X, and thus may occupy the first track. The front wiring line 41a may be electrically connected to the gate line 44a through the gate contact CB. For example, the front wiring line 41a may transmit the first input signal to the gate line 44a corresponding to the gate of the first transistor TR21. The front wiring line 41b may be electrically connected to the gate line 44e through the gate contact CB. For example, the front wiring line 41b may transmit the fourth input signal to the gate line 44e corresponding to the gate of the fourth transistor TR24.

[0118] For example, the front wiring line 41c may be separated from the front wiring lines 41a and 41b in the second direction Y and may occupy the second track. In some embodiments, the front wiring line 41c may at least partially overlap with the first active area RX1 and / or the first back power rail 42a. In some embodiments, the front wiring line 41c may not overlap with the first active area RX1 and / or the first back power rail 42a. The front wiring line 41c may be electrically connected to the source / drain contact CA of the first active area RX1 through the via VA. For example, the front wiring line 41c may correspond to a local interconnect. In this case, the interlayer insulating layer ILD1 may also be disposed between the front wiring line 41c and the interlayer insulating layer ILD.

[0119] For example, the front wiring lines 41d and 41e may be arranged in the upper part of the second active region RX2. In this case, the front wiring lines 41d and 41e may be arranged in a row along the first direction X, and thus may occupy the third track. The front wiring line 41d may be electrically connected to the gate line 44b via the gate contact CB. For example, the front wiring line 41d may transmit the second input signal to the gate line 44b corresponding to the gate of the second transistor TR22. The front wiring line 41e may be electrically connected to the gate line 44d via the gate contact CB. For example, the front wiring line 41e may transmit the third input signal to the gate line 44d corresponding to the gate of the third transistor TR23.

[0120] For example, the first back power rail 42a may overlap the first active region RX1 and may be electrically connected to the source / drain region of the first active region RX1 through the back via BVA. For example, the second back power rail 42b may overlap the second active region RX2 and may be electrically connected to the source / drain region of the second active region RX2 through the back via BVA.

[0121] For example, the back contact 43 may include patterns PT1a and PT1b extending in the first direction X and a pattern PT2c extending in the second direction Y. The pattern PT2c may intersect the first active region RX1 and the second active region RX2 and may be connected to the patterns PT1a and PT1b. The pattern PT1a may be connected to the source / drain region 45c of the second transistor TR22 and the source / drain region 45d of the third transistor TR23. The pattern PT2c may be connected to the source / drain region 45d of the third transistor TR23 and the source / drain region 45g of the fifth transistor TR25. The pattern PT1b may be connected to the source / drain region 45g of the fifth transistor TR25 and the source / drain region 45f of the fifth transistor TR25. In some embodiments, a back via BVA may be provided between the back contact 43 and the source / drain regions 45c, 45d, 45g, and 45f.

[0122] exist Fig.13A In the embodiment, for example, the source / drain region 45a may correspond to the source of the first transistor TR21, the source / drain region 45b may correspond to the drain of the first transistor TR21, and the gate line 44a may correspond to the gate of the first transistor TR21. In this case, the second back power rail 42b may provide the ground voltage VSS to the source of the first transistor TR21 through the back via BVA. In this case, the gate line 44b may correspond to the gate of the second transistor TR22, and the source / drain region 45c may correspond to the drain of the second transistor TR22. For example, the gate line 44d may correspond to the gate of the third transistor TR23, and the gate line 44d may be connected to the front wiring line 41e through the gate contact CB. The source / drain regions 45c and 45d may be electrically connected to each other through the pattern PT1a of the back contact 43. In some embodiments, the back via BVA may be provided between the source / drain regions 45c and 45d and the pattern PT1a of the back contact 43. The back contact 43 may correspond to the output node of the standard cell SCb.

[0123] exist Fig. 13B In the embodiment, for example, the gate line 44d may correspond to the gate of the fifth transistor TR25, the source / drain region 45g may correspond to the drain of the fifth transistor TR25, and the source / drain region 45f may correspond to the source of the fifth transistor TR25. The source / drain regions 45g and 45f may be electrically connected to each other through the pattern PT1b of the back contact 43. In some embodiments, a back via BVA may be provided between the source / drain regions 45g and 45f and the pattern PT1a of the back contact 43. The back contact 43 may correspond to the output node of the standard cell SCb.

[0124] For example, in Fig. 13C , the source / drain region 45g may correspond to the drain of the fifth transistor TR25, and the source / drain region 45d may correspond to the drain of the third transistor TR23. The source / drain regions 45d and 45g may be electrically connected to each other through the pattern PT2c of the back contact 43. In some embodiments, a back via BVA may be provided between the source / drain regions 45d and 45g and the pattern PT1a of the back contact 43. The back contact 43 may correspond to the output node of the standard cell SCb.

[0125] Fig.14 The layout of integrated circuit 40a is shown.

[0126] Reference Fig.14 , the integrated circuit 40a includes a standard cell SCc' and may correspond to Fig.12In some embodiments, the front wiring layer M1 may have a 4-track structure including 4-track signal lines (e.g., front wiring lines 41a and 41c to 41f) on the standard cell SCc'. For example, the front wiring line 41a may occupy the first track, the front wiring line 41c may occupy the second track, the front wiring lines 41d and 41e may be arranged in a row along the first direction X and may occupy the third track, and the front wiring line 41f may occupy the fourth track. In some embodiments, the back contact BSCA may include a back contact 43a.

[0127] Fig.15 The layout of integrated circuit 50 is shown. Fig.16 is along Fig.15 A cross-sectional view taken along line X8-X8'.

[0128] Reference Fig.15 and Fig.16 , the integrated circuit 50 includes a first active area RX1 and a second active area RX2, a gate line GT, a source / drain contact CA, a gate contact CB, vias VA and V1, front wiring layers M1 and M2, a back wiring layer BM, a back via BVA, a back gate contact BCB, and a back contact BSCA. In this case, the back wiring layer BM and the back contact BSCA may be arranged at different levels. Specifically, the bottom level of the back contact BSCA may be different from the top level of the back wiring layer BM. For example, the gate line GT, the source / drain contact CA, the gate contact CB, and the back gate contact BCB may constitute a standard cell SCd, and the standard cell SCd may be defined by a cell boundary BD. For example, the standard cell SCd may correspond to an AOI22 cell, and may include a plurality of transistors including a first transistor TR31 to a fifth transistor TR34.

[0129] In some embodiments, the front wiring layer M1 may have a 3-track structure including a 3-track signal line (e.g., front wiring lines 51a to 51e) on the standard cell SCd. In some embodiments, the back wiring layer BM may have a 2-track structure including a 2-track power rail (e.g., a first back power rail 52a and a second back power rail 52b) on the standard cell SCd. In some embodiments, the back contact BSCA may include back contacts 53a and 53b, which are arranged in a row along the first direction X between the standard cell SCd and the back wiring layer BM, and the back contact BSCA may correspond to the input node of the standard cell SCd of the back contacts 53a and 53d. In this case, the back contacts 53a and 53b may be electrically insulated from the first back power rail 52a and the second back power rail 52b. For example, the gate line GT may include gate lines 54a to 54e.

[0130] For example, the front wiring lines 51a and 51b may be disposed in the upper portion of the first active region RX1. In this case, the front wiring lines 51a and 51b may be arranged in a row along the first direction X, and thus may occupy the first track. The front wiring line 51a may be electrically connected to the gate line 54a through the gate contact CB, and may send the first input signal to the gate line 54a corresponding to the gate of the first transistor TR31. The front wiring line 51b may be connected to the source / drain region of the fourth transistor TR34 through the via VA, and may be connected to the front wiring layer M2 through the via V1.

[0131] For example, the front wiring line 51c may occupy the second track. In some embodiments, the front wiring line 51c may at least partially overlap the first active area RX1 and / or the first back power rail 52a. In some embodiments, the front wiring line 51c may not overlap the first active area RX1 and / or the first back power rail 52a. The front wiring line 51c may be connected to the source / drain contact CA of the first active area RX1 through the via VA. For example, the front wiring line 51c may correspond to a local interconnect that connects the drain of the first transistor TR31 to the source of the fourth transistor TR34.

[0132] For example, the back contacts 53a and 53b may be arranged in a row along the first direction X. The back contact 53a may be electrically connected to the gate line 54b through the back gate contact BCB, and may transmit the second input signal to the gate line 54b corresponding to the gate of the second transistor TR32. The back contact 53b may be electrically connected to the gate line 54d through the back gate contact BCB, and may transmit the third input signal to the gate line 54d corresponding to the gate of the third transistor TR33.

[0133] For example, the front wiring lines 51d and 51e may be disposed in the upper portion of the second active region RX2. In this case, the front wiring lines 51d and 51e may be arranged in a row along the first direction X, and thus may occupy the third track. The front wiring line 51d may be connected to the source / drain region of the fifth transistor TR35 through the via VA, and may be connected to the front wiring layer M2 through the via V1. The front wiring line 51e may transmit the fourth input signal to the gate line 54e corresponding to the gate of the fourth transistor TR34 through the gate contact CB.

[0134] For example, the first back power rail 52a may overlap the first active region RX1 and may be electrically connected to the source / drain region of the first active region RX1 through the back via BVA. For example, the second back power rail 52b may overlap the second active region RX2 and may be electrically connected to the source / drain region of the second active region RX2 through the back via BVA.

[0135] Fig.17 The layout of integrated circuit 50a is shown.

[0136] Reference Fig.17 , the integrated circuit 50a includes a standard cell SCd' and may correspond to Fig.15 A modified version of the integrated circuit 50 of FIG. 50 is shown. In some embodiments, the back contacts 53a and 53b may at least partially overlap the front wiring line 51c, the first active region RX1, and / or the first power rail 52a. However, the present disclosure is not limited thereto, and in other examples, the back contacts 53a and 53b may at least partially overlap the second active region RX2 and / or the second power rail 52b.

[0137] Fig.18 The layout of integrated circuit 60 is shown. Fig.19 is along Fig.18 A cross-sectional view taken along line X9-X9'.

[0138] Reference Fig.18 and Fig.19 , the integrated circuit 60 includes a first active region RX1 and a second active region RX2, a gate line GT, a source / drain contact CA, a gate contact CB, vias VA and V1, front wiring layers M1 and M2, a back wiring layer BM, and a back via BVA. For example, the gate line GT, the source / drain contact CA, and the gate contact CB may constitute a standard cell SCe, and the standard cell SCe may be defined by a cell boundary BD. For example, the standard cell SCe may correspond to an inverter cell.

[0139] In some embodiments, the front wiring layer M1 may have a 3-track structure including 3-track signal lines (e.g., front wiring lines 61a to 61c) on the standard cell SCe. In some embodiments, the back wiring layer BM may have a 2-track structure including 2-track power rails (e.g., first back power rail 62a and second back power rail 62b) on the standard cell SCe. For example, the gate line GT may include a gate line 63.

[0140] For example, the front wiring line 61a may be disposed in the upper portion of the first active region RX1 and may occupy the first track. The front wiring line 61a may be connected to the source / drain region 64a of the first active region RX1 through the via VA and the source / drain contact CA, and may be connected to the front wiring layer M2 through the via V1. For example, the front wiring line 61c may be disposed in the upper portion of the second active region RX2 and may occupy the third track. The front wiring line 61c may be connected to the source / drain region of the second active region RX2 through the via VA and the source / drain contact CA, and may be connected to the front wiring layer M2 through the via V1. As described above, the front wiring layer M2 may correspond to the output node of the standard cell SCe.

[0141] For example, the front wiring line 61b may be disposed between the front wiring lines 61a and 61c and may occupy the second track. The front wiring line 61b may be connected to the gate line 63 through the gate contact CB and may transmit an input signal to the gate line 63. As described above, the front wiring layer 61b may correspond to an input node of the standard cell SCe.

[0142] For example, the first back power rail 62a may overlap the first active region RX1 and may be electrically connected to the source / drain region of the first active region RX1 through the back via BVA. For example, the second back power rail 62b may overlap the second active region RX2 and may be electrically connected to the source / drain region of the second active region RX2 through the back via BVA.

[0143] Fig. 20 The layout of integrated circuit 70 is shown. Fig.21A is along Fig. 20 A cross-sectional view taken along the line X10-X10', and Fig. 21B is along Fig. 20 A cross-sectional view taken along line X11-X11'.

[0144] Reference Fig. 20 , Fig.21A and Fig. 21B, the integrated circuit 70 includes a first active region RX1 and a second active region RX2, a gate line GT, a source / drain contact CA, vias VA and V1, front wiring layers M1 and M2, a back wiring layer BM, a back gate contact BCA, and a back via BVA. For example, the gate line GT, the source / drain contact CA, and the back gate contact BCB may constitute a standard cell SCf, and the standard cell SCf may be defined by a cell boundary BD. For example, the standard cell SCf may correspond to an inverter cell.

[0145] In some embodiments, the front wiring layer M1 may have a 2-track structure including a 2-track signal line (e.g., front wiring lines 71a and 71b) on the standard cell SCf. In some embodiments, the back wiring layer BM may have a 3-track structure including a 2-track power rail (e.g., a first back power rail 72a and a second back power rail 72b) at the lower portion of the standard cell SCf and a 1-track signal line (e.g., back signal line 72c) at the lower portion of the standard cell SCf. For example, the gate line GT may include a gate line 73.

[0146] For example, the front wiring line 71a may extend along the first direction X at the upper portion of the first active region RX1, and may occupy the first track. The front wiring line 71a may be connected to the source / drain region 74a of the first active region RX1 through the via VA and the source / drain contact CA, and may be connected to the front wiring layer M2 through the via V1. For example, the front wiring line 71b may extend along the first direction X at the upper portion of the second active region RX2, and may occupy the second track. The front wiring line 71b may be connected to the source / drain region of the second active region RX2 through the via VA and the source / drain contact CA, and may be connected to the front wiring layer M2 through the via V1. As described above, the front wiring layer M2 may correspond to the output node of the standard cell SCf.

[0147] For example, the back signal line 72c may extend in the first direction X at the lower portion of the standard cell SCf and may occupy one track. In some embodiments, the back signal line 72c may not overlap with the front wiring lines 71a and 71b. The back signal line 72c may be connected to the gate line 73 through the back gate contact BCB and may transmit an input signal to the gate line 73. As described above, the back signal line 72c may correspond to an input node of the standard cell SCf.

[0148] For example, the first back power rail 72a may overlap the cell boundary BD and may be shared by another standard cell adjacent to the standard cell SCf in the second direction Y. For example, the second back power rail 72b may overlap the cell boundary BD and may be shared by another standard cell adjacent to the standard cell SCf in the second direction Y. The first back power rail 72a may provide a first power supply voltage (e.g., a power supply voltage) to the source / drain region through the back via BVA, and the second back power rail 72b may provide a second power supply voltage (e.g., a ground voltage) to the source / drain region through the back via BVA.

[0149] FIG. 22A to FIG. 22D Devices in some embodiments are shown. For example, Fig.22A A fin field effect transistor (FinFET) 80a is shown, Fig. 22B A gate-all-around field effect transistor (GAAFET) 80b is shown, Fig. 22C A multi-bridge channel field effect transistor (MBCFET) 80c is shown, and Fig.22D A vertical field effect transistor (VFET) 80d is shown. FIG. 22A to FIG. 22C An example is shown in which one of the two source / drain regions has been removed, and Fig.22D A cross section of the VFET 80d taken along a plane parallel to a plane consisting of the second direction Y and the vertical direction Z and passing through the channel CH of the VFET 50d is shown.

[0150] Reference Fig.22A , a fin-type active pattern extending in the first direction X between the STIs and a gate G extending in the second direction Y may constitute a FinFET 80a. A source / drain S / D may be formed on each of both sides of the gate G, and thus the source and the drain may be separated from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. In some embodiments, the gate G and a plurality of active patterns separated from each other in the second direction Y may constitute a FinFET 80a.

[0151] Reference Fig. 22B , the active patterns (i.e., nanowires) separated from each other in the vertical direction Z and extending in the first direction X and the gate G extending in the second direction Y may constitute the GAAFET 80b. The source / drain S / D may be formed on each of both sides of the gate G, and thus the source and the drain may be separated from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. The number of nanowires included in the GAAFET 80b is not limited to Fig. 22B .

[0152] Reference Fig. 22C, the active patterns (i.e., nanosheets) separated from each other in the vertical direction Z and extending in the first direction X and the gate G extending in the second direction Y may constitute the MBCFET 80c. The source / drain S / D may be formed on each of both sides of the gate G, and thus the source and the drain may be separated from each other in the first direction X. An insulating layer may be formed between the channel CH and the gate G. The number of nanowires included in the MBCFET 80c is not limited to Fig. 22C .

[0153] Reference Fig.22D , the VFET 80d may include a top source / drain T_S / D and a bottom source / drain B_S / D separated from each other in the vertical direction Z, with a channel CH interposed between the top source / drain T_S / D and the bottom source / drain B_S / D. The VFET 80d may include a gate G surrounding the perimeter of the channel CH between the top source / drain T_S / D and the bottom source / drain B_S / D. An insulating layer may be formed between the channel CH and the gate G.

[0154] However, the transistor in the present disclosure is not limited to the above structure. For example, the integrated circuit may include a ForkFET having a structure in which the N-type transistor is relatively closer to the P-type transistor because the nanosheet for the P-type transistor and the nanosheet for the N-type transistor are separated from each other by a dielectric wall. In addition, the integrated circuit may include a bipolar junction transistor and a FET such as a complementary FET (CFET), a negative capacitance FET (NCFET), or a carbon nanotube (CNT) FET.

[0155] Fig.23 is a flow chart illustrating a method of manufacturing an integrated circuit.

[0156] Reference Fig.23 , a method for manufacturing an integrated circuit IC including a standard cell includes a plurality of operations S10, S30, S50, S70, and S90. The cell library (or standard cell library) D12 may include information about the standard cell, and may include, for example, information about functions, characteristics, layouts, and the like. In some embodiments, the cell library D12 may define a tap cell and a dummy cell and a functional cell that generates an output signal from an input signal. In some embodiments, the cell library D12 may define a storage cell and a dummy cell having the same footprint. The design rule D14 may include factors that the layout of the integrated circuit IC satisfies. For example, the design rule D14 may include factors such as the spacing between patterns in the same layer, the minimum width of each pattern, and the routing direction of the wiring layer. In some embodiments, the design rule D14 may define the minimum separation distance in the same track of the wiring layer.

[0157] In operation S10, a logic synthesis operation of generating netlist data D13 according to register transfer level (RTL) data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis with reference to a cell library D12 according to RTL data D11, and may generate netlist data D13 including a netlist or a bitstream, wherein the RTL data D11 is written in a hardware description language (HDL) (e.g., very high speed integrated circuit (VHSIC) HDL (VHDL) and Verilog). Netlist data D13 may correspond to inputs of placement and routing described below.

[0158] In operation S30, standard cells may be placed. For example, a semiconductor design tool (e.g., a P&R tool) may refer to the cell library D12 to place standard cells used in the netlist data D13. In an embodiment, the semiconductor design tool may place standard cells in a row extending along the X-axis direction or the Y-axis direction, and the placed standard cells may be powered from a power rail extending along a boundary of the row.

[0159] In operation S50, the pins of the standard cell may be routed. For example, the semiconductor design tool may generate interconnections that electrically connect the output pins and input pins of the placed standard cell to each other, and may generate layout data D15 defining the placed standard cell and the generated interconnections. The interconnections may include vias of a via layer and / or a pattern of a wiring layer. The wiring layer may include a front wiring layer disposed on the front side of the substrate and a back wiring layer disposed on the rear surface of the substrate. The layout data D15 may have a format such as GDSII, for example, and may include geometric information about the standard cell and the interconnections. The semiconductor design tool may refer to the design rule D14 when routing the pins of the standard cell. The layout data D15 may correspond to the output of placement and routing. Operation S50 or operations S30 and S50 may be referred to as a method for designing an integrated circuit.

[0160] In some embodiments, Figures 1 to 7B as well as Figures 18 to 21B As shown, the integrated circuit may include a backside wiring layer including a backside power rail and at least one backside signal line. In detail, the standard cell may receive power such as a power supply voltage or a ground voltage through the backside power rail. In addition, the standard cell may receive an input signal or may transmit an output signal through at least one backside signal line. Therefore, the performance of the integrated circuit may be enhanced, and the routing freedom of the frontside wiring layer may be enhanced.

[0161] In some embodiments, Figures 8 to 17As shown, the integrated circuit may include a back wiring layer and at least one back contact, which are arranged at different levels and insulated from each other. Specifically, the standard cell may receive power such as a power supply voltage or a ground voltage through the back wiring layer. Moreover, the standard cell may receive an input signal or may transmit an output signal through at least one back contact. Therefore, the performance of the integrated circuit may be enhanced, and the routing freedom of the front wiring layer may be enhanced.

[0162] In operation S70, a process of manufacturing a mask may be performed. For example, optical proximity correction (OPC) for correcting distortions such as refraction caused by the characteristics of light in photolithography may be applied to the layout data D15. Based on the data to which OPC is applied, a pattern of a mask may be defined for forming a pattern set in a plurality of layers, and at least one mask (or photomask) for forming a pattern for each of the plurality of layers may be manufactured. In some embodiments, the layout of the integrated circuit IC may be restrictively modified in operation S70, and the process of restrictively modifying the integrated circuit IC in operation S70 may be a post-process for optimizing the structure of the integrated circuit IC, and may be referred to as design polishing.

[0163] In operation S90, a process of manufacturing an integrated circuit IC may be performed. For example, multiple layers may be patterned using at least one mask manufactured in operation S70, so that an integrated circuit IC may be manufactured. The front-end process (FEOL) may include, for example, operations of planarizing and cleaning the wafer, operations of forming a trench, operations of forming a well, operations of forming a gate line, and operations of forming a source and a drain. Individual components (e.g., transistors, capacitors, and resistors) may be formed on a substrate by FEOL. In addition, the back-end process (BEOL) may include, for example, operations of performing silicide of a gate region, a source region, and a drain region, operations of adding a dielectric, planarizing operations, operations of forming a hole, operations of adding a metal layer, operations of forming a via, and operations of forming a passivation layer. Individual components (e.g., transistors, capacitors, and resistors) may be connected to each other by BEOL. In some embodiments, a middle process (MOL) may be performed between FEOL and BEOL, and contacts may be formed on individual components. Subsequently, the integrated circuit IC may be packaged in a semiconductor package and may be used as a part of each application in various applications.

[0164] Fig.24 is a block diagram illustrating a system on chip (SoC) 210 .

[0165] Reference Fig.24, SoC 210 may be referred to as an integrated circuit that integrates parts of a computing system or other electronic system. For example, in SoC 210, an application processor (AP) may include a processor and parts for other functions. SoC 210 may include a core 211, a digital signal processor (DSP) 212, a graphics processing unit (GPU) 213, an embedded memory 214, a communication interface 215, and a memory interface 216. The elements of SoC 210 may communicate with each other through a bus 217.

[0166] The core 211 may process instructions and may control the operation of the elements included in the SoC 210. For example, the core 211 may process a series of instructions, and thus may drive an operating system and may execute an application of the operating system. The DSP 212 may process digital signals (e.g., digital signals provided by the communication interface 215), and thus may generate useful data. The GPU 213 may generate data of an image displayed by a display device based on image data provided from the embedded memory 214 or the memory interface 216, and may encode the image data. In some embodiments, the integrated circuit described above with reference to the accompanying drawings may be included in the core 211, the DSP 212, the GPU 213, and / or the embedded memory 214.

[0167] The embedded memory 214 may store data required for the operation of the core 211, the DSP 212, and the GPU 213. The communication interface 215 may provide an interface for one-to-one communication or a communication network. The memory interface 216 may provide an interface for an external memory (e.g., dynamic random access memory (DRAM), flash memory, etc.) of the SoC 210.

[0168] Fig.25 is a block diagram illustrating a computing system 220 including a memory storing programs.

[0169] Reference Fig.25 , the computing system 220 (or computer) may perform the method of designing an integrated circuit in some implementations, and, for example, may perform at least some of the operations of the above-described flowchart. The computing system 220 includes a processor 221, an input / output (I / O) device 222, a network interface 223, a random access memory (RAM) 224, a read-only memory (ROM) 225, and a storage device 226. The processor 221, the I / O device 222, the network interface 223, the RAM 224, the ROM 225, and the storage device 226 may be connected to a bus 227, and may communicate with each other through the bus 227.

[0170] The processor 221 may be referred to as a processing unit, and may include, for example, at least one core for executing any instruction set (e.g., Intel Architecture-32 (IA-32), 64-bit extensions, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.), such as a microprocessor, AP, DSP, and GPU. For example, the processor 221 may access a memory (e.g., RAM 224 or ROM 225) through a bus 227, and may execute instructions stored in the RAM 224 or ROM 225.

[0171] In some embodiments, the RAM 224 may store a program 224_1 for a method of designing an integrated circuit or at least a portion of the program 224_1, and the program 224_1 may allow the processor 221 to execute the method of designing an integrated circuit (eg, Fig.23 That is, the program 224_1 may include a plurality of instructions executable by the processor 221, and the plurality of instructions included in the program 224_1 may allow the processor 221 to perform, for example, at least some of the operations included in the above-mentioned flowchart.

[0172] The storage device 226 may maintain the data stored therein even when the power supplied to the computing system 220 is cut off. In some embodiments, the storage device 226 may store the program 224_1, and further, before the processor 221 executes the program 224_1, the program 224_1 or at least a portion thereof may be loaded from the storage device 226 into the RAM 224. Alternatively, the storage device 226 may store a file written in a program language, and the program 224_1 or at least a portion thereof generated from the file by a compiler may be loaded into the RAM 224. The storage device 226 may store a database (DB) 226_1, and the database 226_1 may include information required for designing an integrated circuit (e.g., information about Fig.23 information of design blocks and / or cell libraries D12 and / or design rules D14).

[0173] The storage device 226 may store data to be processed by the processor 221 or data obtained by processing by the processor 221. That is, the processor 221 may process the data stored in the storage device 226 based on the program 224_1 to generate data, and may store the generated data in the storage device 226. For example, the storage device 226 may store Fig.23 RTL data D11, netlist data D13 and / or layout data D15.

[0174] I / O device 222 may include input devices such as a keyboard or a pointing device, and may include output devices such as a display device or a printer. For example, a user may trigger the execution of program 224_1 using processor 221 through I / O device 222, and may input Fig.23 The RTL data D11 and / or netlist data D13 can be checked Fig.23 The layout data D15. The network interface 223 may provide access to a network external to the computing system 220. For example, the network may include multiple computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

[0175] In the above, example embodiments have been described in the drawings and the specification. The embodiments have been described by using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning or scope of the inventive concept defined in the appended claims. Therefore, it can be understood by those of ordinary skill in the art that various modifications and other equivalent embodiments can be implemented according to the inventive concept. Therefore, the spirit and scope of the inventive concept can be defined based on the spirit and scope of the appended claims.

[0176] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of possible protection. In a single embodiment, the specific features described in the context of independent embodiments in the present disclosure can also be combined to achieve. On the contrary, the different features described in the context of a single implementation can also be implemented separately in multiple implementations, or implemented in appropriate sub-combinations. In addition, although the features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination can be deleted from the combination in some cases, and the combination can be for sub-combinations or variants of sub-combinations.

[0177] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: A standard cell including a first transistor and a second transistor, each of the first transistor and the second transistor being disposed on a front side of a substrate; a backside via hole passing through the substrate in a vertical direction relative to the substrate; a backside wiring layer, comprising a backside power rail, the backside power rail being disposed on the backside of the substrate and connected to the first source / drain of the first transistor through the backside via; as well as a back contact extending along a first direction between the standard cell and the back wiring layer and electrically connecting the second source / drain of the first transistor to the first source / drain of the second transistor, The bottom level of the back contact is at a height different from the top level of the back power rail, and the back contact is electrically insulated from the back power rail.

2. The integrated circuit of claim 1 , further comprising: A front wiring layer is arranged above the front side of the substrate, wherein the front wiring layer comprises: a first front wiring line electrically connected to a gate of the first transistor; and a second front wiring line electrically connected to a second source / drain of the second transistor, The first front wiring line and the second front wiring line extend along the first direction and are arranged in a row along the first direction.

3. The integrated circuit according to claim 2, wherein: The front wiring layer further comprises: a third front side wiring line spaced apart from the first front side wiring line or the second front side wiring line in the second direction; and a fourth front wiring line separated from the third front wiring line in the second direction, The second direction is perpendicular to the first direction.

4. The integrated circuit according to claim 2, wherein: The back contact at least partially overlaps the first front-side wiring line in a vertical direction, and at least partially overlaps the second front-side wiring line in the vertical direction.

5. The integrated circuit according to claim 2, wherein: The back contact does not overlap with the first front wiring line in a vertical direction, and does not overlap with the second front wiring line in the vertical direction.

6. The integrated circuit of claim 1, wherein: The back contact at least partially overlaps the back power rail in a vertical direction.

7. The integrated circuit according to claim 1, wherein: The back contact does not overlap the back power rail in a vertical direction.

8. The integrated circuit of claim 1, wherein: The back contact portion comprises: a first pattern connected to the second source / drain of the first transistor and extending in a second direction perpendicular to the first direction; a second pattern connected to the first source / drain of the second transistor and extending along the second direction; and The third pattern electrically connects the first pattern to the second pattern and extends along the first direction.

9. An integrated circuit comprising: A standard cell including a first transistor and a second transistor, each of the first transistor and the second transistor being disposed on a front side of a substrate; a backside via hole passing through the substrate in a vertical direction relative to the substrate; a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected to a source of the first transistor through the backside via; as well as a back contact portion, disposed between the standard cell and the back wiring layer and electrically connected to the drain of the second transistor, the back contact portion forming a part of an output node, The bottom level of the back contact is at a height different from the top level of the back power rail, and the back contact is electrically insulated from the back power rail.

10. The integrated circuit of claim 9, wherein: The standard unit includes: a first active region extending along a first direction, and a second active region disposed to be separated from the first active region in a second direction perpendicular to the first direction to extend along the first direction; and The back contact portion comprises: a first pattern overlapping the first active region in a vertical direction and extending along the first direction, and The second pattern contacts the first pattern and extends along the second direction.

11. The integrated circuit of claim 10, wherein: The back contact further includes a third pattern that contacts the second pattern, overlaps the second active region along the vertical direction, and extends along the first direction.

12. The integrated circuit of claim 10, wherein: The first transistor and the second transistor are disposed in the first active region, The standard cell further includes a third transistor disposed in the second active region, The first pattern is connected to the drain of the second transistor, and The second pattern connects the drain of the third transistor to the drain of the second transistor.

13. The integrated circuit of claim 12, further comprising: A front wiring layer is arranged above the front side of the substrate, wherein the front wiring layer comprises: a first front wiring line extending along the first direction at an upper portion of the first active region; and A second front-side wiring line extends along the first direction at an upper portion of the second active region.

14. The integrated circuit of claim 13, wherein: The front-side wiring layer further includes a third front-side wiring line extending from the first front-side wiring line and the second front-side wiring line along the first direction.

15. The integrated circuit of claim 13, wherein: The first front-side wiring line is connected to a gate of the second transistor.

16. An integrated circuit comprising: A standard cell including a first transistor disposed on a front side of a substrate; a backside via hole passing through the substrate in a vertical direction relative to the substrate; a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected to a source of the first transistor through the backside via; a first back gate contact connected to the gate of the first transistor to pass through the substrate along the vertical direction; as well as a first back contact extending in a first direction between the standard cell and the back wiring layer and connected to the gate of the first transistor through the first back gate contact, The height of the bottom level of the first back contact portion is different from the height of the top level of the back power rail, and the first back contact portion is electrically insulated from the back power rail.

17. The integrated circuit of claim 16, wherein: The standard cell further includes: a first active region and a second active region, the first active region and the second active region extending along the first direction and spaced apart from each other in a second direction perpendicular to the first direction, and The first back contact is disposed between the first active region and the second active region.

18. The integrated circuit of claim 16, wherein: The standard cell further includes a first active region and a second active region, the first active region and the second active region extending along the first direction and spaced apart from each other in a second direction perpendicular to the first direction, and The first back contact at least partially overlaps the first active region or the second active region in a vertical direction.

19. The integrated circuit of claim 16, wherein: The standard cell further includes a second transistor, and the integrated circuit further includes: a second back gate contact connected to the gate of the second transistor to pass through the substrate in the vertical direction; and a second back contact extending along the first direction between the standard cell and the back wiring layer and connected to the gate of the second transistor through the second back gate contact, and The first back contact portion and the second back contact portion are arranged in a row along the first direction.

20. The integrated circuit of claim 16, wherein: The standard cell further includes: a first active region and a second active region, the first active region and the second active region extending along the first direction and spaced apart from each other in a second direction perpendicular to the first direction, The integrated circuit further comprises: a front wiring layer, arranged above the front surface of the substrate, Wherein, the front wiring layer further includes: A first front wiring line extending along the first direction at an upper portion of the first active area; a second front-side wiring line extending along the first direction at an upper portion of the second active region; and A third front-side wiring line extends from the first front-side wiring line and the second front-side wiring line along the first direction.

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