Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The device comprises a substrate, a gate structure, a first epitaxial layer and a first metal silicide layer, the gate structure is convexly arranged on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer; the first epitaxial layer covers the top surface of the gate layer, the upper surface of the first epitaxial layer is a curved surface, and the first epitaxial layer is a Si layer; the first metal silicide layer covers the first epitaxial layer in a conformal manner, the upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer. According to the semiconductor device provided by the invention, the first epitaxial layer is formed on the substrate, so that the line width of the device is increased, the line width effect is overcome, the forming quality of the metal silicide layer is improved, and the overall performance of the device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the semiconductor field, metal silicide can be used as a low-resistance contact layer between a metal layer and a semiconductor layer due to its low resistivity, thereby improving device performance and reducing device power consumption.

[0003] At present, with the miniaturization of the characteristic size of semiconductor devices, the material selection and formation quality of the metal silicide layer have also been greatly affected. For example, the metal silicide layer formed by cobalt silicide materials can adapt to the semiconductor high-temperature process, but the cobalt silicide film layer has high requirements for the characteristic size of the device. When the characteristic size is small, as the process temperature increases, the cobalt silicide film layer will have agglomeration defects, resulting in the film layer being broken and unusable. The existing devices with characteristic sizes cannot form a metal silicide layer with good performance, small resistance and complete film layer.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] In view of this, a semiconductor device and a manufacturing method thereof are provided, wherein the semiconductor device has a larger line width, thereby reducing the line width effect of forming a metal silicide layer, and at the same time can reduce the thermal stability difference and avoid the generation of agglomeration defects in the subsequent formation process of the metal silicide layer.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, there is provided a semiconductor device, the device comprising:

[0008] substrate;

[0009] A gate structure, wherein the gate structure is protrudingly disposed on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewall formed by the gate oxide layer and the gate layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer;

[0010] a first epitaxial layer, wherein the first epitaxial layer covers a top surface of the gate layer, and an upper surface of the first epitaxial layer is a curved surface, and the first epitaxial layer is a Si layer;

[0011] A first metal silicide layer, wherein the first metal silicide layer conformally covers the first epitaxial layer, and an upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer.

[0012] In an exemplary embodiment of the present disclosure, the top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes a portion of the sidewall of the gate layer, and the first epitaxial layer covers the top surface and the exposed sidewall of the gate layer.

[0013] In an exemplary embodiment of the present disclosure, a top surface of the gate protection layer is flush with a top surface of the gate layer, the first epitaxial layer covers the top surface of the gate layer, and a side wall of the first epitaxial layer is flush with a side wall of the gate layer.

[0014] In an exemplary embodiment of the present disclosure, a middle portion of an upper surface of the first metal silicide layer protrudes in a direction away from the substrate.

[0015] In an exemplary embodiment of the present disclosure, the device further includes a first source-drain electrode and a second source-drain electrode, wherein the first source-drain electrode and the second source-drain electrode are respectively located on both sides of the gate structure, and a surface of the first source-drain electrode is flush with a surface of the substrate, and a surface of the second source-drain electrode is flush with a surface of the substrate;

[0016] The device also includes a second epitaxial layer and a second metal silicide layer;

[0017] The second epitaxial layer covers at least one of the surface of the first source and drain electrode or the surface of the second source and drain electrode, and the second epitaxial layer protrudes from the surface of the substrate, the upper surface of the second epitaxial layer is a curved surface, and the second epitaxial layer is a Si layer;

[0018] The second metal silicide layer conformally covers the surface of the second epitaxial layer, the upper surface of the second metal silicide layer is a curved surface, and the second metal silicide layer is a CoSi2 layer.

[0019] In an exemplary embodiment of the present disclosure, a middle portion of an upper surface of the second metal silicide layer protrudes in a direction away from the substrate.

[0020] In an exemplary embodiment of the present disclosure, the thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

[0021] In an exemplary embodiment of the present disclosure, the semiconductor device is selected from at least one of a PMOS device, an NMOS device or a CMOS device.

[0022] According to another aspect of the present disclosure, there is provided a semiconductor device, the device comprising:

[0023] substrate;

[0024] A gate structure, wherein the gate structure is protrudingly disposed on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewall formed by the gate oxide layer and the gate layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer;

[0025] A first metal silicide layer, wherein the first metal silicide layer covers the top surface of the gate layer, and the upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer.

[0026] In an exemplary embodiment of the present disclosure, the top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes a portion of the sidewall of the gate layer, and the first metal silicide layer covers the top surface and the exposed sidewall of the gate layer.

[0027] In an exemplary embodiment of the present disclosure, the top surface of the gate protection layer is flush with the top surface of the gate layer, the first metal silicide layer covers the top surface of the gate layer, and the sidewall of the first metal silicide layer is flush with the sidewall of the gate layer.

[0028] In an exemplary embodiment of the present disclosure, a middle portion of an upper surface of the first metal silicide layer protrudes in a direction away from the substrate.

[0029] In an exemplary embodiment of the present disclosure, the device further includes a first source-drain electrode and a second source-drain electrode, wherein the first source-drain electrode and the second source-drain electrode are respectively located on both sides of the gate structure, and a surface of the first source-drain electrode is flush with a surface of the substrate, and a surface of the second source-drain electrode is flush with a surface of the substrate;

[0030] The device also includes a second metal silicide layer, which covers at least one of the surfaces of the first source and drain or the second source and drain, the upper surface of the second metal silicide layer is a curved surface, and the second metal silicide layer is a CoSi2 layer.

[0031] In an exemplary embodiment of the present disclosure, a middle portion of an upper surface of the second metal silicide layer protrudes in a direction away from the substrate.

[0032] In an exemplary embodiment of the present disclosure, the thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

[0033] In an exemplary embodiment of the present disclosure, the semiconductor device is selected from at least one of a PMOS device, an NMOS device or a CMOS device.

[0034] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising:

[0035] providing a substrate;

[0036] A gate structure protruding from the surface of the substrate is formed on the substrate, the gate structure comprising a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the surface of the gate oxide layer, the gate protection layer is formed on a side wall formed by the gate layer and the gate oxide layer, and a top surface of the gate protection layer is not lower than a top surface of the gate layer;

[0037] forming a first initial epitaxial layer protruding from the top surface of the gate layer, wherein the upper surface of the first initial epitaxial layer is a curved surface, and the first initial epitaxial layer is a Si layer;

[0038] forming a Co metal layer, wherein the Co metal layer conformally covers the first initial epitaxial layer;

[0039] The Co metal layer is heat treated to diffuse the Co in the Co metal layer into the first initial epitaxial layer, so that at least a portion of the first initial epitaxial layer is converted into a first metal silicide layer, the first metal silicide layer is a CoSi2 layer, and the remaining unconverted first initial epitaxial layer is a first epitaxial layer.

[0040] In an exemplary embodiment of the present disclosure, the heat treatment of the Co metal layer to diffuse the Co in the Co metal layer into the first initial epitaxial layer includes: the Co in the Co metal layer diffuses from the top surface to the bottom surface of the first initial epitaxial layer until the first initial epitaxial layer is completely converted into the first metal silicide layer.

[0041] In an exemplary embodiment of the present disclosure, before forming the first initial epitaxial layer protruding from the top surface of the gate layer, the method further includes:

[0042] The gate layer is subjected to laser annealing treatment to transform the gate layer into a single crystal structure.

[0043] In an exemplary embodiment of the present disclosure, the method further includes:

[0044] forming a first source-drain electrode and a second source-drain electrode in the substrate, wherein the first source-drain electrode and the second source-drain electrode are respectively located at two sides of the gate structure, and a surface of the first source-drain electrode is flush with a surface of the substrate, and a surface of the second source-drain electrode is flush with a surface of the substrate;

[0045] A second initial epitaxial layer is formed, wherein the second initial epitaxial layer covers at least one of the surfaces of the first source and drain or the second source and drain, and the second initial epitaxial layer protrudes from the surface of the substrate, the upper surface of the second initial epitaxial layer is a curved surface, and the second initial epitaxial layer is a Si layer.

[0046] In an exemplary embodiment of the present disclosure, the forming of the Co metal layer further includes: the Co metal layer conformally covers the second initial epitaxial layer.

[0047] In an exemplary embodiment of the present disclosure, the heat treatment of the Co metal layer further includes:

[0048] The Co metal layer is heat treated to diffuse the Co in the Co metal layer into the first initial second epitaxial layer, so that at least a portion of the second initial epitaxial layer is converted into a second metal silicide layer, the second metal silicide layer is a CoSi2 layer, and the remaining unconverted second initial epitaxial layer is a second epitaxial layer.

[0049] In an exemplary embodiment of the present disclosure, the Co metal layer is heat treated to diffuse the Co in the Co metal layer into the second initial epitaxial layer, including: the Co in the Co metal layer diffuses from the top surface to the bottom surface of the second initial epitaxial layer until the second initial epitaxial layer is completely converted into the second metal silicide layer.

[0050] In an exemplary embodiment of the present disclosure, the thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

[0051] In an exemplary embodiment of the present disclosure, a middle portion of an upper surface of the first metal silicide layer or the second metal silicide layer protrudes in a direction away from the substrate.

[0052] In an exemplary embodiment of the present disclosure, forming a gate structure protruding from a surface of the substrate on the substrate includes:

[0053] forming a stacked structure on the surface of the substrate, the stacked structure sequentially comprising an oxide material layer, a gate material layer and an etch stop layer;

[0054] Performing patterning on the stacked structure to form an initial gate structure;

[0055] forming a gate protection layer, wherein the gate protection layer conformally covers the surface of the initial gate structure and extends onto the surface of the substrate;

[0056] The gate protection layer and the etching stop layer on the top surface of the initial gate structure are removed simultaneously to expose the surface of the gate layer.

[0057] In an exemplary embodiment of the present disclosure, the method further includes:

[0058] Continue to remove the gate protection layer in a direction perpendicular to the substrate to expose a portion of the sidewall of the gate layer;

[0059] The first initial epitaxial layer covers the top surface and exposed sidewalls of the gate protection layer at the same time.

[0060] In an exemplary embodiment of the present disclosure, the heat treatment includes a first sub-heat treatment and a second sub-heat treatment, and the Co metal layer is heat treated, including:

[0061] A first sub-heat treatment is performed on the Co metal layer to diffuse Co in the Co metal layer into the first initial epitaxial layer, so as to form a first sub-metal silicide layer in the first initial epitaxial layer.

[0062] In an exemplary embodiment of the present disclosure, after forming the first sub-metal silicide layer, the method further includes:

[0063] The first sub-metal silicide layer is subjected to a second sub-heat treatment to at least partially transform the first sub-metal silicide layer into the first metal silicide layer, wherein the resistivity of the first metal silicide layer is less than the resistivity of the first sub-metal silicide layer.

[0064] In an exemplary embodiment of the present disclosure, after forming the first sub-metal silicide layer and before converting the first sub-metal silicide layer into the first metal silicide layer, the method further includes: removing the remaining unreacted Co metal layer.

[0065] On the one hand, the present disclosure provides a semiconductor device, in which a first epitaxial layer is formed between a metal silicide layer and a gate layer, and the upper surface of the first epitaxial layer is a curved surface, so as to increase the line width of the device. In the process of forming the metal silicide layer, the influence of the line width effect on the quality of the metal silicide film layer formation is overcome, and the generation of agglomeration defects of the metal silicide film layer is avoided. The formed metal silicide film layer has the characteristics of low resistivity, which helps to reduce the contact resistance of the device. In addition, due to the existence of the first epitaxial layer, the difference in thermal stability of the device caused by factors such as doping during the process can be balanced, thereby improving the thermal stability of the device and thus improving the overall performance of the device.

[0066] On the other hand, the present disclosure provides a semiconductor device, which forms a metal silicide layer on the surface of the gate layer, and the upper surface of the metal silicide layer is a curved surface. Since the metal silicide layer is formed outside the gate structure, it is different from directly doping the gate layer to form the metal silicide layer. This device overcomes the line width effect, and the formed metal silicide layer has better formation quality and overcomes the agglomeration defects caused by small line width, thereby improving the overall performance of the device.

[0067] On the other hand, the present disclosure provides a method for manufacturing a semiconductor device, which overcomes the line width effect by forming an epitaxial layer to increase the line width of the device and by doping the epitaxial layer to form a metal silicide layer. At the same time, the volume of the metal silicide layer can be increased while ensuring that the basic structure of the device is not damaged, thereby improving the functionality of the metal silicide layer, further reducing the contact resistance of the device, and improving the performance of the device. In addition, the introduction of the epitaxial layer can also balance the thermal stability differences of different parts of the device in the process flow, thereby improving the formation quality of the device.

[0068] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0070] Figure 1 The present invention discloses a flow chart of a method for manufacturing a semiconductor device in an exemplary embodiment.

[0071] Figure 2 The figure is a schematic diagram of a device structure having a gate oxide layer and a gate layer in an exemplary embodiment of the present disclosure.

[0072] Figure 3 It is a schematic diagram of a device structure with a protective material layer in an exemplary embodiment of the present disclosure.

[0073] Figure 4 It is a schematic diagram of the structure of the gate layer after laser annealing in an exemplary embodiment of the present disclosure.

[0074] Figure 5 It is a schematic diagram of a device structure having a gate structure, a first source and a drain, and a second source and a drain in an exemplary embodiment of the present disclosure.

[0075] Figure 6 It is a schematic diagram of a device structure having a first initial epitaxial layer and a second initial epitaxial layer in an exemplary embodiment of the present disclosure.

[0076] Figure 7 It is a schematic diagram of a device structure having a first metal silicide layer and a second metal silicide layer in an exemplary embodiment of the present disclosure.

[0077] Figure 8 The figure is a schematic diagram of a device structure with a protective layer in an exemplary embodiment of the present disclosure.

[0078] Fig. 9 It is a schematic diagram of a device structure with connection holes in an exemplary embodiment of the present disclosure.

[0079] Fig.10 It is a schematic diagram of another device structure having a first initial epitaxial layer and a second initial epitaxial layer in an exemplary embodiment of the present disclosure.

[0080] Fig.11 It is a schematic diagram of another device structure having a first metal silicide layer and a second metal silicide layer in an exemplary embodiment of the present disclosure.

[0081] Fig.12 It is a schematic diagram of another device structure with a protective layer in an exemplary embodiment of the present disclosure.

[0082] Fig.13 It is a schematic diagram of another device structure with connection holes in an exemplary embodiment of the present disclosure.

[0083] The reference numerals are described as follows:

[0084] 100, substrate; 200, gate structure; 210, gate oxide layer; 220, gate layer; 230, gate protection layer; 310, first source and drain; 320, second source and drain; 410, first initial epitaxial layer; 411, first epitaxial layer; 420, second initial epitaxial layer; 421, second epitaxial layer; 510, first metal silicide layer; 520, second metal silicide layer; 610, etch stop layer; 620, protection material layer; 700, isolation structure; 800, protection layer; 900, connection hole. DETAILED DESCRIPTION

[0085] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0086] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0087] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0088] In the related art, due to the increasing requirements for the degree of integration of semiconductor devices, the size of semiconductor devices is also constantly shrinking, which poses a huge challenge to the semiconductor process, especially with the reduction of feature size, the change in the performance of the film layer inside the device directly or indirectly changes the overall performance of the device. In the semiconductor structure, metal silicide is usually one of the indispensable film layers in semiconductor devices due to its characteristics of reducing contact resistance, improving thermal stability, and improving device performance. When it contacts the source, drain or gate in the device, it can significantly reduce resistance and improve the conductivity of current, which is crucial to the improvement of the overall electrical performance of the device; in addition, the metal silicide film layer has good thermal stability and is not easy to decompose or degrade in high-temperature processes. It also plays an important role in the semiconductor process. Therefore, it is necessary to ensure the formation of a uniform and low-resistance metal silicide film layer.

[0089] At present, the formation of metal silicide is usually carried out by depositing a metal layer on the surface of a silicon-based material, and then performing a high-temperature annealing process to allow the metal to react with silicon to form a metal silicide. The metal silicide layer has multiple resistance phases during its formation. Under low temperature conditions, the formed metal silicide layer is in a high resistance state. If the temperature is further increased, silicon ions continue to diffuse into the high resistance metal silicide film layer, so that the metal silicide is converted from a high resistance state to a low resistance state.

[0090] However, due to the reduction in the characteristic size of the device, in the process of diffusing silicon ions in the silicon-based material into the formed high-resistance metal silicide layer through a heat treatment process, the silicon ions are inhibited from diffusing by the film layer boundary and it is difficult for them to diffuse evenly into the formed metal silicide layer, so that the surface layer of the metal silicide layer is still in a high-resistance molecular structure, resulting in the inability to form a metal silicide film layer with uniform structure and low resistance, thereby reducing the performance of the metal silicide layer.

[0091] Based on this, the present disclosure provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, the manufacturing method includes: steps S10 to S50.

[0092] Wherein, step S10: providing a substrate;

[0093] Step S20: forming a gate structure protruding from the surface of the substrate on the substrate, the gate structure comprising a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the surface of the gate oxide layer, the gate protection layer is formed on a side wall formed by the gate layer and the gate oxide layer, and the top surface of the gate protection layer is not lower than the top surface of the gate layer;

[0094] Step S30: forming a first initial epitaxial layer protruding from the top surface of the gate layer, wherein the upper surface of the first initial epitaxial layer is a curved surface, and the first initial epitaxial layer is a Si layer;

[0095] Step S40: forming a Co metal layer, wherein the Co metal layer conformally covers the first initial epitaxial layer;

[0096] Step S50: heat-treating the Co metal layer to diffuse the Co in the Co metal layer into the first initial epitaxial layer, so that at least a portion of the first initial epitaxial layer is converted into a first metal silicide layer, the first metal silicide layer is a CoSi2 layer, and the remaining unconverted first initial epitaxial layer is the first epitaxial layer.

[0097] The present invention provides a method for manufacturing a semiconductor device, which forms a first initial epitaxial layer on the surface of a gate layer and a metal layer on the first initial epitaxial layer, and converts at least a portion of the first initial epitaxial layer into a metal silicide layer through a diffusion doping process. The epitaxial layer is formed to increase the line width of the device, thereby overcoming the influence of the line width effect on the formation quality of the metal silicide layer, improving the formation quality of the metal silicide layer, thereby reducing the contact resistance in the device and improving the overall performance of the device.

[0098] The following will describe in detail the various steps of the method for manufacturing a semiconductor device according to the embodiment of the present disclosure in conjunction with the accompanying drawings:

[0099] In the embodiments provided in the present disclosure, Figure 2 As shown, in step S10 , a substrate 100 is provided.

[0100] Wherein, the substrate 100 may be a silicon (Si) substrate, SOI (Silicon on Insulator), etc., and its surface may be used to directly generate an epitaxial layer having a single crystal silicon structure. In some embodiments, the substrate 100 may also be other types of substrates, such as a sapphire (Al2O3) substrate, SOS (Silicon-on-Sapphire) or GOI (Germanium on Insulator), or a substrate including other element semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs), etc. It should be noted that when the substrate 100 is other types of substrates, it may be used as a heterogeneous substrate, on which a silicon buffer layer is grown to provide a film layer foundation for the subsequent growth of the epitaxial layer. The embodiments provided in the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the scope of protection of the present disclosure.

[0101] In the embodiment provided in the present disclosure, in order to form multiple active regions on the substrate 100, the positions of the multiple active regions on the substrate 100 may be predefined, and multiple isolation structures 700 may be formed in the substrate 100 to divide the substrate 100 to form multiple active regions. Figure 2 As shown, a plurality of isolation structures 700 may be arranged at intervals on the substrate 100 and may be distributed in an array, and each isolation structure 700 may electrically isolate and insulate the semiconductor devices located in adjacent active regions, thereby improving the electrical performance of the devices. At least one semiconductor device is arranged in each active region, and the distribution form of the semiconductor devices and the distance between adjacent semiconductor structures may be selected according to the actual design requirements of the devices.

[0102] The method for forming the isolation structure 700 on the substrate 100 may include: defining an area on the substrate 100 where the isolation structure 700 is formed by photolithography, and etching a shallow trench in the defined area by dry or wet etching; filling the shallow trench with an insulating material, such as silicon oxide (SiO2), to form an isolation film layer in the shallow trench; and then performing a planarization process to expose the surface of the substrate 100. By providing the isolation structure 700 on the substrate 100, current leakage between devices can be effectively prevented, and the performance and reliability of the device can be improved.

[0103] In the embodiment provided in the present disclosure, in step S20, a gate structure 200 protruding from the surface of the substrate 100 is formed on the substrate 100, and the gate structure 200 includes a gate oxide layer 210, a gate layer 220 and a gate protection layer 230. The gate oxide layer 210 is formed on the surface of the substrate 100, the gate layer 220 is formed on the surface of the gate oxide layer 210, and the gate protection layer 230 is formed on the side wall jointly formed by the gate layer 220 and the gate oxide layer 210, and the top surface of the gate protection layer 230 is not lower than the top surface of the gate layer 220.

[0104] After forming the isolation structure 700 in the substrate 100, as shown in FIG. Figure 5As shown, the manufacturing method also includes: forming a gate structure 200 protruding from the surface of the substrate 100 on the substrate 100. Specifically, the gate structure 200 includes a gate oxide layer 210, and the gate oxide layer 210 is formed on the surface of the substrate 100. Among them, the gate oxide layer 210 can be silicon dioxide (SiO2) or other high-K dielectric material layers, such as one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or yttrium oxide (Y2O3). It can be formed by one or more of methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE) or plasma enhanced chemical vapor deposition (PECVD). The specific formation method can be adaptively selected and adjusted according to the material and other characteristics of the gate oxide layer 210.

[0105] The gate structure 200 further includes a gate layer 220, such as Figure 2 As shown, the gate layer 220 is formed on the surface of the gate oxide layer 210. The gate layer 220 is formed on the surface of the gate oxide layer 210, and the gate layer 220 can be polysilicon (poly) or other metal materials, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), cobalt (Co), nickel (Ni), ruthenium (Ru) or iridium (Ir) One or more. It can be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALE), sputtering, photolithography or etching, etc., and can be selected according to the material and other characteristics of the gate layer 220. In the embodiment provided in the present disclosure, the gate layer 220 is polysilicon as an example for explanation, but it should be noted that the gate layer 220 of the present disclosure can also be made of materials other than polysilicon. If the gate layer 220 is made of other metal materials, in order to form an epitaxial layer on the gate layer 220 in subsequent processes, a buffer layer may be first formed on the exposed top surface of the gate layer 220 to provide a structural basis for the subsequent growth of the epitaxial layer.

[0106] The gate structure 200 also includes a gate protection layer 230, which is formed on the side wall formed by the gate layer 220 and the gate oxide layer 210. Among them, the gate protection layer 230 may include at least one insulating layer and at least one passivation layer formed in sequence along the side wall direction away from the gate layer 220. Of course, according to the actual structural requirements of the device, the gate protection layer 230 may also be formed by an insulating layer or a passivation layer. If there are multiple insulating layers and passivation layers, the multiple insulating layers and the multiple passivation layers are alternately distributed on the side wall of the gate layer 220 in sequence along the side wall direction away from the gate layer 220, and the film layer farthest from the gate side wall can be a passivation layer. In the embodiment of the present disclosure, the gate protection layer 230 is taken as an example of a multi-layer structure.

[0107] The insulating layer in the gate protection layer 230 may be silicon dioxide (SiO2) or other high dielectric constant material layer, such as one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3) or yttrium oxide (Y2O3). It may be formed by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The specific formation method may be adaptively selected and adjusted according to the material and other characteristics of the insulating layer.

[0108] The passivation layer can be made of materials such as silicon nitride (Si3N4), which can be formed by methods such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). Of course, the material of the passivation layer can also be formed by other materials and process methods according to the actual structural requirements of the device.

[0109] In some embodiments, forming a gate structure 200 protruding from a surface of the substrate 100 on the substrate 100 may include: steps S201 to S204 .

[0110] Wherein, step S201: forming a stack structure on the surface of the substrate 100, the stack structure sequentially comprising an oxide material layer, a gate material layer and an etching stop layer 610;

[0111] Step S202: performing patterning on the stacked structure to form an initial gate structure 200;

[0112] Step S203 : forming a gate protection layer 230 , wherein the gate protection layer 230 conformally covers the surface of the initial gate structure 200 and extends to the surface of the substrate 100 ;

[0113] Step S204 : removing the gate protection layer 230 and the etching stop layer 610 on the top surface of the initial gate structure 200 simultaneously to expose the surface of the gate layer 220 .

[0114] In order to facilitate the formation of subsequent film layers on the surface of the gate layer 220, the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. Figure 5 As shown, when the top surface of the gate protection layer 230 is lower than the top surface of the gate layer 220, after the surface of the gate layer 220 is exposed, in order to further increase the line width of the gate and provide a device structure foundation with a better structure for the formation of subsequent film layers, the method may also include: continuing to remove the gate protection layer 230 in a direction perpendicular to the substrate 100 to expose part of the side wall of the gate layer 220; the first initial epitaxial layer 410 simultaneously covers the top surface and the exposed side wall of the gate protection layer 230. By removing the gate protection layer 230 in a direction close to the substrate 100 to expose part of the side wall of the gate layer 220 close to the top surface, the exposed side wall can form the process line width of the gate structure 200 together with the top surface, so as to increase the line width of the gate structure 200 and provide a larger line width for the formation of the metal silicide layer.

[0115] It should be noted that, since the gate protection layer 230 can be formed by alternating multiple passivation layers and multiple insulation layers, the etching selectivity of the two layers under the same process conditions is different, and it is difficult to ensure that the size of the insulation layer and the passivation layer removed is the same or approximately the same through the same process. Therefore, two or more steps of processing can be used to remove the insulation layer and the passivation layer respectively to achieve the purpose of exposing the side wall of the gate layer 220. The specific etching process can be selected according to the actual process requirements. Among them, the height of the exposed side wall of the gate layer 220 can be 10% to 30% of the overall height of the gate layer 220, which not only ensures the insulation and isolation effect of the gate protection layer 230, but also ensures that the gate structure 200 achieves the purpose of increasing the line width, so as to provide a device foundation for the formation of subsequent film layers.

[0116] In the embodiment provided in the present disclosure, after forming the gate structure 200 on the substrate 100, the manufacturing method may further include: forming a first source and drain 310 and a second source and drain 320 in the substrate 100, the first source and drain 310 and the second source and drain 320 are respectively located on both sides of the gate structure 200, the surface of the first source and drain 310 is flush with the surface of the substrate 100, and the surface of the second source and drain 320 is flush with the surface of the substrate 100.

[0117] Among them, the single semiconductor device composed of the gate structure 200, the first source and drain 310 and the second source and drain 320 can be any one selected from an NMOS (N-type Metal-Oxide-Semiconductor Field-Effect Transistor) device, a PMOS (P-type Metal-Oxide-SemiconductorField-Effect Transistor, P-type Metal-Oxide-SemiconductorField-Effect Transistor) device or a CMOS (Complementary Metal-Oxide-Semiconductor) device.

[0118] When the single semiconductor device is an NMOS device, the substrate 100 can be a P-type silicon substrate, and an N-type well or an N-type isolation region is formed on the substrate 100; two high-concentration N-type regions are formed in the N-type well by ion implantation or diffusion process to form a source or drain.

[0119] When the single semiconductor device is a PMOS device, the substrate 100 may be a P-type silicon substrate, an epitaxial layer is formed on the substrate 100, and the epitaxial layer may be N-type; an N-type well or an N-type isolation region is formed in the epitaxial layer by ion implantation or diffusion process; two high-concentration P-type regions are formed in the N-type well by ion implantation or diffusion process to form a source or a drain. In the present disclosure, it can be understood that the substrate 100 proposed herein includes an epitaxial layer required to form a PMOS device.

[0120] Of course, a single semiconductor device can also be a CMOS device, and its formation method can be analogous to the formation method of PMOS or NMOS, or the combination of the above two formation methods can be adaptively deformed to obtain the formation process of the CMOS device, which will not be described in detail here. The embodiment provided in the present disclosure is described by taking a single semiconductor device as a CMOS device as an example, but it should be noted that when a single semiconductor device is a device structure of different types, it can be formed by the manufacturing method provided in the present disclosure after adaptive deformation.

[0121] The inventors discovered that in the above-mentioned device structure, the line width of the formed device is already fixed. Especially for the existing small line width (line width less than 40nm) devices, it is difficult to achieve the purpose of increasing the line width of the top of the device through etching processes, etc., so that the subsequent processes are severely restricted by the line width of the device, especially the formed metal silicide film layer, which is affected by the line width effect and will have agglomeration defects, affecting the contact resistance and performance of the device.

[0122] In the embodiment provided in the present disclosure, in step S30, a first initial epitaxial layer 410 protruding from the top surface of the gate layer 220 is formed, the upper surface of the first initial epitaxial layer 410 is a curved surface, and the first initial epitaxial layer 410 is a Si layer.

[0123] Before forming the first initial epitaxial layer 410, Figure 4 As shown, the method further includes: performing laser annealing on the gate layer 220 to convert the gate layer 220 into a single crystal structure. Since the gate layer 220 is made of polycrystalline silicon material, it is difficult to grow an epitaxial layer when an epitaxial process is adopted. Therefore, it is necessary to perform laser annealing on the gate layer 220 to convert the polycrystalline silicon structure of the gate layer 220 into a single crystal structure, so as to facilitate the subsequent formation of an epitaxial layer on its surface.

[0124] Before the gate layer 220 is subjected to laser degradation treatment, Figure 3 As shown, the method further includes: forming a protective material layer 620, the protective material layer 620 conformally covers the surface of the gate layer 220 and extends to the surface of the substrate 100. The protective material layer 620 can protect the gate layer 220 and can also control the heat distribution during the laser annealing process to ensure that the heat can be evenly transferred to the gate layer 220, thereby avoiding damage to the gate layer 220 caused by thermal unevenness.

[0125] Among them, the protective material layer 620 can be made of materials such as silicon nitride (Si3N4), which can be formed by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) and other methods. Of course, the material of the protective material layer 620 can also be formed by other materials and process methods according to the actual structural requirements of the device.

[0126] like Figure 6 As shown, the first initial epitaxial layer 410 is formed on the top surface of the gate layer 220, including: when the top surface of the gate protection layer 230 is flush with the top surface of the gate layer 220, the first initial epitaxial layer 410 is formed on the top surface of the gate layer 220; when the top surface of the gate protection layer 230 is lower than the top surface of the gate layer 220, the first initial epitaxial layer 410 is formed on the top surface of the gate layer 220 and its exposed side walls.

[0127] Among them, the first initial epitaxial layer 410 can be formed on the gate layer 220 by an epitaxial process, such as forming a first initial epitaxial layer 410 composed of single crystal silicon on the surface of the gate layer 220 by chemical vapor deposition (CVD) and other methods. The thickness of the first initial epitaxial layer 410 can be 6nm~14nm, such as 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, etc. The thickness of the first initial epitaxial layer 410 can refer to the maximum thickness value, the minimum thickness value or the average thickness value between the upper surface and the lower surface of the first initial epitaxial layer 410. When measuring and comparing the thickness value of the first initial epitaxial layer 410, one of the above values ​​can be used as a standard, but other film layers used for comparison need to be based on the same standard. Among them, the upper surface and the lower surface refer to the surface of the film layer on the side away from the substrate 100 and the surface on the side close to the substrate 100, respectively, and the upper and lower surfaces do not limit the specific position of the film layer.

[0128] In some embodiments, the upper surface of the first initial epitaxial layer 410 is a curved surface, which can be concave or convex relative to the surface of the substrate 100. In the present disclosure, the middle portion of the upper surface of the first initial epitaxial layer 410 protrudes in the direction away from the substrate 100, that is, the upper surface of the first initial epitaxial layer 410 is convex relative to the surface of the substrate 100, thereby increasing the surface area of ​​the upper surface of the first initial epitaxial layer 410 to increase the line width of the device gate structure 200. Of course, different process parameters can also be set to control the upper surface of the first initial epitaxial layer 410 to be concave relative to the surface of the substrate 100, which can also achieve the purpose of increasing the device line width.

[0129] While forming the first initial epitaxial layer 410, Figure 6 As shown, the method may further include: forming a second initial epitaxial layer 420, the second initial epitaxial layer 420 covers at least one of the surfaces of the first source and drain 310 or the second source and drain 320, and the second initial epitaxial layer 420 protrudes from the surface of the substrate 100, the upper surface of the second initial epitaxial layer 420 is a curved surface, and the second initial epitaxial layer 420 is a Si layer. The first initial epitaxial layer 410 and the second initial epitaxial layer 420 can be formed simultaneously using an epitaxial process, and both can be formed in the same process step to save process steps and simplify the process. Of course, both can also be formed in steps according to process requirements. The process and thickness used to form the second initial epitaxial layer 420 can be the same or similar to those of the first initial epitaxial layer 410, and will not be repeated here.

[0130] The second initial epitaxial layer 420 covers at least one of the surface of the first source and drain 310 or the surface of the second source and drain 320. For example, the second initial epitaxial layer 420 may cover the surface of the first source and drain 310 and the surface of the second source and drain 320; or the second initial epitaxial layer 420 only covers the surface of the first source and drain 310; or the second initial epitaxial layer 420 only covers the surface of the second source and drain 320. In order to increase the line width of the first source and drain 310 and the second source and drain 320 at the same time, the second initial epitaxial layer 420 may cover the surface of the first source and drain 310 and the surface of the second source and drain 320.

[0131] The second initial epitaxial layer 420 protrudes from the surface of the substrate 100, the upper surface of the second initial epitaxial layer 420 is a curved surface, and the second initial epitaxial layer 420 is a Si layer. If the first source and drain 310 and the second source and drain 320 are the source and drain of an NMOS device, the second initial epitaxial layer 420 can cover the first source and drain 310 and the second source and drain 320, and the edge of the second initial epitaxial layer 420 can be aligned with the edge position of the first source and drain 310 and the second source and drain 320; if the first source and drain 310 and the second source and drain 320 are the source and drain of a PMOS device, the second initial epitaxial layer 420 can cover the first source and drain 310 and the second source and drain 320 and extend to the surface of the substrate 100, and the orthographic projection of the second initial epitaxial layer 420 on a certain cross section on the substrate 100 covers the orthographic projection of the first source and drain 310 and the second source and drain 320 on the same cross section.

[0132] In some embodiments, the upper surface of the second initial epitaxial layer 420 is a curved surface, which can be concave or convex relative to the surface of the substrate 100. In the present disclosure, the middle portion of the upper surface of the second initial epitaxial layer 420 protrudes in the direction away from the substrate 100, that is, the upper surface of the second initial epitaxial layer 420 is convex relative to the surface of the substrate 100, thereby increasing the surface area of ​​the upper surface of the second initial epitaxial layer 420 to increase the line width of the source and drain of the device. Of course, different process parameters can also be set to control the upper surface of the second initial epitaxial layer 420 to be concave relative to the surface of the substrate 100, which can also achieve the purpose of increasing the line width of the source and drain of the device.

[0133] The shapes of the first initial epitaxial layer 410 and the second initial epitaxial layer 420 can be the same or different according to process requirements. However, for process convenience, the same shape is usually selected, such as both are convex surfaces relative to the substrate 100.

[0134] In the embodiment provided by the present disclosure, in step S40, a Co metal layer is formed, and the Co metal layer conformally covers the first initial epitaxial layer 410. In the process of forming the metal silicide layer in the device, since CoSi2 has the characteristic of forming a molecular structure of a low resistance state in a high temperature process, it is often used to prepare a metal silicide layer in a semiconductor device to reduce the contact resistance of the device and improve the overall performance of the device. The formation of CoSi2 can be achieved by controlling the process temperature so that the metals in the Si film layer and the Co film layer diffuse with each other, and controlling its molecular structure so that it forms a low resistance film layer structure.

[0135] In some embodiments, the Co metal layer can conformally cover the first initial epitaxial layer 410 and the second initial epitaxial layer 420 at the same time, and the thickness of the Co metal layer can be 5nm to 20nm, for example, it can be 5nm, 10nm, 15nm, 20nm, etc. The Co metal layer can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or other methods, and the specific formation process and parameters of the Co metal layer can be selected according to actual process requirements.

[0136] In order to avoid the influence of external impurities on the Co metal layer, especially to avoid the oxidation of the Co metal layer by oxygen, after forming the Co metal layer, the method may further include: forming a covering film, which is conformally covered on the surface of the Co metal layer. The covering film may be one or more of materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), etc., which may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) and the like. The specific material and formation process of the covering film may be adaptively selected and adjusted according to the device process design. Taking the covering film as titanium nitride (TiN) as an example, the thickness of the covering film may be 5nm to 15nm, for example, the covering film may be 5nm, 8nm, 10nm, 13nm, 15nm, etc.

[0137] In the embodiments provided in the present disclosure, Figure 7 As shown, in step S50, the Co metal layer is heat treated to diffuse the Co in the Co metal layer into the first initial epitaxial layer 410, so that at least a portion of the first initial epitaxial layer 410 is converted into a first metal silicide layer 510, and the first metal silicide layer 510 is a CoSi2 layer.

[0138] If the device further includes a second initial epitaxial layer 420, the Co metal layer is subjected to heat treatment, such as Figure 7As shown, the method also includes: heat treating the Co metal layer to diffuse the Co in the Co metal layer into the second initial epitaxial layer 420, so that at least a portion of the second initial epitaxial layer 420 is converted into a second metal silicide layer 520, and the second metal silicide layer 520 is a CoSi2 layer.

[0139] Through the above-mentioned heat treatment process, a CoSi2 layer is formed in the area near the top of the first initial epitaxial layer 410 and the second initial epitaxial layer 420. Since this CoSi2 layer is formed in the first initial epitaxial layer 410 and the second initial epitaxial layer 420, it has a larger line, overcomes the agglomeration defect caused by the line width effect, and can reduce the contact resistance of the device. In addition, due to the formation of the first initial epitaxial layer 410 and the second initial epitaxial layer 420, the thermal stability difference inside the device can be effectively balanced, further improving the formation quality of the device and improving the performance of the device.

[0140] In some embodiments, the Co metal layer is heat treated to diffuse the Co in the Co metal layer into the first initial epitaxial layer 410. Fig.10 and Fig.11 As shown, the Co in the Co metal layer diffuses from the top surface to the bottom surface of the first initial epitaxial layer 410 until the first initial epitaxial layer 410 is completely converted into the first metal silicide layer 510. By completely converting the first initial epitaxial layer 410 into the first metal silicide layer 510, the thickness of the first initial epitaxial layer 410 is reduced, and the resistance of the device can be reduced. At the same time, due to the increase in the thickness of the first metal silicide layer 510, the contact resistance of the device is further reduced.

[0141] In some embodiments, the Co metal layer is heat treated to diffuse the Co in the Co metal layer into the second initial epitaxial layer 420. Fig.10 and Fig.11 As shown, the Co in the Co metal layer diffuses from the top surface to the bottom surface of the second initial epitaxial layer 420 until the second initial epitaxial layer 420 is completely converted into the second metal silicide layer 520. By completely converting the second initial epitaxial layer 420 into the second metal silicide layer 520, the thickness of the second initial epitaxial layer 420 is reduced, and the resistance of the device can be reduced. At the same time, due to the increase in the thickness of the second metal silicide layer 520, the contact resistance of the device is further reduced.

[0142] The transformation process of the first initial epitaxial layer 410 and the second initial epitaxial layer 420 in the above two embodiments can be performed simultaneously, so as to save process steps and improve process convenience.

[0143] It should be noted that, in the process of heat treating the Co metal layer to form a first metal silicide, due to the uncertainty of the diffusion of Co metal, a first metal silicide layer 510 will also be formed in the top layer area of ​​the gate layer 220. The first metal silicide layer 510 formed in the gate layer 220 is included in the first metal silicide layer 510 provided in the present disclosure, and it also has the function of reducing contact resistance and improving device performance.

[0144] During the process of heat treating the Co metal layer to form a second metal silicide, due to the uncertainty of the diffusion of Co metal, a second metal silicide layer 520 will also be formed in the top layer area of ​​the first source and drain 310 and the second source and drain 320. The second metal silicide layer 520 formed in the first source and drain 310 and the second source and drain 320 is included in the second metal silicide layer 520 provided in the present disclosure, and it also has the function of reducing contact resistance and improving device performance.

[0145] In the embodiment provided in the present disclosure, since the CoSi2 layer is formed by mutual diffusion doping between Si and Co, at different heat treatment temperatures, the molecular morphology of the formed metal silicide layer is different, resulting in different resistance values. In order to obtain a low-resistance CoSi2 layer, the heat treatment may include a first sub-heat treatment and a second sub-heat treatment. The Co metal layer is heat treated, including: performing a first sub-heat treatment on the Co metal layer to diffuse the Co in the Co metal layer into the first initial epitaxial layer 410 to form a first sub-metal silicide layer in the first initial epitaxial layer 410.

[0146] The first sub-metal silicide layer may include dicobalt silicon (Co2Si) and cobalt silicon (CoSi), and the thickness of the first sub-metal silicide layer may be 6nm to 14nm, for example, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm or 14nm, etc. The thickness of the formed first sub-metal silicide layer may be different according to the ratio between dicobalt silicon (Co2Si) and cobalt silicon (CoSi) in the first sub-metal silicide layer. In this embodiment, the thickness of the first sub-metal silicide layer refers to the size of the film layer in a direction perpendicular to the substrate 100.

[0147] The first sub-heat treatment can be divided into two steps, wherein the first step of the first sub-heat treatment includes: at a temperature of 250°C to 410°C, using cobalt in the Co metal layer as a diffusion source to allow cobalt to be doped into the first initial epitaxial layer 410 and the second initial epitaxial layer 420, to form dicobaltized silicon (Co2Si) in the first initial epitaxial layer 410 and the second initial epitaxial layer 420, especially in the first initial epitaxial layer 410 and the second initial epitaxial layer 420 near the surface, the concentration of cobalt ions is higher, and more dicobaltized silicon (Co2Si) is formed.

[0148] The second step of the first sub-heat treatment includes: at a temperature of 410°C to 700°C, cobalt continues to serve as a diffusion source and further diffuses into the first initial epitaxial layer 410 and the second initial epitaxial layer 420, forming cobaltized silicon (CoSi) in the first initial epitaxial layer 410 and the second initial epitaxial layer 420. After the heat treatment, dicobaltized silicon (Co2Si) and cobaltized silicon (CoSi) can exist in the first sub-metal silicide layer at the same time, and the resistivity of dicobaltized silicon (Co2Si) and cobaltized silicon (CoSi) are both high, and the resistance value of the formed first sub-metal silicide layer is also large. The temperature ranges in the first and second steps of the above-mentioned first sub-heat treatment are only shown as exemplary embodiments. In the actual heat treatment process, the above-mentioned temperature ranges do not have strict limits and can be adaptively adjusted according to actual process requirements.

[0149] In order to further form a metal silicide film layer with a lower resistance, after forming the first sub-metal silicide layer, the method also includes: performing a second sub-heat treatment on the first sub-metal silicide layer to convert the first sub-metal silicide layer at least partially into a first metal silicide layer 510, wherein the resistivity of the first metal silicide layer 510 is less than the resistivity of the first sub-metal silicide layer.

[0150] As the temperature of the heat treatment further increases, such as when the temperature increases to greater than 700°C, the silicon in the device diffuses into the first sub-metal silicide layer as a diffusion source, and the formed dicobalt silicon (Co2Si) and cobalt silicon (CoSi) continue to combine with silicon to form cobalt disilicide (CoSi2). The resistivity of cobalt disilicide (CoSi2) is smaller than that of dicobalt silicon (Co2Si) and cobalt silicon (CoSi). The resistance value of cobalt disilicide (CoSi2) is small, which can effectively reduce the contact resistance and improve the overall electrical performance of the device.

[0151] The temperature of the second sub-heat treatment may be greater than 700°C, such as 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C or even higher. The time of the second sub-heat treatment may also be different according to the temperature in the temperature condition. The second sub-heat treatment time may be in the nanosecond to millisecond range. For example, under a higher temperature condition, the treatment time may be appropriately shortened; under a lower temperature condition, the treatment time may be appropriately increased.

[0152] In some embodiments, after forming the first sub-metal silicide layer and before the first sub-metal silicide layer is converted into the first metal silicide layer 510, the method further includes: removing the remaining unreacted Co metal layer. The remaining unreacted Co metal layer can be removed by wet chemical etching, dry etching, mechanical polishing, laser etching, electrochemical etching, etc. The specific process can be selected according to the actual process design requirements.

[0153] Before removing the remaining unreacted Co metal layer, the method further includes: removing the covering film. Taking TiN as an example, wet etching, dry etching, chemical mechanical polishing or laser stripping can be used. The specific method can be selected according to the actual process design requirements.

[0154] In some embodiments, the thickness of the first metal silicide layer 510 and the second metal silicide layer 520 can be 6nm to 14nm, such as 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm or 14nm. The thickness of the first metal silicide layer 510 and the second metal silicide layer 520 can be adaptively selected and adjusted according to process requirements, and the thickness of the two can be the same or different.

[0155] In some embodiments, the middle portion of the upper surface of the first metal silicide layer 510 or the second metal silicide layer 520 protrudes in a direction away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 or the second metal silicide layer 520 is convex relative to the surface of the substrate 100. This structural shape facilitates process manufacturing, simplifies the process, and at the same time achieves the purpose of increasing the device line width.

[0156] In some embodiments, after forming the first metal silicide layer 510 and the second metal silicide layer 520, as shown in FIG. Figure 8 and Fig.12As shown, the method further includes: forming a protective layer 800 covering the surface of the device structure. The protective layer 800 can protect the device structure located thereunder. The protective layer 800 can be made of materials such as silicon nitride (Si3N4) and can be formed by one or more methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD).

[0157] In some embodiments, after forming the protective layer 800, multiple stacked film layers may be formed on the device having the protective layer 800, and then multiple connection holes 900 may be etched in the stacked film layers by etching or other processes, such as Fig. 9 and Fig.13 As shown, the connection hole 900 may be filled with a conductive material, and the device may be electrically connected to the outside through the connection hole 900. Of course, the semiconductor device provided by the present disclosure may also have other film layers and structures not shown, such as structures and film layers necessary for the semiconductor device to achieve conventional functions, etc. Although these structures are not specifically described in this article, it should be understood that the semiconductor device in the present disclosure also includes other film layers and structures required to achieve its conventional functions.

[0158] The present disclosure provides a method for manufacturing a semiconductor device, which forms a first initial epitaxial layer 410 on the surface of a gate layer 220, and forms a Co metal layer on the first initial epitaxial layer 410, and converts at least a portion of the first initial epitaxial layer 410 into a metal silicide layer through a diffusion doping process. The epitaxial layer is formed to increase the line width of the device, thereby overcoming the influence of the line width effect on the formation quality of the metal silicide layer, improving the formation quality of the metal silicide layer, thereby reducing the contact resistance in the device and improving the overall performance of the device.

[0159] It should be noted that, although the steps of the method for manufacturing a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0160] The present disclosure provides a semiconductor device, such as Fig. 9 As shown, the device includes: a substrate 100 , a gate structure 200 , a first epitaxial layer 411 and a first metal silicide layer 510 .

[0161] Among them, the gate structure 200 is protrudingly arranged on the surface of the substrate 100, and the gate structure 200 includes a gate oxide layer 210, a gate layer 220 and a gate protection layer 230. The gate oxide layer 210 is formed on the surface of the substrate 100, the gate layer 220 is formed on the gate oxide layer 210, and the gate protection layer 230 covers the side wall jointly formed by the gate oxide layer 210 and the gate layer 220, and the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220; the first epitaxial layer 411 covers the top surface of the gate layer 220, and the upper surface of the first epitaxial layer 411 is a curved surface, and the first epitaxial layer 411 is a Si layer; the first metal silicide layer 510 conformally covers the first epitaxial layer 411, and the upper surface of the first metal silicide layer 510 is a curved surface, and the first metal silicide layer 510 is a CoSi2 layer.

[0162] The semiconductor device provided by the present invention has a first epitaxial layer 411 formed between the metal silicide layer and the gate layer 220, and the upper surface of the first epitaxial layer 411 is a curved surface, so as to increase the line width of the device. In the process of forming the metal silicide layer, the influence of the line width effect on the quality of the metal silicide film layer formation is overcome, and the generation of agglomeration defects of the metal silicide film layer is avoided. The formed metal silicide film layer has the characteristics of low resistivity, which helps to reduce the contact resistance of the device. In addition, due to the existence of the first epitaxial layer 411, the difference in thermal stability of the device caused by factors such as doping during the process can be balanced, thereby improving the thermal stability of the device and thus improving the overall performance of the device.

[0163] The various parts of the semiconductor device provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings:

[0164] The semiconductor device provided by the present disclosure can be manufactured by the above-mentioned manufacturing method.

[0165] Wherein, the substrate 100 may be a silicon (Si) substrate, SOI (Silicon on Insulator), etc., and its surface may be used to directly generate an epitaxial layer having a single crystal silicon structure. In some embodiments, the substrate 100 may also be other types of substrates, such as a sapphire (Al2O3) substrate, SOS (Silicon-on-Sapphire) or GOI (Germanium on Insulator), or a substrate including other element semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs), etc. It should be noted that when the substrate 100 is other types of substrates, it may be used as a heterogeneous substrate, on which a silicon buffer layer is grown to provide a film layer foundation for the subsequent growth of the epitaxial layer. The embodiments provided in the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the scope of protection of the present disclosure.

[0166] In some embodiments, the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. The top surface of the gate protection layer 230 may be lower than the top surface of the gate layer 220, and the gate protection layer 230 exposes part of the sidewall of the gate layer 220. The first epitaxial layer 411 covers the top surface and the exposed sidewall of the gate layer 220. The exposed sidewall and the top surface may form the process line width of the gate structure 200 together to increase the line width of the gate structure 200 and provide a larger line width for the formation of the metal silicide layer. The top surface of the gate protection layer 230 may be flush with the top surface of the gate layer 220, and the first epitaxial layer 411 covers the top surface of the gate layer 220, and the sidewall of the first epitaxial layer 411 is flush with the sidewall of the gate layer 220.

[0167] Among them, the exposed height of the side wall of the gate layer 220 can be 10% to 30% of the overall height of the gate layer 220, which not only ensures the insulation and isolation function of the gate protection layer 230, but also ensures that the gate structure 200 achieves the purpose of increasing the line width, thereby providing a device foundation for the formation of subsequent film layers.

[0168] In some embodiments, the upper surface of the first epitaxial layer 411 is convex or concave relative to the surface of the substrate 100, and such surfaces can achieve the purpose of increasing the line width of the device gate structure 200. Among them, the first metal silicide layer 510 is conformally formed on the first epitaxial layer 411. When the first epitaxial layer 411 is convex, the middle part of the upper surface of the first metal silicide layer 510 protrudes in the direction away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is convex relative to the surface of the substrate 100; when the first epitaxial layer 411 is concave, the middle part of the upper surface of the first metal silicide layer 510 is recessed in the direction away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is concave relative to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the steps of the device preparation process, the first epitaxial layer 411 and the first metal silicide layer 510 can be convex relative to the surface of the substrate 100.

[0169] In the embodiment provided in the present disclosure, the device also includes a first source and drain 310 and a second source and drain 320, the first source and drain 310 and the second source and drain 320 are respectively located on both sides of the gate structure 200, the surface of the first source and drain 310 is flush with the surface of the substrate 100, and the surface of the second source and drain 320 is flush with the surface of the substrate 100; the device also includes a second epitaxial layer 421 and a second metal silicide layer 520; the second epitaxial layer 421 covers at least one of the surfaces of the first source and drain 310 or the second source and drain 320, and the second epitaxial layer 421 protrudes from the surface of the substrate 100, the upper surface of the second epitaxial layer 421 is a curved surface, and the second epitaxial layer 421 is a Si layer; the second metal silicide layer 520 conformally covers the surface of the second epitaxial layer 421, the upper surface of the second metal silicide layer 520 is a curved surface, and the second metal silicide layer 520 is a CoSi2 layer.

[0170] The structures, materials, shapes and formation methods of the gate structure 200 , the first source and drain 310 and the second source and drain 320 in the semiconductor device are as shown in the above-mentioned embodiment of the manufacturing method and will not be described in detail here.

[0171] In the embodiment provided by the present disclosure, the first epitaxial layer 411 and the second epitaxial layer 421 can be formed simultaneously by epitaxial process, and both can be formed in the same process step, so as to save process steps and simplify the process. Of course, both can also be formed in steps according to process requirements. The process and thickness used to form the second epitaxial layer 421 can be the same or similar to that of the first epitaxial layer 411, and will not be repeated here.

[0172] In some embodiments, the upper surface of the second epitaxial layer 421 is convex or concave relative to the surface of the substrate 100, and such surfaces can achieve the purpose of increasing the line width of the device gate structure 200. Among them, the second metal silicide layer 520 is conformally formed on the second epitaxial layer 421. When the second epitaxial layer 421 is convex, the middle part of the upper surface of the second metal silicide layer 520 protrudes in the direction away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is convex relative to the surface of the substrate 100; when the second epitaxial layer 421 is concave, the middle part of the upper surface of the second metal silicide layer 520 is recessed in the direction away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is concave relative to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the steps of the device preparation process, the second epitaxial layer 421 and the second metal silicide layer 520 can be convex relative to the surface of the substrate 100.

[0173] The thickness of the first epitaxial layer 411 and the second epitaxial layer 421 may be 6nm to 14nm, for example, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm or 14nm. The thickness of the first metal silicide layer 510 and the second metal silicide layer 520 may be 6nm to 14nm, for example, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm or 14nm. Since the first metal silicide layer 510 is formed by doping and diffusing the first epitaxial layer 411, the thickness of the first epitaxial layer 411 and the first metal silicide layer 510 may be coordinated with each other. Similarly, the thickness of the second epitaxial layer 421 and the second metal silicide layer 520 may be coordinated with each other.

[0174] In the embodiments provided in the present disclosure, the semiconductor device may be at least one selected from an NMOS device, a PMOS device, or a CMOS device. The semiconductor device may be a semiconductor composed of a plurality of NMOS devices, a semiconductor composed of a plurality of PMOS devices, a semiconductor composed of a plurality of CMOS devices, or a semiconductor device composed of any two or three of the above three devices. The specific device type may be selected according to actual needs.

[0175] The composition and formation method of other film layers and structures of the semiconductor device provided in this embodiment can be found in the manufacturing method embodiment, and will not be described in detail here.

[0176] The semiconductor device provided by the present invention has a first epitaxial layer 411 formed between the metal silicide layer and the gate layer 220, and the upper surface of the first epitaxial layer 411 is a curved surface, so as to increase the line width of the device. In the process of forming the metal silicide layer, the influence of the line width effect on the quality of the metal silicide film layer formation is overcome, and the generation of agglomeration defects of the metal silicide film layer is avoided. The formed metal silicide film layer has the characteristics of low resistivity, which helps to reduce the contact resistance of the device. In addition, due to the existence of the first epitaxial layer 411, the difference in thermal stability of the device caused by factors such as doping during the process can be balanced, thereby improving the thermal stability of the device and thus improving the overall performance of the device.

[0177] The present disclosure provides a semiconductor device, such as Fig.13 As shown, the device includes: a substrate 100 , a gate structure 200 and a first metal silicide layer 510 .

[0178] Among them, the gate structure 200 is protrudingly arranged on the surface of the substrate 100, and the gate structure 200 includes a gate oxide layer 210, a gate layer 220 and a gate protection layer 230. The gate oxide layer 210 is formed on the surface of the substrate 100, the gate layer 220 is formed on the gate oxide layer 210, and the gate protection layer 230 covers the side wall jointly formed by the gate oxide layer 210 and the gate layer 220, and the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220; the first metal silicide layer 510 covers the top surface of the gate layer 220, and the upper surface of the first metal silicide layer 510 is a curved surface, and the first metal silicide layer 510 is a CoSi2 layer.

[0179] The semiconductor device provided by the present invention forms a metal silicide layer on the surface of the gate layer 220, and the upper surface of the metal silicide layer is curved. Since the metal silicide layer is formed outside the gate structure 200, it is different from directly doping the gate layer 220 to form a metal silicide layer. This device overcomes the line width effect, and the formed metal silicide layer has better formation quality and overcomes the agglomeration defects caused by small line width, thereby improving the overall performance of the device.

[0180] The various parts of the semiconductor device provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings:

[0181] The semiconductor device provided by the present disclosure can be manufactured by the above-mentioned manufacturing method.

[0182] Wherein, the substrate 100 may be a silicon (Si) substrate, SOI (Silicon on Insulator), etc., and its surface may be used to directly generate an epitaxial layer having a single crystal silicon structure. In some embodiments, the substrate 100 may also be other types of substrates, such as a sapphire (Al2O3) substrate, SOS (Silicon-on-Sapphire) or GOI (Germanium on Insulator), or a substrate including other element semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs), etc. It should be noted that when the substrate 100 is other types of substrates, it may be used as a heterogeneous substrate, on which a silicon buffer layer is grown to provide a film layer foundation for the subsequent growth of the epitaxial layer. The embodiments provided in the present disclosure are described by taking the substrate 100 as a silicon (Si) substrate as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the scope of protection of the present disclosure.

[0183] In some embodiments, the top surface of the gate protection layer 230 is not higher than the top surface of the gate layer 220. The top surface of the gate protection layer 230 may be lower than the top surface of the gate layer 220, and the gate protection layer 230 exposes part of the sidewall of the gate layer 220. The first epitaxial layer 411 covers the top surface and the exposed sidewall of the gate layer 220. The exposed sidewall and the top surface may form the process line width of the gate structure 200 together to increase the line width of the gate structure 200 and provide a larger line width for the formation of the metal silicide layer. The top surface of the gate protection layer 230 may be flush with the top surface of the gate layer 220, and the first epitaxial layer 411 covers the top surface of the gate layer 220, and the sidewall of the first epitaxial layer 411 is flush with the sidewall of the gate layer 220.

[0184] Among them, the exposed height of the side wall of the gate layer 220 can be 10% to 30% of the overall height of the gate layer 220, which not only ensures the insulation and isolation function of the gate protection layer 230, but also ensures that the gate structure 200 achieves the purpose of increasing the line width, thereby providing a device foundation for the formation of subsequent film layers.

[0185] In some embodiments, the middle portion of the upper surface of the first metal silicide layer 510 protrudes in a direction away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is convex relative to the surface of the substrate 100; or the middle portion of the upper surface of the first metal silicide layer 510 is recessed in a direction away from the substrate 100, that is, the upper surface of the first metal silicide layer 510 is concave relative to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the steps of the device preparation process, the first metal silicide layer 510 can be convex relative to the surface of the substrate 100.

[0186] In the embodiment provided in the present disclosure, the device also includes a first source and drain 310 and a second source and drain 320, the first source and drain 310 and the second source and drain 320 are respectively located on both sides of the gate structure 200, the surface of the first source and drain 310 is flush with the surface of the substrate 100, and the surface of the second source and drain 320 is flush with the surface of the substrate 100; the device also includes a second metal silicide layer 520; the second metal silicide layer 520 covers at least one of the surfaces of the first source and drain 310 or the second source and drain 320, the upper surface of the second metal silicide layer 520 is a curved surface, and the second metal silicide layer 520 is a CoSi2 layer.

[0187] The structures, materials, shapes and formation methods of the gate structure 200 , the first source and drain 310 and the second source and drain 320 in the semiconductor device are as shown in the above-mentioned embodiment of the manufacturing method and will not be described in detail here.

[0188] In the embodiment provided by the present disclosure, the first metal silicide layer 510 and the second metal silicide layer 520 can be formed in the same process step to save process steps and simplify the process. Of course, the two can also be formed in steps according to process requirements. The process and thickness used to form the second metal silicide layer 520 can be the same or similar to that of the first metal silicide layer 510, and will not be repeated here.

[0189] In some embodiments, the middle portion of the upper surface of the second metal silicide layer 520 protrudes in a direction away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is convex relative to the surface of the substrate 100; the middle portion of the upper surface of the second metal silicide layer 520 is recessed in a direction away from the substrate 100, that is, the upper surface of the second metal silicide layer 520 is concave relative to the surface of the substrate 100. In order to adapt to the shape of the film layer formed in the epitaxial process and simplify the steps of the device preparation process, the second metal silicide layer 520 can be convex relative to the surface of the substrate 100.

[0190] The thickness of the first metal silicide layer 510 and the second metal silicide layer 520 may be 6 nm to 14 nm, for example, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm or 14 nm.

[0191] In the embodiments provided in the present disclosure, the semiconductor device may be at least one selected from an NMOS device, a PMOS device, or a CMOS device. The semiconductor device may be a semiconductor composed of a plurality of NMOS devices, a semiconductor composed of a plurality of PMOS devices, a semiconductor composed of a plurality of CMOS devices, or a semiconductor device composed of any two or three of the above three devices. The specific device type may be selected according to actual needs.

[0192] The composition and formation method of other film layers and structures of the semiconductor device provided in this embodiment can be found in the manufacturing method embodiment, and will not be described in detail here.

[0193] The semiconductor device provided by the present invention forms a metal silicide layer on the surface of the gate layer 220, and the upper surface of the metal silicide layer is curved. Since the metal silicide layer is formed outside the gate structure 200, it is different from directly doping the gate layer 220 to form a metal silicide layer. This device overcomes the line width effect, and the formed metal silicide layer has better formation quality and overcomes the agglomeration defects caused by small line width, thereby improving the overall performance of the device.

[0194] The semiconductor device provided by the present disclosure can be applied to dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (Flash Memory), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), etc. Of course, it can also be applied to other storage devices not listed, which are not listed here.

[0195] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A gate structure, wherein the gate structure is protrudingly disposed on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewall formed by the gate oxide layer and the gate layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer; a first epitaxial layer, wherein the first epitaxial layer covers a top surface of the gate layer, and an upper surface of the first epitaxial layer is a curved surface, and the first epitaxial layer is a Si layer; A first metal silicide layer, wherein the first metal silicide layer conformally covers the first epitaxial layer, and an upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer.

2. The semiconductor device according to claim 1, wherein: The top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes a portion of the side wall of the gate layer, and the first epitaxial layer covers the top surface and the exposed side wall of the gate layer.

3. The semiconductor device according to claim 1, wherein: The top surface of the gate protection layer is flush with the top surface of the gate layer, the first epitaxial layer covers the top surface of the gate layer, and the side wall of the first epitaxial layer is flush with the side wall of the gate layer.

4. The semiconductor device according to claim 1, wherein: A middle portion of an upper surface of the first metal silicide layer protrudes in a direction away from the substrate.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The device further includes a first source and a drain and a second source and a drain, wherein the first source and the drain are respectively located on two sides of the gate structure, and a surface of the first source and the drain is flush with a surface of the substrate, and a surface of the second source and the drain is flush with a surface of the substrate; The device also includes a second epitaxial layer and a second metal silicide layer; The second epitaxial layer covers at least one of the surface of the first source and drain electrode or the surface of the second source and drain electrode, and the second epitaxial layer protrudes from the surface of the substrate, the upper surface of the second epitaxial layer is a curved surface, and the second epitaxial layer is a Si layer; The second metal silicide layer conformally covers the surface of the second epitaxial layer, the upper surface of the second metal silicide layer is a curved surface, and the second metal silicide layer is a CoSi2 layer.

6. The semiconductor device according to claim 5, characterized in that A middle portion of an upper surface of the second metal silicide layer protrudes in a direction away from the substrate.

7. The semiconductor device according to claim 5, characterized in that The thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

8. The semiconductor device according to claim 1, wherein: The semiconductor device is selected from at least one of a PMOS device, an NMOS device or a CMOS device.

9. A semiconductor device, characterized in that: include: substrate; A gate structure, wherein the gate structure is protrudingly disposed on the surface of the substrate, the gate structure comprises a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the gate oxide layer, the gate protection layer covers the sidewall formed by the gate oxide layer and the gate layer, and the top surface of the gate protection layer is not higher than the top surface of the gate layer; A first metal silicide layer, wherein the first metal silicide layer covers the top surface of the gate layer, and the upper surface of the first metal silicide layer is a curved surface, and the first metal silicide layer is a CoSi2 layer.

10. The semiconductor device according to claim 9, characterized in that The top surface of the gate protection layer is lower than the top surface of the gate layer, the gate protection layer exposes a portion of the side wall of the gate layer, and the first metal silicide layer covers the top surface and the exposed side wall of the gate layer.

11. The semiconductor device according to claim 9, characterized in that The top surface of the gate protection layer is flush with the top surface of the gate layer, the first metal silicide layer covers the top surface of the gate layer, and the side wall of the first metal silicide layer is flush with the side wall of the gate layer.

12. The semiconductor device according to claim 9, characterized in that A middle portion of an upper surface of the first metal silicide layer protrudes in a direction away from the substrate.

13. The semiconductor device according to any one of claims 9 to 12, characterized in that: The device further includes a first source and a drain and a second source and a drain, wherein the first source and the drain are respectively located on two sides of the gate structure, and a surface of the first source and the drain is flush with a surface of the substrate, and a surface of the second source and the drain is flush with a surface of the substrate; The device also includes a second metal silicide layer, which covers at least one of the surfaces of the first source and drain or the second source and drain, the upper surface of the second metal silicide layer is a curved surface, and the second metal silicide layer is a CoSi2 layer.

14. The semiconductor device according to claim 13, characterized in that A middle portion of an upper surface of the second metal silicide layer protrudes in a direction away from the substrate.

15. The semiconductor device according to claim 13, wherein: The thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

16. The semiconductor device according to claim 9, characterized in that The semiconductor device is selected from at least one of a PMOS device, an NMOS device or a CMOS device.

17. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; A gate structure protruding from the surface of the substrate is formed on the substrate, the gate structure comprising a gate oxide layer, a gate layer and a gate protection layer, the gate oxide layer is formed on the surface of the substrate, the gate layer is formed on the surface of the gate oxide layer, the gate protection layer is formed on a side wall formed by the gate layer and the gate oxide layer, and a top surface of the gate protection layer is not lower than a top surface of the gate layer; forming a first initial epitaxial layer protruding from the top surface of the gate layer, wherein the upper surface of the first initial epitaxial layer is a curved surface, and the first initial epitaxial layer is a Si layer; forming a Co metal layer, wherein the Co metal layer conformally covers the first initial epitaxial layer; The Co metal layer is heat treated to diffuse the Co in the Co metal layer into the first initial epitaxial layer, so that at least a portion of the first initial epitaxial layer is converted into a first metal silicide layer, the first metal silicide layer is a CoSi2 layer, and the remaining unconverted first initial epitaxial layer is a first epitaxial layer.

18. The manufacturing method according to claim 17, characterized in that: The heat-treating the Co metal layer to diffuse the Co in the Co metal layer into the first initial epitaxial layer includes: diffusing the Co in the Co metal layer from the top surface to the bottom surface of the first initial epitaxial layer until the first initial epitaxial layer is completely transformed into the first metal silicide layer.

19. The manufacturing method according to claim 17, characterized in that: Before forming the first initial epitaxial layer protruding from the top surface of the gate layer, the method further includes: The gate layer is subjected to laser annealing treatment to transform the gate layer into a single crystal structure.

20. The manufacturing method according to any one of claims 17 to 19, characterized in that: The method further comprises: forming a first source-drain electrode and a second source-drain electrode in the substrate, wherein the first source-drain electrode and the second source-drain electrode are respectively located at two sides of the gate structure, and a surface of the first source-drain electrode is flush with a surface of the substrate, and a surface of the second source-drain electrode is flush with a surface of the substrate; A second initial epitaxial layer is formed, wherein the second initial epitaxial layer covers at least one of the surfaces of the first source and drain or the second source and drain, and the second initial epitaxial layer protrudes from the surface of the substrate, the upper surface of the second initial epitaxial layer is a curved surface, and the second initial epitaxial layer is a Si layer.

21. The manufacturing method according to claim 20, characterized in that: The forming of the Co metal layer further includes: the Co metal layer conformally covers the second initial epitaxial layer.

22. The manufacturing method according to claim 21, characterized in that: The heat treatment of the Co metal layer further comprises: The Co metal layer is heat-treated to diffuse the Co in the Co metal layer into the second initial epitaxial layer, so that at least a portion of the second initial epitaxial layer is converted into a second metal silicide layer, the second metal silicide layer is a CoSi2 layer, and the remaining unconverted second initial epitaxial layer is a second epitaxial layer.

23. The manufacturing method according to claim 22, characterized in that: The Co metal layer is heat treated to diffuse the Co in the Co metal layer into the second initial epitaxial layer, including: diffusing the Co in the Co metal layer from the top surface to the bottom surface of the second initial epitaxial layer until the second initial epitaxial layer is completely converted into the second metal silicide layer.

24. The manufacturing method according to claim 22, characterized in that: The thickness of the first metal silicide layer and the second metal silicide layer is 6 nm to 14 nm.

25. The manufacturing method according to claim 22, characterized in that: A middle portion of an upper surface of the first metal silicide layer or the second metal silicide layer protrudes in a direction away from the substrate.

26. The manufacturing method according to claim 17, characterized in that: The gate structure protruding from the surface of the substrate is formed on the substrate, comprising: forming a stacked structure on the surface of the substrate, the stacked structure sequentially comprising an oxide material layer, a gate material layer and an etch stop layer; Performing patterning on the stacked structure to form an initial gate structure; forming a gate protection layer, wherein the gate protection layer conformally covers the surface of the initial gate structure and extends onto the surface of the substrate; The gate protection layer and the etching stop layer on the top surface of the initial gate structure are removed simultaneously to expose the surface of the gate layer.

27. The manufacturing method according to claim 26, characterized in that: The method further comprises: Continue to remove the gate protection layer in a direction perpendicular to the substrate to expose a portion of the sidewall of the gate layer; The first initial epitaxial layer covers the top surface and exposed sidewalls of the gate protection layer at the same time.

28. The manufacturing method according to claim 17, characterized in that: The heat treatment includes a first sub-heat treatment and a second sub-heat treatment, and the Co metal layer is heat treated, including: A first sub-heat treatment is performed on the Co metal layer to diffuse Co in the Co metal layer into the first initial epitaxial layer, so as to form a first sub-metal silicide layer in the first initial epitaxial layer.

29. The manufacturing method according to claim 28, characterized in that: After forming the first sub-metal silicide layer, the method further comprises: The first sub-metal silicide layer is subjected to a second sub-heat treatment to at least partially transform the first sub-metal silicide layer into the first metal silicide layer, wherein the resistivity of the first metal silicide layer is less than the resistivity of the first sub-metal silicide layer.

30. The manufacturing method according to claim 29, characterized in that: After forming the first sub-metal silicide layer and before converting the first sub-metal silicide layer into the first metal silicide layer, the method further includes: removing the remaining unreacted Co metal layer.

Images