Array substrate, preparation method of array substrate and display panel

Abstract

The embodiment of the invention provides an array substrate, a preparation method of the array substrate and a display panel, and relates to the technical field of display equipment. The array substrate comprises a substrate, an insulating layer, a first metal layer and an isolating layer, the insulating layer is located on one side of the substrate, and the material of the insulating layer comprises azide groups; the first metal layer is located on one side of the insulating layer away from the substrate; at least part of the isolation layer is located between the insulating layer and the first metal layer. According to the array substrate, the isolation layer is additionally arranged between the insulation layer and the first metal layer, and compounds which are generated by the first metal layer and the azide group and are difficult to etch are reduced through the isolation layer, so that after etching is completed, etching residual materials of the first metal layer are reduced, the risk of metal wiring short circuit is reduced, and the use performance of the array substrate is improved.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to an array substrate, a method for preparing the array substrate, and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides an array substrate, a method for fabricating the array substrate, and a display panel, aiming to improve the performance of the array substrate and reduce the risk of short circuits in the metal traces.

[0005] An embodiment of the first aspect of this application provides an array substrate, the array substrate including a substrate, an insulating layer, a first metal layer and an isolation layer; the insulating layer is located on one side of the substrate, and the material of the insulating layer includes azide groups; the first metal layer is located on the side of the insulating layer opposite to the substrate; at least a portion of the isolation layer is located between the insulating layer and the first metal layer.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the insulating layer includes a conductive via, the orthographic projection of the conductive via on the substrate being located within the orthographic projection range of the first metal layer on the substrate, and the array substrate further includes a connection portion located at the conductive via; the isolation layer includes a first portion and a second portion, the first portion being located on the side of the insulating layer away from the substrate, and the second portion being located at the conductive via and surrounding at least a portion of the connection portion.

[0007] Preferably, the first metal layer at least partially fills the conductive via.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the array substrate further includes a second metal layer located between the substrate and the insulating layer, the material of the insulating layer includes a conductive material, and the second metal layer is connected to the first metal layer through a second portion.

[0009] Preferably, the second metal layer includes the source and / or drain of the transistor;

[0010] Preferably, the transistor includes a thin-film transistor;

[0011] Preferably, the transistor comprises an oxide thin-film transistor.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the material of the isolation layer includes a metal or a metal oxide;

[0013] Preferably, the material of the insulating layer includes indium tin oxide or molybdenum.

[0014] Preferably, the thickness of the isolation layer is 30 to 80 angstroms.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the first metal layer includes a titanium layer, and the titanium layer and the insulating layer are in contact.

[0016] Preferably, the insulating layer is made of photosensitive polyimide photoresist.

[0017] Preferably, the first metal layer is used to connect the first electrode of the light-emitting device.

[0018] An embodiment of the second aspect of this application provides a method for fabricating an array substrate, the method comprising:

[0019] An insulating layer is prepared on one side of the substrate, and the material of the insulating layer includes azide groups;

[0020] An isolation material layer is prepared on the side of the insulating layer away from the substrate;

[0021] A first metal material layer is prepared on the side of the isolation material layer away from the substrate;

[0022] The first metal material layer and the isolation material layer are patterned to form the first metal layer and the isolation layer, thus obtaining the array substrate.

[0023] In conjunction with the second aspect, in some implementations of the second aspect, the first metal material layer and the isolation material layer are patterned to form the first metal layer and the isolation layer, resulting in an array substrate comprising:

[0024] The first metal material layer is patterned using a photomask to form the first metal layer;

[0025] The isolation material layer is patterned to form an isolation layer, thus obtaining an array substrate.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, the step of patterning the isolation material layer to form the isolation layer includes:

[0027] The isolation material layer is etched using a dry etching process, wherein the etching gas used in the dry etching process includes at least one of argon, methane, and boron trichloride.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the step of preparing the first metal material layer on the side of the insulating material layer facing away from the substrate further includes:

[0029] Conductorizing treatment is applied to the insulating material layer.

[0030] Preferably, the conductive treatment of the insulating material layer includes: plasma conductive treatment of the insulating material layer.

[0031] An embodiment of the third aspect of this application provides a display panel, which includes the array substrate provided in any of the above embodiments.

[0032] In the array substrate provided in this application embodiment, the array substrate includes a substrate, an insulating layer, a first metal layer, and an isolation layer; the insulating layer is located on one side of the substrate, and the material of the insulating layer includes azide groups; the first metal layer is located on the side of the insulating layer facing away from the substrate; at least a portion of the isolation layer is located between the insulating layer and the first metal layer. This application adds an isolation layer between the insulating layer and the first metal layer. The isolation layer reduces the formation of difficult-to-etch compounds between the first metal layer and the azide groups, thereby reducing the amount of etching residue on the first metal layer after etching, thus reducing the risk of short circuits in the metal traces and improving the performance of the array substrate. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 The diagram shown is a cross-sectional structural schematic of an array substrate provided in an embodiment of this application.

[0035] Figure 2 The diagram shown is a cross-sectional structural schematic of an array substrate provided in another embodiment of this application.

[0036] Figure 3 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application.

[0037] Figure 4 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application.

[0038] Figure 5 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application.

[0039] Figure 6The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0040] Explanation of reference numerals in the drawings: Array substrate 100; Substrate 110; Insulating layer 120; First metal layer 130; Isolation layer 140; Conductive via 121; Connecting portion 150; First portion 141; Second portion 142; Second metal layer 160; Display panel 10. Detailed Implementation

[0041] In the array substrate provided by the related technology, the array substrate includes a substrate, an insulating layer, and a first metal layer; the insulating layer is located on one side of the substrate, and the material of the insulating layer includes azide groups; the first metal layer is located on the side of the insulating layer opposite to the substrate. The first metal layer can be a combination layer of titanium layer-aluminum layer-titanium layer, with the titanium layer in contact with the insulating layer. During etching of the first metal layer, the azide groups in the titanium layer and the insulating layer generate compounds that are difficult to etch, resulting in titanium layer residue, which further leads to short circuits in the metal traces and abnormalities.

[0042] To address the aforementioned technical problems, this application provides an array substrate comprising a substrate, an insulating layer, a first metal layer, and an isolation layer. The insulating layer is located on one side of the substrate and its material includes azide groups. The first metal layer is located on the side of the insulating layer facing away from the substrate. At least a portion of the isolation layer is located between the insulating layer and the first metal layer. This application adds an isolation layer between the insulating layer and the first metal layer. This isolation layer reduces the formation of difficult-to-etch compounds between the first metal layer and the azide groups, thereby reducing the amount of etching residue on the first metal layer after etching. This reduces the risk of short circuits in the metal traces and improves the performance of the array substrate.

[0043] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0044] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0045] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0046] Figure 1 The diagram shown is a cross-sectional structural schematic of an array substrate provided in an embodiment of this application. Figure 1 As shown, an embodiment of the first aspect of this application provides an array substrate 100, which includes a substrate 110, an insulating layer 120, a first metal layer 130, and an isolation layer 140; the insulating layer 120 is located on one side of the substrate 110, and the material of the insulating layer 120 includes azide groups; the first metal layer 130 is located on the side of the insulating layer 120 away from the substrate 110; at least a portion of the isolation layer 140 is located between the insulating layer 120 and the first metal layer 130.

[0047] The array substrate 100 is a multilayer structure formed on a flat substrate 110 through a series of micro-processing techniques such as deposition, photolithography, and etching. With the development of flexible display technology, the array substrate 100 can be a flexible array substrate 100, which can be bent and folded, bringing more form factors to display devices.

[0048] The azide group is a chemical functional group consisting of one nitrogen atom and two additional nitrogen atoms linked together by single bonds, forming a linear structure. When the azide group comes into contact with the first metal layer 130, it forms a compound that is difficult to etch.

[0049] For example, the isolation layer 140 is used to isolate the azide groups in the first metal layer 130 and the insulating layer 120, thereby reducing the chemical reaction between the two and reducing the formation of difficult-to-etch compounds.

[0050] This application adds an isolation layer 140 between the insulating layer 120 and the first metal layer 130. The isolation layer 140 reduces the difficult-to-etch compounds generated by the first metal layer 130 and the azide groups. As a result, after etching, the etching residue of the first metal layer 130 is reduced, thereby reducing the risk of short circuits in the metal traces and improving the performance of the array substrate 100.

[0051] Figure 2 The diagram shown is a cross-sectional structural schematic of an array substrate provided in another embodiment of this application. Figure 2 As shown, in conjunction with the first aspect, in some implementations of the first aspect, the insulating layer 120 includes a conductive via 121, the orthographic projection of the conductive via 121 on the substrate 110 being located within the orthographic projection range of the first metal layer 130 on the substrate 110, and the array substrate 100 also includes a connection portion 150 located at the conductive via 121; the isolation layer 140 includes a first portion 141 and a second portion 142, the first portion 141 being located on the side of the insulating layer 120 away from the substrate 110, and the second portion 142 being located at the conductive via 121 and surrounding at least a portion of the connection portion 150.

[0052] The conductive via 121 is used to establish an electrical connection between different film layers, allowing current to flow between the different film layers, thereby realizing the function of the circuit. "The orthogonal projection of the conductive via 121 on the substrate 110 is within the orthogonal projection range of the first metal layer 130 on the substrate 110" means that the position of the conductive via 121 is designed to be covered by the first metal layer 130, thus ensuring a reliable electrical connection from the lower layer to the upper layer.

[0053] The connection portion 150 is used to establish physical contact with the first metal layer 130 or other conductive layers. This contact point is crucial for ensuring a good electrical connection.

[0054] For example, the first metal layer 130 at least partially fills the conductive via 121 to facilitate electrical connection between the first metal layer 130 and other conductive layers.

[0055] The first portion 141 is located on the side of the insulating layer 120 facing away from the substrate 110. This helps to reduce direct contact between the first metal layer 130 and the azide groups in the insulating layer 120, thereby reducing the formation of compounds that are difficult to etch. The second portion 142 is located in the conductive via 121 and is disposed around at least a portion of the connection portion 150. This means that the second portion 142 surrounds at least a portion of the conductive via 121 to protect the connection portion 150 from the influence of the external environment and to reduce direct contact between the connection portion 150 and the azide groups.

[0056] This embodiment of the application further reduces the formation of difficult-to-etch compounds by providing a second portion 142, thereby reducing the residual material of the first metal layer 130 after etching. Furthermore, the first portion 141 and the second portion 142 can be formed in a single step using a physical vapor deposition process, resulting in a simpler and less complex process.

[0057] refer to Figure 1 and Figure 2 In conjunction with the first aspect, in some implementations of the first aspect, the array substrate 100 further includes a second metal layer 160 located between the substrate 110 and the insulating layer 120, the material of the isolation layer 140 includes a conductive material, and the second metal layer 160 is connected to the first metal layer 130 through a second portion 142.

[0058] The isolation layer 140 contains a conductive material, which enables the second metal layer 160 to form an electrical connection with the first metal layer 130 through the second portion 142. This means that the second metal layer 160 can be connected to the first metal layer 130 through the conductive via 121 to form a continuous conductive path. Furthermore, the isolation layer 140 has a low resistance, which reduces the power consumption of the array substrate 100.

[0059] Optionally, the second metal layer 160 includes the source and / or drain of the transistor.

[0060] Optionally, the transistor includes a thin-film transistor.

[0061] Optionally, the transistor includes an oxide thin-film transistor.

[0062] Transistors are used to control the state of sub-pixels; for example, they control whether a sub-pixel is lit and to what extent. When a transistor is turned on, current can flow through, causing the sub-pixel to emit light or change its optical properties. Transistors can also be used to transmit data voltage from data lines to sub-pixels, thereby controlling the brightness or color of the sub-pixels.

[0063] The main difference between oxide thin-film transistors and amorphous silicon thin-film transistors is that the electron channel material is oxide rather than amorphous silicon, which has many advantages such as higher mobility, better large-area uniformity, and lower fabrication temperature.

[0064] The composition and fabrication of thin-film transistors are further described in patents 202311631979.8, 202311219272.6, 202310798733.3, 202310790822.3, and 202410212096.1, the contents of which are incorporated herein by reference.

[0065] The second metal layer 160 can form the source and / or drain of a transistor. The source is one port of the transistor, typically used to introduce charge carriers (electrons or holes) into the transistor, while the drain is the other port through which charge carriers leave the transistor. The second metal layer 160 is connected to the first metal layer 130 via a second portion 142 of the isolation layer 140, which allows the second metal layer 160 (source and drain) to establish electrical connections with other components in the first metal layer 130.

[0066] In conjunction with the first aspect, in some implementations of the first aspect, the material of the isolation layer 140 includes a metal or a metal oxide to achieve electrical connection between the first metal layer 130 and the second metal layer 160. Exemplarily, the material of the isolation layer 140 includes indium tin oxide or molybdenum.

[0067] Indium tin oxide (ITO) is a transparent conductive oxide with good conductivity and high transparency. In display technology, ITO is often used as a transparent electrode material because it allows light to pass through while maintaining good conductivity. As the material of the insulating layer 140, ITO provides a conductive path to achieve the electrical connection between the second metal layer 160 and the first metal layer 130.

[0068] Molybdenum is a metal with excellent electrical conductivity, which can effectively transfer current from one film layer to another. Molybdenum also has high mechanical strength, which improves the durability of the insulating layer 140 and reduces damage caused by external forces. Molybdenum has good corrosion resistance to a variety of chemicals, helping to protect the underlying film layers from corrosion and extending the service life of the array substrate 100.

[0069] Optionally, the thickness of the isolation layer 140 is 30 to 80 angstroms.

[0070] refer to Figure 1 and Figure 2 In conjunction with the first aspect, in some implementations of the first aspect, the first metal layer 130 includes a titanium layer, and the titanium layer and the insulating layer 140 are in contact.

[0071] This embodiment of the application, by setting an isolation layer 140, reduces the formation of difficult-to-etch compounds from the titanium layer and azide groups, thereby improving the precision of subsequent etching processes. Reduced etching residue means clearer edges on metal traces, which helps improve circuit reliability and reduce the risk of short circuits between metal traces. This is crucial for improving product yield and reliability, especially in high-density integrated display panels. Reducing etching residue also helps improve overall circuit performance, including reducing signal loss and increasing response speed.

[0072] Optionally, the material of the insulating layer 120 may include photosensitive polyimide photoresist.

[0073] Optionally, the first metal layer 130 is used to connect the first electrode of the light-emitting device.

[0074] In some embodiments, the first electrode may be an anode.

[0075] A light-emitting device typically includes a first electrode, a light-emitting layer, and a second electrode (which may be a cathode) stacked sequentially along a direction away from the substrate 110. Light-emitting devices are used to generate light and are fundamental to image display. By controlling the current or voltage, the brightness and color of the light-emitting device can be adjusted to achieve different grayscale levels and color representations.

[0076] In an organic light-emitting diode (OLED), the anode is used to generate positive charges (holes), and the cathode is used to generate negative charges (electrons). When current passes through, electrons and holes meet and recombine in the light-emitting layer, releasing energy and emitting light.

[0077] The first metal layer 130 can be used for electrical connection, responsible for transmitting the signal generated by the driving circuit to the first electrode of the light-emitting device, ensuring that the current can flow accurately from the driving circuit to the light-emitting device, so that the light-emitting device can work normally.

[0078] The structure of the array substrate 100 provided in this application has been described in detail above. The fabrication method of the array substrate 100 is described below. It is understood that the fabrication method corresponds to the structure of the array substrate 100. Therefore, the structure mentioned in the fabrication method can be referred to the above description of the array substrate 100, and will not be repeated here.

[0079] Figure 3 The diagram shown is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of this application. Figure 3 As shown, an embodiment of the second aspect of this application provides a method for fabricating an array substrate, which can be referred to in conjunction with the above. Figures 1 to 3 The preparation method includes the following steps:

[0080] Step S310: An insulating layer 120 is prepared on one side of the substrate 110.

[0081] The insulating layer 120 is made of azide groups.

[0082] Step S320: An isolation material layer is prepared on the side of the insulating layer 120 facing away from the substrate 110.

[0083] Step S330: Prepare a first metal material layer on the side of the isolation material layer away from the substrate 110.

[0084] In step S340, the first metal material layer and the isolation material layer are patterned to form the first metal layer 130 and the isolation layer 140, thereby obtaining the array substrate 100.

[0085] The preparation method provided in this application embodiment adds an isolation layer 140 between the insulating layer 120 and the first metal layer 130. The isolation layer 140 reduces the difficult-to-etch compounds generated by the first metal layer 130 and azide groups. As a result, after etching, the etching residue of the first metal layer 130 is reduced, thereby reducing the risk of short circuits in the metal traces and improving the performance of the array substrate 100.

[0086] Figure 4 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application. Figure 4 As shown, in conjunction with the second aspect, in some implementations of the second aspect, patterning the first metal material layer and the isolation material layer to form the first metal layer 130 and the isolation layer 140 to obtain the array substrate includes the following steps:

[0087] In step S410, the first metal material layer is patterned using a photomask to form the first metal layer 130.

[0088] In step S420, the isolation material layer is patterned to form an isolation layer 140, thereby obtaining an array substrate 100.

[0089] Patterning the first metal layer 130 and the isolation layer 140 using a single masking process simplifies the production process, reduces the number of masks required, and saves costs. Furthermore, it reduces alignment errors and improves process accuracy. The mask defines the areas where material is removed or retained. Using the same masking process for both the first metal layer 130 and the isolation layer 140 facilitates their alignment and improves the accuracy of their positions. Using the same mask for patterning reduces potential deviations or defects caused by multi-step alignment.

[0090] In conjunction with the second aspect, in some implementations of the second aspect, the step of patterning the isolation material layer to form the isolation layer 140 includes:

[0091] The isolation material layer is etched using a dry etching process, wherein the etching gas used in the dry etching process includes at least one of argon, methane, and boron trichloride.

[0092] Dry etching allows for highly precise patterning. By controlling the type and concentration of etching gases, desired patterns can be formed on a barrier material layer. Dry etching exhibits strong anisotropy, meaning the etching direction is primarily perpendicular to the material surface, reducing lateral diffusion and contributing to sharper edges and finer feature dimensions.

[0093] Figure 5 The diagram shown is a flowchart illustrating a method for fabricating an array substrate according to another embodiment of this application. Figure 5As shown, in conjunction with the second aspect, in some implementations of the second aspect, before the first metal material layer is prepared on the side of the isolation material layer away from the substrate, the method further includes: step S510, which involves conductive treatment of the isolation material layer.

[0094] Conductive treatment can transform a non-conductive or poorly conductive isolation material layer into a highly conductive material, which facilitates the establishment of a good electrical connection between the first metal layer 130 and the second metal layer 160. Conductive treatment reduces the resistance of the isolation layer 140, thereby reducing energy loss during signal transmission and improving the overall circuit efficiency. Furthermore, conductive treatment can reduce malfunctions caused by poor contact or excessive resistance, improving the long-term stability and reliability of the array substrate 100.

[0095] Optionally, the conductive treatment of the insulating material layer includes: plasma conductive treatment of the insulating material layer.

[0096] Plasma conductor treatment can generate materials with good electrical conductivity by reacting active substances in plasma with the insulating material layer.

[0097] Plasma conductor treatment can transform the original insulating or semi-insulating isolation material layer into an isolation material layer with a certain degree of conductivity, thereby improving the conductivity of the isolation layer 140 and establishing a stable electrical connection between the first metal layer 130 and the second metal layer 160.

[0098] Figure 6 The diagram shown is a structural schematic of a display panel provided in one embodiment of this application. Figure 6 As shown, an embodiment of the third aspect of this application provides a display panel 10, which includes the array substrate 100 provided in any of the above embodiments. The technical principles and effects are similar, and will not be described again here.

[0099] It is understood that the display panel 10 can be applied to display devices, including but not limited to mobile phones, personal digital assistants (PDAs), tablets, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0100] The embodiments described above are not exhaustive and do not limit the invention to specific examples. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that: include: substrate; An insulating layer, located on one side of the substrate, wherein the material of the insulating layer includes an azide group; A first metal layer, located on a side of the insulating layer facing away from the substrate; An isolation layer, at least a portion of which is located between the insulating layer and the first metal layer.

2. The array substrate according to claim 1, characterized in that: The insulating layer includes a conductive via, the orthographic projection of the conductive via on the substrate is located within the orthographic projection range of the first metal layer on the substrate, and the array substrate also includes a connecting portion located at the conductive via; the isolation layer includes a first sub-portion and a second sub-portion, the first sub-portion is located at a side of the insulating layer away from the substrate, and the second sub-portion is located at the conductive via and is arranged around at least a portion of the connecting portion; Preferably, the first metal layer at least partially fills the conductive via.

3. The array substrate according to claim 2, characterized in that: The array substrate further includes a second metal layer, the second metal layer is located between the substrate and the insulating layer, the material of the isolation layer includes a conductive material, and the second metal layer is connected to the first metal layer through the second section; Preferably, the second metal layer includes a source and / or a drain of a transistor; Preferably, the transistor comprises a thin film transistor; Preferably, the transistor comprises an oxide thin film transistor.

4. The array substrate according to claim 1, characterized in that: The material of the isolation layer includes metal or metal oxide; Preferably, the material of the isolation layer includes indium tin oxide or molybdenum; Preferably, the isolation layer has a thickness of 30 angstroms to 80 angstroms.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The first metal layer includes a titanium layer, and the titanium layer is in contact with the isolation layer; Preferably, the material of the insulating layer includes photosensitive polyimide photoresist; Preferably, the first metal layer is used to connect a first electrode of the light-emitting device.

6. A method for preparing an array substrate, characterized in that: include: Prepare an insulating layer on one side of the substrate, wherein the material of the insulating layer includes an azide group; preparing an isolation material layer on a side of the insulating layer facing away from the substrate; Prepare a first metal material layer on the side of the isolation material layer facing away from the substrate; The first metal material layer and the isolation material layer are patterned to form a first metal layer and an isolation layer, thereby obtaining the array substrate.

7. The preparation method according to claim 6, characterized in that: The step of patterning the first metal material layer and the isolation material layer to form a first metal layer and an isolation layer to obtain the array substrate includes: Using a mask to pattern the first metal material layer to form the first metal layer; The isolation material layer is patterned to form the isolation layer, thereby obtaining the array substrate.

8. The preparation method according to claim 7, characterized in that: The step of patterning the isolation material layer to form the isolation layer comprises: The isolation material layer is etched using a dry etching process, wherein the etching gas of the dry etching process includes at least one of argon, methane and boron trichloride.

9. The preparation method according to any one of claims 6 to 8, characterized in that: Before preparing the first metal material layer on the side of the isolation material layer facing away from the substrate, the method further includes: Conducting the isolation material layer; Preferably, the conducting treatment of the isolation material layer includes: The isolation material layer is subjected to plasma conductive treatment.

10. A display panel, characterized in that: An array substrate comprising any one of claims 1 to 5 or an array substrate prepared by the preparation method of any one of claims 6 to 9.

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