Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. According to one embodiment, a display device is provided with: a flexible resin substrate; a circuit layer including a plurality of insulating layers disposed over the resin substrate over a display region in which an image is displayed and a peripheral region outside the display region; a first organic insulating layer disposed over the circuit layer over the display region and the peripheral region; a first inorganic insulating layer disposed over the first organic insulating layer so as to extend over the display region and the peripheral region; and a first partition wall having, in the peripheral region, a first lower portion disposed on the first inorganic insulating layer, and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion, the circuit layer having a band-shaped region in which at least one of the plurality of insulating layers is missing in a band-shaped manner, and the first partition wall having, in the peripheral region, a first lower portion disposed on the first inorganic insulating layer, and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion. The first partition wall is disposed in the band-shaped region.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority based on Japanese Patent Application No. 2023-123285 filed on July 28, 2023, and cites all the contents described in the Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. The display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the invention

[0006] An object of the embodiment is to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0007] According to one embodiment, a display device includes:

[0008] A resin substrate having flexibility; a circuit layer including a plurality of insulating layers arranged on the resin substrate and covering a display area for displaying an image and a peripheral area outside the display area; a first organic insulating layer arranged on the circuit layer and covering the display area and the peripheral area; a first inorganic insulating layer arranged on the first organic insulating layer and covering the display area and the peripheral area; and a first partition wall having a first lower portion arranged on the first inorganic insulating layer in the peripheral area, and a first upper portion arranged on the first lower portion and protruding from a side surface of the first lower portion, wherein the circuit layer has a strip-shaped area in which at least one of the plurality of insulating layers is missing in a strip shape, and the first partition wall is arranged in the strip-shaped area.

[0009] According to one embodiment, a display device includes:

[0010] A display panel having a display area for displaying an image and a peripheral area on the outside of the display area, and being bent in a strip-shaped area, wherein the display panel comprises: a resin substrate having flexibility; a first organic insulating layer arranged above the resin substrate to extend over the display area and the peripheral area; a first inorganic insulating layer arranged above the first organic insulating layer to extend over the display area and the peripheral area; and a first partition wall having a first lower portion arranged above the first inorganic insulating layer in the strip-shaped area, and a first upper portion arranged above the first lower portion and protruding from a side surface of the first lower portion.

[0011] According to one embodiment, in a method for manufacturing a display device,

[0012] A circuit layer including a plurality of insulating layers is formed on a flexible resin substrate, covering a display area for displaying an image and a peripheral area outside the display area; a first organic insulating layer is formed on the circuit layer, covering the display area and the peripheral area; a first inorganic insulating layer is formed on the first organic insulating layer, covering the display area and the peripheral area; in the peripheral area, a first partition wall is formed, which includes a first lower portion located above the first inorganic insulating layer and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion; wherein the circuit layer has a strip-shaped area in which at least one of the plurality of insulating layers is missing in a strip shape, and the first partition wall is located in the strip-shaped area.

[0013] According to the embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a top view showing a configuration example of the display device DSP.

[0015] Figure 2 It means that Figure 1 The display panel PNL is shown in a perspective view in a bent state.

[0016] Figure 3 It is a plan view showing another configuration example of the display device DSP.

[0017] Figure 4 It means that Figure 3 The display panel PNL is shown in a perspective view in a bent state.

[0018] Figure 5 It is a plan view showing another configuration example of the display device DSP.

[0019] Figure 6 It means that Figure 5The display panel PNL is shown in a perspective view in a bent state.

[0020] Figure 7 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0021] Figure 8 It is along Figure 7 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0022] Fig. 9A It is a plan view showing an example of the shape of the partition wall 7 .

[0023] Fig. 9B It is a plan view showing another example of the shape of the partition wall 7 .

[0024] Fig. 9C It is a plan view showing another example of the shape of the partition wall 7 .

[0025] Fig.10 It is a cross-sectional view of the display device DSP along the partition wall 7 intersecting the strip-shaped area BA.

[0026] Fig.11 It is a cross-sectional view of the display device DSP taken along line CD in FIG. 9 .

[0027] Fig.12 2 is a cross-sectional view of the display device DSP including the metal wiring ML intersecting the strip-shaped area BA.

[0028] Fig.13 It is a diagram for explaining a method of manufacturing the display device DSP.

[0029] Fig.14A It is a diagram for explaining a method of manufacturing the display device DSP.

[0030] Fig. 14B It is a diagram for explaining a method of manufacturing the display device DSP.

[0031] Fig.15A It is a diagram for explaining a method of manufacturing the display device DSP.

[0032] Fig. 15B It is a diagram for explaining a method of manufacturing the display device DSP.

[0033] Fig.16A It is a diagram for explaining a method of manufacturing the display device DSP.

[0034] Fig. 16B It is a diagram for explaining a method of manufacturing the display device DSP.

[0035] Fig.17It is a diagram for explaining a method of manufacturing the display device DSP.

[0036] Fig.18 It is a diagram for explaining a method of manufacturing the display device DSP.

[0037] Fig.19 It is a diagram for explaining a method of manufacturing the display device DSP.

[0038] Fig. 20 It is a cross-sectional view for explaining a state where the laminated film FL1 is formed in the band-shaped area BA. DETAILED DESCRIPTION

[0039] The embodiments are described with reference to the drawings.

[0040] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, with respect to the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the constituent elements that have the same or similar functions as the constituent elements described in the drawings that have appeared, the same reference numerals are marked, and sometimes repeated detailed descriptions are appropriately omitted.

[0041] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis and Z-axis are recorded as needed for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. The method of observing various elements parallel to the third direction Z is called top view.

[0042] The display device according to this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and the like.

[0043] Figure 1 It is a top view showing a configuration example of the display device DSP.

[0044] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 is a flexible resin substrate.

[0045] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, but the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0046] The display area DA includes a plurality of pixels PX arranged in a matrix along a first direction X and a second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors from each other. It should be noted that the pixel PX may also include a sub-pixel SP of other colors such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0047] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0048] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0049] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0050] The display element DE is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0051] The peripheral area SA includes a terminal portion TP, a convex portion PR, and a partition wall 7 .

[0052] The terminal portion TP includes a plurality of terminals TE arranged along a direction. In the example shown in the figure, the plurality of terminals TE are arranged along a first direction X. Each terminal TE extends in a second direction Y, but is not limited thereto. For example, a portion of the plurality of terminals TE may also extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit substrate or an IC chip.

[0053] The convex portion PR is formed in a frame shape surrounding the display area DA. Such a convex portion PR is formed using an organic insulating layer arranged in the display area DA.

[0054] The partition wall 7 is arranged between the display area DA and the convex portion PR and outside the convex portion PR. Such a partition wall 7 can be formed in various shapes such as a grid shape, a straight line shape, a curve shape, a broken line shape, and an island shape. Such a partition wall 7 is conductive and electrically connected to the terminal TE of the common potential. Therefore, compared with the case where the partition wall 7 with a large area is electrically floating, it is possible to suppress electrostatic damage during the manufacturing process at the position where the partition wall 7 is adjacent to the conductive layer (including other partition walls).

[0055] The specific shape of the partition wall 7 will be described in detail later.

[0056] Such a display panel PNL has a strip area BA. In the example shown in the figure, two strip areas BA are located in the peripheral area SA and both extend in the second direction Y. The display area DA and the terminal portion TP are located between the two strip areas BA. Such a strip area BA is an area that can be bent with the axis AX along the second direction Y as the center. The partition wall 7 is also arranged in the strip area BA.

[0057] Figure 2 It means that Figure 1 The display panel PNL is shown in a perspective view in a bent state.

[0058] The strip-shaped area BA is bent. An area of ​​the display panel PNL that is outside the strip-shaped area BA (or an area on the opposite side of the display area DA across the strip-shaped area BA) is located on the back side of the display area DA. In this way, by bending the display panel PNL at the strip-shaped area BA, the width of the periphery of the display area DA along the first direction X can be reduced in the display device DSP, thereby achieving a narrow frame.

[0059] Figure 3 It is a plan view showing another configuration example of the display device DSP.

[0060] Figure 3 The configuration example shown is Figure 1 Compared with the configuration example shown in the figure, the strip-shaped area BA is different in that it extends in the first direction X. In the example shown in the figure, the strip-shaped area BA is located between the display area DA and the terminal portion TP in the peripheral area SA. Such a strip-shaped area BA is an area that can be bent around the axis AX along the first direction X. The partition wall 7 is arranged in the peripheral area SA including the strip-shaped area BA.

[0061] Figure 4 It means that Figure 3 The display panel PNL is shown in a perspective view in a bent state.

[0062] The strip-shaped area BA is bent. The area of ​​the display panel PNL that is opposite to the display area DA across the strip-shaped area BA is located on the back side of the display area DA. In this way, by bending the display panel PNL at the strip-shaped area BA, the width of the periphery of the display area DA along the second direction Y can be reduced in the display device DSP, thereby achieving a narrow frame.

[0063] Figure 5 It is a plan view showing another configuration example of the display device DSP.

[0064] Figure 5 The configuration example shown is Figure 1 Compared with the configuration example shown in the figure, the strip area BA is located in the peripheral area SA and intersects with the display area DA. In the example shown in the figure, the strip area BA is located between the two terminal portions TP in the peripheral area SA. Such a strip area BA is an area that can be bent around the axis AX along the second direction Y. The partition wall 7 is arranged in the peripheral area SA including the strip area BA.

[0065] Figure 6 It means that Figure 5 The display panel PNL is shown in a perspective view in a bent state.

[0066] The strip-shaped area BA is bent. In this way, the display panel PNL can be bent at the strip-shaped area BA intersecting the display area DA, and a foldable display device DSP can be provided.

[0067] Figure 7 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0068] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged along the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged along the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged along the first direction X.

[0069] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, the display area DA includes columns in which the sub-pixels SP2 and the sub-pixels SP3 are alternately arranged in the second direction Y, and columns in which the sub-pixels SP1 are arranged along the second direction Y. These columns are alternately arranged in the first direction X.

[0070] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may also be arranged in sequence along the first direction X.

[0071] In the display area DA, an insulating layer 5 and partitions 6 are arranged. The insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0072] The partition wall 6 overlaps with the insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 may also have openings in the sub-pixels SP1, SP2, and SP3 similarly to the insulating layer 5. The partition wall 6 is conductive and Figure 1 The partition wall 7 shown is electrically connected to the terminal TE of the common potential.

[0073] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 as display elements DE, respectively.

[0074] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the opening AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition 6 in a plan view. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a plan view.

[0075] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition 6 in a plan view. The peripheral portions of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap the insulating layer 5 in a plan view.

[0076] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping the opening AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition 6 in a plan view. The peripheral portions of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap the insulating layer 5 in a plan view.

[0077] In the example shown in the figure, the outer shapes of the lower electrodes LE1, LE2, LE3 are indicated by dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are indicated by single-dot chain lines. It should be noted that the outer shapes of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect the accurate shapes.

[0078] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element, and are in contact with the partition wall 6 .

[0079] In the example shown in the figure, the area of ​​the opening AP1, the area of ​​the opening AP2, and the area of ​​the opening AP3 are different from each other. The area of ​​the opening AP1 is larger than the area of ​​the opening AP2, and the area of ​​the opening AP2 is larger than the area of ​​the opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0080] Figure 8 It is along Figure 7 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0081] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 includes various circuits such as the pixel circuit 1, scanning lines GL, signal lines SL, power lines PL and other wirings. In addition, the circuit layer 11 includes insulating layers 111, 112, 113, 114, 115, 116, and 117 described later. The circuit layer 11 is covered by the insulating layer 12. The insulating layer 12 is arranged on the insulating layer 116 or the insulating layer 117 in the circuit layer 11, and is an organic insulating layer that flattens the unevenness generated by the circuit layer 11.

[0082] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The insulating layer 5 is an inorganic insulating layer, and is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 8 Omitted in .

[0083] The partition wall 6 includes a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0084] In the example shown in the figure, the lower portion 61 has a base layer 63 disposed on the insulating layer 5 and a shaft layer 64 disposed on the base layer 63. For example, the base layer 63 is formed thinner than the shaft layer 64. In addition, in the example shown in the figure, both ends of the base layer 63 protrude from the side surfaces of the shaft layer 64.

[0085] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1 and covers the lower electrode LE1 exposed from the opening AP1, and the peripheral portion of the organic layer OR1 is located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0086] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2 and covers the lower electrode LE2 exposed from the opening AP2, and the peripheral portion of the organic layer OR2 is located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0087] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 and covers the lower electrode LE3 exposed from the opening AP3, and the peripheral portion of the organic layer OR3 is located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61.

[0088] In the example shown in the figure, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the cap layers CP1, CP2, and CP3 may also be omitted.

[0089] The cap layer CP1 is disposed on the upper electrode UE1.

[0090] The cap layer CP2 is disposed on the upper electrode UE2.

[0091] The cap layer CP3 is disposed on the upper electrode UE3.

[0092] The sealing layer SE1 is disposed on the cap layer CP1 , is in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP1 .

[0093] The sealing layer SE2 is disposed on the cap layer CP2 , is in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP2 .

[0094] The sealing layer SE3 is disposed on the cap layer CP3 , is in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP3 .

[0095] In the example shown in the figure, a portion of each of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from portions of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 located at the opening AP1 (parts constituting the display element DE1).

[0096] Similarly, a portion of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is located on the partition wall 6 around the sub-pixel SP2, and these portions are separated from the portions of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 located in the opening AP2 (the portions constituting the display element DE2).

[0097] Similarly, a portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from the portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 located in the opening AP3 (the portion constituting the display element DE3).

[0098] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0099] The ends of the sealing layers SE1, SE2, and SE3 and the ends of the laminated films FL1, FL2, and FL3 are respectively located on the partition wall 6. In the example shown in the figure, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0100] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 13 . The resin layer 13 is covered with a sealing layer 14 . The sealing layer 14 is covered with a resin layer 15 .

[0101] The insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0102] The lower portion 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper portion 62 of the partition wall 6 is made of a conductive material, for example, but may also be made of an insulating material. The lower portion 61 is made of a material different from that of the upper portion 62.

[0103] The lower electrodes LE1, LE2, and LE3 are multilayer bodies including a transparent electrode formed of an oxide conductive material such as indium tin oxide (ITO) and a metal electrode formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer bodies including a metal electrode between a pair of transparent electrodes.

[0104] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in a blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in a green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in a red wavelength region.

[0105] In addition, the organic layers OR1, OR2, and OR3 include a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer, respectively.

[0106] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0107] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0108] The circuit layer 11 , the insulating layer 12 , the insulating layer 5 , the resin layer 13 , the resin layer 15 , and the sealing layer 14 shown in the figure are arranged over the display area DA and the peripheral area SA.

[0109] Next, an example of the shape of the partition wall 7 intersecting the strip-shaped area BA will be described.

[0110] Fig. 9A It is a plan view showing an example of the shape of the partition wall 7 .

[0111] The partition wall 7 is formed in a lattice shape when viewed from above. Each portion of the partition wall 7 forming a closed loop extends in a manner intersecting the axis AX of the band-shaped area BA. Therefore, when the band-shaped area BA is bent, the partition wall 7 is easily stretched, and the breakage of the partition wall 7 can be suppressed. In addition, since the partition wall 7 is formed in a lattice shape, even if a portion of the partition wall 7 is broken, conduction can be ensured by other portions.

[0112] Fig. 9B It is a plan view showing another example of the shape of the partition wall 7 .

[0113] The partition wall 7 is formed in a folded line shape in a plan view. Each straight line component of the partition wall 7 extends so as to intersect the axis AX of the band-shaped area BA. Therefore, when the band-shaped area BA is bent, the partition wall 7 is easily stretched, and the partition wall 7 can be prevented from breaking.

[0114] Fig. 9C It is a plan view showing another example of the shape of the partition wall 7 .

[0115] The next wall 7 has a plurality of annular portions connected to each other in a direction intersecting the axis AX. The annular portions are respectively formed into an ellipse or an oblong shape extending in a direction intersecting the axis AX. Therefore, when the band-shaped area BA is bent, the next wall 7 is easily stretched, and the breakage of the next wall 7 can be suppressed.

[0116] Fig.10 It is a cross-sectional view of the display device DSP along the partition wall 7 intersecting the strip-shaped area BA.

[0117] The circuit layer 11 on the substrate 10 includes a plurality of insulating layers such as insulating layers 111 , 112 , 113 , 114 , 115 , 116 , and 117 .

[0118] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The insulating layer 112 is an inorganic insulating layer and is disposed on the insulating layer 111. The insulating layer 113 is an inorganic insulating layer and is disposed on the insulating layer 112. The insulating layer 114 is an inorganic insulating layer and is disposed on the insulating layer 113. The insulating layer 115 is an inorganic insulating layer and is disposed on the insulating layer 114.

[0119] The insulating layer 116 is an organic insulating layer, and is disposed on the insulating layer 115. In the example shown in the figure, the insulating layer 116 is in contact with the substrate 10 in the strip-shaped area BA.

[0120] The insulating layer 117 is an inorganic insulating layer, and is disposed on the insulating layer 116 .

[0121] The strip-shaped area BA corresponds to an area where at least one of the insulating layers 111 to 117 described above is missing in a strip shape. Figure 1 In the example shown, at least one of the insulating layers 111 to 117 is missing in a strip shape along the second direction Y, forming a strip area BA. Figure 3 In the example shown, at least one of the insulating layers 111 to 117 is missing in a stripe shape along the first direction X to form a stripe-shaped area BA.

[0122] exist Fig.10 In the example shown, the insulating layers 111 to 115 and 117 as inorganic insulating layers are missing in the strip-shaped area BA. It should be noted that the insulating layer 116 as an organic insulating layer may also be missing in the strip-shaped area BA. From the viewpoint of suppressing cracks in the insulating layer when the strip-shaped area BA is bent, it is desirable that all the inorganic insulating layers included in the circuit layer 11 are missing.

[0123] As described above, the insulating layer 12 is an organic insulating layer, and is disposed on the insulating layer 116 and the insulating layer 117. In the example shown in the figure, the insulating layer 12 is in contact with the insulating layer 116 in the strip-shaped area BA.

[0124] As described above, the insulating layer 5 is an inorganic insulating layer and is disposed on the insulating layer 12. The insulating layer 5 is also disposed in the strip area BA. In the dummy pixel DP located outside the strip area BA (or between the strip area BA and the display area), the insulating layer 5 has no opening and covers the insulating layer 12.

[0125] The partition wall 7 includes a conductive lower portion 71 disposed on the insulating layer 5 and an upper portion 72 disposed on the lower portion 71. The upper portion 72 has a greater width than the lower portion 71. Both ends of the upper portion 72 protrude from the side surfaces of the lower portion 71. The dummy pixel DP is surrounded by the partition wall 7.

[0126] In the example shown in the figure, the lower portion 71 includes a base layer 73 disposed on the insulating layer 5 and a shaft layer 74 disposed on the base layer 73. For example, the base layer 73 is formed thinner than the shaft layer 74. In the example shown in the figure, both ends of the base layer 73 protrude from the side surfaces of the shaft layer 74.

[0127] Such partition walls 7 can be formed in the same manner as the partition walls 6 of the display area DA. That is, the lower portion 61 and the lower portion 71 are formed of the same material, and the upper portion 62 and the upper portion 72 are formed of the same material.

[0128] The organic layer OR1 is arranged on the partition wall 7, and is arranged on the insulating layer 5 in the virtual pixel DP surrounded by the partition wall 7. The upper electrode UE1 is arranged on the organic layer OR1 just above the partition wall 7, and is arranged on the organic layer OR1 in the virtual pixel DP, and is in contact with the lower portion 71. The cover layer CP1 is arranged on the upper electrode UE1 just above the partition wall 7, and is arranged on the upper electrode UE1 in the virtual pixel DP. The sealing layer SE1 continuously covers the cover layer CP1 and the partition wall 7. The sealing layer SE1 is covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15.

[0129] Fig.11 It is a cross-sectional view of the display device DSP taken along line CD in FIG. 9 .

[0130] The partition wall 7 is arranged in the strip-shaped area BA. In the strip-shaped area BA, the organic layer OR1 including the light-emitting layer is arranged on the partition wall 7 and the insulating layer 5. The upper electrode UE1 is arranged on the organic layer OR1 and is in contact with the partition wall 7. The cap layer CP1 is arranged on the upper electrode UE1. The organic layer OR1, the upper electrode UE1 and the cap layer CP1 surrounded by the partition wall 7 are separated from the organic layer OR1, the upper electrode UE1 and the cap layer CP1 arranged on the partition wall 7. The sealing layer SE1 is arranged on the cap layer CP1 and continuously covers the cap layer CP1 and the partition wall 7 around it.

[0131] Fig.12 2 is a cross-sectional view of the display device DSP including the metal wiring ML intersecting the strip-shaped area BA.

[0132] The circuit layer 11 includes metal wiring ML. Such metal wiring ML is, for example, wiring that electrically connects various wirings in the display area DA to the terminal TE. The metal wiring ML is arranged on the insulating layer 117, and is arranged on the insulating layer 116 in the strip-shaped area BA. Such metal wiring ML is covered by the insulating layer 12. That is, in the strip-shaped area BA, the metal wiring ML is arranged between the insulating layer 116 and the insulating layer 12. As described above, the insulating layer 116 and the insulating layer 12 are organic insulating layers that are softer than the inorganic insulating layer. Therefore, even if the strip-shaped area BA is bent, the breakage of the metal wiring ML can be suppressed.

[0133] Next, a method for manufacturing the display device DSP is described. Figures 13 to 19 In the figure, the portion below the insulating layer 12 is omitted.

[0134] First, on the substrate 10, after forming the circuit layer 11 and the insulating layer 12 over the display area DA and the peripheral area SA, as shown in FIG. Fig.13 As shown, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12. The process of forming the lower electrodes LE1, LE2, and LE3 includes, for example, the following processes. That is, an ITO layer is formed on the insulating layer 12, a silver layer is formed on the ITO layer, and an ITO layer is formed on the silver layer. Thereafter, the ITO layer, the silver layer, and the ITO layer are patterned. Thus, the lower electrodes LE1, LE2, and LE3 are formed. It should be noted that in the process of forming the circuit layer 11, a Fig.10 The band area BA as shown in etc.

[0135] Then, if Fig.14A As shown, after the insulating layer 5 is formed over the display area DA and the peripheral area SA, a partition wall 6 having a lower portion 61 located above the insulating layer 5 and an upper portion 62 located above the lower portion 61 is formed. Then, openings AP1, AP2, and AP3 are formed in the insulating layer 5. The opening AP1 overlaps with the lower electrode LE1 of the sub-pixel SP1, the opening AP2 overlaps with the lower electrode LE2 of the sub-pixel SP2, and the opening AP3 overlaps with the lower electrode LE3 of the sub-pixel SP3. It should be noted that the process of forming the openings AP1, AP2, and AP3 can also be performed before the process of forming the partition wall 6.

[0136] At this time, if Fig. 14BAs shown, in the strip-shaped area BA, a partition wall 7 having a lower portion 71 located above the insulating layer 5 and an upper portion 72 located above the lower portion 71 is formed. The lower portion 71 is formed simultaneously with the lower portion 61, and the upper portion 72 is formed simultaneously with the upper portion 62. It should be noted that in the strip-shaped area BA, no opening is formed in the insulating layer 5.

[0137] Next, the display element DE1 is formed in the display area DA.

[0138] First, if Fig.15A As shown, a stacked film FL1 is formed. The stacked film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the opening AP1, an upper electrode UE1 that covers the organic layer OR1 and contacts the lower portion 61 of the partition wall 6, and a cap layer CP1 located on the upper electrode UE1. In addition, the organic layer OR1 includes a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer EM1, a hole blocking layer, an electron transport layer, an electron injection layer, etc. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are respectively formed by vapor deposition using the partition wall 6 as a mask. The stacked film FL1 is divided into a plurality of parts by the cantilevered partition wall 6. The above-mentioned organic layer OR1, the upper electrode UE1, and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0139] Thereafter, a sealing layer SE1 is formed on the laminate film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers each partitioned portion of the laminate film FL1 and the partition wall 6.

[0140] At this time, if Fig. 15B As shown, in the strip-shaped area BA, a laminated film FL1 is also formed. The process of forming the laminated film FL1 includes a process of forming an organic layer OR1 including a light-emitting layer EM1 on the partition wall 7 and the insulating layer 5, a process of forming an upper electrode UE1 covering the organic layer OR1 and contacting the lower portion 71 of the partition wall 7, and a process of forming a cap layer CP1 on the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are respectively formed by vapor deposition using the partition wall 7 as a mask. In the strip-shaped area BA, the laminated film FL1 is also divided into a plurality of parts by the cantilevered partition wall 7.

[0141] Thereafter, a sealing layer SE1 is formed on the laminate film FL1. The sealing layer SE1 is formed by CVD. The sealing layer SE1 continuously covers each partitioned portion of the laminate film FL1 and the partition wall 7.

[0142] Then, if Fig.16A As shown in FIG. 1 , a resist R patterned into a predetermined shape is formed on the sealing layer SE1 . The resist R overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0143] At this time, if Fig. 16B As shown, the sealing layer SE1 is covered with the resist R in the strip-shaped area BA.

[0144] Then, if Fig.17 As shown, etching is performed using the resist R as a mask. Thus, the sealing layer SE1 and the laminated film FL1 exposed from the resist R are removed. In this etching, the sealing layer SE1 exposed from the resist R, the cap layer CP1 exposed from the sealing layer SE1, the upper electrode UE1 exposed from the cap layer CP1, and the organic layer OR1 exposed from the upper electrode UE1 are removed in sequence. Thus, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed.

[0145] Thereafter, the resist R is removed. Thus, the display element DE1 is formed in the sub-pixel SP1.

[0146] Then, if Fig.18 As shown, a display element DE2 is formed. The steps for forming the display element DE2 are the same as the steps for forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2 and a cover layer CP2 are sequentially formed on the lower electrode LE2 to form a laminated film FL2. Thereafter, a sealing layer SE2 is formed on the laminated film FL2. Thereafter, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cover layer CP2, the upper electrode UE2 and the organic layer OR2 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0147] Then, if Fig.19 As shown, a display element DE3 is formed. The steps for forming the display element DE3 are the same as the steps for forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3 and a cover layer CP3 are sequentially formed on the lower electrode LE3 to form a laminated film FL3. Thereafter, a sealing layer SE3 is formed on the laminated film FL3. Thereafter, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cover layer CP3, the upper electrode UE3 and the organic layer OR3 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, a display element DE3 is formed in the sub-pixel SP3.

[0148] Afterwards, the Figure 8 The resin layer 13, the sealing layer 14 and the resin layer 15 are shown in the figure. Thus, the display device DSP is completed.

[0149] It should be noted that, in the above manufacturing process, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed, but the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0150] Fig. 20 It is a cross-sectional view for explaining a state where the laminated film FL1 is formed in the band-shaped area BA.

[0151] The laminate film FL1 includes an organic layer OR1, an upper electrode UE1 and a cap layer CP1 for forming the display element DE1. The laminate film FL1 is formed on the insulating layer 5 and the partition wall 7. The partition wall 7 is arranged on the insulating layer 5 and is covered by the sealing layer SE1 together with the laminate film FL1.

[0152] Therefore, the insulating layer 5 is pressed by the partition wall 7 and the sealing layer SE1 , and the lifting of the insulating layer 5 from the insulating layer 12 is suppressed.

[0153] In addition, the laminate film FL1 is subdivided by the partition wall 7. Therefore, compared with the case where the laminate film FL1 is not subdivided, the area of ​​the continuous laminate film FL1 can be reduced, and the stress that may be generated in the laminate film FL1 can be dispersed. In addition, the laminate film FL1 is pressed by the partition wall 7 and the sealing layer SE1. Therefore, the laminate film FL1 is suppressed from the insulating layer 5.

[0154] Therefore, it is possible to suppress the detachment of the insulating layer 5 from the insulating layer 12 and the detachment of the laminated film FL1 from the insulating layer 5 .

[0155] Here, the following describes the possible adverse conditions that may occur when the insulating layer 5 and the laminated film FL1 are detached. The detached insulating layer 5 and the laminated film FL1 become foreign matter and float in the manufacturing device, which may become a source of contamination. In addition, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0156] In contrast, according to the present embodiment, although a relatively large step difference is formed in the strip-shaped area BA where the insulating layer included in the circuit layer 11 is missing, the above-mentioned configuration can suppress the detachment of the insulating layer 5 and the laminated film FL1. Thus, contamination of the manufacturing device and generation of unwanted foreign matter can be suppressed. In addition, even when the strip-shaped area BA is bent, the detachment of the insulating layer 5 and the laminated film FL1 can be suppressed. Thus, a decrease in reliability can be suppressed.

[0157] In the above-described embodiment, for example, the insulating layer 5 corresponds to the first inorganic insulating layer, the insulating layers 111 to 115 correspond to the second inorganic insulating layer, the insulating layer 12 corresponds to the first organic insulating layer, and the insulating layer 116 corresponds to the second organic insulating layer. In addition, the partition wall 7 corresponds to the first partition wall, the lower portion 71 corresponds to the first lower portion, the upper portion 72 corresponds to the first upper portion, the partition wall 6 corresponds to the second partition wall, the lower portion 61 corresponds to the second lower portion, and the upper portion 62 corresponds to the second upper portion.

[0158] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0159] As long as the gist of the present invention is included, all display devices and methods of manufacturing the same that can be implemented by a person skilled in the art by appropriately changing the design based on the display device and method of manufacturing the same described above as the embodiments of the present invention also fall within the scope of the present invention.

[0160] Within the scope of the present invention, those skilled in the art can think of various variations, which should also be understood to belong to the scope of the present invention. For example, those skilled in the art can add, delete or design changes to the above-mentioned embodiments, or add, omit or change the conditions of the process, as long as they have the gist of the present invention, they are also included in the scope of the present invention.

[0161] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, the effects that can be clearly understood from the description of this specification or the effects that can be appropriately thought of by those skilled in the art should naturally be understood as the effects brought about by the present invention.

Claims

1. A display device comprising: A resin substrate having flexibility; A circuit layer including a plurality of insulating layers arranged on the resin substrate over a display area for displaying an image and a peripheral area outside the display area; A first organic insulating layer is disposed on the circuit layer and covers the display area and the peripheral area; A first inorganic insulating layer is disposed on the first organic insulating layer and covers the display area and the peripheral area; and a first partition wall having a first lower portion disposed on the first inorganic insulating layer in the peripheral region and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion, The circuit layer has a strip-shaped region formed by at least one of the plurality of insulating layers being missing in a strip-shaped manner. The first partition wall is arranged in the strip-shaped region.

2. The display device according to claim 1, wherein: The first partition walls are arranged to intersect the strip-shaped regions.

3. The display device according to claim 1, wherein: The first lower portion is formed of a conductive material and is electrically connected to a terminal of a common potential.

4. The display device according to claim 1, wherein: The circuit layer includes a second organic insulating layer, In the strip-shaped region, the first organic insulating layer and the second organic insulating layer are in contact with each other.

5. The display device according to claim 4, wherein: The plurality of insulating layers include a plurality of second inorganic insulating layers disposed between the resin substrate and the second organic insulating layer. In the strip-shaped region, at least one of the plurality of second inorganic insulating layers is missing in a strip-shaped manner.

6. The display device according to claim 5, wherein: In the strip-shaped region, the resin substrate and the second organic insulating layer are in contact with each other.

7. The display device according to claim 1, wherein: The circuit layer includes metal wiring and a second organic insulating layer, In the strip-shaped region, the metal wiring is arranged between the first organic insulating layer and the second organic insulating layer.

8. The display device according to claim 1, further comprising: an organic layer disposed on the first partition wall and the first inorganic insulating layer in the strip-shaped region and including a light-emitting layer; and an upper electrode, which is arranged on the organic layer, in, The organic layer and the upper electrode are surrounded by the first partition wall in a plan view. The upper electrode is in contact with the first partition wall.

9. The display device according to claim 8, further comprising: a capping layer disposed on the upper electrode; and The sealing layer is formed of an inorganic insulating material and covers the cap layer and the first partition wall.

10. The display device according to claim 1, further comprising: a lower electrode, which is disposed on the first organic insulating layer in the display area and overlaps with the opening of the first inorganic insulating layer; an organic layer disposed on the lower electrode in the opening and comprising a light-emitting layer; and The upper electrode is arranged on the organic layer.

11. The display device according to claim 10, further comprising: a second partition wall having, in the display region, a second lower portion disposed on the first inorganic insulating layer and formed of a conductive material, and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion, in, The lower electrode, the organic layer, and the upper electrode are surrounded by the second partition wall in a plan view. The upper electrode is in contact with the second partition wall.

12. The display device according to claim 11, further comprising: a capping layer disposed on the upper electrode; and The sealing layer is formed of an inorganic insulating material and covers the cap layer and the second partition wall.

13. The display device according to claim 11, wherein: The first lower portion and the second lower portion are formed of the same material, The first upper portion and the second upper portion are formed of the same material.

14. A display device comprising: The display panel has a display area for displaying an image and a peripheral area outside the display area, and is bent in a band-shaped area. in, The display panel comprises: A resin substrate having flexibility; A first organic insulating layer is disposed above the resin substrate and covers the display area and the peripheral area; A first inorganic insulating layer is disposed on the first organic insulating layer and covers the display area and the peripheral area; and The first partition wall includes a first lower portion disposed on the first inorganic insulating layer in the strip-shaped region and a first upper portion disposed on the first lower portion and protruding from a side surface of the first lower portion.

15. The display device according to claim 14, wherein: The band-shaped area is located in the peripheral area.

16. The display device according to claim 14, wherein: The strip area intersects with the display area.

17. A method for manufacturing a display device, comprising: A circuit layer including a plurality of insulating layers is formed on a flexible resin substrate over a display area for displaying an image and a peripheral area outside the display area. A first organic insulating layer is formed on the circuit layer and covers the display area and the peripheral area. A first inorganic insulating layer is formed on the first organic insulating layer and covers the display area and the peripheral area. In the peripheral region, a first partition wall having a first lower portion located on the first inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion is formed, in, The circuit layer has a strip-shaped region formed by at least one of the plurality of insulating layers being missing in a strip-shaped manner. The first partition wall is located in the band-shaped region.

18. The method for manufacturing a display device according to claim 17, wherein: Further, after forming the first partition wall, forming an organic layer including a light-emitting layer on the first partition wall and the first inorganic insulating layer, forming an upper electrode on the organic layer, The organic layer and the upper electrode are each formed by vapor deposition using the first partition wall as a mask.

19. The method for manufacturing a display device according to claim 18, wherein: Further, after forming the upper electrode, forming a cap layer on the upper electrode by performing vapor deposition using the first partition wall as a mask, A sealing layer covering the cap layer and the first partition wall is formed using an inorganic insulating material.

20. The method for manufacturing a display device according to claim 19, wherein: Further, after forming the sealing layer, forming a patterned resist over the sealing layer, performing etching using the resist as a mask to sequentially remove a portion of the sealing layer, a portion of the cover layer, a portion of the upper electrode, and a portion of the organic layer in the display region, In the strip-shaped region, the sealing layer is covered with the resist.

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