Pixel and method of manufacturing pixel

Abstract

The invention discloses a pixel and a method of manufacturing the same. The pixel includes: a substrate; a pixel circuit disposed on the substrate and including at least one transistor and at least one capacitor; a first contact metal disposed on the substrate and to which a constant voltage is applied; an inorganic layer covering the first contact metal; a first pixel electrode disposed on the inorganic layer and electrically connected to the pixel circuit; a pixel defining film disposed on the first pixel electrode; a second contact metal disposed on the pixel defining film and electrically connected to the first contact metal; a spacer disposed on the second contact metal; an organic light emitting portion disposed on the first pixel electrode; and a second pixel electrode disposed on the organic light emitting portion and connected to the second contact metal.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0100054 filed in the Korean Intellectual Property Office on July 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a pixel, a method for manufacturing the pixel, and a display device including the pixel. Background Art

[0003] As information technology has developed, the importance of display devices as a connection medium between users and information has been highlighted. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, etc. has been increasing. Summary of the invention

[0004] The present disclosure may provide a pixel that can improve visibility, a method for manufacturing the pixel, and a display device including the pixel.

[0005] The present disclosure may provide a pixel robust against noise, a method for manufacturing the pixel, and a display device including the pixel.

[0006] An embodiment of a pixel includes: a substrate; a pixel circuit, which is disposed on the substrate and includes at least one transistor and at least one capacitor; a first contact metal, which is disposed on the substrate and a constant voltage is applied to the first contact metal; an inorganic layer, covering the first contact metal; a first pixel electrode, which is disposed on the inorganic layer and is electrically connected to the pixel circuit; a pixel defining film, which is disposed on the first pixel electrode; a second contact metal, which is disposed on the pixel defining film and is electrically connected to the first contact metal; a separator, which is disposed on the second contact metal; an organic light-emitting portion, which is disposed on the first pixel electrode; and a second pixel electrode, which is disposed on the organic light-emitting portion and is connected to the second contact metal.

[0007] The constant voltage may be a low potential voltage.

[0008] The partition may have an inverted tapered shape.

[0009] The second contact metal may be connected to the first contact metal through a cathode contact hole formed by removing at least a portion of the pixel defining film and at least a portion of the inorganic layer.

[0010] A plurality of sub-pixels may be disposed on a substrate, and each of the plurality of sub-pixels may include a pixel circuit, a first pixel electrode may include a first anode electrode of a first sub-pixel among the plurality of sub-pixels, a second anode electrode of a second sub-pixel among the plurality of sub-pixels, and a third anode electrode of a third sub-pixel among the plurality of sub-pixels, and a pixel defining film may be disposed in a boundary region between the first anode electrode and the second anode electrode and in a boundary region between the second anode electrode and the third anode electrode.

[0011] The first contact metal and the second contact metal may be disposed in a boundary region between the first anode electrode and the second anode electrode and in a boundary region between the second anode electrode and the third anode electrode.

[0012] The first contact metal and the second contact metal may be disposed in a boundary region between the first anode electrode and the second anode electrode, and may not be disposed in a boundary region between the second anode electrode and the third anode electrode.

[0013] The second contact metal may completely surround the first anode electrode.

[0014] The second contact metal may surround the first anode electrode, and at least a portion of the second contact metal may be opened around the first anode electrode.

[0015] The width of the upper surface of the pixel defining film may be a first distance, the width of the second contact metal may be a second distance, and the second distance may be less than or equal to the first distance.

[0016] The width of the second contact metal may be the second distance, the width of the lower surface of the spacer may be a third distance less than or equal to the second distance, and the width of the upper surface of the spacer may be greater than or equal to the third distance.

[0017] The second pixel electrode may have a step having a size corresponding to the thickness of the second contact metal.

[0018] The lower end portion of the step may be disposed on the same plane as the upper surface of the second contact metal.

[0019] The pixel may further include a third contact metal disposed on the partition and connected to the second contact metal and the second pixel electrode.

[0020] The third contact metal may be connected to the second contact metal through a cathode contact hole formed by removing at least a portion of the separator.

[0021] An embodiment of a method for manufacturing a pixel includes the following steps: forming a first contact metal on a backplane substrate; forming an inorganic layer on the first contact metal; forming a first pixel electrode on the inorganic layer and electrically connecting the first pixel electrode and the backplane substrate; forming a pixel defining film on the first pixel electrode; forming a second contact metal on the pixel defining film, and electrically connecting the second contact metal and the first contact metal in a region where at least a portion of the pixel defining film is removed; forming a partition on the second contact metal; forming an organic light-emitting portion on the first pixel electrode and the partition; and forming a second pixel electrode on the organic light-emitting portion, and electrically connecting the second pixel electrode and the second contact metal.

[0022] The partition may be formed to have an inverted tapered shape.

[0023] The method of manufacturing a pixel may further include removing at least a portion of each of the partition and the organic light emitting portion to form a third contact metal connected to the second contact metal, wherein the second pixel electrode may further be connected to the third contact metal.

[0024] An embodiment of a display device includes: a plurality of pixels arranged on a substrate, each of the plurality of pixels including a pixel circuit; a plurality of scan lines arranged on the substrate and connected to the pixel circuits of the plurality of pixels; and a plurality of data lines arranged on the substrate and connected to the pixel circuits of the plurality of pixels, wherein at least one of the plurality of pixels includes: a first contact metal arranged on the substrate and a constant voltage applied to the first contact metal; an inorganic layer at least partially covering the first contact metal; a first pixel electrode arranged on the inorganic layer and electrically connected to the pixel circuit; a pixel defining film arranged on the first pixel electrode; a second contact metal arranged on the pixel defining film and electrically connected to the first contact metal; a separator arranged on the second contact metal; an organic light emitting portion arranged on the first pixel electrode; and a second pixel electrode arranged on the organic light emitting portion and connected to the second contact metal.

[0025] The substrate may be a silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic top plan view of a display device according to an embodiment of the present disclosure is shown.

[0027] Figure 2A , Figure 2B and Figure 2C Shows Figure 1 A top plan view of an embodiment of a pixel.

[0028] Figure 3 Shown included in FIG. 2A to FIG. 2C Equivalent circuit of a sub-pixel in a pixel.

[0029] Figure 4 Shows Figure 3 A cross-sectional view of an example of a light emitting element.

[0030] Figure 5 Shows Figure 3 A cross-sectional view of another example of a light emitting element.

[0031] Figure 6 Shown include Figure 3 A cross-sectional view of a stacked structure of a pixel of a light-emitting element.

[0032] Figure 7 According to an embodiment, FIG. 2A to FIG. 2C A cross-sectional view of a pixel taken along line AA'.

[0033] Figure 8 According to another embodiment, FIG. 2A to FIG. 2C A cross-sectional view of a pixel taken along line AA'.

[0034] Fig. 9 Shown based on Figure 2A of Figure 8 A top view of a first sub-pixel.

[0035] Fig.10 Shows Figure 8 Magnified view of area "X".

[0036] Fig.11 According to another embodiment, FIG. 2A to FIG. 2C A cross-sectional view of a pixel taken along line AA'.

[0037] Fig.12 Shows Fig.11 Magnified view of area "Y". DETAILED DESCRIPTION

[0038] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0039] In order to clearly describe the present disclosure, parts or portions not related to the description are omitted, and the same or similar constituent elements are indicated by the same reference numerals throughout the specification. Therefore, the above reference numerals may be used in other drawings.

[0040] In addition, in the drawings, for ease of description, the size and thickness of each element are arbitrarily shown, and the present disclosure is not necessarily limited to the cases shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, areas, etc. may be exaggerated for clarity.

[0041] In addition, the expression "equal to or the same as..." in the specification may mean "substantially equal to or substantially the same as..." That is, it may be the same enough to make those skilled in the art believe that it is the same. Even other expressions may be expressions in which "substantially" is omitted.

[0042] Terms such as first, second, etc. will only be used to describe various components and are not to be construed as limiting these components. These terms are only used to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0043] Terms such as "below", "lower side", "lower part", "on", "upper side" and "upper part" are used to describe the relationship or configuration of elements shown in the drawings. Such terms are understood to provide relative descriptions based on one or more directions shown in the drawings.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, terms should be interpreted as having the same meaning as their meaning in the context of the relevant art or as defined in commonly used dictionaries, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0045] It should be understood that the terms "include", "comprising", "having" or "configured" indicate the existence of the features, quantities, steps, operations, constituent elements, parts or combinations thereof described in the specification, but do not exclude the possibility of the pre-existence or addition of one or more other features, quantities, steps, operations, constituent elements, parts or combinations thereof.

[0046] As used herein, the word "or" means a logical "or" such that the statement "A, B, or C" means "A and B and C," "A and B but not C," "A and C but not B," "B and C but not A," "A but not B and not C," "B but not A and not C," and "C but not A and not B," unless the context dictates otherwise.

[0047] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 A schematic top plan view of a display device DD according to an embodiment of the present disclosure is shown. Figure 2A , Figure 2B and Figure 2C Shows Figure 1 A top plan view of an embodiment of a pixel PX.

[0049] Reference Figure 1 The display device DD is a device for displaying moving images or still images, and can be used as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs), and can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices.

[0050] The display device DD may be formed as a flat surface having a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corners where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded to have a predetermined curvature, or may be formed to have a right angle. The flat shape of the display device DD is not limited to a quadrilateral shape, and may be formed to have other polygonal, circular, or elliptical shapes. The display device DD may be formed to be flat, but is not limited thereto. For example, the display device DD may include a curved portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display device DD may be flexibly formed to be bent, curved, folded, or curled.

[0051] The display device DD may include a plurality of pixels PX configured to display an image (picture or video). The display device DD may also include a plurality of scan lines extending along a first direction DR1 and a plurality of data lines extending along a second direction DR2. In some embodiments, the pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. However, the embodiments of the present disclosure are not limited thereto, and the pixels PX may be arranged side by side in a diagonal direction different from the first direction DR1 and the second direction DR2.

[0052] The pixel PX may include two or more sub-pixels. FIG. 2A to FIG. 2C , the pixel PX may include a plurality of sub-pixels SPX1, SPX2, and SPX3. FIG. 2A to FIG. 2C In the embodiment, the pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 as an example. However, the embodiments of the present disclosure are not limited thereto. For example, the pixel PX may include four or more sub-pixels. Below, for better understanding and ease of description, the case where the pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 will be described as an example.

[0053] Each of the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may be connected (eg, electrically connected) to one of the plurality of data lines, and may be connected (eg, electrically connected) to at least one of the plurality of scan lines.

[0054] The sub-pixel may have a shape such as a polygon or a circle. Figure 2A and Figure 2B , each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a quadrilateral plane shape of a rectangle, a square, or a rhombus. Figure 2C , each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a planar shape other than a quadrilateral planar shape (eg, a hexagonal planar shape). Figure 2A , each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. Figure 2B At least one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 (for example, the second subpixel SPX2) may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. Figure 2B , the remaining sub-pixels of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 (eg, the first sub-pixel SPX1 or the third sub-pixel SPX3) may have a square planar shape. Figure 2C , each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a hexagonal plane shape capable of densely filling a plane. Optionally, in some embodiments, each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may also have a square or diamond plane shape including sides having the same length in the first direction DR1 and the second direction DR2. However, the embodiments of the present disclosure are not limited thereto, and at least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a circular shape or a polygonal shape with rounded corners.

[0055] Reference Figure 2A , the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be arranged in the first direction DR1. Figure 2B, one of the second subpixel SPX2 and the third subpixel SPX3 (e.g., the third subpixel SPX3) and the first subpixel SPX1 may be arranged in the first direction DR1, and the other of the second subpixel SPX2 and the third subpixel SPX3 (e.g., the second subpixel SPX2) and the first subpixel SPX1 may be arranged in the second direction DR2. One pixel PX including the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a planar shape close to a square (or substantially a square).

[0056] Alternatively, one of the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 may be arranged in the first direction DR1, and the other of the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 may be arranged in the second direction DR2. Alternatively, one of the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 may be arranged in the first direction DR1, and the other of the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 may be arranged in the second direction DR2.

[0057] Reference Figure 2C , one of the second subpixel SPX2 and the third subpixel SPX3 and the first subpixel SPX1 may be arranged in the first direction DR1, and the other of the second subpixel SPX2 and the third subpixel SPX3 and the first subpixel SPX1 may be arranged in a direction different from the first direction DR1 and the second direction DR2. For example, the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may be arranged in the form of an equilateral triangle.

[0058] The first sub-pixel SPX1 may emit light in a first band, the second sub-pixel SPX2 may emit light in a second band, and the third sub-pixel SPX3 may emit light in a third band. For example, the light in the first band may be light in a red band. For example, the light in the second band may be light in a blue band. For example, the light in the third band may be light in a green band. The red band may be a band of about 600nm (nanometers) to about 750nm. The green band may be a band of about 480nm to about 560nm. The blue band may be a band of about 370nm to about 460nm. However, the embodiments of the present disclosure are not limited thereto.

[0059] The sub-pixel SPX may include a light emitting element. For example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light emitting element that emits light (eg, Figure 4 and Figure 5The light emitting element LD in the embodiment of the present invention may include an organic light emitting element having an organic layer.

[0060] The sub-pixel SPX may include a light emitting area EMA. The light emitting area EMA may correspond to a region in which the light emitting element is disposed. In some embodiments, the shape of the light emitting area EMA may be the same as or similar to the shape of the sub-pixel SPX. Figure 2A and Figure 2B In the embodiment where the shape of the sub-pixel SPX is a quadrilateral shape, the shape of the light emitting area EMA may be a quadrilateral shape, which is the same as the shape of the sub-pixel SPX. In some embodiments, the shape of the light emitting area EMA may be different from the shape of the sub-pixel SPX. For example, referring to Figure 2C In an embodiment where the shape of the sub-pixel SPX is a hexagonal shape, the shape of the light emitting area EMA may be a circular shape different from the shape of the sub-pixel SPX.

[0061] Reference FIG. 2A to FIG. 2C , the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may have a first light emitting area EMA1 , a second light emitting area EMA2 , and a third light emitting area EMA3 , respectively.

[0062] Reference Figure 2A , the shape of the first subpixel SPX1 may be a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. The shape of the first light emitting area EMA1 may be a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. The shape of the second subpixel SPX2 may be a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. The shape of the second light emitting area EMA2 may be a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. The shape of the third subpixel SPX3 may be a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. The shape of the third light emitting area EMA3 may be a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2.

[0063] Reference Figure 2B, the shape of the first sub-pixel SPX1 may be a square shape having one side in the first direction DR1 and another side in the second direction DR2. The shape of the first light emitting area EMA1 may be a square shape having one side in the first direction DR1 and another side in the second direction DR2. The shape of the second sub-pixel SPX2 may be a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2. The shape of the second light emitting area EMA2 may be a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2. The shape of the third sub-pixel SPX3 may be a square shape having one side in the first direction DR1 and another side in the second direction DR2. The shape of the third light emitting area EMA3 may be a square shape having one side in the first direction DR1 and another side in the second direction DR2.

[0064] Reference Figure 2C , the shape of the first sub-pixel SPX1 may be a hexagonal shape (e.g., a regular hexagonal shape) having one side in the second direction DR2. The shape of the first light emitting area EMA1 may be a circular shape. The shape of the second sub-pixel SPX2 may be a hexagonal shape (e.g., a regular hexagonal shape) having one side in the second direction DR2. The shape of the second light emitting area EMA2 may be a circular shape. The shape of the third sub-pixel SPX3 may be a hexagonal shape (e.g., a regular hexagonal shape) having one side in the second direction DR2. The shape of the third light emitting area EMA3 may be a circular shape.

[0065] The area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be the same (or substantially the same), but the embodiments of the present disclosure are not limited thereto. For example, at least one of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from the others. Alternatively, two of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be the same (or substantially the same), and the other of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from the two. Alternatively, the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from each other.

[0066] Figure 3 Shown included in FIG. 2A to FIG. 2C Detailed description of the equivalent circuit of the sub-pixel SPX in the pixel PX.

[0067] Figure 3 The sub-pixel SPX shown in FIG. 1 may be FIG. 2A to FIG. 2C One of the sub-pixels SPX1, SPX2 and SPX3 shown in FIG.

[0068] exist Figure 3 In order to better understand and facilitate description, the sub-pixel SPX set in the i-th (i is an integer greater than or equal to 1) pixel row (or i-th horizontal line) and the j-th (j is an integer greater than or equal to 1) pixel column will be described as an example.

[0069] Reference Figure 3 The sub-pixel SPX may include a light emitting portion EMU configured to emit light having a brightness corresponding to the data signal. The sub-pixel SPX may include a pixel circuit PXC configured to drive the light emitting portion EMU.

[0070] The light emitting unit EMU may include a light emitting element LD. The light emitting element LD may be connected (e.g., electrically connected) to a first power line PL1 to which a voltage of a first driving power source VDD (or a first power source VDD) is applied. The light emitting element LD may be connected (e.g., electrically connected) to a second power line PL2 to which a voltage of a second driving power source VSS (or a second power source VSS) is applied.

[0071] The light emitting element LD may include a first pixel electrode AE ​​and a second pixel electrode CE. The first pixel electrode AE ​​may be one of an anode electrode and a cathode electrode (eg, an anode electrode), and the second pixel electrode CE may be the other of the anode electrode and the cathode electrode (eg, a cathode electrode). Figure 3 , the first pixel electrode AE ​​can be connected to the first driving power source VDD via the pixel circuit PXC and the first power line PL1. The second pixel electrode CE can be connected to the second driving power source VSS via the second power line PL2. In the following, for the convenience of description, it is assumed that the first pixel electrode AE ​​is the anode electrode of the light emitting element LD, and the second pixel electrode CE is the cathode electrode of the light emitting element LD. However, the embodiments of the present disclosure are not limited thereto.

[0072] The first driving power supply VDD and the second driving power supply VSS may have different potentials. In this case, during the light emitting period of the sub-pixel SPX, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be equal to or higher than the threshold voltage of the light emitting element LD. The voltage of the first driving power supply VDD may be a high potential voltage. The voltage of the second driving power supply VSS may be a low potential voltage.

[0073] Reference Figure 3, the pixel circuit PXC may be electrically connected to the i-th scan line Si and the j-th data line Dj. In some embodiments, the pixel circuit PXC may be electrically connected to a control line (eg, the i-th control line CLi). The pixel circuit PXC may be electrically connected to a sensing line (eg, the j-th sensing line SENj).

[0074] The pixel circuit PXC described above may include two or more transistors and at least one capacitor. Figure 3 , the pixel circuit PXC may include first, second and third transistors T1, T2 and T3 and a storage capacitor Cst.

[0075] The first transistor T1 may be configured to control the amount of driving current applied to the light emitting element LD. The first transistor T1 may be referred to as a driving transistor. The first transistor T1 may be connected (e.g., electrically connected) between the first driving power source VDD and the light emitting element LD. For example, the first terminal (one of the drain terminal and the source terminal) of the first transistor T1 may be electrically connected to the first driving power source VDD through the first power line PL1. The second terminal (the other of the drain terminal and the source terminal) of the first transistor T1 may be connected (e.g., electrically connected) to the second node N2. The gate electrode of the first transistor T1 may be connected (e.g., electrically connected) to the first node N1. The first transistor T1 may control the amount of current (e.g., driving current) applied to the light emitting element LD from the first driving power source VDD through the second node N2 according to the voltage applied to the first node N1. In some embodiments, the first terminal of the first transistor T1 may be a drain terminal, and the second terminal of the first transistor T1 may be a source terminal, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the first terminal may be a source terminal, and the second terminal may be a drain terminal.

[0076] The second transistor T2 may be configured to select the sub-pixel SPX and activate the sub-pixel SPX in response to the scan signal. The second transistor T2 may be referred to as a switching transistor. The second transistor T2 may switch the electrical connection between the data line Dj and the first node N1. The second transistor T2 may be connected (e.g., electrically connected) between the data line Dj and the first node N1. The first terminal of the second transistor T2 may be connected (e.g., electrically connected) to the data line Dj. The second terminal of the second transistor T2 may be connected (e.g., electrically connected) to the first node N1 (or the gate electrode of the first transistor T1). The gate electrode of the second transistor T2 may be connected (e.g., electrically connected) to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals, and for example, when the first terminal is a drain terminal, the second terminal may be a source terminal.

[0077] The second transistor T2 may be turned on in response to a scan signal of a conduction level voltage (e.g., a high level voltage). When the second transistor T2 is turned on, the data line Dj and the first node N1 may be connected (e.g., electrically connected). The first node N1 may be a point where the second terminal of the second transistor T2 is connected to the gate electrode of the first transistor T1. The second transistor T2 may transmit a data signal (e.g., a data voltage) to the gate electrode of the first transistor T1.

[0078] The third transistor T3 may be configured to switch the electrical connection between the second node N2 and the sensing line SENj. The third transistor T3 may be connected (e.g., electrically connected) between the first transistor T1 and the sensing line SENj. A sensing signal (e.g., an analog voltage) may be obtained through the sensing line SENj. When the third transistor T3 is turned on, the voltage of the second node N2 may be initialized. The third transistor T3 is also referred to as an initialization transistor. The third transistor T3 may be turned on in response to a sensing control signal of an on-level voltage from the control line CLi. When the third transistor T3 is turned on, the initialization voltage applied to the sensing line SELj may be transmitted to the second node N2. The third transistor T3 may include a first terminal connected (e.g., electrically connected) to the second node N2. The third transistor T3 may include a second terminal connected (e.g., electrically connected) to the sensing line SENj. The third transistor T3 may include a gate electrode connected (e.g., electrically connected) to the control line CLi. The first terminal and the second terminal of the third transistor T3 are different terminals, and for example, the first terminal may be one of a drain terminal and a source terminal, and the second terminal may be the other of the drain terminal and the source terminal.

[0079] The sensing signal may reflect a characteristic value of the sub-pixel SPX (e.g., a characteristic value of the first transistor T1 or a characteristic value of the light-emitting element LD) or a change in the characteristic value. In some embodiments, a characteristic value of the first transistor T1 (e.g., a threshold voltage, mobility, etc.) or a change in the characteristic value may be detected based on the sensing signal. In some embodiments, a characteristic value of the light-emitting element LD (e.g., a threshold voltage) or a change in the characteristic value may be detected based on the sensing signal. The sensing signal may be used to compensate for deviations in the characteristic values ​​between a plurality of sub-pixels SPX.

[0080] The storage capacitor Cst may be configured to maintain a voltage difference between the first node N1 and the second node N2. Figure 3, the storage capacitor Cst may include a first electrode LE (or a first storage electrode) and a second electrode UE (or a second storage electrode). The first electrode LE may be electrically connected to the first node N1. The second electrode UE may be electrically connected to the second node N2. The storage capacitor Cst may be charged with a data signal or a voltage corresponding to the data signal for maintaining a voltage difference between the first node N1 and the second node N2 during one frame period. For example, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0081] Each of the transistors constituting the pixel circuit PXC may be implemented as an N-type transistor or a P-type transistor. In an N-type transistor, the on-level voltage may be a high-level voltage, and the off-level voltage may be a low-level voltage. In a P-type transistor, the on-level voltage may be a low-level voltage, and the off-level voltage may be a high-level voltage. For example, referring to Figure 3 , discloses an embodiment in which the first transistor T1, the second transistor T2, and the third transistor T3 constituting the pixel circuit PXC are all N-type transistors. However, the embodiments of the present disclosure are not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 described above may be implemented as a P-type transistor.

[0082] In some embodiments, the structure of the pixel circuit PXC may be changed differently. Figure 3 , shows an embodiment in which the pixel circuit PXC includes three transistors T1, T2 and T3 and one storage capacitor Cst. However, the embodiments of the present disclosure are not limited thereto. For example, the pixel circuit PXC may include four or more transistors or two or more capacitors.

[0083] Figure 4 Shows Figure 3 FIG. 1 is a cross-sectional view of an example of a light emitting element LD.

[0084] Reference Figure 4 , the light emitting element LD may include a first pixel electrode AE, an organic light emitting portion EL, and a second pixel electrode CE. In some embodiments, the first pixel electrode AE, the organic light emitting portion EL, and the second pixel electrode CE may be sequentially stacked.

[0085] In an embodiment, the first pixel electrode AE ​​may be formed (e.g., patterned) corresponding to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3. In an example, the first pixel electrode AE ​​may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 corresponding to the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3, respectively. The first anode electrode AE1 may be the first pixel electrode AE ​​corresponding to the first subpixel SPX1. The second anode electrode AE2 may be the first pixel electrode AE ​​corresponding to the second subpixel SPX2. The third anode electrode AE3 may be the first pixel electrode AE ​​corresponding to the third subpixel SPX3.

[0086] The organic light emitting portion EL may be disposed (eg, formed) on the first pixel electrode AE. The organic light emitting portion EL may include one or more light generating layers.

[0087] In some embodiments, the organic light emitting portion EL may have a multilayer thin film structure including a plurality of light generating layers. For example, the organic light emitting portion EL may include a hole injection layer HIL, a hole transport layer HTL, an organic light emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. For example, the hole injection layer HIL, the hole transport layer HTL, the organic light emitting layer EML, the electron transport layer ETL, and the electron injection layer EIL may be stacked in sequence.

[0088] The hole injection layer HIL may be configured to smoothly inject holes from the first pixel electrode AE ​​into the organic light emitting layer EML. The hole injection layer HIL may be placed between the first pixel electrode AE ​​and the hole transport layer HTL. The hole injection layer HIL may be configured as an organic layer including an organic material.

[0089] The hole transport layer HTL may be disposed between the hole injection layer HIL and the organic light emitting layer EML. The hole transport layer HTL may be configured to transport holes provided from the first pixel electrode AE ​​to the organic light emitting layer EML.

[0090] The electron injection layer EIL may be configured to smoothly inject electrons from the second pixel electrode CE to the organic light emitting layer EML. The electron injection layer EIL may be disposed between the second pixel electrode CE and the electron transport layer ETL.

[0091] The electron transport layer ETL may be disposed between the electron injection layer EIL and the organic light emitting layer EML. The electron transport layer ETL may be configured to transport electrons provided from the second pixel electrode CE to the organic light emitting layer EML.

[0092] The organic light emitting layer EML is a region that generates light by the recombination of holes and electrons. The organic light emitting layer EML may include an organic light emitting material configured to emit light in a predetermined band. The organic light emitting material may include, for example, a high molecular weight organic material or a low molecular weight organic material. For example, the organic light emitting layer EML may include an organic material that emits blue light. However, the embodiments of the present disclosure are not limited thereto. For example, the organic light emitting layer EML may include an organic material configured to emit light in a red band or light in a green band. In some embodiments, the organic light emitting layer EML may include an inorganic material or a quantum dot.

[0093] In some embodiments, the second pixel electrode CE may be integrally disposed (eg, formed). The second pixel electrode CE may be disposed on the organic light emitting portion EL. The second pixel electrode CE may be integrally formed in a plurality of light emitting elements.

[0094] Figure 5 Shows Figure 3 FIG. 1 is a cross-sectional view of another example of the light emitting element LD.

[0095] Reference Figure 5 , the light emitting element LD may include a first pixel electrode AE, an organic light emitting portion EL, and a second pixel electrode CE. The organic light emitting portion EL may be formed by stacking two or more organic light emitting portions. Figure 5 , the organic light emitting portion EL may be formed by stacking a first organic light emitting portion ELa and a second organic light emitting portion ELb.

[0096] The organic light emitting portion EL may include one or more light generating layers. For example, the organic light emitting portion EL may include a plurality of light generating layers. In some embodiments, the organic light emitting portion EL may include a first organic light emitting portion ELa, a charge generating layer CGL, and a second organic light emitting portion ELb. Figure 5 , the first pixel electrode AE, the first organic light emitting part ELa, the charge generation layer CGL, the second organic light emitting part ELb, and the second pixel electrode CE may be sequentially stacked.

[0097] The first organic light emitting portion ELa may include a hole injection layer HIL, a first hole transport layer HTLa, a first organic light emitting layer EMLa, and a first electron transport layer ETLa. The hole injection layer HIL, the first hole transport layer HTLa, the first organic light emitting layer EMLa, and the first electron transport layer ETLa may be sequentially stacked.

[0098] The second organic light emitting portion ELb may include a second hole transport layer HTLb, a second organic light emitting layer EMLb, a second electron transport layer ETLb, and an electron injection layer EIL. The second hole transport layer HTLb, the second organic light emitting layer EMLb, the second electron transport layer ETLb, and the electron injection layer EIL may be sequentially stacked.

[0099] In some embodiments, a buffer layer (not shown) may be disposed on the first organic light emitting layer EMLa and the second organic light emitting layer EMLb. The buffer layer may include a compound having an electron transport property.

[0100] The charge generation layer CGL may be used to provide charges to the first and second organic light emitting portions ELa and ELb. The charge generation layer CGL may include an n-type charge generation layer n-CGL and a p-type charge generation layer p-CGL.

[0101] The n-type charge generation layer n-CGL may be configured to supply electrons to the first organic light emitting portion ELa. For example, the n-type charge generation layer n-CGL may include a metal material as a dopant.

[0102] The p-type charge generation layer p-CGL may be configured to supply holes to the second organic light emitting portion ELb.

[0103] exist Figure 5 , the organic light emitting portion EL is shown as being formed by stacking a first organic light emitting portion ELa and a second organic light emitting portion ELb, but the embodiments of the present disclosure are not limited thereto. For example, the organic light emitting portion EL may be formed by stacking three or more organic light emitting portions.

[0104] Figure 6 Shown include Figure 3 A cross-sectional view of a stacked structure of a pixel PX of a light emitting element LD.

[0105] Reference Figure 6 , the pixel PX may include a substrate SUB, a light emitting element LD, an encapsulation layer TFE, and a color filter layer CFL.

[0106] The substrate SUB may be implemented as a glass substrate, a plastic substrate or a silicon substrate. Figure 3 ) may be formed on a substrate SUB. The substrate SUB on which the pixel circuit PXC is formed may be referred to as a backplane substrate. Hereinafter, for better understanding and ease of description, the backplane substrate is referred to as a substrate SUB, but the embodiments of the present disclosure are not limited thereto.

[0107] The pixel circuit layer may be formed (eg, patterned) on the substrate SUB. The pixel circuit layer may include various circuit elements and wirings for driving the light emitting element LD. For example, in the pixel circuit layer, a plurality of transistors (eg, a first transistor T1, a second transistor T2, and a third transistor T3 (see Figure 3 ))、Storage capacitor Cst (see Figure 3 ), scanning line Si (see Figure 3 ), data line Dj (see Figure 3 ), the first power line PL1 (see Figure 3 ), the second power line PL2 (see Figure 3 ) etc. However, the embodiments of the present disclosure are not limited thereto.

[0108] The light emitting element LD may be disposed on the substrate SUB. The light emitting element LD may include a first pixel electrode AE, an organic light emitting portion EL, and a second pixel electrode CE.

[0109] The first pixel electrode AE ​​may be formed (e.g., patterned) corresponding to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. For example, the first pixel electrode AE ​​may be patterned into a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3, and the patterned first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may correspond to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, respectively. For example, the first pixel electrode AE ​​may include a light-transmitting conductive material having a high work function. For example, the first pixel electrode AE ​​may include a light-transmitting (e.g., transparent) conductive material such as tin oxide (TO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and indium gallium zinc oxide (IGZO). However, embodiments of the present disclosure are not limited thereto.

[0110] The organic light emitting portion EL may be disposed between the first pixel electrode AE ​​and the second pixel electrode CE. The organic light emitting portion EL may emit light by the recombination of holes supplied from the first pixel electrode AE ​​and electrons supplied from the second pixel electrode CE. The organic light emitting portion EL may be, for example, a white light emitting layer that emits white light. In some embodiments, the organic light emitting portion EL may be, for example, a blue light emitting layer that emits blue light. In some embodiments, the light (e.g., white light) emitted from the organic light emitting portion EL may be converted into one of red band light, green band light, and blue band light by the color filter layer CFL. The internal design of the organic light emitting portion EL may also vary according to the color of the light to be achieved. In some embodiments, the organic light emitting portion EL may include a blue light emitting layer and may emit light in a blue band. In some embodiments, the organic light emitting portion EL may include a green light emitting layer and may emit light in a green band. In some embodiments, the organic light emitting portion EL may include a red light emitting layer and may emit light in a red band.

[0111] The second pixel electrode CE may be disposed on the organic light emitting portion EL. The second pixel electrode CE may be entirely formed on the substrate SUB and may be formed as a layer. The second pixel electrodes CE of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be connected to each other to form a whole. For example, the second pixel electrode CE may include a conductive material having a low work function. For example, the second pixel electrode CE may include a light-transmitting conductive material such as an alloy of tin oxide (TO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), and ytterbium (Yb). For example, the second pixel electrode CE may include a metal material such as silver (Ag) and copper (Cu) and a magnesium-silver (Mg-Ag) alloy. The second pixel electrode CE may be formed by thinly arranging a metal material, an alloy, etc., but is not limited thereto.

[0112] The encapsulation layer TFE may be disposed on the second pixel electrode CE. The encapsulation layer TFE may be configured to protect the light emitting element LD by blocking moisture or oxygen flowing in from the outside. The encapsulation layer TFE may be implemented as a multilayer film in which one or more inorganic films and one or more organic films are alternately disposed.

[0113] The color filter layer CFL may be disposed on the encapsulation layer TFE. The color filter layer CFL may be configured to convert light (e.g., light in a white band) emitted from the organic light emitting portion EL of the light emitting element LD into light of a specific color. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 disposed to correspond to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, respectively.

[0114] The first color filter CF1 may be disposed in a region corresponding to the first anode electrode AE1 (e.g., a region overlapping the first anode electrode AE1 in the third direction DR3). For example, the first color filter CF1 may selectively transmit light in a first wavelength band. For example, the first color filter CF1 may include a color filter material of a first color that transmits light in the first wavelength band and blocks light in the second wavelength band and the third wavelength band.

[0115] The second color filter CF2 may be disposed in a region corresponding to the second anode electrode AE2 (e.g., a region overlapping the second anode electrode AE2 in the third direction DR3). For example, the second color filter CF2 may selectively transmit light in the second wavelength band. For example, the second color filter CF2 may include a color filter material of a second color that transmits light in the second wavelength band and blocks light in the first wavelength band and the third wavelength band.

[0116] The third color filter CF3 may be disposed in a region corresponding to the third anode electrode AE3 (e.g., a region overlapping the third anode electrode AE3 in the third direction DR3). For example, the third color filter CF3 may selectively transmit light in a third wavelength band. For example, the third color filter CF3 may include a color filter material of a third color that transmits light in the third wavelength band and blocks light in the first wavelength band and the second wavelength band.

[0117] In an embodiment, when the first sub-pixel SPX1 is a red sub-pixel, the first color filter CF1 may include a red color filter material. When the second sub-pixel SPX2 is a green sub-pixel, the second color filter CF2 may include a green color filter material. When the third sub-pixel SPX3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter material.

[0118] In some embodiments, the color filter CF may be omitted. For example, in an embodiment in which light in a first band (e.g., a red band) is emitted from the organic light emitting portion EL corresponding to the first sub-pixel SPX1, light in a second band (e.g., a blue band) is emitted from the organic light emitting portion EL corresponding to the second sub-pixel SPX2, and light in a third band (e.g., a green band) is emitted from the organic light emitting portion EL corresponding to the third sub-pixel SPX3, the color filter CF may be omitted.

[0119] Figure 7 According to an embodiment, FIG. 2A to FIG. 2C A cross-sectional view of a pixel PX taken along line AA'.

[0120] Reference Figure 7, the pixel PX may include a substrate SUB, an inorganic layer IOL, a first pixel electrode AE, an organic light emitting portion EL, a second pixel electrode CE, a pixel defining film PDL, and a spacer SPT.

[0121] The inorganic layer IOL may be disposed on the substrate SUB. Figure 7 , the inorganic layer IOL may be entirely disposed on the substrate SUB. The inorganic layer IOL may be disposed between the substrate SUB and the light emitting element LD. The inorganic layer IOL may be used as a cavity control layer that amplifies light emitted from the organic light emitting portion EL and improves light emitting efficiency. For example, the inorganic layer IOL may be formed into a structure that realizes a microcavity effect. Figure 7 , the inorganic layer IOL is shown to have a uniform thickness on the substrate SUB. However, the embodiments of the present disclosure are not limited thereto. For example, in order to enable the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 to achieve a microcavity effect in response to the wavelength of light emitted from the corresponding sub-pixel, the thickness of the inorganic layer IOL may be different for the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0122] The first pixel electrode AE ​​may be disposed on the inorganic layer IOL. The first pixel electrode AE ​​may include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 corresponding to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Figure 7 , the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be disposed to be spaced apart from each other in the first direction DR1. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may be connected (e.g., electrically connected) to the substrate SUB through the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3, respectively. The first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 may be formed in the inorganic layer IOL.

[0123] The pixel defining film PDL may be disposed on the first pixel electrode AE. The pixel defining film PDL may be configured to distinguish the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 from each other. The pixel defining film PDL may define a position where the organic light emitting portion EL is disposed. The pixel defining film PDL may include an opening that exposes at least a portion of the first pixel electrode AE. For example, referring to Figure 7, the pixel defining film PDL may include a first opening OPN1, a second opening OPN2, and a third opening OPN3 configured to expose at least a portion of each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first opening OPN1, the second opening OPN2, and the third opening OPN3 may correspond to light emitting regions from which light is emitted from the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, respectively. The first opening OPN1 may expose at least a portion of the first anode electrode AE1. The second opening OPN2 may expose at least a portion of the second anode electrode AE2. The third opening OPN3 may expose at least a portion of the third anode electrode AE3.

[0124] The pixel definition film PDL may include an inorganic material. For example, the pixel definition film PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ) In some embodiments, the pixel definition film PDL may have a stacked structure including silicon oxide (SiO x ) layer and a layer containing silicon nitride (SiN x ) of the layer. However, the present disclosure is not limited thereto. In another embodiment, the pixel defining film PDL may include an organic material. For example, the pixel defining film PDL may include one or more of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0125] The spacer SPT may be disposed on the pixel defining film PDL. In some embodiments, the spacer SPT may have an inverted tapered shape whose width gradually increases toward the upper side. The spacer SPT may separate the organic light emitting portions EL commonly disposed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 corresponding to the respective sub-pixels. Therefore, the lateral leakage phenomenon between adjacent sub-pixels may be improved by the organic light emitting portions EL commonly disposed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Therefore, the display device DD (see Figure 1 ) deterioration in brightness or color purity. The partition SPT may include an inorganic material. For example, the partition SPT may include silicon oxide (SiO x ) and silicon nitride (SiN x ) In some embodiments, the spacer SPT may have a stack containing silicon oxide (SiO x ) layer and a layer containing silicon nitride (SiN x) of the layers. However, the present disclosure is not limited thereto. In another embodiment, the spacer SPT may include an organic material. For example, the spacer SPT may include one or more of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin.

[0126] The organic light-emitting portion EL may be disposed on the first pixel electrode AE ​​and the pixel defining film PDL. The organic light-emitting portion EL may be divided into a plurality of light-emitting portions by being cut off from each other by the pixel defining film PDL and the partition SPT. The organic light-emitting portion EL may be divided into a first light-emitting portion EL1, a second light-emitting portion EL2, a third light-emitting portion EL3, and a remaining light-emitting portion REL by the pixel defining film PDL and the partition SPT. In some embodiments, a plurality of light-generating layers included in the organic light-emitting portion EL may be disposed to be separated by the pixel defining film PDL and the partition SPT, respectively. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least some of the plurality of light-generating layers included in the organic light-emitting portion EL may be connected (e.g., continuously extended) in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, and the remaining some of the plurality of light-generating layers may be separated (e.g., cut off) by the pixel defining film PDL and the partition SPT. For example, among the plurality of light-generating layers configuring the organic light-emitting portion EL, the hole injection layer HIL (see Figure 4 and Figure 5 ) or charge generation layer CGL (see Figure 5 ) may be separated by the pixel defining film PDL and the spacer SPT.

[0127] At least a portion of the organic light emitting portion EL may be disposed in a region surrounded by the pixel defining film PDL or the partition SPT. Figure 7 , the first light emitting part EL1 may be surrounded by a pixel defining film PDL or a partition SPT to form a first sub-pixel SPX1. The second light emitting part EL2 may be surrounded by a pixel defining film PDL or a partition SPT to form a second sub-pixel SPX2. The third light emitting part EL3 may be surrounded by a pixel defining film PDL or a partition SPT to form a third sub-pixel SPX3.

[0128] The remaining portion of the organic light emitting portion EL may be disposed on the pixel defining film PDL or the spacer SPT. Figure 7 , the remaining light emitting part REL may be disposed on the partition SPT. The remaining light emitting part REL may be separated from the first light emitting part EL1, the second light emitting part EL2, and the third light emitting part EL3 by the partition SPT.

[0129] Reference Figure 7, the upper surfaces of the first light emitting part EL1, the second light emitting part EL2, and the third light emitting part EL3 and the upper surface of the pixel defining film PDL may be disposed on substantially the same plane. For example, the upper surface of the pixel defining film PDL and the upper surfaces of the first light emitting part EL1, the second light emitting part EL2, and the third light emitting part EL3 may both be disposed on a plane defined by the first direction DR1 and the second direction DR2.

[0130] The spacer SPT may be disposed in a boundary region between adjacent light emitting parts (eg, light emitting parts adjacent to each other in the first direction DR1) or adjacent sub-pixels (eg, sub-pixels adjacent to each other in the first direction DR1). Figure 7 , the partition SPT may be disposed in a boundary region between the first light emitting portion EL1 and the second light emitting portion EL2, or in a boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2. The partition SPT may be disposed in a boundary region between the second light emitting portion EL2 and the third light emitting portion EL3, or in a boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0131] The second pixel electrode CE may be disposed on the organic light emitting portion EL. For example, the second pixel electrode CE may be disposed (or formed) in one layer as a whole on the organic light emitting portion EL. The second pixel electrode CE may be disposed according to the contours of the first light emitting portion EL1, the second light emitting portion EL2, and the third light emitting portion EL3 and the partition SPT. In some embodiments, a plurality of light generating layers configuring the organic light emitting portion EL may all be separated by the partition SPT, and the second pixel electrode CE may contact at least a portion of the partition SPT (e.g., a side surface of the partition SPT).

[0132] In some embodiments, a reflective electrode (not shown) may be further provided on the substrate SUB. The reflective electrode may be placed between the substrate SUB and the first pixel electrode AE. The reflective electrode may be configured to reflect light emitted from the organic light emitting portion EL toward an upper surface (e.g., a third direction DR3). The reflective electrode may include a metal material having excellent reflectivity. Thus, visibility may be improved. The reflective electrode may include, for example, aluminum (Al), silver (Ag), a silver (Ag) alloy, copper (Cu), a magnesium-silver (Mg-Ag) alloy, etc., but the embodiments of the present disclosure are not limited thereto.

[0133] Reference Figure 7 , the spacer SPT may have an inverted tapered shape. Therefore, a problem may occur that the second pixel electrode CE is disconnected at a boundary region between sub-pixels. As a result, display quality may be deteriorated.

[0134] In some embodiments, when a plurality of pixels PX are integrated in a display device DD at a high density (see Figure 1 ), interference may occur between adjacent sub-pixels. For example, the substrate SUB may be a silicon substrate, and the widths of the first opening OPN1, the second opening OPN2, and the third opening OPN3 may be about 3 μm (micrometer) wide or less. Due to the voltage applied to the first anode electrode AE1, interference (e.g., interference of parasitic capacitance) may occur in the second anode electrode AE2 adjacent thereto. Due to the voltage applied to the second anode electrode AE2, interference (e.g., interference of parasitic capacitance) may occur in the third anode electrode AE3 adjacent thereto. Due to the influence of the interference, current may flow in adjacent sub-pixels. As a result, a problem of color mixing may occur.

[0135] A method is needed to solve the problem of disconnection of the second pixel electrode CE and the problem of interference between adjacent sub-pixels.

[0136] Figure 8 According to another embodiment, FIG. 2A to FIG. 2C A cross-sectional view of a pixel PX taken along line AA'.

[0137] Reference Figure 8 , the pixel PX may include a substrate SUB, a first contact metal CMT1, an inorganic layer IOL, a first pixel electrode AE, a pixel defining film PDL, a second contact metal CMT2, a spacer SPT, an organic light emitting portion EL, and a second pixel electrode CE.

[0138] The first contact metal CMT1, the inorganic layer IOL, the first pixel electrode AE, the pixel defining layer PDL, the second contact metal CMT2, the spacer SPT, the organic light emitting portion EL, and the second pixel electrode CE may be sequentially formed.

[0139] In some embodiments, a first contact metal CMT1 may be formed on a substrate SUB (or a backplane substrate). For example, the first contact metal CMT1 may be connected to a pixel circuit PXC (see Figure 3 ) are formed together. For example, the first contact metal CMT1 may be formed between the pixel circuit PXC and the inorganic layer IOL. Hereinafter, for the convenience of description, an embodiment in which the first contact metal CMT1 is formed on the backplane substrate will be described as an example, but the embodiments of the present disclosure are not limited thereto.

[0140] A constant voltage may be applied to the first contact metal CMT1. For example, a voltage of the second driving power source VSS may be applied to the first contact metal CMT1. In some embodiments, the first contact metal CMT1 may receive a voltage of the second driving power source VSS from the substrate SUB. In some embodiments, the first contact metal CMT1 may be grounded.

[0141] The first contact metal CMT1 may be formed to have a single-layer or multi-layer structure.

[0142] The first contact metal CMT1 may be disposed under the pixel definition film PDL. For example, the first contact metal CMT1 may overlap at least a portion of the pixel definition film PDL (for example, overlap at least a portion of the pixel definition film PDL in the third direction DR3). The first contact metal CMT1 may be adjacent to the first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 (for example, adjacent in the first direction DR1).

[0143] The width of the first contact metal CMT1 (eg, the width in the first direction DR1) is shown to be smaller than the width of the pixel definition film PDL in the same direction. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the width of the first contact metal CMT1 may be equal to or greater than the width of the pixel definition film PDL.

[0144] Reference Figure 8 , shows an embodiment in which the first contact metal CMT1 is disposed under all the spacers SPT. However, the embodiments of the present disclosure are not limited thereto, and the first contact metal CMT1 may be disposed under at least a portion of the spacer SPT, and the first contact metal CMT1 may not be disposed under the remaining portion of the spacer SPT. For example, the first contact metal CMT1 may be disposed under the spacer SPT in the boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2, and the first contact metal CMT1 may not be disposed under the spacer SPT in the boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3. For example, the first contact metal CMT1 may not be disposed under the spacer SPT in the boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2, and the first contact metal CMT1 may be disposed under the spacer SPT in the boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0145] The inorganic layer IOL may be formed while covering the first contact metal CMT 1. The inorganic layer IOL may be disposed between the first contact metal CMT 1 and the pixel defining layer PDL.

[0146] The second contact metal CMT2 may be formed on the pixel definition film PDL. The second contact metal CMT2 may be disposed between the pixel definition film PDL and the spacer SPT. The second contact metal CMT2 may be connected (eg, electrically connected) to the first contact metal CMT1. Figure 8, the second contact metal CMT2 may be connected (eg, electrically connected) to the first contact metal CMT1 through the first cathode contact hole CCNT1 , the second cathode contact hole CCNT2 , and the third cathode contact hole CCNT3 .

[0147] Reference Figure 8 , shows an embodiment in which the second contact metal CMT2 is disposed under all the spacers SPT. However, the embodiments of the present disclosure are not limited thereto, and the second contact metal CMT2 may be disposed under at least a portion of the spacer SPT, and the second contact metal CMT2 may not be disposed under the remaining portion of the spacer SPT. For example, the second contact metal CMT2 may be disposed under the spacer SPT in the boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2, and the second contact metal CMT2 may not be disposed under the spacer SPT in the boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3. For example, the second contact metal CMT2 may not be disposed under the spacer SPT in the boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2, and the second contact metal CMT2 may be disposed under the spacer SPT in the boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0148] The cathode contact hole may be formed by removing at least a portion of each of the pixel definition film PDL and the inorganic layer IOL. Figure 8 , the first cathode contact hole CCNT1 , the second cathode contact hole CCNT2 , and the third cathode contact hole CCNT3 may be formed by removing at least a portion of each of the pixel defining film PDL and the inorganic layer IOL, respectively.

[0149] The spacer SPT may be formed on the second contact metal CMT2. The spacer SPT may be disposed between the second contact metal CMT2 and the remaining light emitting portion REL.

[0150] The second pixel electrode CE may be connected (eg, electrically connected) to the second contact metal CMT2. Figure 8 , the second pixel electrode CE may contact at least a portion of the upper surface of the second contact metal CMT2. Figure 8 , the second pixel electrode CE may contact at least a portion of a side surface of the second contact metal CMT2.

[0151] By using the second contact metal CMT2, the problem of disconnection of the second pixel electrode CE may be alleviated or eliminated.

[0152] The second contact metal CMT2 may be connected to the first contact metal CMT1 through the cathode contact holes (e.g., the first cathode contact hole CCNT1, the second cathode contact hole CCNT2, and the third cathode contact hole CCNT3). As a result, the second contact metal CMT2 may perform a function of blocking noise. Therefore, interference problems occurring between adjacent anode electrodes (e.g., interference problems occurring due to parasitic capacitance between adjacent anode electrodes) may be mitigated or eliminated.

[0153] Fig. 9 Shown based on Figure 2A of Figure 8 FIG. 1 is a top view of the first sub-pixel SPX1.

[0154] Reference Fig. 9 , mainly showing the first anode electrode AE1, the pixel definition film PDL and the second contact metal CMT2.

[0155] The pixel defining layer PDL may be disposed around the first anode electrode AE1 .

[0156] The second contact metal CMT2 may be provided while surrounding the first anode electrode AE1. Fig. 9 , shows an embodiment in which the second contact metal CMT2 is disposed while completely surrounding the first anode electrode AE1. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least a portion of the second contact metal CMT2 may be opened around the first anode electrode AE1.

[0157] Fig.10 Shows Figure 8 Magnified view of area "X".

[0158] In the region "X", the first contact metal CMT1, the inorganic layer IOL, the first and second anode electrodes AE1 and AE2, the pixel defining film PDL, the second contact metal CMT2, the separator SPT, the first and second light emitting parts EL1 and EL2, and the second pixel electrode CE are mainly shown.

[0159] The first contact metal CMT1, the inorganic layer IOL, the first and second anode electrodes AE1 and AE2, the pixel defining film PDL, the second contact metal CMT2, the separator SPT, the first and second light emitting parts EL1 and EL2, and the second pixel electrode CE may be sequentially stacked.

[0160] The upper width of the pixel defining film PDL (e.g., the width in the first direction DR1) may be a first distance D1. The width of the second contact metal CMT2 (e.g., the width in the first direction DR1) may be a second distance D2. The lower width of the spacer SPT (e.g., the width in the first direction DR1) may be a third distance D3. The upper width of the spacer SPT (e.g., the width in the first direction DR1) may be a fourth distance D4.

[0161] The second distance D2 may be equal to or less than the first distance D1. The second contact metal CMT2 may be formed on an upper surface of the pixel defining film PDL.

[0162] The third distance D3 may be equal to or less than the second distance D2. The second pixel electrode CE may contact an upper surface or a side surface of the second contact metal CMT2.

[0163] The fourth distance D4 may be greater than the third distance D3. The first light emitting part EL1 and the second light emitting part EL2 may be separated by a partition SPT having an inverse tapered shape.

[0164] The thickness of the second contact metal CMT2 (eg, the thickness in the third direction DR3) may be the first size H1. When the second pixel electrode CE contacts the second contact metal CMT2, the second pixel electrode CE may have a step STEP. Fig.10 , the second pixel electrode CE may have a step STEP formed when it contacts the upper surface and the side surface of the second contact metal CMT2. The size of the step STEP may be a second size H2. The second size H2 may be the same as or similar to the first size H1. The lower end of the step STEP may be disposed in the same plane as the upper surface of the second contact metal CMT2.

[0165] Fig.11 According to another embodiment, FIG. 2A to FIG. 2C A cross-sectional view of a pixel taken along line AA'.

[0166] Reference Fig.11 , the pixel PX may include a substrate SUB, a first contact metal CMT1, an inorganic layer IOL, a first pixel electrode AE, a pixel defining film PDL, a second contact metal CMT2, a spacer SPT, an organic light emitting portion EL, a third contact metal CMT3 and a second pixel electrode CE.

[0167] The first contact metal CMT1, the inorganic layer IOL, the first pixel electrode AE, the pixel defining layer PDL, the second contact metal CMT2, the spacer SPT, the organic light emitting portion EL, the third contact metal CMT3, and the second pixel electrode CE may be sequentially formed.

[0168] The third contact metal CMT3 may be formed on the remaining light emitting portion REL. The third contact metal CMT3 may be disposed between the remaining light emitting portion REL and the second pixel electrode CE. The third contact metal CMT3 may be disposed between the separator SPT and the second pixel electrode CE. The third contact metal CMT3 may be connected (eg, electrically connected) to the second contact metal CMT2. Fig.11 , the third contact metal CMT3 may be connected (eg, electrically connected) to the second contact metal CMT2 through the fourth cathode contact hole CCNT4 , the fifth cathode contact hole CCNT5 , and the sixth cathode contact hole CCNT6 .

[0169] Reference Fig.11 , shows an embodiment in which the third contact metal CMT3 is disposed above all the spacers SPT. However, the embodiments of the present disclosure are not limited thereto, and the second contact metal CMT2 may be disposed above at least a portion of the spacer SPT, and the second contact metal CMT2 may not be disposed above the remaining portion of the spacer SPT. For example, the third contact metal CMT3 may be disposed below the spacer SPT in the boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2, and the third contact metal CMT3 may not be disposed below the spacer SPT in the boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3. For example, the third contact metal CMT3 may not be disposed below the spacer SPT in the boundary region between the first sub-pixel SPX1 and the second sub-pixel SPX2, and the third contact metal CMT3 may be disposed below the spacer SPT in the boundary region between the second sub-pixel SPX2 and the third sub-pixel SPX3.

[0170] The cathode contact hole may be formed by removing at least a portion of each of the remaining light emitting portion REL and the partition SPT. Fig.11 , the fourth cathode contact hole CCNT4 , the fifth cathode contact hole CCNT5 , and the sixth cathode contact hole CCNT6 may be respectively formed by removing at least a portion of each of the remaining light emitting portion REL and the separator SPT.

[0171] The second pixel electrode CE may be formed on the third contact metal CMT3. The second pixel electrode CE may be connected (eg, electrically connected) to the third contact metal CMT3. Fig.11 , the second pixel electrode CE may contact at least a portion of the upper surface of the third contact metal CMT3. Fig.11 , the second pixel electrode CE may contact at least a portion of a side surface of the third contact metal CMT3.

[0172] By using the third contact metal CMT3, the problem of disconnection of the second pixel electrode CE may be alleviated or eliminated.

[0173] The third contact metal CMT3 may be connected to the second contact metal CMT2 through the cathode contact hole (e.g., the fourth cathode contact hole CCNT4, the fifth cathode contact hole CCNT5, and the sixth cathode contact hole CCNT6). As a result, the third contact metal CMT3 may perform a function of blocking noise. Therefore, interference problems occurring between adjacent anode electrodes (e.g., interference problems occurring due to parasitic capacitance between adjacent anode electrodes) may be mitigated or eliminated.

[0174] Fig.12 Shows Fig.11 Magnified view of area "Y".

[0175] and Fig.10 Compared with the region 'X', the third contact metal CMT3 may be further disposed on the remaining light emitting portion REL in the region 'Y'.

[0176] The third contact metal CMT3 may be connected (eg, electrically connected) to the second contact metal CMT2 through the fourth cathode contact hole CCNT4 .

[0177] The width of the third contact metal CMT3 (e.g., the width in the first direction DR1) may be the same as (or substantially the same as) the width of the upper surface of the separator SPT. The width of the third contact metal CMT3 may be, for example, the fourth distance D4. The width of the third contact metal CMT3 may be the same as (or substantially the same as) the width of the remaining light emitting portion REL.

[0178] According to the pixel, the method for manufacturing the pixel, and the display device including the pixel according to the embodiments of the present disclosure, visibility can be improved.

[0179] According to the pixel, the method for manufacturing the pixel, and the display device including the pixel according to the embodiments of the present disclosure, interference caused by noise can be reduced or eliminated.

[0180] Although the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the scope and spirit of the present disclosure as set forth in the claims.

Claims

1. A pixel, comprising: substrate; A pixel circuit is disposed on the substrate and includes at least one transistor and at least one capacitor; a first contact metal disposed on the substrate and to which a constant voltage is applied; an inorganic layer covering the first contact metal; a first pixel electrode, disposed on the inorganic layer and electrically connected to the pixel circuit; A pixel defining film, disposed on the first pixel electrode; a second contact metal disposed on the pixel definition film and electrically connected to the first contact metal; a separator, disposed on the second contact metal; An organic light emitting portion, disposed on the first pixel electrode; as well as A second pixel electrode is disposed on the organic light emitting portion and connected to the second contact metal.

2. The pixel according to claim 1, wherein: The constant voltage is a low potential voltage.

3. The pixel according to claim 1, wherein: The second contact metal is connected to the first contact metal through a cathode contact hole formed by removing at least a portion of the pixel defining film and at least a portion of the inorganic layer.

4. The pixel according to claim 1, wherein: The separator has an inverted conical shape; A plurality of sub-pixels are disposed on the substrate, and each of the plurality of sub-pixels includes the pixel circuit; The first pixel electrode includes a first anode electrode of a first sub-pixel among the plurality of sub-pixels, a second anode electrode of a second sub-pixel among the plurality of sub-pixels, and a third anode electrode of a third sub-pixel among the plurality of sub-pixels; and A pixel defining film is disposed in a boundary region between the first anode electrode and the second anode electrode and in a boundary region between the second anode electrode and the third anode electrode.

5. The pixel according to claim 4, wherein: The first contact metal and the second contact metal are disposed in the boundary region between the first anode electrode and the second anode electrode, and in the boundary region between the second anode electrode and the third anode electrode.

6. The pixel according to claim 4, wherein: The first contact metal and the second contact metal are disposed in the boundary region between the first anode electrode and the second anode electrode, and are not disposed in the boundary region between the second anode electrode and the third anode electrode.

7. The pixel according to claim 1, wherein: The width of the upper surface of the pixel definition film is a first distance, the width of the second contact metal is a second distance, and the second distance is less than or equal to the first distance; and The width of the second contact metal is a second distance, the width of the lower surface of the spacer is a third distance less than or equal to the second distance, and the width of the upper surface of the spacer is greater than or equal to the third distance.

8. The pixel according to claim 1, wherein: The second pixel electrode has a step having a size corresponding to the thickness of the second contact metal; and The lower end of the step is arranged on the same plane as the upper surface of the second contact metal.

9. The pixel according to claim 1, further comprising: a third contact metal disposed on the partition and connected to the second contact metal and the second pixel electrode, The third contact metal is connected to the second contact metal through a cathode contact hole, and the cathode contact hole is formed by removing at least a portion of the separator.

10. A method of manufacturing a pixel, the method comprising: forming a first contact metal on the backplane substrate; forming an inorganic layer on the first contact metal; forming a first pixel electrode on the inorganic layer, and electrically connecting the first pixel electrode and the backplane substrate; forming a pixel defining film on the first pixel electrode; forming a second contact metal on the pixel defining film, and electrically connecting the second contact metal and the first contact metal in a region where at least a portion of the pixel defining film is removed; forming a spacer on the second contact metal; forming an organic light emitting portion on the first pixel electrode and the partition; as well as A second pixel electrode is formed on the organic light emitting portion, and the second pixel electrode and the second contact metal are electrically connected.

Images