Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of reducing or minimizing a dead zone area. According to one or more embodiments of the present disclosure, a display device includes a substrate having a display area and a non-display area, a signal transfer line including a signal line in the display area of the substrate and a fan-out line extending from the signal line and in the non-display area of the substrate, and a plurality of pixels in the display area of the substrate, the plurality of signal transmission lines include signal transmission lines and are respectively connected to the plurality of pixels, and the plurality of signal transmission lines are on different layers on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0102647 filed in the Korean Intellectual Property Office on August 7, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and, for example, to a display device capable of reducing or minimizing a dead zone area. Background Art

[0004] The organic light emitting display device includes a display element whose brightness is changed by electric current, for example, an organic light emitting diode. Summary of the invention

[0005] Aspects of embodiments of the present disclosure provide a display device capable of reducing or minimizing a dead zone area.

[0006] According to one or more embodiments of the present disclosure, a display device includes a substrate having a display area and a non-display area, a signal transmission line including a signal line in the display area of ​​the substrate and a fan-out line extending from the signal line and in the non-display area of ​​the substrate, and a plurality of pixels in the display area of ​​the substrate, wherein the plurality of signal transmission lines include signal transmission lines and are respectively connected to the plurality of pixels, and wherein the plurality of signal transmission lines are on different layers on the substrate.

[0007] In one or more embodiments, a plurality of signal transmission lines overlap in the non-display area.

[0008] In one or more embodiments, a plurality of fan-out lines of the plurality of signal transmission lines overlap in the non-display area and include the fan-out lines.

[0009] In one or more embodiments, when the longest fan-out line among the plurality of fan-out lines of the plurality of signal transmission lines is a reference fan-out line, an overlapping area between the reference fan-out line and each of the plurality of fan-out lines other than the reference fan-out line is different.

[0010] In one or more embodiments, the plurality of signal transmission lines do not overlap in the display area.

[0011] In one or more embodiments, a plurality of signal lines of the plurality of signal transmission lines do not overlap in the display area and include the signal line.

[0012] In one or more embodiments, a plurality of fan-out lines of a plurality of signal transmission lines have different lengths and include the fan-out lines.

[0013] In one or more embodiments, a plurality of signal transmission lines are subsequently on a higher layer as they are arranged with each other in one direction.

[0014] In one or more embodiments, the display device further includes a plurality of connection electrodes that respectively connect the plurality of signal transmission lines to the plurality of pixels. In one or more embodiments, the display device may further include a connection electrode, and each of at least some of the plurality of signal transmission lines is connected to a corresponding pixel in the plurality of pixels through the connection electrode.

[0015] In one or more embodiments, the plurality of signal transmission lines have different lengths, and the plurality of signal lines of the plurality of signal transmission lines are connected to the plurality of pixels through a smaller number of connection electrodes as they have greater lengths, and the plurality of signal lines include the signal lines.

[0016] In one or more embodiments, a plurality of signal transmission lines are connected to a plurality of pixels through a greater number of connection electrodes as they are subsequently on a higher layer.

[0017] In one or more embodiments, multiple signal lines of the multiple signal transmission lines are connected to multiple transistors of multiple pixels through multiple connection electrodes and include signal lines. In one or more embodiments, each of at least some of the multiple signal lines of the multiple signal transmission lines is connected to corresponding transistors of the multiple transistors of the multiple pixels through a connection electrode and includes a signal line.

[0018] In one or more embodiments, the plurality of signal transmission lines are signal transmission lines of a first group, and the display device further includes a second group of signal transmission lines, the second group of signal transmission lines being adjacent to the first group of signal transmission lines and including a plurality of other signal transmission lines that do not overlap with the first group of signal transmission lines.

[0019] In one or more embodiments, two signal transmission lines that are in different groups of signal transmission lines and are positioned adjacent to each other are at the same layer.

[0020] In one or more embodiments, the signal transmission lines of the first group are subsequently on a higher layer as they are arranged with each other in one direction, and the signal transmission lines of the second group are subsequently on a lower layer as they are arranged with each other in one direction.

[0021] In one or more embodiments, the display device further includes a plurality of first capacitor layers respectively in the plurality of pixels and a plurality of second capacitor layers respectively on the plurality of first capacitor layers.

[0022] In one or more embodiments, at least one of the plurality of signal transmission lines is at the same layer as at least one capacitor layer selected from among the plurality of first capacitor layers and the plurality of second capacitor layers.

[0023] In one or more embodiments, a capacitor layer on a layer different from the at least one signal transmission line has a larger area than a capacitor layer at the same layer as the at least one signal transmission line.

[0024] In one or more embodiments, the capacitor layer on a different layer from the at least one signal transmission line overlaps the at least one signal transmission line in the display area.

[0025] In one or more embodiments, a capacitor layer on a different layer from the at least one signal transmission line overlaps a signal line of the at least one signal transmission line in the display area.

[0026] In one or more embodiments, at least one signal transmission line among the plurality of signal transmission lines overlaps an edge of at least one pixel.

[0027] In one or more embodiments, at least one signal transmission line among the plurality of signal transmission lines overlaps with a center of at least one pixel.

[0028] In one or more embodiments, one unit pixel includes two or more pixels among a plurality of pixels, and a plurality of signal transmission lines respectively connected to pixels of the one unit pixel are at an edge of the unit pixel.

[0029] In one or more embodiments, the display device further includes a display driver in a non-display area of ​​the substrate, wherein the plurality of signal transmission lines are connected to the display driver in the non-display area.

[0030] According to one or more embodiments of the present disclosure, a display device includes a substrate having a display area and a non-display area, a plurality of pixels in the display area, and a plurality of signal transmission lines respectively connected to the plurality of pixels in the display area and extending from the display area to the non-display area, wherein the plurality of signal transmission lines are positioned on different layers on the substrate.

[0031] In one or more embodiments, a plurality of signal transmission lines overlap in the non-display area.

[0032] In one or more embodiments, when the longest signal transmission line among the plurality of signal transmission lines is the reference signal transmission line, an overlapping area between the reference signal transmission line and each of the plurality of signal transmission lines other than the reference signal transmission line is different.

[0033] In one or more embodiments, the plurality of signal transmission lines do not overlap in the display area.

[0034] In one or more embodiments, a plurality of signal transmission lines are subsequently on a higher layer as they are arranged with each other in one direction.

[0035] In one or more embodiments, the display device further includes a plurality of connection electrodes respectively connecting the plurality of signal transmission lines to the plurality of pixels.

[0036] In one or more embodiments, the plurality of signal transmission lines have different lengths, and the plurality of signal transmission lines are connected to the plurality of pixels through a smaller number of connection electrodes as they have a greater length.

[0037] In one or more embodiments, a plurality of signal transmission lines are connected to a plurality of pixels through a greater number of connection electrodes as they are subsequently on a higher layer.

[0038] In the display device according to the present disclosure, a plurality of signal transmission lines overlap in the non-display area, and thus the density of the fan-out lines in the fan-out area can be increased. Accordingly, the size of the fan-out area can be reduced and the dead zone area of ​​the display device can be minimized or reduced.

[0039] The effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and other effects, aspects, and features not described herein will become apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other aspects and features of embodiments of the present disclosure will become more apparent by describing in more detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0041] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0042] Figure 2 is a cross-sectional view showing a display device according to one or more embodiments;

[0043] Figure 3 is a plan view showing a display unit of a display device according to one or more embodiments;

[0044] Figure 4 is a block diagram showing a display panel and a display driver according to one or more embodiments;

[0045] Figure 5 is a circuit diagram of one pixel of a display device according to one or more embodiments;

[0046] Figure 6 is a cross-sectional view of a display device according to one or more embodiments;

[0047] Figure 7 yes Figure 3 Detailed configuration diagram of part P;

[0048] Figure 8 is along Figure 7 A cross-sectional view taken along line II';

[0049] Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II';

[0050] Fig.10 is along Figure 7 A cross-sectional view taken along line III-III';

[0051] Fig.11 yes Figure 3 Detailed configuration diagram of part P;

[0052] Fig.12 is along Fig.11 A cross-sectional view taken along line A-IV;

[0053] Fig.13 is along Fig.11 A cross-sectional view taken along line B-IV;

[0054] Fig.14 is along Fig.11 A sectional view taken along line C-IV;

[0055] Fig.15 is along Fig.11 A sectional view taken along line D-IV;

[0056] Fig.16 is along Fig.11 A cross-sectional view taken along line E-IV;

[0057] Fig.17 is along Fig.11 A sectional view taken along line F-IV;

[0058] Fig.18 is a plan view of a display device according to one or more embodiments;

[0059] Fig.19 is along Fig.18 A cross-sectional view taken along line V-V';

[0060] Fig. 20 is a plan view of a display device according to one or more embodiments;

[0061] Fig.21 is along Fig. 20 A cross-sectional view taken along line VI-VI';

[0062] Fig. 22 is along Fig. 20A cross-sectional view taken along line VII-VII';

[0063] Fig.23 is along Fig. 20 A cross-sectional view taken along line VIII-VIII';

[0064] Fig.24 is a plan view of a display device according to one or more embodiments;

[0065] Fig.25 is along Fig.24 A sectional view taken along line IX-IX';

[0066] Fig.26 is a plan view of a display device according to one or more embodiments;

[0067] Fig. 27 is along Fig.26 A cross-sectional view taken along line XX';

[0068] Fig.28 is a plan view of a display device according to one or more embodiments;

[0069] Fig.29 is along Fig.28 A cross-sectional view taken along line XI-XI';

[0070] Fig.30 is a plan view of a first capacitor layer and a third signal transmission line of a display device according to one or more embodiments;

[0071] Fig.31 is a plan view of a second capacitor layer of a display device according to one or more embodiments;

[0072] Fig.32 It is used to explain Fig.30 The third data line is Fig.31 a diagram of an overlapping relationship between a second capacitor layer and a

[0073] Fig.33 is along Fig.30 and Fig.31 A sectional view taken along line XII-XII';

[0074] Fig.34 yes Fig.30 A detailed configuration diagram of the first capacitor layer;

[0075] Fig.35 is a plan view of a first capacitor layer of a display device according to one or more embodiments;

[0076] Fig.36is a plan view of a second capacitor layer and a fourth signal transmission line of a display device according to one or more embodiments;

[0077] Fig.37 It is used to explain Fig.36 The fourth data line is connected to Fig.35 a graph of an overlapping relationship between first capacitor layers;

[0078] Fig.38 is along Fig.35 , Fig.36 and Fig.37 A sectional view taken along line XIII-XIII';

[0079] Fig.39 is a plan view of a display device according to one or more embodiments;

[0080] Fig.40 is a plan view of a display device according to one or more embodiments;

[0081] Fig.41 is a plan view of a display device according to one or more embodiments;

[0082] Fig.42 is a layout view showing pixels of a display area according to one or more embodiments;

[0083] Fig.43 is a perspective view showing a head mounted display device according to one or more embodiments;

[0084] Fig.44 It is shown Fig.43 An exploded perspective view of an example of a head mounted display device; and

[0085] Fig.45 is a perspective view showing a head mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0086] Hereinafter, the present disclosure will now be described more fully with reference to the accompanying drawings showing embodiments of the present disclosure. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0087] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there may be intervening layers. Throughout this disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions are exaggerated for clarity.

[0088] Although the terms "first", "second", etc. may be used in this article to describe one or more suitable elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another element. Therefore, without departing from the teaching of one or more embodiments of the present disclosure, the first element discussed may be referred to as the second element. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used in this article to distinguish different classes or groups of elements. For simplicity, the terms "first", "second", etc. may respectively represent "first class (or first group)", "second class (or second group)", etc.

[0089] The aspects and features of one or more suitable embodiments of the present disclosure may be combined in part or in whole. As will be clearly appreciated by those skilled in the art, one or more suitable interactions and operations in technology are possible. One or more embodiments can be practiced individually or in combination.

[0090] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings.

[0091] Figure 1 is a perspective view showing a display device 10 according to one or more embodiments.

[0092] Reference Figure 1 The display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, ultra mobile PCs (UMPCs), and / or the like. For example, the display device 10 may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) device. For another example, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type or glasses-like displays, or head-mounted displays (HMDs).

[0093] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, the display device 10 may have a planar shape similar to a quadrilateral shape having short sides in the first direction DR1 and long sides in the second direction DR2. The angle at which the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be a right angle or rounded with a suitable curvature (e.g., a set or predetermined curvature). The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, circular shapes, and / or elliptical shapes.

[0094] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0095] The display panel 100 may include a main area MA and a sub area SBA.

[0096] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA arranged around the display area DA along an edge or periphery of the display area DA. The display area DA may be used to emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0097] For example, the self-luminous element may include at least one of an organic light emitting diode (organic LED, OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0098] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver configured to supply a gate signal to a gate line and a fan-out line connecting the display driver 200 to the display area DA.

[0099] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded and / or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3) of the display device 10. The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In one or more embodiments, the sub-area SBA may not be provided (e.g., may be excluded), and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0100] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply voltages to the data lines DL (eg, see Figure 4 ). The display driver 200 may supply a power voltage to the power line, and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, and / or an ultrasonic bonding method. For example, the display driver 200 may be arranged in the sub-area SBA, and may overlap with the main area MA in the thickness direction (e.g., the third direction DR3) of the display device 10 by bending the sub-area SBA. For another example, the display driver 200 may be mounted on the circuit board 300.

[0101] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), and / or a flexible film such as a chip on film.

[0102] The touch driver 400 may be mounted on the circuit board 300 .

[0103] The power supply unit 500 may be arranged on the circuit board 300 to supply a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to the driving voltage line VDL (eg, see Figure 3 ), and a common voltage may be generated to supply it to a common electrode common to the light emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light emitting element, and the common voltage may be a low potential voltage for driving the light emitting element.

[0104] Figure 2 is a cross-sectional view showing a display device 10 according to one or more embodiments.

[0105] Reference Figure 2 , the display panel 100 may include a display unit DU and a color filter layer CFL. The display unit DU may include a substrate SUB, a driving circuit layer DCL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0106] The substrate SUB may be a base substrate SUB or a base member. The substrate SUB may be a flexible substrate SUB that can be bent, folded and / or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material and / or a metal material.

[0107] The driving circuit layer DCL may be arranged on the substrate SUB. The driving circuit layer DCL may include a plurality of transistors. The driving circuit layer DCL may also include a gate line, a data line DL (eg, see Figure 3 ), power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines DL, and leads connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0108] The driving circuit layer DCL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines DL (eg, see FIG. 4 ) of the pixels of the driving circuit layer DCL Figure 3) and power lines may be arranged in the display area DA. Gate control lines and fan-out lines of the driving circuit layer DCL may be arranged in the non-display area NDA. Lead lines of the driving circuit layer DCL may be arranged in the sub-area SBA.

[0109] The light emitting element layer EMTL may be disposed on the driving circuit layer DCL. The light emitting element layer EMTL may include a plurality of light emitting elements ED (eg, see FIG. 1 ) in which pixel electrodes, light emitting layers, and common electrodes are sequentially stacked to emit light. Figure 5 ) and a pixel defining layer defining pixels. A plurality of light emitting elements ED of the light emitting element layer EMTL (for example, see Figure 5 ) may be arranged in the display area DA.

[0110] For example, the light emitting element ED (see, for example, Figure 5 ) may be an organic light-emitting layer including an organic material. Figure 5 ) may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the pixel electrode receives a suitable voltage (e.g., a set or predetermined voltage) through the transistor of the driving circuit layer DCL and the common electrode receives a cathode voltage, holes and electrons may be transferred to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0111] For another example, a plurality of light emitting elements ED (see, for example, Figure 5 ) may each include a quantum dot light-emitting diode comprising a quantum dot light-emitting layer, an inorganic light-emitting diode comprising an inorganic semiconductor, and / or a micro light-emitting diode.

[0112] The encapsulation layer ENC may cover the top and side surfaces of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and / or at least one organic layer for encapsulating the light emitting element layer EMTL.

[0113] The color filter layer CFL may be arranged on the encapsulation layer ENC. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength and may block or reduce or absorb light of a different wavelength. The color filter layer CFL may absorb part of the light from outside the display device 10 to reduce reflected light due to external light. Accordingly, the color filter layer CFL may prevent or reduce color distortion caused by reflection of external light.

[0114] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, and / or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3) of the display device 10. The sub-area SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0115] When the sub-area SBA is bent, such as Figure 2 As shown in FIG. 8 , a protection layer 800 may be further disposed on the bent portion of the sub-area SBA.

[0116] Figure 3 is a plan view showing a display unit of a display device according to one or more embodiments. Figure 4 is a block diagram illustrating a display panel and a display driver according to one or more embodiments.

[0117] Reference Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0118] The display area DA may include a plurality of pixels PX and a plurality of signal transmission lines connected to the plurality of pixels PX. Here, the plurality of signal transmission lines may include a plurality of gate lines GL, a plurality of common voltage lines VSL (eg, see Figure 5 ), multiple emission lines EML, multiple data lines DL, and fan-out lines connected to the aforementioned lines.

[0119] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, an emission line EML, a driving voltage line VDL, and a common voltage line VSL. Each of the pixels PX may include at least one transistor, a light emitting element ED (eg, see Figure 5 ) and capacitors.

[0120] Each of the plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart (eg, spaced and / or separated) from each other in a second direction DR2 crossing the first direction DR1. The gate lines GL may be arranged along the second direction DR2. The gate lines GL may sequentially supply gate signals to the plurality of pixels PX.

[0121] The emission lines EML may each extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The emission lines EML may be arranged along the second direction DR2. The emission lines EML may sequentially supply emission signals to the plurality of pixels PX.

[0122] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may be arranged along the first direction DR1. The data lines DL may supply data voltages to the plurality of pixels PX. The data voltages may determine the brightness of each of the pixels PX.

[0123] The driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The driving voltage lines VDL may be arranged along the first direction DR1. The driving voltage lines VDL may supply a driving voltage to a plurality of pixels PX. The driving voltage may be a high potential voltage for driving the light emitting elements ED of the pixels PX.

[0124] The non-display area NDA may be around (eg, may surround) the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, and first and second gate control lines GSL1 and GSL2.

[0125] The fan-out line FL may extend to the display area DA from the display driver 200. The fan-out line FL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0126] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may transmit a gate control signal GCS (eg, see Figure 4 ) is supplied to the gate driver 610.

[0127] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may transmit the emission control signal ECS (eg, see Figure 4 ) is supplied to the emission control driver 620.

[0128] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include the display driver 200 and the pad portion DP. The pad portion DP may be arranged closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 (for example, see FIG. 1 ) through an anisotropic conductive film (ACF). Figure 1 and Figure 2 ).

[0129] The display driver 200 may include a timing controller 210 (eg, see Figure 4 ) and data driver 220 (see, for example, Figure 4 ).

[0130] The timing controller 210 may receive the digital video data signal DATA and the timing signal from the circuit board 300. The timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a gate control signal GCS for controlling the operation timing of the gate driver 610, and an emission control signal ECS for controlling the operation timing of the emission control driver 620 based on the timing signal. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through the first gate control line GSL1. The timing controller 210 may supply the emission control signal ECS to the emission control driver 620 through the second gate control line GSL2. The timing controller 210 may supply the digital video data signal DATA and the data control signal DCS to the data driver 220.

[0131] The data driver 220 may convert the digital video data signals DATA into analog data voltages and supply them to the data lines DL through the fan-out lines FL. The gate signal of the gate driver 610 may select the pixel PX supplied with the data voltage, and the selected pixel PX may receive the data voltage through the data line DL.

[0132] The power supply unit 500 may be arranged on the circuit board 300 to supply a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to the driving voltage line VDL, and may generate a common voltage to supply it to the light emitting elements ED for a plurality of pixels PX (for example, see Figure 5 )A common common electrode.

[0133] The gate driver 610 may be arranged at one outer side of the display area DA or at one side of the non-display area NDA. The emission control driver 620 may be arranged at the other outer side of the display area DA or at the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be arranged at any one of one side and the other side of the non-display area NDA.

[0134] The gate driver 610 may include a plurality of transistors for generating gate signals based on the gate control signal GCS. The emission control driver 620 may include a plurality of transistors for generating emission signals based on the emission control signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed on the same layer as the transistors of each of the pixels PX (e.g., at the same layer as the transistors of each of the pixels PX). The gate driver 610 may supply the gate signal to the gate line GL, and the emission control driver 620 may supply the emission signal to the emission line EML.

[0135] Figure 5 is a circuit diagram of one pixel of a display device according to one or more embodiments.

[0136] Pixel PX (see, for example, Figure 3 and Figure 4 ) may be connected to the first gate line GWL, the second gate line GCL, the third gate line GRL, the emission line EML, the data line DL, the driving voltage line VDL, the common voltage line VSL and the reference voltage line VRL. Here, the common voltage line VSL may be connected to the common electrode (e.g., cathode electrode) of the light emitting element ED.

[0137] The pixel PX may include a pixel circuit PC and a light emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1 and a second capacitor C2.

[0138] The first transistor T1 (e.g., a driving transistor) may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter, a driving current) according to a data voltage applied to the gate electrode of the first transistor T1. A driving current (e.g., a driving current Isd) flowing through a channel region of the first transistor T1 may be proportional to the square of a difference between a threshold voltage Vth of the first transistor T1 and a voltage Vsg between a source electrode and a gate electrode of the first transistor T1 (Isd=k×(Vsg–Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is a source-gate voltage of the first transistor T1, and Vth is a threshold voltage of the first transistor T1.

[0139] The light emitting element ED may emit light by receiving the driving current Isd. The emission amount or brightness of the light emitting element ED may be proportional to the magnitude of the driving current Isd.

[0140] The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode. For another example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. For another example, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer arranged between the first electrode and the second electrode. For another example, the light emitting element ED may be a micro light emitting diode.

[0141] A first electrode of the light emitting element ED may be electrically connected to the third node N3. A second electrode of the light emitting element ED may be connected to a common voltage line VSL. A second electrode of the light emitting element ED may receive a common voltage ELVSS (eg, a low potential voltage) from the common voltage line VSL.

[0142] The second transistor T2 may be turned on by the first gate signal GW of the first gate line GWL to electrically connect the data line DL to the second electrode of the second capacitor C2. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL to receive the first gate signal GW, the source electrode of the second transistor T2 may be electrically connected to the data line DL, and the drain electrode of the second transistor T2 may be electrically connected to the second electrode of the second capacitor C2. The data line DL may transmit the digital video data signal DATA to the pixel PX.

[0143] The third transistor T3 may be turned on by the second gate signal GC of the second gate line GCL to electrically connect the first node N1 to the second node N2. A gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL to receive the second gate signal GC, a source electrode of the third transistor T3 may be electrically connected to the first node N1, and a drain electrode of the third transistor T3 may be electrically connected to the second node N2.

[0144] The fourth transistor T4 may be turned on by the third gate signal GR of the third gate line GRL to electrically connect the reference voltage line VRL to the first node N1. The gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GRL to receive the third gate signal GR, the source electrode of the fourth transistor T4 may be electrically connected to the reference voltage line VRL, and the drain electrode of the fourth transistor T4 may be electrically connected to the first node N1. The reference voltage line VRL may be used to transmit a reference voltage Vref. The reference voltage Vref may be, for example, greater than (e.g., higher in level than) the common voltage ELVSS and less than (e.g., lower in level than) the driving voltage ELVDD.

[0145] The fifth transistor T5 may be turned on by the third gate signal GR of the third gate line GRL to electrically connect the first node N1 to the third node N3. A gate electrode of the fifth transistor T5 may be electrically connected to the third gate line GRL to receive the third gate signal GR, a source electrode of the fifth transistor T5 may be electrically connected to the first node N1, and a drain electrode of the fifth transistor T5 may be electrically connected to the third node N3.

[0146] The sixth transistor T6 may be turned on by the emission signal EM of the emission line EML to electrically connect the second node N2 which is the drain electrode of the first transistor T1 with the third node N3 which is the first electrode of the light emitting element ED. A gate electrode of the sixth transistor T6 may be electrically connected to the emission line EML to receive the emission signal EM, a source electrode of the sixth transistor T6 may be electrically connected to the second node N2, and a drain electrode of the sixth transistor T6 may be electrically connected to the third node N3.

[0147] The first capacitor C1 may be connected between the first node N1 which is the gate electrode of the first transistor T1 and the driving voltage line VDL. For example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the driving voltage line VDL.

[0148] The second capacitor C2 may be electrically connected between the first node N1 which is the gate electrode of the first transistor T1 and the drain electrode of the second transistor T2. For example, the first electrode of the second capacitor C2 may be electrically connected to the first node N1, and the second electrode of the second capacitor C2 may be electrically connected to the drain electrode of the second transistor T2.

[0149] When the first transistor T1 and the sixth transistor T6 are turned on, a driving current (eg, a driving current Isd) may be supplied to the light emitting element ED so that the light emitting element ED may emit light.

[0150] At least one of the aforementioned first transistor T1 to sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to sixth transistor T6 may be a P-type or P-class MOSFET. In some embodiments, each of the first transistor T1 to sixth transistor T6 may be an N-type or N-class MOSFET. In another example, some of the first transistor T1 to sixth transistor T6 may be a P-type or P-class MOSFET, and the remaining transistors may be an N-type or N-class MOSFET.

[0151] Figure 6 is a cross-sectional view of a display device according to one or more embodiments.

[0152] like Figure 6 As shown in FIG. 1 , the display device 10 (see, for example, Figure 1 and Figure 2 ) may include a driving circuit layer DCL, a light emitting element layer EMTL, an encapsulation layer ENC and a color filter layer CFL.

[0153] The substrate SUB may be a silicon substrate SUB, a germanium substrate SUB and / or a silicon-germanium substrate SUB. The substrate SUB may be a substrate SUB doped with a first type or first class of impurities.

[0154] The well region W may be arranged on (or in) the substrate SUB. The well region W may be a region doped with a second type or second class impurity. The second type or second class impurity may be different from the aforementioned first type or first class impurity. For example, when the first type or first class impurity is a p-type or p-class (e.g., P-type or P-class) impurity, the second type or second class impurity may be an n-type or n-class (e.g., N-type or N-class) impurity. In one or more embodiments, when the first type or first class impurity is an n-type or n-class impurity, the second type or second class impurity may be a p-type or p-class impurity.

[0155] The source region S, drain region D and channel region CH of the transistor TR may be arranged in the well region W. For example, the source region S (or source electrode) and drain region D (or drain electrode) of the transistor TR may be arranged in the well region W. Each of the source region S and the drain region D may be a region doped with the aforementioned first type or first class impurities. The gate electrode G of the transistor TR may intersect and overlap with the well region W in the third direction DR3. In a plan view, the well region W intersecting with the gate electrode G may be defined as two parts, and the source region S may be arranged in any one of the two parts, and the drain region D may be arranged in the other of the two parts. In other words, in the well region W, the source region S and the drain region D may be arranged on both sides of the gate electrode G across the gate electrode G (for example, at the same time). The channel region CH of the transistor TR may be arranged in a region of the well region W that overlaps with the gate electrode G in the third direction DR3. Figure 6 The transistor TR shown in FIG. 1 may be, for example, Figure 5 The first transistor T1.

[0156] In one or more embodiments, the source region S may include a first low-concentration impurity region having an impurity concentration relatively lower than that of other portions of the source region S. In other words, a portion of the source region S may include an impurity concentration lower than that of other portions of the source region S. The drain region D may include a second low-concentration impurity region having an impurity concentration relatively lower than that of other portions of the drain region D. In other words, a portion of the drain region D may include an impurity concentration lower than that of other portions of the drain region D.

[0157] The first low-concentration impurity region and the second low-concentration impurity region may be arranged close to the channel region CH of the transistor TR. For example, the first low-concentration impurity region may be arranged close to the channel region CH to overlap with the first spacer arranged on one side of the gate electrode G, and the second low-concentration impurity region may be arranged close to the channel region CH to overlap with the second spacer arranged on the other side of the gate electrode G. In this way, the distance between the high-concentration impurity region of the source region S and the high-concentration impurity region of the drain region D may be increased due to the first low-concentration impurity region and the second low-concentration impurity region, and the length of the channel region CH may be increased due to the increase in the distance. Accordingly, punch-through and hot carrier phenomena caused by a short channel may be prevented or reduced.

[0158] An interlayer insulating layer VA may be disposed on the substrate SUB and the well region W.

[0159] A passivation layer PAS may be disposed on the interlayer insulating layer VA.

[0160] The light emitting element layer EMTL may be arranged on the passivation layer PAS. The light emitting element layer EMTL may include, for example, a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 arranged in different emission regions. For example, the first light emitting element ED1 of the light emitting element layer EMTL may be arranged in the first emission region EA1, the second light emitting element ED2 of the light emitting element layer EMTL may be arranged in the second emission region EA2, and the third light emitting element ED3 of the light emitting element layer EMTL may be arranged in the third emission region EA3.

[0161] Each of the first light emitting element ED1 , the second light emitting element ED2 , and the third light emitting element ED3 may be configured to emit white light.

[0162] The first light emitting element ED1 may include a first pixel electrode PE1 (or a first anode electrode), a light-providing layer LPL (eg, a light emitting layer), and a common electrode CE stacked in the third direction DR3 .

[0163] The second light emitting element ED2 may include a second pixel electrode PE2 (or a second anode electrode), a light-supplying layer LPL, and a common electrode CE stacked in the third direction DR3.

[0164] The third light emitting element ED3 may include a third pixel electrode PE3 (or a third anode electrode), a light-providing layer LPL, and a common electrode CE stacked in the third direction DR3.

[0165] Here, the light-providing layer LPL and the common electrode CE may be a common layer commonly used by the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3. In other words, a plurality of light-emitting elements (e.g., the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3) of the light-emitting element layer EMTL may share the light-providing layer LPL and the common electrode CE.

[0166] The light providing layer LPL may include a plurality of light emitting layers configured to emit light of different colors, and the plurality of light emitting layers may be stacked along the third direction DR3. Different lights from the plurality of light emitting layers may be mixed to generate white light. In one or more embodiments, the light providing layer LPL may further include a charge generating layer.

[0167] Each of the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 may be connected to a source region S of the transistor TR of a corresponding emission region through a pixel connection electrode PCE of the emission region.

[0168] The first pixel electrode PE1 may be arranged to correspond to the first emission area EA1, the second pixel electrode PE2 may be arranged to correspond to the second emission area EA2, and the third pixel electrode PE3 may be arranged to correspond to the third emission area EA3.

[0169] A dam PDL (or a pixel defining layer) may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , the third pixel electrode PE3 , and the passivation layer PAS.

[0170] The dam PDL may define an emission region of a pixel (eg, a first pixel PX1 (eg, see Figure 7 ) of the first emission area EA1, the second pixel PX2 (for example, see Figure 7 ) of the second emission area EA2 and the third pixel PX3 (for example, see Figure 7 ) of the third emission area EA3. To this end, the dam PDL may be arranged to expose a partial area of ​​each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 on the passivation layer PAS. The dam PDL may cover an edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The dam PDL may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, and / or the like.

[0171] The light-providing layer LPL may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , the third pixel electrode PE3 , and the dam PDL.

[0172] The light providing layer LPL may include a plurality of light emitting units. For example, the light providing layer LPL may include a first light emitting unit, a second light emitting unit, and a third light emitting unit stacked in the third direction DR3. The plurality of light emitting units may be configured to emit light of different wavelengths. For example, the first light emitting unit, the second light emitting unit, and the third light emitting unit may be configured to emit light of different colors. For example, the light providing layer LPL may have a series structure in which a plurality of light emitting units configured to emit light of different colors are stacked in a vertical direction (e.g., the third direction DR3).

[0173] The first light emitting unit may be disposed on the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The first light emitting unit may include a first light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0174] The second light emitting unit may be disposed on the first light emitting unit. The second light emitting unit may include a second light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0175] The third light emitting unit may be disposed on the second light emitting unit. The third light emitting unit may include a third light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0176] The first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be configured to emit white light by mixing light of a first color (e.g., blue) from the first light-emitting unit, light of a second color (e.g., red) from the second light-emitting unit, and light of a third color (e.g., green) from the third light-emitting unit. For example, each of the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the dummy light-emitting element may be configured to emit white light.

[0177] In addition, in addition to the aforementioned light-emitting units, the light-providing layer LPL may further include at least one charge generation layer. For example, the charge generation layer may be arranged between light-emitting units adjacent to each other in the third direction DR3. For example, the charge generation layer may include a first charge generation layer and a second charge generation layer stacked in the third direction DR3. In this case, the first charge generation layer may be arranged between the first light-emitting unit and the second light-emitting unit, and the second charge generation layer may be arranged between the second light-emitting unit and the third light-emitting unit.

[0178] On the other hand, each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0179] The common electrode CE may be arranged on the light providing layer LPL. For example, the common electrode CE may be arranged on the light providing layer LPL to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first emission area EA1, the second emission area EA2, the third emission area EA3, and the dam PDL. In the top emission structure, the common electrode CE may be formed of a transparent conductive material (TCO) configured to transmit light (such as ITO and / or IZO), or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium (Mg) and silver (Ag)). When the common electrode CE is formed of a semi-transmissive conductive material, the luminous efficiency may be increased due to the microcavity effect.

[0180] The cover layer CPL may be disposed on the common electrode CE. The cover layer CPL may include an inorganic insulating material. In one or more embodiments, the cover layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0181] The encapsulation layer ENC may be arranged on the cover layer CPL. The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL, and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer (e.g., a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE3) to prevent or reduce the penetration of oxygen or moisture into the light emitting element layer EMTL. In some embodiments, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign substances such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0182] The first encapsulation inorganic layer TFE1 may be arranged on the cover layer CPL, the encapsulation organic layer TFE2 may be arranged on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be arranged on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be formed of a multilayer in which one or more inorganic layers of silicon nitride layer, silicon oxynitride layer, silicon oxide layer, titanium oxide layer and aluminum oxide layer are alternately stacked. The encapsulation organic layer TFE2 may be an organic layer such as an acryl resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin and / or the like.

[0183] The light blocking layer BM may be arranged on the encapsulation layer ENC. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 arranged to overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the first hole OPT1 may be arranged to overlap the first emission area EA1. The second hole OPT2 may be arranged to overlap the second emission area EA2, and the third hole OPT3 may be arranged to overlap the third emission area EA3. The areas or sizes of the holes OPT1, OPT2, and OPT3 may be larger than the areas or sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3 defined by the dam PDL, respectively. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the first emission area EA1, the second emission area EA2, and the third emission area EA3 so that the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 can be visually recognized by the user not only from the front surface of the display device 10 but also from the side surface of the display device 10.

[0184] The light-blocking layer BM may include a light-absorbing material. For example, the light-blocking layer BM may include an inorganic black pigment and / or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not limited thereto. The light-blocking layer BM may prevent or reduce visible light penetration and color mixing between the first emission area EA1, the second emission area EA2, and the third emission area EA3, which results in an improvement in the color reproducibility of the display device 10.

[0185] In addition, the display device 10 may include a plurality of color filters CF1, CF2, and CF3 arranged on the first emission area EA1, the second emission area EA2, and the third emission area EA3. The plurality of color filters CF1, CF2, and CF3 may be arranged to correspond to the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be arranged on the light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3 arranged to correspond to the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively.

[0186] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 arranged to correspond to different emission areas, respectively (e.g., a first emission area EA1, a second emission area EA2, and a third emission area EA3). The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light in a wavelength band other than light in a specific wavelength band, and may be arranged to correspond to the color of light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3. For example, the first color filter CF1 may be a red color filter arranged to overlap with the first emission area EA1 and transmit only a red first light. The second color filter CF2 may be a green color filter arranged to overlap with the second emission area EA2 and transmit only a green second light, and the third color filter CF3 may be a blue color filter arranged to overlap with the third emission area EA3 and transmit only a blue third light.

[0187] A plurality of color filters CF1, CF2, and CF3 may each be spaced apart from other adjacent color filters on the light-blocking layer BM. The color filters CF1, CF2, and CF3 may each have an area larger than the area of ​​the holes OPT1, OPT2, and OPT3 of the light-blocking layer BM, while covering the holes OPT1, OPT2, and OPT3, and may have an area sufficient to be spaced apart from other color filters CF1, CF2, and CF3 on the light-blocking layer BM. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2, and CF3 may each be arranged to partially overlap with other adjacent color filters. At least two different color filters among the color filters CF1, CF2, and CF3 may overlap each other on the light-blocking layer BM in an area that does not overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3. In the display device 10, the color filters CF1, CF2, and CF3 are arranged to overlap each other so that the intensity of light reflected by external light can be reduced. Furthermore, the color of light reflected by external light may be controlled or selected by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, and CF3 in a plan view.

[0188] The overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the tops of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0189] Figure 7 yes Figure 3 Detailed configuration diagram of part P, Figure 8 is along Figure 7 A cross-sectional view taken along line II' of Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II', and Fig.10 is along Figure 7 A cross-sectional view taken along line III-III'.

[0190] First, in the display device 10 according to one or more embodiments (for example, see Figure 1 and Figure 2), one signal transmission line may include a signal line (e.g., a data line) arranged in a display area DA of a substrate SUB and a fan-out line extending from the signal line (e.g., a data line) and arranged in a non-display area NDA of the substrate SUB. In one or more embodiments, one signal transmission line may include a gate line arranged in a display area DA of the substrate SUB and a fan-out line extending from the gate line and arranged in a non-display area NDA of the substrate SUB. In one or more embodiments, one signal transmission line may include a common voltage line arranged in a display area DA of the substrate SUB and a fan-out line extending from the common voltage line and arranged in a non-display area NDA of the substrate SUB. Each line and the fan-out line connected thereto may be formed integrally. For example, a data line and a fan-out line connected to the data line may be formed integrally.

[0191] Herein, a data line and a fan-out line connected to the data line will be described as a representative signal transmission line.

[0192] like Figure 7 As shown in , one signal transmission line may include a data line (e.g., data line DL1) arranged in a display area DA of a substrate SUB and a fan-out line (e.g., fan-out line FL1) arranged in a non-display area NDA of the substrate SUB. The data line DL1 may be arranged in the display area DA of the substrate SUB, and the fan-out line FL1 may be arranged in the non-display area NDA of the substrate SUB. The data line DL1 and the fan-out line FL1 may be formed integrally.

[0193] In the display device 10 according to one or more embodiments, a plurality of signal transmission lines may be provided. In other words, the display device 10 according to one or more embodiments may include a plurality of signal transmission lines STL1, STL2, STL3, STL4, STL5, and STL6. As an example, Figure 7 A first signal transmitting line STL1 , a second signal transmitting line STL2 , a third signal transmitting line STL3 , a fourth signal transmitting line STL4 , a fifth signal transmitting line STL5 , and a sixth signal transmitting line STL6 are shown.

[0194] Each of the signal transmission lines STL1, STL2, STL3, STL4, STL5, and STL6 may have a meander shape. For example, each of the first signal transmission line STL1, the second signal transmission line STL2, the third signal transmission line STL3, the fourth signal transmission line STL4, the fifth signal transmission line STL5, and the sixth signal transmission line STL6 may have an L shape. In this case, a bend portion of each of the first signal transmission line STL1, the second signal transmission line STL2, the third signal transmission line STL3, the fourth signal transmission line STL4, the fifth signal transmission line STL5, and the sixth signal transmission line STL6 may be arranged in the non-display area NDA.

[0195] Each of the signal transmission lines STL1, STL2, STL3, STL4, STL5, and STL6 may include a data line and a fan-out line as described above. Figure 7 In the example shown in FIG. 1 , the first signal transmission line STL1 may include a first data line DL1 arranged in the display area DA and a first fan-out line FL1 extending from the first data line DL1 and arranged in the non-display area NDA, the second signal transmission line STL2 may include a second data line DL2 arranged in the display area DA and a second fan-out line FL2 extending from the second data line DL2 and arranged in the non-display area NDA, and the third signal transmission line STL3 may include a third data line DL3 arranged in the display area DA and a third fan-out line FL3 extending from the third data line DL3 and arranged in the non-display area NDA. L3, the fourth signal transmission line STL4 may include a fourth data line DL4 arranged in the display area DA and a fourth fan-out line FL4 extending from the fourth data line DL4 and arranged in the non-display area NDA, the fifth signal transmission line STL5 may include a fifth data line DL5 arranged in the display area DA and a fifth fan-out line FL5 extending from the fifth data line DL5 and arranged in the non-display area NDA, and the sixth signal transmission line STL6 may include a sixth data line DL6 arranged in the display area DA and a sixth fan-out line FL6 extending from the sixth data line DL6 and arranged in the non-display area NDA.

[0196] The first to sixth signal transmission lines STL1 to STL6 may be electrically connected to the display driver 200 in the non-display area NDA (eg, see Figure 3 ).

[0197] The first to sixth signal transmission lines STL1 to STL6 and the first, second, third, fourth, fifth, and sixth insulating layers VA1, VA2, VA3, VA4, VA5, and VA6 may be included in the driving circuit layer DCL described above (eg, see Figure 2 ) in the components.

[0198] A plurality of pixels PX1 , PX2 , PX3 , PX4 , PX5 , and PX6 arranged along the first direction DR1 may be disposed in the display area DA.

[0199] The data lines of the signal transmission lines may be connected to the pixels in the display area DA. For example, the first data line DL1 of the first signal transmission line STL1 may be connected to the first pixel PX1, the second data line DL2 of the second signal transmission line STL2 may be connected to the second pixel PX2, the third data line DL3 of the third signal transmission line STL3 may be connected to the third pixel PX3, the fourth data line DL4 of the fourth signal transmission line STL4 may be connected to the fourth pixel PX4, the fifth data line DL5 of the fifth signal transmission line STL5 may be connected to the fifth pixel PX5, and the sixth data line DL6 of the sixth signal transmission line STL6 may be connected to the sixth pixel PX6. For example, Fig.10 As shown in , the first data line DL1 may be connected to the drain electrode D of the second transistor T2_1 provided in the first pixel PX1, the second data line DL2 of the second signal transmission line STL2 may be connected to the drain electrode D of the second transistor T2_2 provided in the second pixel PX2, the third data line DL3 of the third signal transmission line STL3 may be connected to the drain electrode D of the second transistor T2_3 provided in the third pixel PX3, the fourth data line DL4 of the fourth signal transmission line STL4 may be connected to the drain electrode D of the second transistor T2_4 provided in the fourth pixel PX4, the fifth data line DL5 of the fifth signal transmission line STL5 may be connected to the drain electrode D of the second transistor T2_5 provided in the fifth pixel PX5, and the sixth data line DL6 of the sixth signal transmission line STL6 may be connected to the drain electrode D of the second transistor T2_6 provided in the sixth pixel PX6. Here, Fig.10 The second transistors T2_1 to T2_6 can be connected with the above Figure 5 The second transistors T2 are the same as those of the second transistors T2. Each of the second transistors T2 may include a gate electrode G, a channel region CH, a source electrode S, and a drain electrode D. The source electrode S, the drain electrode D, and the channel region CH of each of the second transistors T2 may be arranged in a well region W of the substrate SUB.

[0200] The plurality of signal transmission lines STL1 to STL6 may have different lengths. Figure 7 and Figure 8As shown in , the first signal transmission line STL1 may have a maximum length, the second signal transmission line STL2 may have a second maximum length, the third signal transmission line STL3 may have a third maximum length, the fourth signal transmission line STL4 may have a fourth maximum length, the fifth signal transmission line STL5 may have a fifth maximum length, and the sixth signal transmission line STL6 may have a minimum length. In other words, the first fan-out line FL1 of the first signal transmission line STL1 may have a maximum length, the second fan-out line FL2 of the second signal transmission line STL2 may have a second maximum length, the third fan-out line FL3 of the third signal transmission line STL3 may have a third maximum length, the fourth fan-out line FL4 of the fourth signal transmission line STL4 may have a fourth maximum length, the fifth fan-out line FL5 of the fifth signal transmission line STL5 may have a fifth maximum length, and the sixth fan-out line FL6 of the sixth signal transmission line STL6 may have a minimum length.

[0201] The plurality of signal transmission lines STL1 to STL6 may be connected to the drain electrode D of the second transistor T2 through a greater number of connection electrodes as they are subsequently arranged on a higher layer. For example, a data line of a signal transmission line arranged on the lowest layer among the plurality of signal transmission lines may be directly connected to (or in contact with) the drain electrode D of the second transistor T2. Fig.10As shown in FIG, the first data line DL1 of the first signal transmission line STL1 arranged closest to the substrate SUB on the first insulating layer VA1 may be directly connected to the drain electrode D of the second transistor T2_1 without any connection electrode (e.g., no connection electrode). The second data line DL2 of the second signal transmission line STL2 may be connected to the drain electrode D of the second transistor T2_2 through the connection electrode CNE2. The third data line DL3 of the third signal transmission line STL3 may be connected to the drain electrode D of the second transistor T2_3 through the 3-1st connection electrode CNE3-1 on the first insulating layer VA1 and the 3-2nd connection electrode CNE3-2 on the second insulating layer VA2. The fourth data line DL4 of the fourth signal transmission line STL4 may be connected to the drain electrode D of the second transistor T2_4 through the 4-1st connection electrode CNE4-1 on the first insulating layer VA1, the 4-2nd connection electrode CNE4-2 on the second insulating layer VA2, and the 4-3rd connection electrode CNE4-3 on the third insulating layer VA3. The fifth data line DL5 of the fifth signal transmission line STL5 may be connected to the drain electrode D of the second transistor T2_5 through the 5-1st connection electrode CNE5-1 on the first insulating layer VA1, the 5-2nd connection electrode CNE5-2 on the second insulating layer VA2, the 5-3rd connection electrode CNE5-3 on the third insulating layer VA3, and the 5-4th connection electrode CNE5-4 on the fourth insulating layer VA4. The sixth data line DL6 of the sixth signal transmission line STL6 may be connected to the drain electrode D of the second transistor T2_6 through the 6-1st connection electrode CNE6-1 on the first insulating layer VA1, the 6-2nd connection electrode CNE6-2 on the second insulating layer VA2, the 6-3rd connection electrode CNE6-3 on the third insulating layer VA3, the 6-4th connection electrode CNE6-4 on the fourth insulating layer VA4, and the 6-5th connection electrode CNE6-5 on the fifth insulating layer VA5.

[0202] The connection electrode connected to one data line may be arranged on the same layer as another data line (for example, at the same layer as another data line). For example, the first data line DL1, the connection electrode CNE2, the 3-1st connection electrode CNE3-1, the 4-1st connection electrode CNE4-1, the 5-1st connection electrode CNE5-1, and the 6-1st connection electrode CNE6-1 may be arranged on the same layer (for example, at the same layer). For example, the first data line DL1, the connection electrode CNE2, the 3-1st connection electrode CNE3-1, the 4-1st connection electrode CNE4-1, the 5-1st connection electrode CNE5-1, and the 6-1st connection electrode CNE6-1 may be arranged on the first insulating layer VA1. The second data line DL2, the 3-2nd connection electrode CNE3-2, the 4-2nd connection electrode CNE4-2, the 5-2nd connection electrode CNE5-2, and the 6-2nd connection electrode CNE6-2 may be arranged on the same layer (for example, at the same layer). For example, the second data line DL2, the 3-2nd connection electrode CNE3-2, the 4-2nd connection electrode CNE4-2, the 5-2nd connection electrode CNE5-2, and the 6-2nd connection electrode CNE6-2 may be arranged on the second insulating layer VA2. The third data line DL3, the 4-3rd connection electrode CNE4-3, the 5-3rd connection electrode CNE5-3, and the 6-3rd connection electrode CNE6-3 may be arranged on the same layer (for example, at the same layer). For example, the third data line DL3, the 4-3rd connection electrode CNE4-3, the 5-3rd connection electrode CNE5-3, and the 6-3rd connection electrode CNE6-3 may be arranged on the third insulating layer VA3. The fourth data line DL4, the 5-4th connection electrode CNE5-4, and the 6-4th connection electrode CNE6-4 may be arranged on the same layer (for example, at the same layer). For example, the fourth data line DL4, the 5-4th connection electrode CNE5-4, and the 6-4th connection electrode CNE6-4 may be arranged on the fourth insulating layer VA4. The fifth data line DL5 and the 6-5th connection electrode CNE6-5 may be arranged on the same layer (for example, at the same layer). For example, the fifth data line DL5 and the 6-5th connection electrode CNE6-5 may be arranged on the fifth insulating layer VA5.

[0203] The data line and the connection electrode may be connected to electrodes below the data line and the connection electrode through the through hole of the insulating layer. For example, the first data line DL1, the connection electrode CNE2, the 3-1st connection electrode CNE3-1, the 4-1st connection electrode CNE4-1, the 5-1st connection electrode CNE5-1, and the 6-1st connection electrode CNE6-1 may be respectively connected to the drain electrodes D of the second transistors T2_1 to T2_6 through the contact holes penetrating the first insulating layer VA1. The second data line DL2, the 3-2nd connection electrode CNE3-2, the 4-2nd connection electrode CNE4-2, the 5-2nd connection electrode CNE5-2, and the 6-2nd connection electrode CNE6-2 may be respectively connected to the connection electrode CNE2, the 3-1st connection electrode CNE3-1, the 4-1st connection electrode CNE4-1, the 5-1st connection electrode CNE5-1, and the 6-1st connection electrode CNE6-1 through the contact holes penetrating the second insulating layer VA2. The third data line DL3, the 4-3rd connecting electrode CNE4-3, the 5-3rd connecting electrode CNE5-3 and the 6-3rd connecting electrode CNE6-3 may be respectively connected to the 3-2nd connecting electrode CNE3-2, the 4-2nd connecting electrode CNE4-2, the 5-2nd connecting electrode CNE5-2 and the 6-2nd connecting electrode CNE6-2 through the contact holes penetrating the third insulating layer VA3. The fourth data line DL4, the 5-4th connecting electrode CNE5-4 and the 6-4th connecting electrode CNE6-4 may be respectively connected to the 4-3rd connecting electrode CNE4-3, the 5-3rd connecting electrode CNE5-3 and the 6-3rd connecting electrode CNE6-3 through the contact holes penetrating the fourth insulating layer VA4. The fifth data line DL5 and the 6-5th connecting electrode CNE6-5 may be respectively connected to the 5-4th connecting electrode CNE5-4 and the 6-4th connecting electrode CNE6-4 through the contact holes penetrating the fifth insulating layer VA5. The sixth data line DL6 may be connected to the 6-5th connection electrode CNE6-5 through a contact hole penetrating the sixth insulating layer VA6.

[0204] The signal transmission lines STL1 to STL6 may be arranged on different layers. Figures 8 to 10As shown in , the first signal transmission line STL1 to the sixth signal transmission line STL6 may be arranged in layers at different heights in the third direction DR3 relative to the substrate SUB (e.g., the top surface of the substrate SUB). For example, the first signal transmission line STL1 may be arranged on the first insulating layer VA1, the second signal transmission line STL2 may be arranged on the second insulating layer VA2, the third signal transmission line STL3 may be arranged on the third insulating layer VA3, the fourth signal transmission line STL4 may be arranged on the fourth insulating layer VA4, the fifth signal transmission line STL5 may be arranged on the fifth insulating layer VA5, and the sixth signal transmission line STL6 may be arranged on the sixth insulating layer VA6. As a specific example, the first data line DL1 and the first fan-out line FL1 of the first signal transmission line STL1 may be respectively arranged on the first insulating layer VA1, the second data line DL2 and the second fan-out line FL2 of the second signal transmission line STL2 may be respectively arranged on the second insulating layer VA2, the third data line DL3 and the third fan-out line FL3 of the third signal transmission line STL3 may be respectively arranged on the third insulating layer VA3, the fourth data line DL4 and the fourth fan-out line FL4 of the fourth signal transmission line STL4 may be respectively arranged on the fourth insulating layer VA4, the fifth data line DL5 and the fifth fan-out line FL5 of the fifth signal transmission line STL5 may be arranged on the fifth insulating layer VA5, and the sixth data line DL6 and the sixth fan-out line FL6 of the sixth signal transmission line STL6 may be respectively arranged on the sixth insulating layer VA6.

[0205] In other words, the plurality of signal transmission lines STL1 to STL6 may be arranged on higher layers as they are arranged one to another along the first direction DR1. For example, the first signal transmission line STL1 may be arranged on the first insulating layer VA1 which is the lowest, the second signal transmission line STL2 may be arranged on the second insulating layer VA2 which is the second lowest, the third signal transmission line STL3 may be arranged on the third insulating layer VA3 which is the third lowest, the fourth signal transmission line STL4 may be arranged on the fourth insulating layer VA4 which is the fourth lowest, the fifth signal transmission line STL5 may be arranged on the fifth insulating layer VA5 which is the fifth lowest, and the sixth signal transmission line STL6 may be arranged on the sixth insulating layer VA6 which is the highest.

[0206] Accordingly, the first signal transmission line STL1 may be arranged closest to the substrate SUB, and the sixth signal transmission line STL6 may be arranged farthest from the substrate SUB. In one or more embodiments, the second signal transmission line STL2 may be arranged between the first signal transmission line STL1 and the third signal transmission line STL3 in the third direction DR3, the third signal transmission line STL3 may be arranged between the second signal transmission line STL2 and the fourth signal transmission line STL4 in the third direction DR3, the fourth signal transmission line STL4 may be arranged between the third signal transmission line STL3 and the fifth signal transmission line STL5 in the third direction DR3, and the fifth signal transmission line STL5 may be arranged between the fourth signal transmission line STL4 and the sixth signal transmission line STL6 in the third direction DR3.

[0207] The signal transmission lines STL1 to STL6 may overlap in the non-display area NDA, and may not overlap in the display area DA. Figures 7 to 10 As shown in FIG. 1 , the first to sixth signal transmission lines STL1 to STL6 may overlap in the third direction DR3 in the non-display area NDA, and may not overlap in the third direction DR3 in the display area DA. Figure 7 and Fig.10 As shown in , the first fan-out lines FL1 to the sixth fan-out lines FL6 of the first signal transmission lines STL1 to the sixth signal transmission lines STL6 may overlap in the third direction DR3 in the non-display area NDA, and the first data lines DL1 to the sixth data lines DL6 of the first signal transmission lines STL1 to the sixth signal transmission lines STL6 may not overlap in the third direction DR3 in the display area DA.

[0208] In one or more embodiments, Figure 8As shown in , the overlapping areas between the signal transmission lines STL1 to STL6 may be different. For example, when the longest signal transmission line (e.g., the first signal transmission line STL1) among the first signal transmission line STL1 to the sixth signal transmission line STL6 is defined as the reference signal transmission line, the overlapping area between the reference signal transmission line STL1 and each of the signal transmission lines STL2 to STL6 other than the reference signal transmission line STL1 may be different. For example, the overlapping area between the reference signal transmission line STL1 and the second signal transmission line STL2 may be the largest, the overlapping area between the reference signal transmission line STL1 and the third signal transmission line STL3 may be the second largest, the overlapping area between the reference signal transmission line STL1 and the fourth signal transmission line STL4 may be the third largest, the overlapping area between the reference signal transmission line STL1 and the fifth signal transmission line STL5 may be the fourth largest, and the overlapping area between the reference signal transmission line STL1 and the sixth signal transmission line STL6 may be the smallest. In other words, when the longest fan-out line (e.g., the first fan-out line FL1) among the fan-out lines of the signal transmission lines (e.g., selected from among the fan-out lines of the signal transmission lines) is defined as the reference fan-out line, the overlapping area between the reference fan-out line FL1 and each of the fan-out lines FL2 to FL6 other than the reference fan-out line FL1 may be different. For example, the overlapping area between the reference fan-out line FL1 and the second fan-out line FL2 may be the largest, the overlapping area between the reference fan-out line FL1 and the third fan-out line FL3 may be the second largest, the overlapping area between the reference fan-out line FL1 and the fourth fan-out line FL4 may be the third largest, the overlapping area between the reference fan-out line FL1 and the fifth fan-out line FL5 may be the fourth largest, and the overlapping area between the reference fan-out line FL1 and the sixth fan-out line FL6 may be the smallest.

[0209] The plurality of signal transmission lines STL1 to STL6 may be connected to a smaller number of connection electrodes as they have a greater length. For example, among the first to sixth signal transmission lines STL1 to STL6 overlapping in the non-display area NDA, the first signal transmission line STL1 having the largest length may be directly connected to the drain electrode D of the second transistor T2_1 without any connection electrode (e.g., no connection electrode), the second signal transmission line STL2 having the second largest length may be connected to the drain electrode D of the second transistor T2_2 through one connection electrode CNE2, the third signal transmission line STL3 having the third largest length may be connected to the drain electrode D of the second transistor T2_3 through two connection electrodes CNE3-1 and CNE3-2, and the third signal transmission line STL4 having the third largest length may be connected to the drain electrode D of the second transistor T2_4 through two connection electrodes CNE3-1 and CNE3-2. The fourth signal transmission line STL4 having four largest lengths may be connected to the drain electrode D of the second transistor T2_4 through three connection electrodes CNE4-1, CNE4-2, and CNE4-3, the fifth signal transmission line STL5 having the fifth largest length may be connected to the drain electrode D of the second transistor T2_5 through four connection electrodes CNE5-1, CNE5-2, CNE5-3, and CNE5-4, and the sixth signal transmission line STL6 having the smallest length may be connected to the drain electrode D of the second transistor T2_6 through five connection electrodes CNE6-1, CNE6-2, CNE6-3, CNE6-4, and CNE6-5. As described above, the signal transmission lines STL1 to STL6 may be connected to the corresponding connection electrodes through the data lines DL1 to DL6, respectively.

[0210] When the plurality of signal transmission lines STL1 to STL6 are connected to a smaller number of connection electrodes as they have a greater length, the plurality of signal transmission lines STL1 to STL6 may be subsequently arranged on a lower layer as they have a greater length. In other words, the plurality of signal transmission lines STL1 to STL6 may be arranged closer to the corresponding transistors as they have a greater length. For example, the distance between the first data line DL1 of the first signal transmission line STL1 having the largest length and the drain electrode D of the second transistor T2_1 may be the shortest, while the distance between the sixth data line DL6 of the sixth signal transmission line STL6 having the smallest length and the drain electrode D of the second transistor T2_6 may be the longest.

[0211] According to one or more embodiments, since the signal transmission lines STL1 to STL6 overlap in the third direction DR3 in the non-display area NDA, the density of the fan-out lines in the area where the fan-out lines FL1 to FL6 are arranged (hereinafter, the fan-out area) can be increased. Therefore, the area of ​​the fan-out area (e.g., the size in the first direction DR1×the size in the second direction DR2) can be reduced, so that the dead zone area of ​​the display device 10 can be reduced or minimized.

[0212] In addition, according to one or more embodiments, since the plurality of signal transmission lines STL1 to STL6 overlapped in the non-display area NDA are connected to a greater number of connection electrodes as they have a smaller length, the length deviation of the connection path between the signal transmission lines STL1 to STL6 and the second transistors T2_1 to T2_6 can be reduced or minimized. Accordingly, the voltage drop deviation between the data signals supplied to the pixels PX1 to PX6 through the signal transmission lines STL1 to STL6 can be reduced or minimized. Therefore, the brightness deviation between the pixels PX1 to PX6 can be reduced or minimized, so that the image quality of the display device 10 can be improved.

[0213] Fig.11 yes Figure 3 Detailed configuration diagram of part P. Fig.12 is along Fig.11 A cross-sectional view taken along line A-IV. Fig.13 is along Fig.11 A cross-sectional view taken along line B-IV. Fig.14 is along Fig.11 A cross-sectional view taken along line C-IV. Fig.15 is along Fig.11 A cross-sectional view taken along line D-IV. Fig.16 is along Fig.11 A cross-sectional view taken along line E-IV. Fig.17 is along Fig.11 The sectional view is taken along the line F-IV. In addition to the different positions of the section lines, Fig.11 As described above Figure 7 same.

[0214] like Fig.11 and Fig.12 As shown in , the first data line DL1 of the first signal transmission line STL1 may be arranged in the display area DA, and the first fan-out line FL1 of the first signal transmission line STL1 may be arranged in the non-display area NDA. In this case, the first data line DL1 may be connected to the second transistor T2_1 of the first pixel PX1. For example, the first data line DL1 may be directly connected to the drain electrode D of the second transistor T2_1. In some embodiments, the first fan-out line FL1 of the first signal transmission line STL1 may overlap with the second fan-out line FL2 to the sixth fan-out line FL6 in the non-display area NDA.

[0215] like Fig.11 and Fig.13As shown in , the second data line DL2 of the second signal transmission line STL2 may be arranged in the display area DA, and the second fan-out line FL2 of the second signal transmission line STL2 may be arranged in the non-display area NDA. In this case, the second data line DL2 may be connected to the second transistor T2_2 of the second pixel PX2. For example, the second data line DL2 may be connected to the drain electrode D of the second transistor T2_2 through the connection electrode CNE2. In some embodiments, the second fan-out line FL2 of the second signal transmission line STL2 may overlap with the first fan-out line FL1, the third fan-out line FL3, the fourth fan-out line FL4, the fifth fan-out line FL5, and the sixth fan-out line FL6 in the non-display area NDA.

[0216] like Fig.11 and Fig.14 As shown in , the third data line DL3 of the third signal transmission line STL3 may be arranged in the display area DA, and the third fan-out line FL3 of the third signal transmission line STL3 may be arranged in the non-display area NDA. In this case, the third data line DL3 may be connected to the second transistor T2_3 of the third pixel PX3. For example, the third data line DL3 may be connected to the drain electrode D of the second transistor T2_3 through the 3-1 connection electrode CNE3-1 and the 3-2 connection electrode CNE3-2. In addition, the third fan-out line FL3 of the third signal transmission line STL3 may overlap with the first fan-out line FL1, the second fan-out line FL2, the fourth fan-out line FL4, the fifth fan-out line FL5, and the sixth fan-out line FL6 in the non-display area NDA.

[0217] like Fig.11 and Fig.15 As shown in , the fourth data line DL4 of the fourth signal transmission line STL4 may be arranged in the display area DA, and the fourth fan-out line FL4 of the fourth signal transmission line STL4 may be arranged in the non-display area NDA. In this case, the fourth data line DL4 may be connected to the second transistor T2_4 of the fourth pixel PX4. For example, the fourth data line DL4 may be connected to the drain electrode D of the second transistor T2_4 through the 4-1st connection electrode CNE4-1, the 4-2nd connection electrode CNE4-2, and the 4-3rd connection electrode CNE4-3. In addition, the fourth fan-out line FL4 of the fourth signal transmission line STL4 may overlap with the first fan-out line FL1, the second fan-out line FL2, the third fan-out line FL3, the fifth fan-out line FL5, and the sixth fan-out line FL6 in the non-display area NDA.

[0218] like Fig.11 and Fig.16As shown in , the fifth data line DL5 of the fifth signal transmission line STL5 may be arranged in the display area DA, and the fifth fan-out line FL5 of the fifth signal transmission line STL5 may be arranged in the non-display area NDA. In this case, the fifth data line DL5 may be connected to the second transistor T2_5 of the fifth pixel PX5. For example, the fifth data line DL5 may be connected to the drain electrode D of the second transistor T2_5 through the 5-1st connection electrode CNE5-1, the 5-2nd connection electrode CNE5-2, the 5-3rd connection electrode CNE5-3, and the 5-4th connection electrode CNE5-4. In addition, the fifth fan-out line FL5 of the fifth signal transmission line STL5 may overlap with the first fan-out line FL1, the second fan-out line FL2, the third fan-out line FL3, the fourth fan-out line FL4, and the sixth fan-out line FL6 in the non-display area NDA.

[0219] like Fig.11 and Fig.17 As shown in , the sixth data line DL6 of the sixth signal transmission line STL6 may be arranged in the display area DA, and the sixth fan-out line FL6 of the sixth signal transmission line STL6 may be arranged in the non-display area NDA. In this case, the sixth data line DL6 may be connected to the second transistor T2_6 of the sixth pixel PX6. For example, the sixth data line DL6 may be connected to the drain electrode D of the second transistor T2_6 through the 6-1st connection electrode CNE6-1, the 6-2nd connection electrode CNE6-2, the 6-3rd connection electrode CNE6-3, the 6-4th connection electrode CNE6-4, and the 6-5th connection electrode CNE6-5. In addition, the sixth fan-out line FL6 of the sixth signal transmission line STL6 may overlap with the first fan-out line FL1 to the fifth fan-out line FL5 in the non-display area NDA.

[0220] Fig.18 is a plan view of a display device according to one or more embodiments, and Fig.19 is along Fig.18 A cross-sectional view taken along line V-V'.

[0221] like Fig.18 As shown in FIG. 1 , the first to twelfth pixels PX1 to PX12 may be arranged in the first direction DR1 (eg, arranged along the first direction DR1 ) in the display area DA.

[0222] The first to twelfth signal transmission lines STL1 to STL12 may be connected to the first to twelfth pixels PX1 to PX12, respectively. For example, the seventh data line DL7 of the seventh signal transmission line STL7 may be directly connected to the drain electrode D of the second transistor T2_7 provided in the seventh pixel PX7, the eighth data line DL8 of the eighth signal transmission line STL8 may be connected to the drain electrode D of the second transistor T2_8 provided in the eighth pixel PX8 through one connection electrode CNE, the ninth data line DL9 of the ninth signal transmission line STL9 may be connected to the drain electrode D of the second transistor T2_9 provided in the ninth pixel PX9 through two connection electrodes CNE, and the tenth data line DL10 of the tenth signal transmission line STL11 may be connected to the drain electrode D of the second transistor T2_9 provided in the ninth pixel PX9 through two connection electrodes CNE. The tenth data line DL10 can be connected to the drain electrode D of the second transistor T2_10 provided in the tenth pixel PX10 through three connecting electrodes CNE, the eleventh data line DL11 of the eleventh signal transmission line STL11 can be connected to the drain electrode D of the second transistor T2_11 provided in the eleventh pixel PX11 through four connecting electrodes CNE, and the twelfth data line DL12 of the twelfth signal transmission line STL12 can be connected to the drain electrode D of the second transistor T2_12 provided in the twelfth pixel PX12 through five connecting electrodes CNE.

[0223] In one or more embodiments, the connection relationship between the first to sixth signal transmission lines STL1 to STL6 and the first to sixth pixels PX1 to PX6 can refer to the above description of Figure 7 and Fig.10 Description.

[0224] The first to twelfth signal transmission lines STL1 to STL12 may be divided into signal transmission lines of the first group GRP1 and signal transmission lines of the second group GRP2. For example, the first to sixth signal transmission lines STL1 to STL6 which are adjacently arranged in the first direction DR1 and overlap in the third direction DR3 may be signal transmission lines of the first group GRP1, and the seventh to twelfth signal transmission lines STL7 to STL12 which are adjacently arranged in the first direction DR1 and overlap in the third direction DR3 may be signal transmission lines of the second group GRP2.

[0225] The signal transmission lines of the second group GRP2 may be arranged adjacent to the signal transmission lines of the first group GRP1 in the first direction DR1.

[0226] The signal transmission lines of the same group may overlap each other in the non-display area NDA. Fig.18 and Fig.19As shown in FIG. 1 , the first to sixth signal transmitting lines STL1 to STL6 may overlap in the third direction DR3 in the non-display area NDA, and the seventh to twelfth signal transmitting lines STL7 to STL12 may overlap in the third direction DR3 in the non-display area NDA.

[0227] Different groups of signal transmission lines may not overlap in the non-display area NDA. Fig.18 and Fig.19 As shown in FIG. 1 , the first to sixth signal transmitting lines STL1 to STL6 and the seventh to twelfth signal transmitting lines STL7 to STL12 may not overlap in the third direction DR3 in the non-display area NDA.

[0228] The signal transmission lines of the same group may be arranged on a higher layer subsequently as they are arranged one next to another along the first direction DR1. Fig.19 As shown in , the first to sixth signal transmitting lines STL1 to STL6 may be subsequently arranged on a higher layer as they are arranged one another along the first direction DR1, and the seventh to twelfth signal transmitting lines STL7 to STL12 may be subsequently arranged on a higher layer as they are arranged one another along the first direction DR1.

[0229] The signal transmission lines arranged in different groups and adjacent to each other may be arranged on different layers in the display area DA. Fig.19 As shown in FIG. 1 , the sixth signal transmission line STL6 of the first group GRP1 and the seventh signal transmission line STL7 of the second group GRP2 may be arranged on different layers. Fig.19 In one example shown in , the sixth signal transmission line STL6 and the seventh signal transmission line STL7 may be arranged to have a maximum distance therebetween. In other words, the sixth signal transmission line STL6 may be arranged on the highest layer (e.g., the sixth insulating layer VA6), and the seventh signal transmission line STL7 may be arranged on the lowest layer (e.g., the first insulating layer VA1).

[0230] Fig. 20 is a plan view of a display device according to one or more embodiments, Fig.21 is along Fig. 20 A cross-sectional view taken along line VI-VI', Fig. 22 is along Fig. 20 A cross-sectional view taken along line VII-VII', and Fig.23 is along Fig. 20 A cross-sectional view taken along line VIII-VIII'.

[0231] like Fig. 20As shown in FIG, the signal transmission lines of the first group GRP1 and the signal transmission lines of the second group GRP2 may be arranged adjacent to each other. Here, the signal transmission lines of the first group GRP1 may be arranged adjacent to the above-mentioned Figures 7 to 17 The first to sixth signal transmitting lines STL1 to STL6 are the same.

[0232] like Fig. 20 As shown in FIG. 1 , the signal transmitting lines of the second group GRP2 may include seventh to twelfth signal transmitting lines STL7 to STL12 .

[0233] like Fig. 20 As shown in the figure, the seventh signal transmission line STL7 may include a seventh data line DL7 arranged in the display area DA and a seventh fan-out line FL7 extending from the seventh data line DL7 and arranged in the non-display area NDA, the eighth signal transmission line STL8 may include an eighth data line DL8 arranged in the display area DA and an eighth fan-out line FL8 extending from the eighth data line DL8 and arranged in the non-display area NDA, the ninth signal transmission line STL9 may include a ninth data line DL9 arranged in the display area DA and a ninth fan-out line FL9 extending from the ninth data line DL9 and arranged in the non-display area NDA, and the tenth signal transmission line STL9 may include a seventh data line DL7 arranged in the display area DA and a seventh fan-out line FL7 extending from the seventh data line DL7 and arranged in the non-display area NDA. L10 may include a tenth data line DL10 arranged in the display area DA and a tenth fan-out line FL10 extending from the tenth data line DL10 and arranged in the non-display area NDA, the eleventh signal transmission line STL11 may include an eleventh data line DL11 arranged in the display area DA and an eleventh fan-out line FL11 extending from the eleventh data line DL11 and arranged in the non-display area NDA, and the twelfth signal transmission line STL12 may include a twelfth data line DL12 arranged in the display area DA and a twelfth fan-out line FL12 extending from the twelfth data line DL12 and arranged in the non-display area NDA.

[0234] The seventh data line DL7 of the seventh signal transmission line STL7 may be connected to the seventh pixel PX7, the eighth data line DL8 of the eighth signal transmission line STL8 may be connected to the eighth pixel PX8, the ninth data line DL9 of the ninth signal transmission line STL9 may be connected to the ninth pixel PX9, the tenth data line DL10 of the tenth signal transmission line STL10 may be connected to the tenth pixel PX10, the eleventh data line DL11 of the eleventh signal transmission line STL11 may be connected to the eleventh pixel PX11, and the twelfth data line DL12 of the twelfth signal transmission line STL12 may be connected to the twelfth pixel PX12. For example, Fig.23As shown in , the seventh data line DL7 may be connected to the drain electrode D of the second transistor T2_7 provided in the seventh pixel PX7, the eighth data line DL8 of the eighth signal transmission line STL8 may be connected to the drain electrode D of the second transistor T2_8 provided in the eighth pixel PX8, the ninth data line DL9 of the ninth signal transmission line STL9 may be connected to the drain electrode D of the second transistor T2_9 provided in the ninth pixel PX9, the tenth data line DL10 of the tenth signal transmission line STL10 may be connected to the drain electrode D of the second transistor T2_10 provided in the tenth pixel PX10, the eleventh data line DL11 of the eleventh signal transmission line STL11 may be connected to the drain electrode D of the second transistor T2_11 provided in the eleventh pixel PX11, and the twelfth data line DL12 of the twelfth signal transmission line STL12 may be connected to the drain electrode D of the second transistor T2_12 provided in the twelfth pixel PX12. Here, Fig.23 Each of the second transistors T2_7 to T2_12 can be connected to the above Figure 5 Each of the second transistors T2_7 to T2_12 may include a gate electrode G, a channel region CH, a source electrode S, and a drain electrode D. The source electrode S, the drain electrode D, and the channel region CH of each of the second transistors T2_7 to T2_12 may be arranged in a well region W of the substrate SUB.

[0235] The seventh to twelfth signal transmitting lines STL7 to STL12 may be subsequently arranged on a lower layer as they are aligned with each other along the first direction DR1. Fig. 22 and Fig.23 As shown in the figure, the seventh signal transmission line STL7 can be arranged on the sixth insulating layer VA6 which is the highest layer, the eighth signal transmission line STL8 can be arranged on the fifth insulating layer VA5 which is the next highest layer, the ninth signal transmission line STL9 can be arranged on the fourth insulating layer VA4 which is the next highest layer, the tenth signal transmission line STL10 can be arranged on the third insulating layer VA3 which is the next highest layer, the eleventh signal transmission line STL11 can be arranged on the second insulating layer VA2 which is the next highest layer, and the twelfth signal transmission line STL12 can be arranged on the first insulating layer VA1 which is the lowest layer.

[0236] like Fig.23As shown in FIG. 1 , the seventh data line DL7 of the seventh signal transmission line STL7 may be connected to the drain electrode D of the second transistor T2_7 through the 7-1st connection electrode CNE7-1 on the first insulating layer VA1, the 7-2nd connection electrode CNE7-2 on the second insulating layer VA2, the 7-3rd connection electrode CNE7-3 on the third insulating layer VA3, the 7-4th connection electrode CNE7-4 on the fourth insulating layer VA4, and the 7-5th connection electrode CNE7-5 on the fifth insulating layer VA5. The eighth data line DL8 of the eighth signal transmission line STL8 may be connected to the drain electrode D of the second transistor T2_8 through the 8-1st connection electrode CNE8-1 on the first insulating layer VA1, the 8-2nd connection electrode CNE8-2 on the second insulating layer VA2, the 8-3rd connection electrode CNE8-3 on the third insulating layer VA3, and the 8-4th connection electrode CNE8-4 on the fourth insulating layer VA4. The ninth data line DL9 of the ninth signal transmission line STL9 may be connected to the drain electrode D of the second transistor T2_9 through the 9-1st connection electrode CNE9-1 on the first insulating layer VA1, the 9-2nd connection electrode CNE9-2 on the second insulating layer VA2, and the 9-3rd connection electrode CNE9-3 on the third insulating layer VA3. The tenth data line DL10 of the tenth signal transmission line STL10 may be connected to the drain electrode D of the second transistor T2_10 through the 10-1st connection electrode CNE10-1 on the first insulating layer VA1 and the 10-2nd connection electrode CNE10-2 on the second insulating layer VA2. The eleventh data line DL11 of the eleventh signal transmission line STL11 may be directly connected to the drain electrode D of the second transistor T2_11 through the eleventh connection electrode CNE11 on the first insulating layer VA1.

[0237] like Fig.21 and Fig.23 As shown in , the seventh signal transmission line STL7 to the twelfth signal transmission line STL12 may overlap in the third direction DR3 in the non-display area NDA, and may not overlap in the third direction DR3 in the display area DA. In other words, the seventh fan-out line FL7 to the twelfth fan-out line FL12 of the seventh signal transmission line STL7 to the twelfth signal transmission line STL12 may overlap in the third direction DR3 in the non-display area NDA, and the seventh data line DL7 to the twelfth data line DL12 of the seventh signal transmission line STL7 to the twelfth signal transmission line STL12 may not overlap in the third direction DR3 in the display area DA.

[0238] In this way, since the signal transmission lines STL7 to STL12 overlap in the third direction DR3 in the non-display area NDA, the density of the fan-out lines in the area where the fan-out lines FL7 to FL12 are arranged (hereinafter, referred to as the fan-out area) can be increased. As a result, the area of ​​the fan-out area (e.g., the size in the first direction DR1×the size in the second direction DR2) can be reduced, so that the dead zone area of ​​the display device can be reduced or minimized.

[0239] Fig.24 is a plan view of a display device according to one or more embodiments, and Fig.25 is along Fig.24 Here, in addition to the position of the section line, Fig.24 As described above Fig. 20 same.

[0240] like Fig.24 and Fig.25 As shown in , while the signal transmission lines STL1 to STL6 of the first group GRP1 may be arranged on a higher layer as they are arranged with each other along the first direction DR1, the signal transmission lines STL7 to STL12 of the second group GRP2 may be arranged on a lower layer as they are arranged with each other along the first direction DR1. Accordingly, the signal transmission lines that respectively belong to different groups among the adjacent groups and are arranged to be adjacent to each other may be placed on the same layer (e.g., at the same layer) in the display area DA. For example, as Fig.25 As shown in , the sixth signal transmission line STL6 of the first group GRP1 and the seventh signal transmission line STL7 of the second group GRP2 adjacent to the first group GRP1 may be arranged on the same layer (eg, at the same layer). Fig.25 As shown in , the deviation between the distance from the sixth signal transmission line STL6 to the drain electrode D of the second transistor T2_6 and the distance from the seventh signal transmission line STL7 to the drain electrode D of the second transistor T2_7 can be reduced or minimized. Therefore, the deviation between the voltage drop of the data signal supplied to the sixth pixel PX6 through the sixth signal transmission line STL6 and the voltage drop of the data signal supplied to the seventh pixel PX7 through the seventh signal transmission line STL7 can be reduced or minimized. Therefore, when the data signal of the same gray level is supplied to the sixth pixel PX6 and the seventh pixel PX7 adjacent to each other, the brightness deviation between the adjacent sixth pixel PX6 and the seventh pixel PX7 can be reduced or minimized, so that the display device 10 (for example, see Figure 1 and Figure 2 ) image quality.

[0241] Fig.26 is a plan view of a display device according to one or more embodiments, and Fig. 27is along Fig.26 A cross-sectional view taken along line XX'.

[0242] Fig.26 and Fig. 27 The display device 10 (see, for example, Figure 1 and Figure 2 )and Figure 20 to Figure 25 The display device of FIG. 1 is different in heights of the first to twelfth signal transmitting lines STL1 to STL12 in the third direction DR3 , and the following description will mainly focus on this difference.

[0243] like Fig.26 and Fig. 27 As shown in FIG. 1 , the signal transmission lines of the first group GRP1 may include first to sixth signal transmission lines STL1 to STL6. Fig. 27 As shown in, the first data line DL1 of the first signal transmission line STL1 can be directly connected to the drain electrode D of the second transistor T2_1, the second data line DL2 of the second signal transmission line STL2 can be connected to the drain electrode D of the second transistor T2_2 through two connecting electrodes CNE, the third data line DL3 of the third signal transmission line STL3 can be connected to the drain electrode D of the second transistor T2_3 through four connecting electrodes CNE, the fourth data line DL4 of the fourth signal transmission line STL4 can be connected to the drain electrode D of the second transistor T2_4 through five connecting electrodes CNE, the fifth data line DL5 of the fifth signal transmission line STL5 can be connected to the drain electrode D of the second transistor T2_5 through three connecting electrodes CNE, and the sixth data line DL6 of the sixth signal transmission line STL6 can be connected to the drain electrode D of the second transistor T2_6 through one connecting electrode CNE.

[0244] like Fig.26 and Fig. 27As shown in , the signal transmission lines of the second group GRP2 may include the seventh signal transmission line STL7 to the twelfth signal transmission line STL12. Here, the seventh data line DL7 of the seventh signal transmission line STL7 may be directly connected to the drain electrode D of the second transistor T2_7, the eighth data line DL8 of the eighth signal transmission line STL8 may be connected to the drain electrode D of the second transistor T2_8 through two connection electrodes CNE, the ninth data line DL9 of the ninth signal transmission line STL9 may be connected to the drain electrode D of the second transistor T2_9 through four connection electrodes CNE, the tenth data line DL10 of the tenth signal transmission line STL10 may be connected to the drain electrode D of the second transistor T2_10 through five connection electrodes CNE, the eleventh data line DL11 of the eleventh signal transmission line STL11 may be connected to the drain electrode D of the second transistor T2_11 through three connection electrodes CNE, and the twelfth data line DL12 of the twelfth signal transmission line STL12 may be connected to the drain electrode D of the second transistor T2_12 through one connection electrode CNE.

[0245] like Fig. 27 As shown in , the height difference between the sixth signal transmission line STL6 of the first group GRP1 and the seventh signal transmission line STL7 of the second group GRP2 adjacent to the first group GRP1 can be reduced. Fig. 27 As shown in , the deviation between the distance from the sixth signal transmission line STL6 to the drain electrode D of the second transistor T2_6 and the distance from the seventh signal transmission line STL7 to the drain electrode D of the second transistor T2_7 can be reduced or minimized. Therefore, the deviation between the voltage drop of the data signal supplied to the sixth pixel PX6 through the sixth signal transmission line STL6 and the voltage drop of the data signal supplied to the seventh pixel PX7 through the seventh signal transmission line STL7 can be reduced or minimized. Therefore, when the data signal of the same gray level is supplied to the sixth pixel PX6 and the seventh pixel PX7 adjacent to each other, the brightness deviation between the adjacent sixth pixel PX6 and the seventh pixel PX7 can be reduced or minimized, so that the image quality of the display device 10 can be improved.

[0246] Fig.28 is a plan view of a display device according to one or more embodiments, and Fig.29 is along Fig.28 A cross-sectional view taken along line XI-XI'.

[0247] Fig.28 and Fig.29 The display device 10 (see, for example, Figure 1 and Figure 2 )and Figure 20 to Figure 25The display device of FIG. 1 is different in heights of the first to twelfth signal transmitting lines STL1 to STL12 in the third direction DR3 , and the following description will mainly focus on this difference.

[0248] like Fig.28 and Fig.29 As shown in , the signal transmission lines of the first group GRP1 may include the first signal transmission line STL1 to the sixth signal transmission line STL6. Here, the first data line DL1 of the first signal transmission line STL1 may be connected to the drain electrode D of the second transistor T2_1 through one connection electrode CNE, the second data line DL2 of the second signal transmission line STL2 may be connected to the drain electrode D of the second transistor T2_2 through three connection electrodes CNE, the third data line DL3 of the third signal transmission line STL3 may be connected to the drain electrode D of the second transistor T2_3 through five connection electrodes CNE, the fourth data line DL4 of the fourth signal transmission line STL4 may be connected to the drain electrode D of the second transistor T2_4 through four connection electrodes CNE, the fifth data line DL5 of the fifth signal transmission line STL5 may be connected to the drain electrode D of the second transistor T2_5 through two connection electrodes CNE, and the sixth data line DL6 of the sixth signal transmission line STL6 may be directly connected to the drain electrode D of the second transistor T2_6.

[0249] like Fig.28 and Fig.29 As shown in , the signal transmission lines of the second group GRP2 may include the seventh signal transmission line STL7 to the twelfth signal transmission line STL12. Here, the seventh data line DL7 of the seventh signal transmission line STL7 may be connected to the drain electrode D of the second transistor T2_7 through one connection electrode CNE, the eighth data line DL8 of the eighth signal transmission line STL8 may be connected to the drain electrode D of the second transistor T2_8 through three connection electrodes CNE, the ninth data line DL9 of the ninth signal transmission line STL9 may be connected to the drain electrode D of the second transistor T2_9 through five connection electrodes CNE, the tenth data line DL10 of the tenth signal transmission line STL10 may be connected to the drain electrode D of the second transistor T2_10 through four connection electrodes CNE, the eleventh data line DL11 of the eleventh signal transmission line STL11 may be connected to the drain electrode D of the second transistor T2_11 through two connection electrodes CNE, and the twelfth data line DL12 of the twelfth signal transmission line STL12 may be directly connected to the drain electrode D of the second transistor T2_12.

[0250] like Fig.29 As shown in , the height difference between the sixth signal transmission line STL6 of the first group GRP1 and the seventh signal transmission line STL7 of the second group GRP2 adjacent to the first group GRP1 can be reduced. Fig.29As shown in , the deviation between the distance from the sixth signal transmission line STL6 to the drain electrode D of the second transistor T2_6 and the distance from the seventh signal transmission line STL7 to the drain electrode D of the second transistor T2_7 can be reduced or minimized. Therefore, the deviation between the voltage drop of the data signal supplied to the sixth pixel PX6 through the sixth signal transmission line STL6 and the voltage drop of the data signal supplied to the seventh pixel PX7 through the seventh signal transmission line STL7 can be reduced or minimized. Therefore, when the data signal of the same gray level is supplied to the sixth pixel PX6 and the seventh pixel PX7 adjacent to each other, the brightness deviation between the adjacent sixth pixel PX6 and the seventh pixel PX7 can be reduced or minimized, so that the image quality of the display device 10 can be improved.

[0251] Fig.30 is a plan view of a first capacitor layer CL1 and a third signal transmitting line STL3 of a display device according to one or more embodiments, Fig.31 is a plan view of a second capacitor layer CL2 of a display device according to one or more embodiments, Fig.32 It is used to explain Fig.30 The third data line DL3 is connected to Fig.31 FIG. 1 is a diagram of the overlapping relationship between the second capacitor layer CL2, Fig.33 is along Fig.30 and Fig.31 A sectional view taken along line XII-XII' of Fig.34 yes Fig.30 Detailed configuration diagram of the first capacitor layer CL1.

[0252] like Figure 30 to Figure 34 As shown in , the third pixel PX3 may include a second transistor T2_3, a first capacitor layer CL1, and a second capacitor layer CL2. Here, Figure 30 to Figure 32 The third pixel PX3 may correspond to, for example, the aforementioned Figure 7 In some embodiments, Fig.30 The third signal transmission line STL3 may correspond to the aforementioned Figure 7 The third signal transmission line STL3.

[0253] The first capacitor layer CL1 can provide the above Figure 5 The first capacitor C1. Fig.30 As shown in , the first capacitor layer CL1 may be arranged adjacent to the third data line DL3 of the third signal transfer line STL3. Fig.33As shown in , the first capacitor layer CL1 may be arranged on the same layer as the third signal transmission line STL3 (eg, at the same layer as the third signal transmission line STL3). For example, the first capacitor layer CL1 and the third data line DL3 of the third signal transmission line STL3 may be arranged on the third insulating layer VA3.

[0254] like Fig.34 As shown in , the first capacitor layer CL1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2 arranged on the same layer (e.g., at the same layer). The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be arranged to face each other. A fourth insulating layer VA4 may be arranged between the first capacitor electrode CPE1 and the second capacitor electrode CPE2.

[0255] The first capacitor electrode CPE1 may include a first electrode EE1 extending in the second direction DR2 and a plurality of second electrodes EE2 extending from the first electrode EE1 in the first direction DR1 .

[0256] The second capacitor electrode CPE2 may include a third electrode EE3 extending in the second direction DR2 and a plurality of fourth electrodes EE4 extending from the third electrode EE3 in a direction opposite to the first direction DR1. The first capacitor C1 may be formed between the second electrode EE2 of the first capacitor electrode CPE1 and the fourth electrode EE4 of the second capacitor electrode CPE2.

[0257] The third data line DL3 of the third signal transmitting line STL3 may be connected to the drain electrode D of the second transistor T2_3 through the 3-1st connection electrode CNE3-1 on the first insulating layer VA1 and the 3-2nd connection electrode CNE3-2 on the second insulating layer VA2.

[0258] The second capacitor layer CL2 can provide the above Figure 5 The second capacitor C2. Fig.31 As shown in , the second capacitor layer CL2 may have an area larger than that of the first capacitor layer CL1. In some embodiments, as Fig.33 As shown in , the second capacitor layer CL2 may be arranged on a layer higher than the first capacitor layer CL1 and the third signal transmission line STL3. For example, the second capacitor layer CL2 may be arranged on the fourth insulating layer VA4. Here, since the third data line DL3 of the third signal transmission line STL3 and the second capacitor layer CL2 are arranged on different layers, the second capacitor layer CL2 may have an area larger than that of the first capacitor layer CL1.

[0259] like Fig.32 As shown in FIG. 1 , the second capacitor layer CL2 may overlap the third data line DL3 in the third direction DR3 .

[0260] For example, the second capacitor layer CL2 may have Fig.34 For example, the second capacitor layer CL2 may include a first capacitor electrode and a second capacitor electrode that are arranged to face each other on (eg, at) the same layer.

[0261] Fig.35 is a display device 10 according to one or more embodiments (for example, see Figure 1 and Figure 2 ) is a plan view of the first capacitor layer CL1, Fig.36 is a plan view of a second capacitor layer CL2 and a fourth signal transmitting line STL4 of a display device according to one or more embodiments, Fig.37 It is used to explain Fig.36 The fourth data line DL4 is connected to Fig.35 A diagram of the overlapping relationship between the first capacitor layer CL1, and Fig.38 is along Fig.35 , Fig.36 and Fig.37 A cross-sectional view taken along line XIII-XIII'.

[0262] like Figures 35 to 38 As depicted in FIG. 1 , the fourth pixel PX4 may include a second transistor T2_4, a first capacitor layer CL1, and a second capacitor layer CL2. Here, Figure 35 to Figure 37 The fourth pixel PX4 may correspond to, for example, the above-mentioned Figure 7 In some embodiments, Fig.36 The fourth signal transmission line STL4 may correspond to the above Figure 7 The fourth signal transmission line STL4.

[0263] The first capacitor layer CL1 can provide the above Figure 5 In some embodiments, as Fig.37 As shown in FIG. 1 , the first capacitor layer CL1 may overlap the fourth data line DL4 in the third direction DR3. The first capacitor layer CL1 may have the same Fig.34 The first capacitor layer CL1 has the same shape and structure.

[0264] The second capacitor layer CL2 can provide the above Figure 5 The second capacitor C2. Fig.36 As shown in , the second capacitor layer CL2 may be arranged adjacent to the fourth data line DL4 of the fourth signal transfer line STL4. Fig.38As shown in , the second capacitor layer CL2 may be arranged on the same layer as the fourth signal transmission line STL4 (e.g., at the same layer as the fourth signal transmission line STL4). For example, the second capacitor layer CL2 and the fourth data line DL4 of the fourth signal transmission line STL4 may be arranged on the fourth insulating layer VA4 (e.g., at the same layer). The second capacitor layer CL2 may have the same Fig.34 The first capacitor layer CL1 has the same shape and structure. Fig.38 As shown in , the second capacitor layer CL2 may be arranged on a layer higher than the first capacitor layer CL1 and may be at the same layer as the fourth signal transmission line STL4. For example, the second capacitor layer CL2 may be arranged on the fourth insulating layer VA4. Here, since the fourth data line DL4 of the fourth signal transmission line STL4 and the first capacitor layer CL1 are arranged on different layers, the first capacitor layer CL1 may have an area larger than that of the second capacitor layer CL2.

[0265] The fourth data line DL4 of the fourth signal transmitting line STL4 may be connected to the drain electrode D of the second transistor T2_4 through a 4-1th connection electrode CNE4-1 on the first insulating layer VA1, a 4-2nd connection electrode CNE4-2 on the second insulating layer VA2, and a 4-3rd connection electrode CNE4-3 on the third insulating layer VA3.

[0266] Fig.39 is a plan view of a display device according to one or more embodiments.

[0267] like Fig.39 As shown in FIG. 3 , the third signal transmitting line STL3 may be disposed at an edge of the third pixel PX3 . For example, the third data line DL3 of the third signal transmitting line STL3 may be disposed at an edge of the third pixel PX3 .

[0268] Here, Fig.39 The third pixel PX3 may correspond to, for example, the above-mentioned Figure 7 In some embodiments, Fig.39 The third signal transmission line STL3 may correspond to the above Figure 7 The third signal transmission line STL3.

[0269] Fig.40 is a plan view of a display device according to one or more embodiments.

[0270] like Fig.40 As shown in , the fourth signal transmitting line STL4 may be disposed at the center of the fourth pixel PX4. In other words, the fourth data line DL4 of the fourth signal transmitting line STL4 may be disposed at the center of the fourth pixel PX4.

[0271] Here, Fig.40 The fourth pixel PX4 may correspond to, for example, the above-mentioned Figure 7 In some embodiments, Fig.40 The fourth signal transmission line STL4 may correspond to the above Figure 7 The fourth signal transmission line STL4.

[0272] like Fig.39 and Fig.40 As shown in , corresponding data lines among a plurality of signal transmission lines may be arranged at different portions of corresponding pixels.

[0273] Fig.41 is a plan view of a display device according to one or more embodiments.

[0274] like Fig.41 As shown in , the unit pixel UPX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be configured to emit light of different colors. For example, the first pixel PX1 may be configured to emit red light, the second pixel PX2 may be configured to emit green light, and the third pixel PX3 may be configured to emit blue light.

[0275] The first signal transmission line STL1 may be connected to the first pixel PX1. For example, the first data line DL1 of the first signal transmission line STL1 may be connected to the second transistor T2 (eg, see FIG. 1 ) provided in the first pixel PX1. Figure 5 )'s drain electrode D.

[0276] The second signal transmission line STL2 may be connected to the second pixel PX2. For example, the second data line DL2 of the second signal transmission line STL2 may be connected to the second transistor T2 (eg, see FIG. 1 ) provided in the second pixel PX2. Figure 5 )'s drain electrode D.

[0277] The third signal transmission line STL3 may be connected to the third pixel PX3. For example, the third data line DL3 of the third signal transmission line STL3 may be connected to the second transistor T2 (eg, see FIG. 1 ) provided in the third pixel PX3. Figure 5 )'s drain electrode D.

[0278] The first data line DL1 of the first signal transmission line STL1, the second data line DL2 of the second signal transmission line STL2, and the third data line DL3 of the third signal transmission line STL3 may be arranged adjacent to one edge of the unit pixel UPX. Here, at least one of the first to third data lines DL1 to DL3 may overlap the third pixel PX3. For example, the first data line DL1 and the second data line DL2 may overlap the third pixel PX3 in the third direction DR3.

[0279] In one or more embodiments, the first, second, and third signal transmitting lines STL1, STL2, and STL3 may be arranged on different layers.

[0280] Fig.42 1 is a diagram showing a display area DAA (eg, corresponding to Figures 1 to 4 Layout view of pixels in the display area DA).

[0281] Reference Fig.42 Each of the plurality of unit pixels UPX includes a first pixel PX1 (eg, see Fig.41 ) of the emission area, the first emission area EA1, as the second pixel PX2 (for example, see Fig.41 ) of the emission area and the second emission area EA2 as the third pixel PX3 (for example, see Fig.41 )'s third emission area EA3.

[0282] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, or a rhombus in a plan view. For example, the first emission area EA1 may have a rectangular shape with a short side in the first direction DR1 and a long side in the second direction DR2 in a plan view. In some embodiments, each of the second emission area EA2 and the third emission area EA3 may have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2 in a plan view.

[0283] The length of the first emission area EA1 in the first direction DR1 may be smaller than the length of the second emission area EA2 in the first direction DR1 and may be smaller than the length of the third emission area EA3 in the first direction DR1. The length of the second emission area EA2 in the first direction DR1 and the length of the third emission area EA3 in the first direction DR1 may be substantially the same.

[0284] The length of the first emission region EA1 in the second direction DR2 may be greater than the sum of the length of the second emission region EA2 in the second direction DR2 and the length of the third emission region EA3 in the second direction DR2. The length of the second emission region EA2 in the second direction DR2 may be greater than the length of the third emission region EA3 in the second direction DR2.

[0285] Although in Fig.42, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 is shown to have a rectangular shape in a plan view, but the present disclosure is not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape, a circular shape, or an elliptical shape in addition to a quadrilateral shape in a plan view.

[0286] In each of the plurality of unit pixels UPX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In some embodiments, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different.

[0287] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third pixel PX3 may emit light of a third color. Here, the light of the first color may be light of a blue wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 370nm to about 460nm, the green wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 480nm to about 560nm, and the red wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 600nm to about 750nm.

[0288] Although in Fig.42 , each of the plurality of unit pixels UPX includes three emission areas (eg, a first emission area EA1, a second emission area EA2, and a third emission area EA3), but the present disclosure is not limited thereto. For example, each of the plurality of unit pixels UPX may include four emission areas.

[0289] In some embodiments, the layout of the emission regions of the plurality of unit pixels UPX is not limited to Fig.42 For example, the emission regions of the plurality of unit pixels UPX may be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, or in a diamond shape. structure, or a hexagonal structure in which emission areas having a hexagonal shape in a plan view are arranged side by side. The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). It is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0290] Fig.43 is a perspective view showing a head mounted display device 1000 according to one or more embodiments. Fig.44 It is shown Fig.43 1 is an exploded perspective view of an example of a head mounted display device 1000.

[0291] Reference Fig.43 and Fig.44 According to one or more embodiments, a head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0292] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 42 The display devices 10 described are substantially the same, and thus a description of the first display device 10_1 and the second display device 10_2 will not be provided.

[0293] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0294] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0295] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into a digital video data signal DATA (eg, see Figure 4 ), and transmits the digital video data signal DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0296] The control circuit board 1600 may be used to transmit a digital video data signal DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may be used to transmit a digital video data signal DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. In some embodiments, the control circuit board 1600 may be used to transmit the same digital video data signal DATA to the first display device 10_1 and the second display device 10_2.

[0297] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector therein. The housing cover 1200 is arranged to cover one open side of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is arranged and a second eyepiece 1220 at which the user's right eye is arranged. Although in Fig.43 and Fig.44 2 and 3. It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately arranged, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0298] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0299] The headband 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be kept in a state where they are placed on the left eye and the right eye of the user, respectively. When the display device housing 1100 is implemented to be lightweight and compact, the head mounted display device 1000 can provide a user-friendly display device. Fig.45 The eyeglass frame shown in FIG. 1 is used to replace the headband 1300.

[0300] In some embodiments, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0301] Fig.45 is a perspective view showing a head mounted display device 1000_1 according to one or more embodiments.

[0302] Reference Fig.45 According to one or more embodiments, the head mounted display device 1000_1 may be a glasses type or glasses-like display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. According to one or more embodiments, the head mounted display device 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0303] The display device housing 1200_1 may be used to accommodate therein the display device 10_3, the optical member 1060, and the optical path conversion member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060, and may be provided to the right eye of the user through the right eye lens 1020 after its optical path is converted by the optical path conversion member 1070. As a result, the user may observe an augmented reality image in which the virtual image displayed on the display device 10_3 and the real image viewed through the right eye lens 1020 are combined through the right eye.

[0304] Although in Fig.45 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be arranged at the left end of the support frame 1030, in which case the image of the display device 10_3 may be provided to the left eye of the user. In some embodiments, the display device housing 1200_1 may be arranged at both the left and right ends of the support frame 1030 (e.g., simultaneously), in which case the user may observe the image displayed on the display device 10_3 through both the left eye and the right eye (e.g., simultaneously).

[0305] It will be understood by those skilled in the art to which the present disclosure belongs that the present disclosure may be implemented in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the example embodiments described above are illustrative rather than restrictive in all aspects. It should be understood that the scope of the present disclosure is defined by the claims and their equivalents, rather than by the detailed description described above, and that all modifications and changes derived from the claims and their equivalents fall within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate having a display area and a non-display area; signal transmission lines including a signal line in the display area of ​​the substrate and a fan-out line extending from the signal line and in the non-display area of ​​the substrate; as well as a plurality of pixels, the plurality of pixels being in the display area of ​​the substrate, wherein a plurality of signal transmission lines include the signal transmission line and are respectively connected to the plurality of pixels, and Wherein, the plurality of signal transmission lines are on different layers on the substrate.

2. The display device according to claim 1, wherein: The plurality of signal transmission lines overlap in the non-display area.

3. The display device according to claim 2, wherein: A plurality of fan-out lines of the plurality of signal transmission lines overlap in the non-display area and include the fan-out lines.

4. The display device according to claim 3, wherein: When the longest fan-out line among the plurality of fan-out lines of the plurality of signal transmission lines is a reference fan-out line, an overlapping area between the reference fan-out line and each of the plurality of fan-out lines other than the reference fan-out line is different.

5. The display device according to claim 1, wherein: The plurality of signal transmission lines do not overlap in the display area.

6. The display device according to claim 5, wherein: A plurality of signal lines of the plurality of signal transmission lines do not overlap in the display area and include the signal line.

7. The display device according to claim 1, wherein: A plurality of fan-out lines of the plurality of signal transmission lines have different lengths and include the fan-out lines.

8. The display device according to claim 1, wherein: The plurality of signal transmission lines are subsequently on a higher layer as they are arranged one to another in one direction.

9. The display device according to claim 1, further comprising: A connection electrode through which each of at least some of the plurality of signal transmission lines is connected to a corresponding pixel among the plurality of pixels.

10. The display device according to claim 9, wherein: The plurality of signal transmission lines have different lengths, and wherein a plurality of signal lines of the plurality of signal transmission lines are connected to the plurality of pixels through a smaller number of the connection electrodes as they have a greater length, and the plurality of signal lines include the signal line.

11. The display device according to claim 9, wherein: The plurality of signal transmission lines are connected to the plurality of pixels through a greater number of the connection electrodes as they are subsequently on a higher layer.

12. The display device according to claim 9, wherein: Each of at least some of the plurality of signal lines of the plurality of signal transmission lines is connected to a corresponding transistor of the plurality of transistors of the plurality of pixels through the connection electrode and includes the signal line.

13. The display device according to claim 1, wherein: The plurality of signal transmission lines are signal transmission lines of a first group, and Wherein, the display device further includes: A second group of signal transmission lines is adjacent to the first group of signal transmission lines and includes a plurality of other signal transmission lines that do not overlap with the first group of signal transmission lines.

14. The display device according to claim 13, wherein: Two signal transmission lines that are in different groups of signal transmission lines and are positioned adjacent to each other are at the same layer.

15. The display device according to claim 13, wherein: The signal transmission lines of the first group are subsequently on a higher layer as they are arranged one to another in one direction, and wherein the signal transmission lines of the second group are subsequently on a lower layer as they are arranged with each other along the one direction.

16. The display device according to claim 1, further comprising: a plurality of first capacitor layers, wherein the plurality of first capacitor layers are respectively in the plurality of pixels; as well as A plurality of second capacitor layers are respectively disposed on the plurality of first capacitor layers.

17. The display device according to claim 16, wherein: At least one of the plurality of signal transmission lines is at the same layer as at least one capacitor layer selected from among the plurality of first capacitor layers and the plurality of second capacitor layers.

18. The display device according to claim 17, wherein: The capacitor layer on a layer different from the at least one signal transmission line has a larger area than the capacitor layer at the same layer as the at least one signal transmission line.

19. The display device according to claim 17, wherein: A capacitor layer on a different layer from the at least one signal transmission line overlaps the at least one signal transmission line in the display area.

20. The display device according to claim 19, wherein: A capacitor layer on a layer different from the at least one signal transmission line overlaps a signal line of the at least one signal transmission line in the display area.

21. The display device according to claim 1, wherein: At least one signal transmission line among the plurality of signal transmission lines overlaps an edge of at least one pixel.

22. The display device according to claim 1, wherein: At least one signal transmission line among the plurality of signal transmission lines overlaps with a center of at least one pixel.

23. The display device according to claim 1, wherein: One unit pixel includes two or more pixels among the plurality of pixels, and Among them, the plurality of signal transmission lines respectively connected to the pixels of the one unit pixel are at the edge of the unit pixel.

24. The display device according to claim 1, further comprising: a display driver, the display driver being in the non-display area of ​​the substrate, Wherein, the plurality of signal transmission lines are connected to the display driver in the non-display area.

Images