Display device

Abstract

The invention provides a display device. The display device includes: a light emitting element layer disposed on a substrate, in which a plurality of emission regions are defined on the light emitting element layer; an encapsulation layer disposed on the light emitting element layer; the touch sensing layer is arranged on the encapsulation layer, and the touch sensing layer comprises a plurality of touch electrodes; a reflection reducing layer disposed on the touch sensing layer; and a window disposed on the reflection reducing layer. The reflection reduction layer includes: a color filter layer disposed on the touch sensing layer; a bank layer disposed on the touch sensing layer between the color filter layers; a light blocking layer disposed on the bank layer; and a low refractive layer disposed on the color filter layer and disposed between the light blocking layers.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device. Background Art

[0002] With the development of information society, more and more demands are put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of light-emitting display devices include organic light-emitting display devices including organic light-emitting elements, inorganic light-emitting display devices including inorganic light-emitting elements (such as inorganic semiconductors), and micro light-emitting display devices including micro light-emitting elements.

[0004] The organic light emitting element may include two opposing electrodes and a light emitting layer interposed therebetween. The light emitting layer receives electrons and holes from the two electrodes and recombines them to generate excitons, and the generated excitons change from an excited state to a ground state, thereby emitting light.

[0005] Organic light-emitting display devices including organic light-emitting elements have attracted attention as the next generation of display devices because they can meet high display quality requirements such as a wide viewing angle, high brightness and contrast, and a fast response speed, and can be manufactured with low power consumption, light weight, and thinness by not including undesirable power sources (such as a backlight unit). Summary of the invention

[0006] An embodiment of the present disclosure provides a display device including a color filter disposed on a light emitting element and capable of reducing reflection of external light and improving light emitting efficiency.

[0007] However, the embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to an embodiment of the present disclosure, a display device includes: a light emitting element layer, which is arranged on a substrate, wherein a plurality of emission areas are defined on the light emitting element layer; an encapsulation layer, which is arranged on the light emitting element layer; a touch sensing layer, which is arranged on the encapsulation layer, wherein the touch sensing layer includes a plurality of touch electrodes; a reflection reducing layer, which is arranged on the touch sensing layer; and a window, which is arranged on the reflection reducing layer, wherein the reflection reducing layer includes: a color filter layer, which is arranged on the touch sensing layer; a dam layer, which is arranged on the touch sensing layer between the color filter layers; a light blocking layer, which is arranged on the dam layer; and a low refractive layer, which is arranged on the color filter layer and between the light blocking layers.

[0009] In an embodiment, the refractive index of the low-refractive layer may be lower than the refractive index of the window.

[0010] In an embodiment, the difference between the refractive index of the low-refractive layer and the refractive index of the window is 0.1 or more.

[0011] In an embodiment, the low-refractive layer may include a resin and hollow particles dispersed in the resin.

[0012] In an embodiment, a top surface of the low-refractive layer and a top surface of the light blocking layer may collectively define a continuous top surface of the reflection reducing layer.

[0013] In an embodiment, the light blocking layer may define a plurality of holes respectively overlapping the plurality of emission regions, and an area of ​​each of the plurality of holes is greater than an area of ​​a corresponding one of the plurality of emission regions.

[0014] In an embodiment, the bank layer and the color filter layer may be disposed in the same layer as each other, and the color filter layer may include a plurality of color filters.

[0015] In an embodiment, the bank layer may have a lateral side overlapping the plurality of emission regions, the lateral side having a taper angle in a range of 30 degrees to 90 degrees.

[0016] In an embodiment, the refractive index of the bank layer may be less than that of the color filter layer.

[0017] In an embodiment, the light emitting element layer may include: a pixel electrode disposed on a substrate; a pixel defining layer covering an edge of the pixel electrode and defining a plurality of emission areas; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer, and a light blocking layer and a dam layer overlap with the pixel defining layer.

[0018] In an embodiment, the low-refractive layer may cover the light blocking layer and be in contact with a top surface of the light blocking layer.

[0019] According to an embodiment of the present disclosure, a display device includes: a light emitting element layer, which is arranged on a substrate, wherein a plurality of emission areas are defined on the light emitting element layer; an encapsulation layer, which is arranged on the light emitting element layer; a touch sensing layer, which is arranged on the encapsulation layer, wherein the touch sensing layer includes a plurality of touch electrodes; a reflection reduction layer, which is arranged on the touch sensing layer; and a window, which is arranged on the reflection reduction layer, wherein the reflection reduction layer includes: a color filter layer, which is arranged on the touch sensing layer; a first light blocking layer, which is arranged on the color filter layer, wherein a plurality of holes are defined through the first light blocking layer to overlap with the plurality of emission areas respectively; and a low refractive layer, which is arranged on the color filter layer and is arranged between the first light blocking layers.

[0020] In an embodiment, the plurality of emission regions may include a first emission region, a second emission region, and a third emission region, and the color filter layer includes a first color filter overlapping the first emission region, a second color filter overlapping the second emission region, and a third color filter overlapping the third emission region, wherein the first color filter transmits red light, the second color filter transmits blue light, and the third color filter transmits green light.

[0021] In an embodiment, the color filter layer may include a color pattern disposed between the first color filter and the first light blocking layer, and the color pattern may be a blue color filter that transmits blue light.

[0022] In an embodiment, the color pattern may overlap with the first light blocking layer and may not overlap with the plurality of emission regions.

[0023] In an embodiment, the display device may further include a second light blocking layer disposed on the touch sensing layer and disposed between the first color filter and the second color filter, between the second color filter and the third color filter, and between the third color filter and the first color filter.

[0024] In an embodiment, the second light blocking layer may overlap with the first light blocking layer and may not overlap with the plurality of emission regions.

[0025] According to an embodiment of the present disclosure, a display device includes: a light emitting element layer, which is arranged on a substrate, wherein a plurality of emission areas are defined on the light emitting element layer; an encapsulation layer, which is arranged on the light emitting element layer; a touch sensing layer, which is arranged on the encapsulation layer, wherein the touch sensing layer includes a plurality of touch electrodes; a reflection reduction layer, which is arranged on the touch sensing layer; and a window, which is arranged on the reflection reduction layer, wherein the reflection reduction layer includes: a color filter layer, which is arranged on the touch sensing layer, wherein the color filter layer includes a first color filter, a second color filter, and a third color filter which are spaced apart from each other; a light blocking layer, which is arranged on the touch sensing layer between the first color filter to the third color filter, wherein a plurality of holes are defined through the light blocking layer to overlap with the plurality of emission areas respectively; a color pattern, which is arranged on the light blocking layer and does not overlap with the plurality of holes; and a low refractive layer, which is arranged on the first color filter to the third color filter and is arranged between the color patterns.

[0026] In an embodiment, the plurality of emission regions may include a first emission region, a second emission region, and a third emission region, the first color filter may overlap with the first emission region and transmit red light, the second color filter may overlap with the second emission region and transmit blue light, and the third color filter may overlap with the third emission region and transmit green light.

[0027] In an embodiment, the color pattern may be a red color filter that transmits red light.

[0028] In the display device according to the embodiment of the present disclosure, a bank layer may be formed between color filters to change the path of light emitted from the light emitting element layer upward, thereby improving light emitting efficiency.

[0029] In this embodiment of the display device, a low refractive layer is formed between the light blocking layers to change the path of external light incident from the outside so that the external light can be absorbed by the light blocking layers. Therefore, reflection of the external light can be reduced.

[0030] However, the effects according to the embodiments of the present disclosure are not limited to the embodiments illustrated above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic plan view of an electronic device according to an embodiment;

[0033] Figure 2 is a perspective view showing a foldable display device in a folded state according to an embodiment;

[0034] Figure 3 It is shown Figure 2 A three-dimensional image of a foldable display device in an unfolded state;

[0035] Figure 4 is a perspective view showing a display device included in an electronic device according to an embodiment;

[0036] Figure 5 Observed from the side Figure 4 A cross-sectional view of a display device;

[0037] Figure 6 is a plan view showing a display layer of a display device according to an embodiment;

[0038] Figure 7 is a plan view showing a touch sensing layer of a display device according to an embodiment;

[0039] Figure 8 is a plan view showing the arrangement of emission areas in a first display area of ​​a display device according to an embodiment;

[0040] Fig. 9 It shows that the setting Figure 8 a plan view of an arrangement of color filters in a first display area;

[0041] Fig.10 It is along Figure 8 A cross-sectional view taken along line XX';

[0042] Fig.11 is a schematic cross-sectional view of a low-refractive layer according to an embodiment;

[0043] Fig.12 is a cross-sectional view schematically showing a reflection reducing layer according to an embodiment;

[0044] Fig.13 is a cross-sectional view schematically showing a light blocking layer, a low refractive layer, and a window according to an embodiment;

[0045] Fig.14 is a cross-sectional view schematically showing a display device according to another embodiment;

[0046] Fig.15 is a cross-sectional view schematically showing a display device according to yet another embodiment;

[0047] Fig.16 is a cross-sectional view schematically showing a display device according to yet another embodiment;

[0048] Fig.17 is a cross-sectional view schematically showing a display device according to yet another embodiment;

[0049] Fig.18 is a diagram showing an optical path of external light incident on a display device; and

[0050] Fig.19 is a diagram illustrating an emission path of internal light of a display device according to an embodiment. DETAILED DESCRIPTION

[0051] The present invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0052] It will also be understood that when a layer is referred to as being 'on' another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. The same reference numerals refer to the same components throughout the specification.

[0053] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of this article, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0054] The terms used herein are only used for the purpose of describing a particular embodiment and are not intended to be limited. As used herein, "one", "a kind of", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Therefore, the mention of "said" element after the mention of "one" element in the claim includes one element and multiple elements. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as a restrictive "one" or "a kind". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It will also be understood that the term "comprising" and / or "comprising" or "comprising" and / or "comprising" when used in this specification, indicates the existence of the stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0055] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top", may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientations depicted in the drawings. For example, if the device in one of the drawings is flipped, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, the term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the drawings. Similarly, if the device in one of the drawings is flipped, the element described as being "below" or "below" the other elements will then be oriented "above" the other elements. Therefore, the term "below" or "below" can include both above and below orientations.

[0056] Each of the features of the various embodiments of the present disclosure can be combined or combined with each other in part or in whole, and various interlocks and drives in technology are possible. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0057] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0059] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be interpreted as being limited to regions of a particular shape as shown herein, but should include shape deviations, for example, caused by manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims set forth.

[0060] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0061] Figure 1 is a schematic plan view of an electronic device according to an embodiment.

[0062] refer to Figure 1 , the electronic device 1 according to the embodiment displays a moving image or a still image. The electronic device 1 may refer to any electronic device that provides a display screen. Examples of the electronic device 1 may include a television that provides a display screen, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a camcorder, etc.

[0063] In an embodiment, the electronic device 1 may include a display device 10 (in Figure 4 ). Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. Hereinafter, for the convenience of description, an embodiment in which an organic light emitting diode display device is used as the display device 10 will be described in detail, but the present disclosure is not limited thereto, and other display devices may be applied within the same scope of the technical spirit.

[0064] The shape of the electronic device 1 may be modified in various ways. In the embodiment, for example, the electronic device 1 may have a shape such as a rectangular shape elongated in the horizontal direction, a rectangular shape elongated in the vertical direction, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, and a circular shape in a plan view. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 An embodiment of the electronic device 1 having a rectangular shape elongated in the second direction DR2 is shown.

[0065] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where an image can be displayed, and the non-display area NDA is an area where an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0066] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas in which components for adding various functions to the electronic device 1 are disposed, and the second display area DA2 and the third display area DA3 may correspond to component areas.

[0067] Figure 2 is a perspective view showing a foldable display device in a folded state according to an embodiment. Figure 3 It is shown Figure 2 A three-dimensional image of a foldable display device in an unfolded state.

[0068] refer to Figure 2 and Figure 3 , the electronic device 1 according to the embodiment may be a foldable display device. The foldable electronic device 1 may be folded around a folding axis FL. The display area DA may be defined outside and / or inside (ie, the outer surface and the inner surface) of the foldable electronic device 1. In an embodiment, Figure 2 and Figure 3 The foldable electronic device 1 shows that a display area DA is defined on each of an outer portion and an inner portion.

[0069] The display area DA may be defined outside the electronic device 1. An outer surface of the folded electronic device 1 may include the display area DA, and an inner surface of the unfolded electronic device 1 may include the display area DA. Figure 3In the foldable electronic device 1, the display area DA may include a first display area DA1 occupying most of the display area DA, and a second display area DA2 and a third display area DA3 occupying an area relatively smaller than the first display area DA1. The first display area DA1 may include a first display portion DA1L and a second display portion DA1R positioned on both sides of the folding axis FL. Each of the second display area DA2 and the third display area DA3 may be disposed in an area in which the second display portion DA1R is positioned, but is not limited thereto. In another embodiment, each of the second display area DA2 and the third display area DA3 may be disposed in an area in which the first display portion DA1L is positioned, or one of the second display area DA2 and the third display area DA3 may be disposed in an area in which the first display portion DA1L is positioned, and the other may also be disposed in an area in which the second display portion DA1R is positioned.

[0070] In an embodiment, Figures 1 to 3 As shown in , each of the second display area DA2 and the third display area DA3 may have a smaller area than the first display area DA1. The second display area DA2 and the third display area DA3 may have different sizes or areas, but are not limited thereto. In the accompanying drawings, an embodiment in which the second display area DA2 has a smaller area than the third display area DA3 is shown as an example. Each of the second display area DA2 and the third display area DA3 may be surrounded by the first display area DA1. However, the present disclosure is not limited thereto.

[0071] Figure 4 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0072] refer to Figure 4 , the electronic device 1 according to the embodiment may include a display device 10. The display device 10 may provide a screen of the electronic device 1. The display device 10 may have a planar shape similar to that of the electronic device 1. In an embodiment, for example, the display device 10 may have a shape similar to a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 in a plan view. Here, a third direction DR3 perpendicular to a plane defined by the first direction DR1 and the second direction DR2 may be a thickness direction of the display device 10. The edge where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a curvature, but is not limited thereto, and may be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0073] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0074] The display panel 100 may include a main area MA and a sub area SBA.

[0075] The main area MA may include a display area DA and a non-display area NDA disposed around the display area DA, the display area DA including pixels for displaying an image. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas thereof. In an embodiment, for example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0076] In an embodiment, for example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0077] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) supplying a gate signal to a gate line, and a fan-out line (not shown) connecting the display driver 200 to the display area DA.

[0078] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or rolled up. In an embodiment, for example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (third direction DR3). The display driver 200 and the pad portion connected to the circuit board 300 may be provided in the sub-region SBA. In another embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0079] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may provide a data voltage to a data line. The display driver 200 may provide a power supply voltage to a power supply line, and may provide a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. In an embodiment, for example, the display driver 200 may be disposed in a sub-region SBA, and may overlap with the main region MA in a thickness direction by bending of the sub-region SBA. In another embodiment, for example, the display driver 200 may be mounted on a circuit board 300.

[0080] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0081] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may provide a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense the amount of change in capacitance between the plurality of touch electrodes. In an embodiment, for example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate whether an input and input coordinates are made based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed of or defined by an IC.

[0082] Figure 5 Observed from the side Figure 4 A cross-sectional view of a display device.

[0083] refer to Figure 5 The display panel 100 according to the embodiment may include a display layer DU, a touch sensing layer TSU and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML and an encapsulation layer TFEL.

[0084] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. In an embodiment, for example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0085] A thin film transistor layer TFTL may be provided on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 to the data line, and a lead connecting the display driver 200 to the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an embodiment, for example, when a gate driver is formed on one side of a non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0086] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, gate line, data line, and power line of each pixel of the thin film transistor layer TFTL may be disposed in the display area DA. The gate control line and fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0087] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer defining pixels, each of the plurality of light emitting elements including a first electrode, a second electrode, and a light emitting layer emitting light. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0088] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be transferred to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0089] In another embodiment, the light emitting element may include a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

[0090] The encapsulation layer TFEL may cover the top surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0091] The touch sensing layer TSU may be disposed on the encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes that sense a user's touch in a capacitive manner and a touch line that connects the plurality of touch electrodes to the touch driver 400. In an embodiment, for example, the touch sensing layer TSU may sense a user's touch by using a mutual capacitance method or a self capacitance method.

[0092] In another embodiment, the touch sensing layer TSU may be provided on a separate substrate provided on the display layer DU. In such an embodiment, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display layer DU.

[0093] A plurality of touch electrodes of the touch sensing layer TSU may be disposed in a touch sensor region overlapping the display area DA. A touch line of the touch sensing layer TSU may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0094] The color filter layer CFL may be disposed on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0095] Since the color filter layer CFL is directly disposed on the touch sensing layer TSU, the display device 10 may not include a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0096] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may emit or receive light in infrared, ultraviolet, and visible light bands. In an embodiment, for example, the optical device 500 may be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, or an image sensor.

[0097] Figure 6 is a plan view showing a display layer of a display device according to an embodiment.

[0098] refer to Figure 6 , the display layer DU according to the embodiment may include a display area DA and a non-display area NDA.

[0099] In an embodiment, the display area DA may be disposed at a central portion of the display panel 100. A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit emitting light.

[0100] The plurality of gate lines GL may provide the plurality of pixels PX with gate signals received from the gate driver 210. The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 intersecting the first direction DR1.

[0101] The plurality of data lines DL may provide the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0102] The plurality of power lines VL may provide the plurality of pixels PX with a power voltage received from the display driver 200. Here, the power voltage may be at least one selected from a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The plurality of power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0103] The non-display area NDA may surround the display area DA. The gate driver 210, the fan-out line FOL, and the gate control line GCL may be disposed in the non-display area NDA. The gate driver 210 may generate a plurality of gate signals based on the gate control signal, and may sequentially provide the plurality of gate signals to the plurality of gate lines GL according to a set order.

[0104] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0105] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may provide the gate driver 210 with a gate control signal received from the display driver 200.

[0106] The sub-area SBA may include an area in which the display driver 200 is disposed, a pad area PA, and first and second touch pad areas TPA1 and TPA2.

[0107] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may provide a data voltage to the data line DL through the fan-out line FOL. The data voltage may be provided to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driver 200 may provide a gate control signal to the gate driver 210 through the gate control line GCL.

[0108] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at the edge of the sub-area SBA and may be electrically connected to the circuit board 300 by using a material such as a self-assembled anisotropic conductive paste (SAP) or an anisotropic conductive film.

[0109] A plurality of display pad portions DP may be provided in the pad area PA. The plurality of display pad portions DP may be connected to a graphics system through the circuit board 300. The plurality of display pad portions DP may be connected to the circuit board 300 to receive digital video data, and may provide the digital video data to the display driver 200.

[0110] Figure 7 is a plan view showing a touch sensing layer of a display device according to an embodiment.

[0111] refer to Figure 7 In an embodiment, the touch sensing layer TSU may include a touch sensor area TSA for sensing a user's touch and a touch peripheral area TOA disposed around the touch sensor area TSA. The touch sensor area TSA may be disposed in the display area DA of the display device 10, and the touch peripheral area TOA may be disposed in the non-display area NDA of the display device 10.

[0112] The touch sensor area TSA may include a plurality of touch electrodes SEN and a plurality of dummy electrodes DME. The plurality of touch electrodes SEN may form mutual capacitance or self capacitance to sense the touch of an object or a person. The plurality of touch electrodes SEN may include a plurality of driving electrodes TE and a plurality of sensing electrodes RE.

[0113] A plurality of driving electrodes TE may be arranged in the first direction DR1 and the second direction DR2. The plurality of driving electrodes TE may be spaced apart from each other in the first direction DR1 and the second direction DR2. Adjacent driving electrodes TE in the second direction DR2 may be electrically connected by a bridge electrode CE.

[0114] A plurality of driving electrodes TE may be connected to the first touch pad unit TP1 through a driving line TL. The driving line TL may include a lower driving line TLa and an upper driving line TLb. In an embodiment, for example, the driving electrode TE disposed on the lower side of the touch sensor area TSA may be connected to the first touch pad unit TP1 through the lower driving line TLa, and the driving electrode TE disposed on the upper side of the touch sensor area TSA may be connected to the first touch pad unit TP1 through the upper driving line TLb. The lower driving line TLa may extend to the first touch pad unit TP1 through the lower side of the touch peripheral area TOA. The upper driving line TLb may extend to the first touch pad unit TP1 through the upper side, the left side, and the lower side of the touch peripheral area TOA. The first touch pad unit TP1 may be connected to the touch driver 400 through the circuit board 300.

[0115] The bridging electrode CE may be bent at least once. In an embodiment, for example, the bridging electrode CE may have a shape similar to an angle bracket (e.g., a shape of a less than symbol or a greater than symbol (i.e., "<" or ">")), but the planar shape of the bridging electrode CE is not limited thereto. The driving electrodes TE adjacent to each other in the second direction DR2 (Y-axis direction) may be connected by a plurality of bridging electrodes CE, and although any one of the bridging electrodes CE is disconnected, the driving electrode TE may be stably connected by the remaining bridging electrodes CE. The driving electrodes TE adjacent to each other may be connected by two bridging electrodes CE, but the number of bridging electrodes CE is not limited thereto.

[0116] The bridging electrode CE may be disposed in a layer different from the plurality of driving electrodes TE and the plurality of sensing electrodes RE (or directly on a layer different from the plurality of driving electrodes TE and the plurality of sensing electrodes RE). The sensing electrodes RE adjacent to each other in the first direction DR1 may be electrically connected by a connection portion disposed on the same layer as the plurality of driving electrodes TE or the plurality of sensing electrodes RE, and the driving electrodes TE adjacent to each other in the second direction DR2 may be electrically connected by a bridging electrode CE disposed in a layer different from the plurality of driving electrodes TE or the plurality of sensing electrodes RE (or directly on a layer different from the plurality of driving electrodes TE or the plurality of sensing electrodes RE). Therefore, although the bridging electrode CE overlaps with the plurality of sensing electrodes RE in the Z-axis direction, the plurality of driving electrodes TE and the plurality of sensing electrodes RE may be insulated from each other. Mutual capacitance may be formed between the driving electrodes TE and the sensing electrodes RE.

[0117] The plurality of sensing electrodes RE may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The plurality of sensing electrodes RE may be arranged in the first direction DR1 and the second direction DR2, and sensing electrodes RE adjacent in the first direction DR1 may be electrically connected through a connection portion.

[0118] A plurality of sensing electrodes RE may be connected to the second touch pad unit TP2 through a sensing line RL. In an embodiment, for example, a sensing electrode RE disposed on the right side of the touch sensor area TSA may be connected to the second touch pad unit TP2 through a sensing line RL. The sensing line RL may extend to the second touch pad unit TP2 through the right side and the lower side of the touch peripheral area TOA. The second touch pad unit TP2 may be connected to the touch driver 400 through the circuit board 300.

[0119] Each of the plurality of dummy electrodes DME may be surrounded by the driving electrode TE or the sensing electrode RE. Each of the dummy electrodes DME may be insulated by being spaced apart from the driving electrode TE or the sensing electrode RE. Therefore, the dummy electrode DME may be electrically floating.

[0120] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at the edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 by using a low-resistance, high-reliability material such as a self-assembled anisotropic conductive paste (SAP) or an anisotropic conductive film.

[0121] The first touch pad area TPA1 may be disposed at one side of the pad area PA and may include a plurality of first touch pad units TP1. The plurality of first touch pad units TP1 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The plurality of first touch pad units TP1 may provide touch driving signals to the plurality of driving electrodes TE through the plurality of driving lines TL.

[0122] The second touch pad area TPA2 may be disposed at the other side of the pad area PA, and may include a plurality of second touch pad units TP2. The plurality of second touch pad units TP2 may be electrically connected to a touch driver 400 disposed on the circuit board 300. The touch driver 400 may receive a touch sensing signal through a plurality of sensing lines RL connected to the plurality of second touch pad units TP2, and may sense a change in mutual capacitance between the driving electrode TE and the sensing electrode RE.

[0123] In another embodiment, the touch driver 400 may provide a touch drive signal to each of the plurality of drive electrodes TE and the plurality of sensing electrodes RE, and may receive a touch sensing signal from each of the plurality of drive electrodes TE and the plurality of sensing electrodes RE. The touch driver 400 may sense the charge change amount of each of the plurality of drive electrodes TE and the plurality of sensing electrodes RE based on the touch sensing signal.

[0124] Figure 8is a plan view showing the arrangement of emission areas in a first display area of ​​a display device according to an embodiment. Fig. 9 It shows that the setting Figure 8 FIG. 1 is a plan view of an arrangement of color filters in a first display area.

[0125] refer to Figure 8 and Fig. 9 , the display device 10 according to the embodiment may include a plurality of pixels PX1 , PX2 , and PX3 disposed in a display area DA and emission areas EA1 , EA2 , EA3 , and EA4 disposed in each of the pixels PX1 , PX2 , and PX3 . Figure 8 and Fig. 9 The display area DA shown in the figure is the first display area DA1, and a plurality of pixels PX1, PX2 and PX3 and emission areas EA1, EA2 and EA3 may be provided in the first display area DA1. In this embodiment, a plurality of pixels PX1, PX2 and PX3 and emission areas EA1, EA2, EA3 and EA4 may also be provided in the second display area DA2 and the third display area DA3 of the display area DA.

[0126] The plurality of pixels PX1, PX2, and PX3 may be arranged in a fourth direction DR4 and a fifth direction DR5, which are between the first direction DR1 and the second direction DR2. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be alternately arranged along the fourth direction DR4 and the fifth direction DR5. In an embodiment, for example, the second pixel PX2 and the third pixel PX3 may be arranged in the fourth direction DR4 and the fifth direction DR5 relative to the first pixel PX1. The plurality of pixels PX1, PX2, and PX3 may be arranged in the display area DA. Type, for example, diamond However, the arrangement or disposition of the pixels PX1, PX2, and PX3 is not limited to Figure 5 and Figure 6 In some embodiments, the plurality of pixels PX1, PX2 and PX3 may also be arranged in a linear or island pattern.

[0127] The emission areas EA1, EA2, EA3, and EA4 of each of the pixels PX1, PX2, and PX3 may include a first emission area EA1, a second emission area EA2, a third emission area EA3, and a fourth emission area EA4 that emit light of different colors. Unlike the first emission area EA1 and the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may emit light having the same color. Each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may emit red light, blue light, or green light, and the color of the light emitted from each of the emission areas EA1, EA2, EA3, and EA4 may be determined according to the light emitting element layer EML to be described later. Fig.10 In the embodiment, the first emission area EA1 may emit a red first light, the second emission area EA2 may emit a blue second light, and the third emission area EA3 and the fourth emission area EA4 may emit a green third light. However, the present disclosure is not limited thereto.

[0128] Multiple emission areas EA1, EA2, EA3 and EA4 can be set as Type, for example, diamond Type. In an embodiment, for example, in each of the pixels PX1, PX2, and PX3, the first emission area EA1 and the second emission area EA2 may be disposed to be spaced apart from each other in the first direction DR1, and the third emission area EA3 and the fourth emission area EA4 may be disposed to be spaced apart from each other in the second direction DR2. The first emission area EA1 may be disposed to be spaced apart from the third emission area EA3 in the fifth direction DR5, and may be disposed to be spaced apart from the fourth emission area EA4 in the fourth direction DR4. The second emission area EA2 may be disposed to be spaced apart from the third emission area EA3 in the fourth direction DR4, and may be disposed to be spaced apart from the fourth emission area EA4 in the fifth direction DR5.

[0129] In the plurality of pixels PX1, PX2, and PX3, the plurality of first emission areas EA1, the second emission areas EA2, the third emission areas EA3, and the fourth emission areas EA4 may be alternately arranged in the fourth direction DR4 or the fifth direction DR5. In an embodiment, for example, the plurality of emission areas EA1, EA2, EA3, and EA4 may be arranged in rows R1, R2, R3, and R4 arranged along the fourth direction DR4, and may be arranged in columns C1, C2, C3, and C4 arranged along the fifth direction DR5. In the first row R1 and the third row R3, the second emission area EA2 and the third emission area EA3 may be alternately arranged along the fourth direction DR4. In the second row R2 and the fourth row R4, the first emission area EA1 and the fourth emission area EA4 may be alternately arranged along the fourth direction DR4. In the first column C1 and the third column C3, the second emission area EA2 and the fourth emission area EA4 may be alternately arranged along the fifth direction DR5. In the second column C2 and the fourth column C4, the first emission areas EA1 and the third emission areas EA3 may be alternately disposed along the fifth direction DR5.

[0130] Alternatively, the plurality of emission areas EA1, EA2, EA3, and EA4 may be arranged along the first direction DR1 or the second direction DR2. The first emission area EA1 and the second emission area EA2 may be alternately disposed along the first direction DR1 and the second direction DR2. The third emission area EA3 and the fourth emission area EA4 may be alternately disposed along the first direction DR1 and the second direction DR2.

[0131] Each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may be formed of a pixel defining layer PDL (see Fig.10 ) is defined by a plurality of openings OPE1, OPE2, OPE3 and OPE4 in the pixel defining layer PDL. In an embodiment, for example, a first emission area EA1 may be defined by a first opening OPE1 of the pixel defining layer PDL, a second emission area EA2 may be defined by a second opening OPE2 of the pixel defining layer PDL, a third emission area EA3 may be defined by a third opening OPE3 of the pixel defining layer PDL, and a fourth emission area EA4 may be defined by a fourth opening OPE4 of the pixel defining layer PDL.

[0132] In an embodiment, the areas or sizes of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may be different from each other. Figure 8As shown in , the area of ​​the second emission area EA2 may be greater than the areas of the first emission area EA1, the third emission area EA3, and the fourth emission area EA4, and the area of ​​the first emission area EA1 may be greater than the areas of the third emission area EA3 and the fourth emission area EA4. The areas of the emission areas EA1, EA2, EA3, and EA4 may vary according to the sizes of the openings OPE1, OPE2, OPE3, and OPE4 formed in the pixel defining layer PDL. The intensity of light emitted from the corresponding emission areas EA1, EA2, EA3, and EA4 may vary according to the areas of the emission areas EA1, EA2, EA3, and EA4, and the areas of the emission areas EA1, EA2, EA3, and EA4 may be adjusted to control the color of the screen displayed on the display device 10 or the electronic device 1. In an embodiment, as Figure 8 As shown in the figure, the second emission area EA2 having the largest area is shown, but it is not limited thereto. The areas of the emission areas EA1, EA2, EA3, and EA4 can be freely adjusted or variously modified based on the color of the screen desired by the display device 10 and the electronic device 1. In addition, the areas of the emission areas EA1, EA2, EA3, and EA4 can be related to the light efficiency and life of the light-emitting element ED, and can have a trade-off relationship with the reflection of external light. The areas of the emission areas EA1, EA2, EA3, and EA4 can be adjusted in consideration of the above factors.

[0133] Each of the plurality of pixels PX1, PX2, and PX3 may include a first emission region EA1, a second emission region EA2, a third emission region EA3, and a fourth emission region EA4 disposed adjacent to each other to characterize a white grayscale. However, the present disclosure is not limited thereto, and the combination of the emission regions EA1, EA2, EA3, and EA4 constituting one pixel group PXG may be variously modified according to the arrangement of the emission regions EA1, EA2, EA3, and EA4, the color of light emitted from the emission regions EA1, EA2, EA3, and EA4, and the like.

[0134] The display device 10 may include a plurality of color filters CF1, CF2, CF3, and CF4 disposed in the emission areas EA1, EA2, EA3, and EA4. The plurality of color filters CF1, CF2, CF3, and CF4 may be disposed to correspond to the emission areas EA1, EA2, EA3, and EA4, respectively. In an embodiment, for example, the color filters CF1, CF2, CF3, and CF4 may be disposed in a light blocking layer BM including a plurality of holes OPT1, OPT2, OPT3, and OPT4 (see Fig.10), the holes OPT1, OPT2, OPT3 and OPT4 are arranged to correspond to the emission areas EA1, EA2, EA3 and EA4 or the openings OPE1, OPE2, OPE3 and OPE4. The holes OPT1, OPT2, OPT3 and OPT4 of the light blocking layer BM can be defined or formed to overlap with the openings OPE1, OPE2, OPE3 and OPE4, and a light exit area can be formed, and the light emitted from the emission areas EA1, EA2, EA3 and EA4 exits from the light exit area. Each of the color filters CF1, CF2, CF3 and CF4 can have an area larger than the openings OPE1, OPE2, OPE3 and OPE4 and the holes OPT1, OPT2, OPT3 and OPT4 of the light blocking layer BM, and each of the color filters CF1, CF2, CF3 and CF4 can completely cover the light exit area formed by the holes OPT1, OPT2, OPT3 and OPT4.

[0135] The color filters CF1, CF2, CF3, and CF4 may include a first color filter CF1, a second color filter CF2, a third color filter CF3, and a fourth color filter CF4 that are respectively arranged to correspond to different emission areas EA1, EA2, EA3, and EA4. The color filters CF1, CF2, CF3, and CF4 may include a colorant such as a dye or a pigment that absorbs light of a wavelength band other than a specific wavelength band, and may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, EA3, and EA4. In an embodiment, for example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and transmits only a red first light. The second color filter CF2 may be a blue color filter that is arranged to overlap with the second emission area EA2 and transmits only a blue second light, the third color filter CF3 may be a green color filter that is arranged to overlap with the third emission area EA3 and transmits only a green third light, and the fourth color filter CF4 may be a green color filter that is arranged to overlap with the fourth emission area EA4.

[0136] Similar to the arrangement of the emission areas EA1, EA2, EA3, and EA4, the color filters CF1, CF2, CF3, and CF4 may be arranged as follows: Type, for example, diamond Type. In an embodiment, for example, in a plurality of pixels PX1, PX2, and PX3, a plurality of first color filters CF1, a second color filter CF2, a third color filter CF3, and a fourth color filter CF4 may be alternately arranged in a fourth direction DR4 or a fifth direction DR5. For example, a plurality of color filters CF1, CF2, CF3, and CF4 may be arranged in rows R1, R2, R3, and R4 arranged along the fourth direction DR4, and may be arranged in columns C1, C2, C3, and C4 arranged along the fifth direction DR5. In the first row R1 and the third row R3, the second color filter CF2 and the third color filter CF3 may be alternately arranged along the fourth direction DR4. In the second row R2 and the fourth row R4, the first color filter CF1 and the fourth color filter CF4 may be alternately arranged along the fourth direction DR4. In the first column C1 and the third column C3, the second color filter CF2 and the fourth color filter CF4 may be alternately arranged along the fifth direction DR5. In the second column C2 and the fourth column C4 , the first color filters CF1 and the third color filters CF3 may be alternately disposed along the fourth direction DR4 .

[0137] According to an embodiment, the plurality of color filters CF1 , CF2 , CF3 , and CF4 may be disposed to partially overlap other adjacent color filters CF1 , CF2 , CF3 , and CF4 . Fig. 9 An embodiment is shown in which adjacent color filters CF1, CF2, CF3 and CF4 are arranged to be adjacent to each other, but as will be described later, adjacent color filters CF1, CF2, CF3 and CF4 may partially overlap at the boundaries where adjacent color filters CF1, CF2, CF3 and CF4 are adjacent to each other. Fig. 9 The arrangement of the color filters CF1, CF2, CF3, and CF4 as viewed from above (that is, when viewed in the third direction DR3) is shown, and it will be understood that, among the color filters CF1, CF2, CF3, and CF4 overlapping each other, the edges of the color filters CF1, CF2, CF3, and CF4 arranged below are covered by the color filters CF1, CF2, CF3, and CF4 arranged above the edges. The different color filters CF1, CF2, CF3, and CF4 are areas that do not overlap with the emission areas EA1, EA2, EA3, and EA4, and may overlap each other on the light blocking layer BM described later.

[0138] In the display device 10 according to the embodiment, the color filters CF1, CF2, CF3 and CF4 are arranged to overlap each other, so that the intensity of the reflected light caused by the external light can be reduced. In such an embodiment, the color of the reflected light caused by the external light can be controlled by adjusting the arrangement, shape and area of ​​the color filters CF1, CF2, CF3 and CF4 in a plan view.

[0139] In an embodiment, Figure 8As shown in FIG. 1 , the touch electrode TL may be disposed between the emission areas EA1, EA2, EA3, and EA4. The touch electrode TL may be disposed to extend in the fourth direction DR4 and the fifth direction DR5, and may be spaced apart from the emission areas EA1, EA2, EA3, and EA4 without overlapping the emission areas EA1, EA2, EA3, and EA4. The touch electrode TL may be disposed to extend in the fourth direction DR4 and the fifth direction DR5. Fig.10 The pixel defining layer PDL defining openings OPE1, OPE2, OPE3 and OPE4 and the light blocking layer BM provided with a plurality of holes OPT1, OPT2, OPT3 and OPT4 to be described later (see Fig.10 ) overlap. Figure 8 The touch electrode TL is briefly shown in FIG. 1 , but the touch electrode TL may be any Figure 7 driving electrode TE or sensing electrode RE.

[0140] In an embodiment, as will be described later, the diameter of the openings OPE1, OPE2, OPE3, and OPE4 defining the emission areas EA1, EA2, EA3, and EA4 may be smaller than the diameter of the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM. The opening width between the openings OPE1, OPE2, OPE3, and OPE4 and the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM may be defined for each of the emission areas EA1, EA2, EA3, and EA4. The opening width may also be defined as the diameter difference between the openings OPE1, OPE2, OPE3, and OPE4 of the pixel defining layer PDL and the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM. In the display device 10 according to the embodiment, the same emission areas EA1, EA2, EA3, and EA4 of different pixels PX1, PX2, and PX3 may have different opening widths between the openings OPE1, OPE2, OPE3, and OPE4 and the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM. In the first pixel PX1, the second pixel PX2, and the third pixel PX3, the emission areas EA1, EA2, EA3, and EA4 may emit light of the same color as each other, but in each of them, the opening widths between the openings OPE1, OPE2, OPE3, and OPE4 and the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM may be different from each other.

[0141] In an embodiment, for example, each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission area EA1 for emitting red light, but in the pixels PX1, PX2, and PX3, the opening widths of the first emission area EA1 may be different from each other. In an embodiment, in the first pixel PX1, the second pixel PX2, and the third pixel PX3, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may also emit light of the same color, but may have opening widths different from each other. In addition, also in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may have opening widths different from each other.

[0142] In the display device 10 according to the embodiment, among the emission areas EA1, EA2, EA3, and EA4 in which the opening widths between the openings OPE1, OPE2, OPE3, and OPE4 and the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM are different from each other, the specific emission areas EA1, EA2, EA3, and EA4 may have at least three. The display device 10 may have three or more types of uniform openings or uniform emission areas with different opening widths from each other. In the embodiment, for example, in the first pixel PX1, the second pixel PX2, and the third pixel PX3, the opening widths of the first emission area EA1 may be different from each other. In the embodiment, in the display area DA of the display device 10, three first emission areas EA1 having different opening widths from each other may be provided, and the three first emission areas EA1 may be provided in the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively. In the case of the second emission area EA2, the third emission area EA3, and the fourth emission area EA4, this may be the same.

[0143] In an embodiment, the display device 10 may include a pixel group PXG in which three first pixels PX1, second pixels PX2, and third pixels PX3 including emission areas that are the same emission areas EA1, EA2, EA3, and EA4 but have different opening widths are arranged in a specific arrangement. In the display area DA of the display device 10, a plurality of pixel groups PXG may be arranged in the first direction DR1 and the second direction DR2, or in the fourth direction DR4 and the fifth direction DR5, and the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in a specific arrangement in one pixel group PXG. Fig. 9The pixel group PXG in the pixel group PXG may have a structure in which the second pixel PX2 and the third pixel PX3 are arranged in the fourth direction DR4 and the fifth direction DR5 relative to the first pixel PX1 arranged at both ends of the first direction DR1. However, the arrangement of the different pixels PX1, PX2 and PX3 in the pixel group PXG is not limited thereto. The arrangement of the different pixels PX1, PX2 and PX3 may be related to the arrangement of the plurality of emission areas EA1, EA2, EA3 and EA4 having opening widths different from each other. A detailed description thereof will be given later.

[0144] Fig.10 It is along Figure 8 A cross-sectional view taken along line XX'. Fig.11 is a schematic cross-sectional view of a low-refractive layer according to an embodiment. Fig.12 is a cross-sectional view schematically showing a reflection reducing layer according to an embodiment. Fig.13 is a cross-sectional view schematically showing a light blocking layer, a low refractive layer and a window according to an embodiment. Here, Fig.10 A cross section spanning the first emission area EA1 , the third emission area EA3 , and the second emission area EA2 is shown.

[0145] Apart from Figure 8 and Fig. 9 In addition, reference will be made to Figures 10 to 13 A cross-sectional structure of the display device 10 is described.

[0146] The display panel 100 of the display device 10 according to the embodiment may include a display layer DU, a touch sensing layer TSU, a reflection reduction layer (or anti-reflection layer) RPL and a window WD. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML and an encapsulation layer TFEL. The display panel 100 may include a reflection reduction layer RPL disposed on the touch sensing layer TSU. The reflection reduction layer RPL may include a bank layer BNL, a light blocking layer BM, a color filter layer CF and a low refractive layer LRL.

[0147] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. In an embodiment, for example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In another embodiment, for example, the substrate SUB may include a glass material or a metal material.

[0148] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0149] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing air or moisture from penetrating. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0150] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or a multilayer including at least one selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), tantalum (Ta), and copper (Cu), or an alloy thereof or made thereof.

[0151] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing air or moisture from penetrating. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0152] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. In an embodiment, for example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0153] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made into a conductor to form a source electrode SE and a drain electrode DE.

[0154] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0155] The gate insulating layer GI may be disposed on the semiconductor layer ACT. In an embodiment, for example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI may be provided with a contact hole through which the first connection electrode CNE1 extends.

[0156] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may be provided with a contact hole through which the first connection electrode CNE1 extends. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0157] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0158] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may be provided with a contact hole through which the first connection electrode CNE1 extends. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0159] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole disposed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0160] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may be provided with a contact hole through which the second connection electrode CNE2 extends.

[0161] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrode AE ​​of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0162] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include a contact hole through which the pixel electrode AE ​​of the light emitting element ED passes.

[0163] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include a pixel electrode AE, a light emitting layer EL, and a common electrode CE.

[0164] The pixel electrode AE ​​may be disposed on the second passivation layer PAS2. The pixel electrode AE ​​may be disposed to overlap a corresponding one of the openings OPE1, OPE2, OPE3, and OPE4 of the pixel defining layer PDL. The pixel electrode AE ​​may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0165] The light emitting layer EL may be disposed on the pixel electrode AE. For example, the light emitting layer EL may be an organic light emitting layer including or made of an organic material, but is not limited thereto. In an embodiment using an organic light emitting layer as the light emitting layer EL, the thin film transistor TFT applies a predetermined voltage to the pixel electrode AE ​​of the light emitting element ED, and if the common electrode CE of the light emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the light emitting layer EL through the hole transport layer and the electron transport layer and recombine to generate light emitted by the light emitting layer EL.

[0166] The common electrode CE may be arranged on the light emitting layer EL. In an embodiment, for example, the common electrode CE may be arranged in the form of an electrode common to all pixels rather than to each specific electrode in the pixel. The common electrode CE may be arranged on the light emitting layer EL in the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4, and may be arranged on the pixel defining layer PDL in an area other than the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4.

[0167] The common electrode CE may receive a common voltage or a low potential voltage. When the pixel electrode AE ​​receives a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrode AE ​​and the common electrode CE, so that the light emitting layer EL may emit light.

[0168] The pixel defining layer PDL may define a plurality of openings OPE1, OPE2, OPE3, and OPE4, and may be disposed on the second passivation layer PAS2 and a portion of the pixel electrode AE. The pixel defining layer PDL may define a first opening OPE1, a second opening OPE2, a third opening OPE3, and a fourth opening OPE4, and each of the openings OPE1, OPE2, OPE3, and OPE4 may expose a portion of the pixel electrode AE. In an embodiment, as described above, each of the openings OPE1, OPE2, OPE3, and OPE4 of the pixel defining layer PDL may define a first emission area EA1, a second emission area EA2, a third emission area EA3, and a fourth emission area EA4, and the areas or sizes of the openings OPE1, OPE2, OPE3, and OPE4 may be different from each other. The pixel defining layer PDL may separate and insulate the pixel electrode AE ​​of each of the plurality of light emitting elements ED.

[0169] The pixel defining layer PDL may include a light absorbing material to prevent light reflection. In an embodiment, for example, the pixel defining layer PDL may include a polyimide (PI)-based adhesive and a pigment in which red, green, and blue are mixed. Alternatively, the pixel defining layer PDL may include a mixture of lactam black pigment and blue pigment and a cardo-based adhesive resin. Alternatively, the pixel defining layer PDL may include carbon black.

[0170] The encapsulation layer TFEL may be disposed on the common electrode CE to cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The encapsulation layer TFEL may include at least one organic layer to protect the light emitting element layer EML from impurities such as dust.

[0171] In an embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0172] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0173] The second encapsulation layer TFE2 may include a polymer-based material. Examples of polymer-based materials may include acrylic resin, epoxy resin, polyimide, polyethylene, or the like. In an embodiment, for example, the second encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate, polyacrylic acid, or the like. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0174] The touch sensing layer TSU may be disposed on the encapsulation layer TFEL. The touch sensing layer TSU may include a touch insulating layer SIL, a touch electrode TL, and an overcoat layer OC.

[0175] The touch insulating layer SIL may be disposed on the encapsulation layer TFEL. The touch insulating layer SIL may have insulating and optical functions. The touch insulating layer SIL may include at least one inorganic layer or an organic layer. Alternatively, the touch insulating layer SIL may be omitted. Another layer of the touch electrode TL may also be disposed on the touch insulating layer SIL.

[0176] A portion of the touch electrode TL may be disposed on the touch insulating layer SIL. Each of the touch electrodes TL may not overlap with the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4. Each of the touch electrodes TL may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), tantalum (Ta), aluminum (Al), or indium tin oxide (ITO), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0177] The overcoat layer OC may cover the touch electrode TL and the touch insulating layer SIL. The overcoat layer OC may have insulating and optical functions. In addition, the overcoat layer OC may have a function of flattening the lower step. The overcoat layer OC may include an organic material, and may include, for example, polyimide (PI).

[0178] The reflection reduction layer RPL may be disposed on the touch sensing layer TSU. The reflection reduction layer RPL may include a bank layer BNL, a color filter layer CF, a light blocking layer BM, and a low refractive layer LRL. The display device 10 according to the embodiment may include a reflection reduction layer RPL implemented using a bank layer BNL, a color filter layer CF, a light blocking layer BM, and a low refractive layer LRL. Therefore, a conventional polarizing layer attached to the display layer DU via a separate bonding member such as a pressure sensitive adhesive (PSA) or an optically clear adhesive (OCA) may be omitted.

[0179] In an embodiment, a bank layer BNL may be disposed on the overcoat layer OC of the touch sensing layer TSU. The bank layer BNL defines a plurality of holes arranged to overlap the emission areas EA1, EA2, EA3, and EA4 so as not to reduce transmittance of light emitted through the emission areas EA1, EA2, EA3, and EA4.

[0180] In an embodiment, the bank layer BNL may be used to allow light emitted from the light emitting element layer EML to propagate to the outside without being absorbed by the light blocking layer BM above. The lateral side of the bank layer BNL overlapping each of the emission areas EA1, EA2, and EA3 may have a predetermined taper angle. In an embodiment, the bank layer BNL may have a taper angle in the range of 30° to 90° so that the light emitted from the light emitting element layer EML is refracted. In this case, if the taper angle of the bank layer BNL is 30° or greater, the light emitted from the light emitting element layer EML may be refracted upward, and thus the light emitting efficiency may be improved. In addition, if the taper angle of the bank layer BNL is 90° or less, the light emitted from the light emitting element layer EML may be prevented from propagating upward. Reference will be made later. Fig.11 Refraction and upward emission of light at the bank layer BNL are described in detail The bank layer BNL may include a transparent organic material such as polyimide (PI) or acrylic resin.

[0181] The color filters CF1, CF2, CF3 and CF4 of the color filter layer CF may be arranged on the bank layer BNL and the outer coating layer OC. In an embodiment, for example, the color filter layer CF may be arranged in the same layer as the bank layer BNL (or directly on the bank layer BNL). Different color filters CF1, CF2, CF3 and CF4 may be arranged to correspond to different emission areas EA1, EA2, EA3 and EA4, respectively. In an embodiment, for example, the first color filter CF1 may be arranged to correspond to the first emission area EA1, the second color filter CF2 may be arranged to correspond to the second emission area EA2, and the third color filter CF3 may be arranged to correspond to the third emission area EA3. Although not shown in the drawings, the fourth color filter CF4 may be arranged to correspond to the fourth emission area EA4. In a plan view, the color filters CF1, CF2, CF3 and CF4 may be arranged to have an area larger than the emission areas EA1, EA2, EA3 and EA4, respectively, and some of them may be arranged directly on the bank layer BNL.

[0182] The light blocking layer BM may be disposed on the bank layer BNL and the color filter layer CF. The light blocking layer BM may be disposed to cover the conductive line of the touch electrode TL, and may include a plurality of holes OPT1, OPT2, OPT3, and OPT4 disposed to overlap with the emission areas EA1, EA2, EA3, and EA4. For example, the first hole OPT1 may be disposed to overlap with the first emission area EA1. The second hole OPT2 may be disposed to overlap with the second emission area EA2, and the third hole OPT3 may be disposed to overlap with the third emission area EA3. Although not shown in the drawings, the fourth hole OPT4 may be disposed to overlap with the fourth emission area EA4.

[0183] The area or size of each of the holes OPT1, OPT2, OPT3, and OPT4 may be larger than the area or size of the openings OPE1, OPE2, OPE3, and OPE4 of the pixel defining layer PDL. The holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM are formed to be larger than the openings OPE1, OPE2, OPE3, and OPE4 of the pixel defining layer PDL, so that light emitted from the emission areas EA1, EA2, EA3, and EA4 can be visually recognized by the user not only from the front surface of the display device 10 but also from the side surfaces of the display device 10.

[0184] The light blocking layer BM may include a light absorbing material. In an embodiment, for example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one selected from lactam black, perylene black, and aniline black, but they are not limited thereto. The light blocking layer BM may effectively prevent visible light from penetrating and color mixing between the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4, which improves the color reproducibility of the display device 10.

[0185] The low refractive layer LRL may be disposed on the color filter layer CF and the light blocking layer BM. The low refractive layer LRL is disposed on different color filters CF1, CF2, CF3, and CF4, and may be disposed to correspond to different emission areas EA1, EA2, EA3, and EA4 or holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM. The low refractive layer LRL may be disposed while being filled in the holes OPT1, OPT2, OPT3, and OPT4 of the light blocking layer BM. The low refractive layer LRL may be disposed to be in direct contact with the side surfaces of the color filters CF1, CF2, CF3, and CF4 and the light blocking layer BM. The height of the low refractive layer LRL may be the same as the height of the light blocking layer BM. In an embodiment, for example, the top surface of the low refractive layer LRL may be aligned and overlapped with the top surface of the light blocking layer BM, that is, the top surface of the low refractive layer LRL and the top surface of the light blocking layer BM may jointly define a continuous top surface of the low refractive layer LRL.

[0186] In an embodiment, Fig.11 As shown in , the low refractive layer LRL may include particles PA dispersed in a transparent resin PR.

[0187] The resin PR may include at least one selected from the group consisting of acrylic, polysiloxane, polyurethane, polyurethane acrylate, polyimide, polymethylsilsesquioxane (PMSSQ), and polymethyl methacrylate (PMMA).

[0188] The particles PA may be hollow particles. In an embodiment, for example, the particles PA may include a material selected from silicon dioxide (SiO 2 ), magnesium fluoride (MgF 2 ) and iron oxide (Fe 3 O 4 ). In an embodiment, for example, the particle PA may include a shell and a hollow portion in the shell, wherein the shell includes or is made of at least one selected from the above materials. In an embodiment, the particle PA may have a diameter in the range of 20 nanometers (nm) to 200 nm, and the diameter of the particle PA may determine the thickness of the shell and the diameter of the hollow portion.

[0189] The particles PA may be contained in the low refractive layer LRL at a weight ratio of 10% to 50% to the resin PR. When the weight ratio of the particles PA to the resin PR is 10% or more, the refractive index of the low refractive layer LRL may be reduced. When the weight ratio of the particles PA to the resin PR is 50% or less, the degradation of adhesion with the adjacent layers may be prevented. The low refractive layer LRL may be formed by applying a solution containing a solvent in which the resin PR and the particles PA are dispersed and curing it.

[0190] Return to reference Fig.10, the window WD may be disposed on the reflection reducing layer RPL. The window WD may include a rigid material such as glass or quartz. The window WD may be attached to the reflection reducing layer RPL via an optically transparent adhesive. The window WD may be in direct contact with the low refractive layer LRL and the light blocking layer BM. In an embodiment, for example, the bottom surface of the window WD may be in direct contact with the top surface of the low refractive layer LRL and the top surface of the light blocking layer BM.

[0191] In an embodiment, the reflection reducing layer RPL may change the optical path of incident external light so that the external light may be absorbed by the light blocking layer BM. In such an embodiment, the reflection reducing layer RPL may change the path of light emitted from the light emitting element layer EML so that the light may propagate upward.

[0192] In an embodiment, Fig.12 As shown in FIG. 1 , the bank layer BNL and the color filter CF may have a specific or predetermined refractive index to change the path of light emitted from the light emitting element layer EML. In an embodiment, for example, the refractive index n of the bank layer BNL is 1 It can be smaller than the refractive index n of the color filter CF 2 In an embodiment, the refractive index n of the bank layer BNL is 1 may be about 1.5, and the refractive index n of the color filter CF 2 It may be about 1.6. In this case, due to the difference in refractive index between the bank layer BNL and the color filter CF, the path of light ① emitted from the light emitting element layer EML may be changed at the interface between the bank layer BNL and the color filter CF. In particular, since the side surface of the bank layer BNL is tapered, the light ① may be reflected and emitted toward the window WD.

[0193] In such an embodiment, the low refractive layer LRL may change the path of external light incident through the window WD. In an embodiment, for example, the refractive index n of the low refractive layer LRL is 3 Can be smaller than the refractive index n of the window WD 4 In an embodiment, the refractive index n of the low refractive layer LRL is 3 The refractive index n of the window WD can be compared 4 That is, the refractive index n of the low refractive layer LRL is 3 Can be smaller than the refractive index n of the window WD 4 , and the refractive index of the low refractive layer LRL is n 3 The refractive index n of the window WD 4 The difference between them may be 0.1 or greater. In some embodiments, the refractive index n of the low refractive layer LRL is 3 can be about 1.2, and the refractive index n of the window WD 4It may be about 1.46. In this case, due to the difference in refractive index between the window WD and the low-refractive layer LRL, the path of external light ② incident from the outside may be changed at the interface between the window WD and the low-refractive layer LRL. In particular, the external light ② may be refracted toward the light blocking layer BM, and thus the refracted external light ② may be absorbed by the light blocking layer BM.

[0194] In an embodiment, the height, width, and interval of the light blocking layer BM may be set to absorb external light.

[0195] refer to Fig.13 , the optical filter characteristics of the light blocking layer BM can be adjusted according to the height width and interval To adjust (or based on height width and interval In this case, the optical filter characteristics of the light blocking layer BM may represent the degree of blocking external light (light blocking characteristics) and the degree of emitting light emitted from the inside (light emitting characteristics). As the height of the light blocking layer BM increases, the light blocking property of the external light increases, but the light emitting property of the internal light decreases. In other words, when the height of the light blocking layer BM increases, the light blocking property of the external light increases, but the light emitting property of the internal light decreases. With interval When the ratio of is close to 1, the optical filter characteristics can show the best efficiency. However, when the height of the light blocking layer BM is With interval When the ratio is close to 1, the width of the light blocking layer BM Therefore, it is desirable to set the height of the light blocking layer BM to be different from that of the window WD and the low refractive layer LRL. With interval The ratio is set to be less than 1 to minimize the width of the light blocking layer BM.

[0196] The emission angle θ2 of light to the incident angle θ1 can be expressed by the following formula 1.

[0197] [Formula 1]

[0198]

[0199] Refractive index n of window WD 4 With n in formula 1 1 Correspondingly, the refractive index n of the low refractive layer LRL 3 With n in formula 1 2 Corresponding.

[0200] Height of light blocking layer BM and interval And the emission angle θ2 can be expressed by the following formula 2.

[0201] [Formula 2]

[0202]

[0203] In an embodiment, the refractive index n of the window WD may be 4 and the refractive index n of the low refractive layer LRL 3 , the height of the light blocking layer BM is set by formula 1 and formula 2 With interval , thereby adjusting the external light blocking characteristics and light emitting characteristics of the display device 10.

[0204] As described above, since the display device 10 according to the embodiment includes the reflection reducing layer RPL, it is possible to increase the light emission efficiency of internal light and reduce the reflection of external light, thereby improving display quality.

[0205] Hereinafter, other embodiments of the display device 10 will be described with reference to other drawings.

[0206] Fig.14 is a cross-sectional view schematically showing a display device according to another embodiment.

[0207] refer to Fig.14 , except that the low refractive layer LRL covers the light blocking layer BM, Fig.14 The embodiment is basically the same as above Figures 10 to 13 Therefore, any repeated detailed description of elements that are the same or similar to those of the above-described embodiments will be omitted, and the differences will be focused on.

[0208] In an embodiment, Fig.14 As shown in , the low refractive layer LRL may be disposed on the color filter layer CF and the light blocking layer BM. The low refractive layer LRL may cover the color filter layer CF and the light blocking layer BM. In an embodiment, for example, the low refractive layer LRL may completely cover the color filter layer CF and the light blocking layer BM. In an embodiment, the low refractive layer LRL may be in contact with the side surface and the top surface of the light blocking layer BM. The top surface of the low refractive layer LRL may be disposed to be spaced apart from the top surface of the light blocking layer BM in the thickness direction. When measured from the substrate SUB, the top surface of the low refractive layer LRL may be higher than the top surface of the light blocking layer BM.

[0209] The low refractive layer LRL can be used not only to change the optical path of external light so that the external light is absorbed by the light blocking layer BM, but also to flatten the lower portion so that the window WD is properly bonded. The low refractive layer LRL is arranged to completely cover the light blocking layer BM to have a flat top surface, thereby enhancing the bonding to the window WD.

[0210] Fig.15 is a cross-sectional view schematically showing a display device according to still another embodiment.

[0211] refer to Fig.15 , except that the bank layer BNL is omitted and the color filter CF is used as a light blocking layer, Fig.15 The embodiment is basically the same as above Figures 10 to 14 The same as the embodiment.

[0212] In an embodiment, Fig.15 As shown in , the color filter layer CF may be disposed on the overcoat layer OC. The color filter layer CF may include a first color filter CF1, a second color filter CF2, a third color filter CF3, and a color pattern CF22. Although not shown, the color filter layer CF may further include a fourth color filter CF4.

[0213] The first color filter CF1 may be arranged to correspond to the first emission area EA1, the second color filter CF2 may be arranged to correspond to the second emission area EA2, and the third color filter CF3 may be arranged to correspond to the third emission area EA3. In such an embodiment, the first color filter CF1 may be arranged to correspond to the pixel defining layer PDL of the light emitting element layer EML. The first color filter CF1 may be arranged to overlap with the pixel defining layer PDL. In an embodiment, for example, the first color filter CF1 may be arranged not only in the area corresponding to the first emission area EA1, but also between the second color filter CF2 and the third color filter CF3. That is, the second color filter CF2 may be arranged between the first color filter CF1, and the third color filter CF3 may be arranged between the first color filter CF1.

[0214] In an embodiment, the first color filter CF1 may be arranged to overlap with the light blocking layer BM and overlap with the pixel defining layer PDL. In a plan view, the first color filter CF1 may overlap with the first emission area EA1 and may also overlap with the light blocking layer BM. In an embodiment, for example, in a plan view, the arrangement of the first color filter CF1 may include the arrangement of the light blocking layer BM.

[0215] The color pattern CF22 may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. The color pattern CF22 may be disposed to overlap with the light blocking layer BM without overlapping with the emission areas EA1, EA2, and EA3. The color pattern CF22 may include the same material as the second color filter CF2. In an embodiment, for example, the color pattern CF22 may be a blue color filter that transmits only the blue second light.

[0216] The color pattern CF22 may be arranged to overlap with the first color filter CF1. In an embodiment, for example, the color pattern CF22 may overlap with the first color filter CF1 in an area that does not overlap with the emission areas EA1, EA2, and EA3. In such an embodiment where the first color filter CF1 overlaps with the color pattern CF22, the first color filter CF1 and the color pattern CF22 may act or be used as a light blocking layer BM. In an embodiment, for example, the first color filter CF1 may be a red color filter that transmits only red first light, and the color pattern CF22 may be a blue color filter that transmits only blue second light. In such an embodiment, when light is incident on the color pattern CF22, only the blue second light may be transmitted therethrough, and the blue second light may be incident on the first color filter CF1 to be blocked. In other words, when the first color filter CF1 and the color pattern CF22 overlap each other, they may block light.

[0217] The light blocking layer BM may be disposed on the color pattern CF22. For example, the light blocking layer BM may be in contact with the top surface of the color pattern CF22, and may be disposed to be spaced apart from the color filters CF1, CF2, and CF3. The low refractive layer LRL may be disposed on the color filters CF1, CF2, and CF3, the color pattern CF22, and the light blocking layer BM. The low refractive layer LRL may be disposed to be in contact with each of the color filters CF1, CF2, and CF3, the color pattern CF22, and the light blocking layer BM.

[0218] In an embodiment, the first color filter CF1 and the color pattern CF22 are disposed to overlap each other to function as a light blocking layer to shield light, thereby absorbing light incident from the outside and thus reducing external light reflection characteristics.

[0219] Fig.16 is a cross-sectional view schematically showing a display device according to still another embodiment.

[0220] refer to Fig.16 , except that the first light blocking layer BM1 is included instead of the bank layer BNL, Fig.16 The embodiment is basically the same as above Figures 10 to 14 The same as the embodiment.

[0221] In an embodiment, Fig.16 As shown in , the reflection reducing layer RPL may include a first light blocking layer BM1, color filters CF1, CF2, and CF3, a second light blocking layer BM2, and a low refractive layer LRL.

[0222] The first light blocking layer BM1 may be disposed on the outer coating layer OC of the touch sensing layer TSU. The first light blocking layer BM1 may be disposed to cover the conductive lines of the touch electrodes TL while including a plurality of holes OPT1, OPT2, OPT3, and OPT4 overlapping the emission areas EA1, EA2, and EA3. The first light blocking layer BM1 may be disposed to overlap the pixel defining layer PDL of the light emitting element layer EML, and may be disposed to surround the emission areas EA1, EA2, and EA3.

[0223] The first light blocking layer BM1 may define a first hole OPT1, a second hole OPT2, and a third hole OPT3. The first hole OPT1 may be disposed to overlap the first emission area EA1. The second hole OPT2 may be disposed to overlap the second emission area EA2, and the third hole OPT3 may be disposed to overlap the third emission area EA3.

[0224] The color filters CF1, CF2, and CF3 of the color filter layer CF may be disposed on the first light blocking layer BM1 and the overcoat layer OC. Different color filters CF1, CF2, and CF3 may be disposed to correspond to different emission areas EA1, EA2, and EA3, respectively, and each of the color filters CF1, CF2, and CF3 may be disposed between the first light blocking layers BM1.

[0225] The second light blocking layer BM2 may be disposed on the first light blocking layer BM1 and the color filters CF1, CF2, and CF3. The second light blocking layer BM2 may be disposed to overlap with the first light blocking layer BM1 without overlapping with the plurality of holes OPT1, OPT2, and OPT3. The lateral sides of the second light blocking layer BM2 may be aligned with and coincide with the lateral sides of the first light blocking layer BM1. In an embodiment, for example, in a plan view, the arrangement of the second light blocking layer BM2 may be substantially the same as that of the first light blocking layer BM1.

[0226] In this embodiment, the first light blocking layer BM1 and the second light blocking layer BM2 may be arranged to overlap each other to cover the path of the external light incident after being refracted at the interface of the low refractive layer LRL and the window WD, thereby further improving the external light blocking property and reducing the external light reflection property.

[0227] Fig.17 is a cross-sectional view schematically showing a display device according to still another embodiment.

[0228] refer to Fig.17 , except that the color pattern CF11 is included instead of the second light blocking layer BM2, Fig.17 The embodiment is basically the same as above Fig.16 The same as the embodiment.

[0229] In an embodiment, Fig.17As shown in , the color pattern CF11 may be disposed on the first light blocking layer BM1 and the color filters CF1, CF2, and CF3. The color pattern CF11 may be disposed to overlap with the first light blocking layer BM1 without overlapping with the plurality of holes OPT1, OPT2, and OPT3. The lateral sides of the color pattern CF11 may be aligned and coincide with the lateral sides of the first light blocking layer BM1. For example, the arrangement of the color pattern CF11 may be substantially the same as the arrangement of the first light blocking layer BM1.

[0230] The color pattern CF11 may include the same material as the first color filter CF1. In an embodiment, for example, the color pattern CF11 may be a red color filter that transmits only the red first light. In such an embodiment in which the color pattern CF11 is formed as a red color filter, the phenomenon that the visibility of the external light reflected in the display device 10 is bluish can be prevented. In an embodiment, for example, when the external light is incident and passes through the color pattern CF11, the external light is converted into red light, and the red light is reflected in the display device 10 and emitted to the outside. That is, since the blue light is removed from the wavelength of the light emitted to the outside, and the light is converted into red light instead of being emitted to the outside, the bluish visibility characteristic can be improved.

[0231] Although not shown, the color pattern CF11 may be formed as a blue filter when visibility of external light reflected in the display device 10 is reddish. Also, when visibility of external light reflected in the display device 10 is greenish, the color pattern CF11 may be formed as a blue filter or a red filter.

[0232] In embodiments, as described above, by forming the color pattern CF11 on the first light blocking layer BM1 and the color filters CF1, CF2, and CF3, a phenomenon in which visibility of reflected external light exhibits a specific color may be reduced, thereby improving visibility of reflected external light.

[0233] Fig.18 is a diagram showing an optical path of external light incident on a display device.

[0234] Fig.18 2 shows the results obtained by simulating the incident path of external light when a window and a low-refractive layer are provided according to an embodiment of the present disclosure. Fig.18 , "air" represents the outside of the display device, the area marked with "1.46" represents a window with a refractive index of 1.46, and the area marked with "low refractive index" represents a low refractive layer with a refractive index of 1.2. In addition, the horizontal axis represents the distance in the X-axis (horizontal) direction, and the vertical axis represents the distance in the Z-axis (vertical) direction.

[0235] refer to Fig.18, when external light is incident at an incident angle in the range of 0° to 90°, the external light is refracted due to the difference in refractive index at the interface between the air layer and the window, and is refracted due to the difference in refractive index at the interface between the window and the low-refractive layer. When the incident angle of the external light is 0°, in the low-refractive layer, the moving distance of the path of the external light in the X-axis direction is zero. When the incident angle of the external light is 30°, in the low-refractive layer, the moving distance of the path of the external light in the X-axis direction is about 23μm. When the incident angle of the external light is 60°, in the low-refractive layer, the moving distance of the path of the external light in the X-axis direction is about 52μm.

[0236] As mentioned above Fig.18 As described above, it was confirmed that by forming a low-refractive layer having a lower refractive index than the window, the incident path of external light can be further moved in the X-axis direction, and thus, the external light can be effectively blocked by the light blocking layer.

[0237] Fig.19 is a diagram illustrating an emission path of internal light of a display device according to an embodiment.

[0238] Fig.19 Shown according to Fig.12 The embodiment shown in FIG. 1 is a result obtained by simulating an emission path of internal light emitted from the inside when a color filter CF, a bank layer BNL, and a light blocking layer BM are provided in the display device 10.

[0239] refer to Fig.19 , it can be confirmed that a portion of the internal light emitted from the inside at a certain angle travels to the light blocking layer BM, while another portion thereof is reflected at the interface of the bank layer BNL and the color filter CF and changes the path to the vertical direction.

[0240] As mentioned above Fig.19 As described above, it was confirmed that internal light was emitted upward by providing the bank layer BNL, and thus light emitting efficiency could be improved.

[0241] The present invention should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0242] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, comprising: substrate; A light emitting element layer is disposed on the substrate, wherein a plurality of emission regions are defined on the light emitting element layer; An encapsulation layer, disposed on the light-emitting element layer; A touch sensing layer, disposed on the encapsulation layer, wherein the touch sensing layer includes a plurality of touch electrodes; a reflection reducing layer disposed on the touch sensing layer; and a window disposed on the reflection reducing layer, Wherein, the reflection reducing layer comprises: A color filter layer, disposed on the touch sensing layer; a bank layer disposed on the touch sensing layer between the color filter layers; a light blocking layer disposed on the bank layer; and A low refractive layer is disposed on the color filter layer and between the light blocking layers.

2. The display device according to claim 1, wherein: The refractive index of the low-refractive layer is lower than the refractive index of the window.

3. The display device according to claim 2, wherein: A difference between the refractive index of the low-refractive layer and the refractive index of the window is 0.1 or more.

4. The display device according to claim 1, wherein: The low-refractive layer includes a resin and hollow particles dispersed in the resin.

5. The display device according to claim 1, wherein: A top surface of the low-refractive layer and a top surface of the light blocking layer jointly define a continuous top surface of the reflection reducing layer.

6. The display device according to claim 1, wherein: The light blocking layer defines a plurality of apertures overlapping the plurality of emission regions, and An area of ​​each of the plurality of holes is larger than an area of ​​a corresponding one of the plurality of emission regions.

7. The display device according to claim 1, wherein: The bank layer and the color filter layer are provided in the same layer as each other, and The color filter layer includes a plurality of color filters.

8. The display device according to claim 7, wherein: The bank layer has a lateral side overlapping the plurality of emission regions, the lateral side having a taper angle in a range of 30 degrees to 90 degrees.

9. The display device according to claim 1, wherein: The refractive index of the bank layer is lower than that of the color filter layer.

10. The display device according to claim 1, wherein: The light emitting element layer comprises: A pixel electrode, disposed on the substrate; A pixel defining layer, covering the edge of the pixel electrode and defining the plurality of emission areas; a light-emitting layer, disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer, and The light blocking layer and the bank layer overlap the pixel defining layer.

11. The display device according to claim 1, wherein: The low-refractive layer covers the light blocking layer and contacts a top surface of the light blocking layer.

12. A display device comprising: substrate; A light emitting element layer is disposed on the substrate, wherein a plurality of emission regions are defined on the light emitting element layer; An encapsulation layer, disposed on the light-emitting element layer; A touch sensing layer, disposed on the encapsulation layer, wherein the touch sensing layer includes a plurality of touch electrodes; a reflection reducing layer disposed on the touch sensing layer; and a window disposed on the reflection reducing layer, Wherein, the reflection reducing layer comprises: A color filter layer, disposed on the touch sensing layer; a first light blocking layer disposed on the color filter layer, wherein a plurality of holes are defined through the first light blocking layer to overlap the plurality of emission regions, respectively; and A low refractive layer is disposed on the color filter layer and between the first light blocking layers.

13. The display device according to claim 12, wherein: The plurality of emission areas include a first emission area, a second emission area, and a third emission area, and The color filter layer includes a first color filter overlapping the first emission area, a second color filter overlapping the second emission area, and a third color filter overlapping the third emission area, The first color filter transmits red light, the second color filter transmits blue light, and the third color filter transmits green light.

14. The display device according to claim 13, wherein: The color filter layer includes a color pattern disposed between the first color filter and the first light blocking layer, and The color pattern is a blue color filter that transmits blue light.

15. The display device according to claim 14, wherein: The color pattern overlaps the first light blocking layer and does not overlap the plurality of emission areas.

16. The display device according to claim 13, further comprising: A second light blocking layer is disposed on the touch sensing layer and is disposed between the first color filter and the second color filter, between the second color filter and the third color filter, and between the third color filter and the first color filter.

17. The display device according to claim 16, wherein: The second light blocking layer overlaps the first light blocking layer and does not overlap the plurality of emission regions.

18. A display device comprising: substrate; A light emitting element layer is disposed on the substrate, wherein a plurality of emission regions are defined on the light emitting element layer; An encapsulation layer, disposed on the light-emitting element layer; A touch sensing layer, disposed on the encapsulation layer, wherein the touch sensing layer includes a plurality of touch electrodes; a reflection reducing layer disposed on the touch sensing layer; and a window disposed on the reflection reducing layer, Wherein, the reflection reducing layer comprises: a color filter layer disposed on the touch sensing layer, wherein the color filter layer includes a first color filter, a second color filter, and a third color filter that are spaced apart from each other; a light blocking layer disposed on the touch sensing layer between the first color filter to the third color filter, wherein a plurality of holes are defined through the light blocking layer to overlap with the plurality of emission areas respectively; a color pattern disposed on the light blocking layer and not overlapping the plurality of holes; and A low refractive layer is disposed on the first to third color filters and between the color patterns.

19. The display device according to claim 18, wherein: The plurality of emission areas include a first emission area, a second emission area and a third emission area, The first color filter overlaps the first emission region and transmits red light, The second color filter overlaps the second emission region and transmits blue light, and The third color filter overlaps the third emission region and transmits green light.

20. The display device according to claim 19, wherein: The color pattern is a red filter that transmits red light.

Images