Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. According to one embodiment, a display device includes: a substrate; a first inorganic insulating layer disposed over the substrate over a display region in which an image is displayed and a peripheral region outside the display region; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display region; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral edge portion of the lower electrode; an organic layer disposed on the lower electrode and including a light emitting layer; an upper electrode disposed on the organic layer; and a plurality of terminals arranged on the first inorganic insulating layer in the peripheral region, the organic insulating layer has a first opening overlapping each of the plurality of terminals and at least one second opening located between adjacent terminals, and the second inorganic insulating layer has a third opening overlapping each of the plurality of terminals and is in contact with the first inorganic insulating layer in the second opening.

Description

[0001] Cross-references to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-124535 filed on July 31, 2023, and cites all the contents described in the Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. The display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer, and functional layers such as a hole transport layer and an electron transport layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the invention

[0006] An object of the embodiment is to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0007] According to one embodiment, a display device comprises:

[0008] A substrate; a first inorganic insulating layer, which is arranged above the above-mentioned substrate and covers a display area for displaying an image and a peripheral area outside the above-mentioned display area; an organic insulating layer, which is arranged on the above-mentioned first inorganic insulating layer; a lower electrode, which is arranged on the above-mentioned organic insulating layer in the above-mentioned display area; a second inorganic insulating layer, which is arranged on the above-mentioned organic insulating layer and overlaps with the peripheral portion of the above-mentioned lower electrode; an organic layer, which is arranged on the above-mentioned lower electrode and includes a light-emitting layer; an upper electrode, which is arranged on the above-mentioned organic layer; and a plurality of terminals arranged on the above-mentioned first inorganic insulating layer in the above-mentioned peripheral area, the above-mentioned organic insulating layer has a first opening respectively overlapping with the above-mentioned plurality of terminals and at least one second opening located between the above-mentioned adjacent terminals, and the above-mentioned second inorganic insulating layer has a third opening respectively overlapping with the above-mentioned plurality of terminals and contacts with the above-mentioned first inorganic insulating layer in the above-mentioned second opening.

[0009] According to one embodiment, in a method for manufacturing a display device,

[0010] In the peripheral area, a plurality of terminals are formed on the first inorganic insulating layer, and an organic insulating layer is formed, wherein the organic insulating layer has a first opening respectively overlapping with the plurality of terminals and at least one second opening located between the adjacent terminals. In the display area, a lower electrode is formed on the organic insulating layer, and a second inorganic insulating layer is formed, wherein the second inorganic insulating layer has a third opening respectively overlapping with the plurality of terminals, contacts with the first inorganic insulating layer in the second opening, and overlaps with the peripheral portion of the lower electrode. An organic layer including a light-emitting layer is formed on the lower electrode, and an upper electrode is formed on the organic layer.

[0011] According to the embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing an example of the configuration of a DSP of a display device.

[0013] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0014] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0015] Figure 4 It is a plan view showing an example of a mother substrate 100 for a display device.

[0016] Figure 5A Yes means Figure 4 FIG. 1 is a plan view of a configuration example of a region including the terminals TE of the mother substrate 100 shown.

[0017] Figure 5B Yes means Figure 1 The illustrated diagram is a plan view of a configuration example of a region including the terminals TE of the display device DSP.

[0018] Figure 6 It is along Figure 5A 1 is a cross-sectional view of the mother substrate 100 along line CD.

[0019] Figure 7 It is along Figure 5A EF line is a cross-sectional view of the mother substrate 100.

[0020] Figure 8 It is along Figure 5B A cross-sectional view of the display device DSP taken along line GH.

[0021] Fig. 9 Yes means Figure 4FIG. 1 is a plan view of another configuration example of a region including the terminals TE of the mother substrate 100 shown.

[0022] Fig.10 Yes means Figure 1 1 is a plan view of still another configuration example of a region including the terminals TE of the display device DSP shown.

[0023] Fig.11 It is a diagram for explaining a method of manufacturing the display device DSP.

[0024] Fig.12 It is a diagram for explaining a method of manufacturing the display device DSP.

[0025] Fig.13 It is a diagram for explaining a method of manufacturing the display device DSP.

[0026] Fig.14 It is a diagram for explaining a method of manufacturing the display device DSP.

[0027] Fig.15 It is a diagram for explaining a method of manufacturing the display device DSP.

[0028] Fig.16 It is a diagram for explaining a method of manufacturing the display device DSP.

[0029] Fig.17 It is a diagram for explaining a method of manufacturing the display device DSP.

[0030] Fig.18 It is a diagram for explaining a method of manufacturing the display device DSP.

[0031] Fig.19 It is a diagram for explaining a method of manufacturing the display device DSP.

[0032] Fig. 20 It is used to illustrate Figure 8 The illustrated terminal TE is a cross-sectional view showing a state where a vapor-deposited film DF is formed.

[0033] Fig.21 It is a cross-sectional view for explaining a comparative example.

[0034] Fig. 22 It is a cross-sectional view for explaining another comparative example. DETAILED DESCRIPTION

[0035] One embodiment will be described with reference to the drawings.

[0036] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the spirit of the invention are of course included in the scope of the present invention. In addition, with respect to the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared with the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the constituent elements that have the same or similar functions as the constituent elements described in the drawings that have appeared, there are cases where the same reference numerals are marked and repeated detailed descriptions are appropriately omitted.

[0037] It should be noted that, for ease of understanding, mutually orthogonal X-axis, Y-axis, and Z-axis are described in the drawings as needed. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. The situation of observing various elements parallel to the third direction Z is referred to as top view.

[0038] The display device according to this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and the like.

[0039] Figure 1 This is a diagram showing an example of the configuration of a DSP of a display device.

[0040] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0041] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, however, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0042] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors from each other. It should be noted that the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0043] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0044] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0045] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0046] The display element 20 is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0047] The peripheral area SA has a plurality of terminals TE. The plurality of terminals TE are arranged in one direction along the panel end PNLE. In the illustrated example, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends in the second direction Y, but is not limited thereto. For example, a portion of the plurality of terminals TE may also extend in an oblique direction. Such a plurality of terminals TE is electrically connected to a flexible printed circuit substrate FPC, for example, indicated by a single dotted line.

[0048] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0049] exist Figure 2 In the example of FIG. 1 , the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0050] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns of sub-pixels SP2 and SP3 arranged alternately in the second direction Y and columns of a plurality of sub-pixels SP1 arranged in the second direction Y are formed in the display area DA. These columns are arranged alternately in the first direction X.

[0051] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in sequence in the first direction X.

[0052] The insulating layer 5 and the partition 6 are arranged in the display area DA. The insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes called a rib.

[0053] The partition 6 overlaps with the insulating layer 5 in a plan view. The partition 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition 6 may have openings in the sub-pixels SP1, SP2, and SP3 similarly to the insulating layer 5.

[0054] The sub-pixels SP1 , SP2 , and SP3 include display elements 201 , 202 , and 203 as the display elements 20 , respectively.

[0055] The display element 201 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the opening AP1. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition wall 6 in a plan view. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap with the insulating layer 5 in a plan view.

[0056] The display element 202 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition wall 6 in a plan view. The peripheral portions of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap with the insulating layer 5 in a plan view.

[0057] The display element 203 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP3. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition wall 6 in a plan view. The peripheral portions of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap with the insulating layer 5 in a plan view.

[0058] exist Figure 2 In the example, the outer shapes of the lower electrodes LE1, LE2, LE3 are indicated by dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are indicated by single-dot dashed lines. It should be noted that the outer shapes of the lower electrodes, organic layers, and upper electrodes shown in the figure are not limited to those that reflect accurate shapes.

[0059] The lower electrodes LE1, LE2, and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes or common electrodes of the display element.

[0060] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 through the contact hole CH1 (see Figure 1 The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0061] exist Figure 2 In the example, the area of ​​the opening AP1, the area of ​​the opening AP2, and the area of ​​the opening AP3 are different from each other. The area of ​​the opening AP1 is larger than the area of ​​the opening AP2, and the area of ​​the opening AP2 is larger than the area of ​​the opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0062] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0063] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 includes various circuits such as the pixel circuit 1 shown, and various wirings such as the scanning line GL, the signal line SL, and the power line PL. In addition, the circuit layer 11 includes insulating layers 111, 112, 113, 114, 115, and 116 described later. The circuit layer 11 is covered with the insulating layer 12. The insulating layer 12 is arranged on the insulating layer 116 in the circuit layer 11, and is an organic insulating layer that flattens the unevenness generated by the circuit layer 11. The insulating layer 12 has a thickness T1.

[0064] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The insulating layer 5 is an inorganic insulating layer, and is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 3 is omitted, but is equivalent to Figure 2 CH1, CH2, CH3.

[0065] The partition wall 6 includes a conductive lower portion (stem) 61 disposed on the insulating layer 5 and an upper portion (shade) 62 disposed on the lower portion 61. The lower portion 61 of the partition wall 6 shown on the right side of the figure is located between the opening AP1 and the opening AP2. The lower portion 61 of the partition wall 6 shown on the left side of the figure is located between the opening AP2 and the opening AP3. The lower portion 61 can be a single layer or a multilayer. The upper portion 62 has a greater width than the lower portion 61. Both ends of the upper portion 62 protrude compared to the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever.

[0066] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral portion located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0067] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral portion located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0068] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 , covers the lower electrode LE3 exposed from the opening AP3 , and its peripheral portion is located on the insulating layer 5 . The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61 .

[0069] exist Figure 3 In the example, sub-pixel SP1 has cap layer CP1 and sealing layer SE1, sub-pixel SP2 has cap layer CP2 and sealing layer SE2, and sub-pixel SP3 has cap layer CP3 and sealing layer SE3. Cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers for improving the extraction efficiency of light emitted from organic layers OR1, OR2, and OR3.

[0070] The cap layer CP1 is disposed on the upper electrode UE1 .

[0071] The cap layer CP2 is disposed on the upper electrode UE2.

[0072] The cap layer CP3 is disposed on the upper electrode UE3.

[0073] The sealing layer SE1 is disposed on the cap layer CP1 , in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP1 .

[0074] The sealing layer SE2 is disposed on the cap layer CP2 , in contact with the partition wall 6 , and continuously covers each member of the sub-pixel SP2 .

[0075] The sealing layer SE3 is disposed on the cap layer CP3 , in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP3 .

[0076] exist Figure 3 In the example, a portion of each of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from the portions of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 located at the opening AP1 (the portions constituting the display element 201).

[0077] Similarly, portions of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 are each located on the partition wall 6 around the subpixel SP2, and these portions are separated from portions of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 located in the opening AP2 (portions constituting the display element 202).

[0078] Similarly, portions of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 are respectively located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from portions of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 located in the opening AP3 (portions constituting the display element 203).

[0079] The ends of the sealing layers SE1, SE2, and SE3 are located on the partition walls 6. Figure 3 In the example, the ends of the sealing layers SE1 and SE2 located on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from each other, and the ends of the sealing layers SE2 and SE3 located on the partition wall 6 between the sub-pixels SP2 and SP3 are separated from each other.

[0080] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 13 . The resin layer 13 is covered with a sealing layer 14 . The sealing layer 14 is covered with a resin layer 15 .

[0081] The insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0082] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper portion 62 of the partition wall 6 is formed of a conductive material, for example, but may also be formed of an insulating material. The lower portion 61 is formed of a material different from that of the upper portion 62.

[0083] The lower electrodes LE1 , LE2 , and LE3 are, for example, a multilayer body including a transparent electrode formed of an oxide conductive material such as indium tin oxide (ITO) and a metal electrode formed of a metal material such as silver.

[0084] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in a red wavelength range.

[0085] In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0086] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0087] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0088] Figure 3 The circuit layer 11 , the insulating layer 12 , and the insulating layer 5 shown are arranged over the display area DA and the peripheral area SA.

[0089] Next, a mother substrate 100 for a display device for collectively manufacturing a plurality of display device DSPs will be described.

[0090] Figure 4 It is a plan view showing an example of a mother substrate 100 for a display device.

[0091] The mother substrate 100 includes a plurality of panel portions PP and a blank portion MP outside the panel portions PP on a large substrate 10. The large substrate 10 is formed in a rectangular shape, for example, and has a first side 10X extending in a first direction X and a second side 10Y extending in a second direction Y.

[0092] The plurality of panel portions PP are arranged in a matrix in the first direction X and the second direction Y. The panel portions PP are taken out by cutting the mother substrate 100 along the cutting lines CL. The taken out panel portions PP are respectively equivalent to Figure 1 The display panel PNL shown in the figure has a display area DA and a peripheral area SA where terminals TE and the like are arranged.

[0093] Figure 5A Yes means Figure 4 FIG. 1 is a plan view of a configuration example of a region including the terminals TE of the mother substrate 100 shown.

[0094] Figure 5B Yes means Figure 1The illustrated diagram is a plan view of a configuration example of a region including the terminals TE of the display device DSP. Figure 5B The display device DSP shown is connected by Figure 5A The mother substrate 100 shown is obtained by being cut at a cutting line CL.

[0095] As indicated by the one-dot chain line, the plurality of terminals TE are arranged in the first direction X and extend in the second direction Y. As described above, the insulating layer 5 and the insulating layer 12 extend to the region including the terminals TE.

[0096] The insulating layer 12 has an opening OPA overlapping each terminal TE, an opening OPB located between adjacent terminals, and an opening OPC overlapping the cutting line CL. Figure 5A The position of the cutting line CL shown in FIG. 1 is different from that of the mother substrate 100 when the mother substrate 100 is cut. Figure 1 as well as Figure 5B The position of the panel end PNLE shown corresponds.

[0097] exist Figure 5A as well as Figure 5B In the example shown, one opening OPA overlaps one terminal TE. One opening OPB is located between two adjacent terminals TE. These openings OPA and openings OPB extend in a direction different from the first direction X corresponding to the direction in which the terminals TE are arranged, and in the example shown in the figure, extend in a second direction Y which is an example of a direction intersecting the first direction X.

[0098] The opening OPC overlaps with the dicing line CL along the first direction X and extends in the first direction X. The opening OPA, the opening OPB, and the opening OPC are separated from each other.

[0099] like Figure 5B As shown, the insulating layer 5 has an opening OP5 overlapping with each opening OPA or each terminal TE. When viewed from above, the area of ​​the opening OP5 is larger than the area of ​​the opening OPA. The edge of the opening OP5 is located outside the edge of the opening OPA and does not intersect with the edge of the opening OPA. The insulating layer 12 is exposed from the insulating layer 5 in the opening OP5. Regarding the width along the first direction X, the width W1 of the insulating layer 5 between adjacent openings OP5 is smaller than the width W2 of the opening OP5.

[0100] In addition, the insulating layer 5 overlaps with the opening OPB and the opening OPC in a plan view.

[0101] Figure 6 It is along Figure 5A 1 is a cross-sectional view of the mother substrate 100 along line CD.

[0102] Figure 7 It is along Figure 5AEF line is a cross-sectional view of the mother substrate 100.

[0103] Figure 8 It is along Figure 5B A cross-sectional view of the display device DSP taken along line GH.

[0104] The circuit layer 11 on the substrate 10 includes insulating layers 111 , 112 , 113 , 114 , 115 , and 116 , and metal layers MA, MB, and MC.

[0105] The insulating layer 111 is an inorganic insulating layer, and is disposed on the substrate 10. The insulating layer 112 is an inorganic insulating layer, and is disposed on the insulating layer 111. The metal layer MA is disposed on the insulating layer 112. The insulating layer 113 is an inorganic insulating layer, and is disposed on the insulating layer 112 and the metal layer MA. The insulating layer 114 is an inorganic insulating layer, and is disposed on the insulating layer 113.

[0106] The metal layer MB is disposed on the insulating layer 114 and is electrically connected to the metal layer MA. The insulating layer 115 is an inorganic insulating layer and is disposed on the insulating layer 114 and the metal layer MB. The metal layer MC is disposed on the insulating layer 115 and is electrically connected to the metal layer MB.

[0107] The insulating layer 116 is an inorganic insulating layer, and is disposed on the insulating layer 115 and the metal layer MC.

[0108] The terminal TE is located directly on the metal layer MA, disposed on the insulating layer 116 , and electrically connected to the metal layer MC.

[0109] The insulating layer 12 is disposed on the insulating layer 116 and the terminal TE. The insulating layer 12 exposes the terminal TE in the opening OPA. The peripheral edge of the terminal TE is entirely covered by the insulating layer 12. The insulating layer 12 exposes the insulating layer 116 in the opening OPB and the opening OPC.

[0110] The terminal TE is electrically connected to the flexible printed circuit board via the anisotropic conductive film. At this time, from the viewpoint of suppressing poor connection between the terminal TE and the flexible printed circuit board, it is preferable that the step difference formed between the terminal TE and the surrounding insulating layer 12 is small. Therefore, the thickness T2 of the insulating layer 12 directly above the terminal TE is smaller than Figure 3 The thickness T1 of the insulating layer 12 for planarization just below the lower electrode LE2 is shown to be small.

[0111] The insulating layer 5 is arranged on the insulating layer 12, and contacts the insulating layer 116 as the base layer in the opening OPB and the opening OPC. In the example shown in the figure, the insulating layer 116 is covered by the insulating layer 5 in the opening OPB and the opening OPC. In this way, the insulating layer 5 and the insulating layer 116 are both inorganic insulating layers, and they are in contact with each other and firmly adhere to each other. Therefore, compared with the case where the insulating layer 5 as an inorganic insulating layer is only in contact with the insulating layer 12 as an organic insulating layer, the adhesion between the insulating layer 5 and the base layer is improved, and the peeling of the insulating layer 5 can be suppressed.

[0112] Insulating layer 5 is disposed on the upper surface of insulating layer 12 near opening OPA, but not on the inclined surface of insulating layer 12 surrounding opening OPA. Therefore, a path capable of releasing moisture (or water vapor) contained in insulating layer 12 can be formed in the region of insulating layer 12 exposed from insulating layer 5.

[0113] In addition, the insulating layer 5 is not in contact with the terminal TE. Therefore, compared with the case where the insulating layer 5 is in contact with the terminal TE, the area where the terminal TE is exposed from the insulating layer 5 (or the area where the flexible printed circuit board is connected to the terminal TE) can be increased.

[0114] The insulating layers 111 to 116 are formed of any one of silicon oxide, silicon nitride, and silicon oxynitride. In one example, the insulating layers 111, 114, and 116 are formed of silicon nitride, and the insulating layers 112, 113, and 115 are formed of silicon oxide. In addition, the insulating layer 5 is formed of, for example, silicon oxynitride.

[0115] like Figure 8 As shown, the terminal TE includes a first conductive layer TE1, a second conductive layer TE2, and a third conductive layer TE3. The first conductive layer TE1 is disposed on the insulating layer 116. The second conductive layer TE2 is disposed on the first conductive layer TE1. The third conductive layer TE3 is disposed on the second conductive layer TE2.

[0116] The first conductive layer TE1 and the third conductive layer TE3 are formed of the same material, for example, and the second conductive layer TE2 is formed of a material different from that of the first conductive layer TE1. In one example, the second conductive layer TE2 is an aluminum layer formed of an aluminum-based material, and the first conductive layer TE1 and the third conductive layer TE3 are titanium layers formed of a titanium-based material. It should be noted that the first conductive layer TE1 and the third conductive layer TE3 may be formed of a molybdenum-based material.

[0117] The insulating layer 12 covers the peripheral edge of the terminal TE. That is, the side surfaces of the first conductive layer TE1, the second conductive layer TE2, and the third conductive layer TE3 are covered by the insulating layer 12. Therefore, it is possible to suppress the undesired corrosion of the aluminum layer caused by the etching solution used in the process of forming the lower electrode on the insulating layer 12.

[0118] Fig. 9 Yes means Figure 4 FIG. 1 is a plan view of another configuration example of a region including the terminals TE of the mother substrate 100 shown.

[0119] Fig.10 Yes means Figure 1 The illustrated diagram is a plan view of a configuration example of a region including the terminals TE of the display device DSP. Fig.10 The display device DSP shown is connected by Fig. 9 The mother substrate 100 shown is obtained by being cut at a cutting line CL.

[0120] Fig. 9 as well as Fig.10 The configuration example shown is Figure 5A as well as Figure 5B Compared with the illustrated configuration example, the difference is that a plurality of openings OPB are arranged between two adjacent terminals TE.

[0121] exist Fig. 9 as well as Fig.10 In the example shown, the plurality of openings OPB are arranged in a row between two adjacent terminals TE along the second direction Y. It should be noted that the plurality of openings OPB may be arranged in a matrix in the first direction X and the second direction Y between two adjacent terminals TE.

[0122] The insulating layer 5 overlaps with a plurality of openings OPB, such as Figure 8 As shown in the cross-sectional views of FIG. 1 and FIG. 2 , each opening OPB is in contact with the insulating layer 116 .

[0123] Next, a method for manufacturing the display device DSP is described. Figures 11 to 14 The illustration below the insulating layer 116 is omitted. Figures 15 to 19 The lower part of the insulating layer 12 is omitted in the figure.

[0124] First, if Fig.11 As shown in FIG. 1 , in the peripheral area SA, a plurality of terminals TE are formed on the insulating layer 116. The process of forming the terminal TE includes the following process. That is, a first conductive layer TE1 is formed on the insulating layer 116, a second conductive layer TE2 is formed on the first conductive layer TE1, and a third conductive layer TE3 is formed on the second conductive layer TE2. Then, the first conductive layer TE1, the second conductive layer TE2, and the third conductive layer TE3 are patterned. Thus, the terminal TE is formed.

[0125] Then, if Fig.12As shown, an insulating layer 12 is formed over the display area DA and the peripheral area SA. In the display area DA, an insulating layer 12 with a thickness of T1 is formed, and in the peripheral area SA, an insulating layer 12 with a thickness T2 that covers the peripheral portion of the terminal TE and is smaller than the thickness T1 is formed just above the terminal TE. At this time, in the insulating layer 12, an opening OPA that overlaps with each terminal TE is formed, and an opening OPB that is located between adjacent terminals is formed. In addition, although not shown, an opening OPC that overlaps with the cutting line is also formed in the insulating layer 12.

[0126] Then, if Fig.13 As shown, in the display area DA, the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12. The process of forming the lower electrodes LE1, LE2, and LE3 includes the following processes. That is, an ITO layer is formed on the insulating layer 12, a silver layer is formed on the ITO layer, and an ITO layer is formed on the silver layer. Then, the ITO layer, the silver layer, and the ITO layer are patterned respectively by wet etching. Thus, the lower electrodes LE1, LE2, and LE3 are formed. At this time, the peripheral portion of the terminal TE is covered by the insulating layer 12, so that the aluminum layer of the terminal TE can be protected.

[0127] Then, if Fig.14 As shown, the insulating layer 5 is formed over the display area DA and the peripheral area SA. At this time, the insulating layer 5 is in contact with the insulating layer 116 in the opening OPB. Although not shown, the insulating layer 5 is also in contact with the insulating layer 116 in the opening OPC.

[0128] Then, in the display area DA, the partition wall 6 having the lower portion 61 located on the insulating layer 5 and the upper portion 62 located on the lower portion 61 is formed.

[0129] Then, openings AP1, AP2, and AP3 are formed in the insulating layer 5 of the display area DA, and an opening OP5 is formed in the insulating layer 5 of the peripheral area SA. The opening AP1 overlaps with the lower electrode LE1 of the sub-pixel SP1, the opening AP2 overlaps with the lower electrode LE2 of the sub-pixel SP2, and the opening AP3 overlaps with the lower electrode LE3 of the sub-pixel SP3. The opening OP5 overlaps with the terminal TE and is formed in such a manner that the insulating layer 12 is exposed.

[0130] It should be noted that the step of forming the openings AP1 , AP2 , and AP3 may be performed before the step of forming the partition 6 .

[0131] Next, the display element 201 is formed in the display area DA.

[0132] First, if Fig.15As shown, using the partition wall 6 as a mask, materials for forming each layer such as a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer EM1, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially evaporated on the lower electrode LE1 to form an organic layer OR1.

[0133] Then, a mixture of magnesium and silver is deposited on the organic layer OR1 using the partition wall 6 as a mask to form an upper electrode UE1 . The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower portion 61 .

[0134] Then, using the partition wall 6 as a mask, a high refractive index material and a low refractive index material are sequentially deposited on the upper electrode UE1 to form a cap layer CP1.

[0135] The organic layer OR1 , the upper electrode UE1 , and the cap layer CP1 are continuously formed while maintaining a vacuum environment.

[0136] Then, the sealing layer SE1 is formed so as to continuously cover the cap layer CP1 and the partition wall 6 .

[0137] The organic layer OR1 , the upper electrode UE1 , and the cap layer CP1 are partitioned by a cantilever-shaped partition wall 6 .

[0138] When the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by evaporation, respectively, the material emitted from the evaporation source is blocked by the upper portion 62. Therefore, a portion of each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is deposited on the upper portion 62. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the upper portion 62 are separated from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located just above the lower electrode LE1, respectively.

[0139] The organic layer OR1 , the upper electrode UE1 , the cap layer CP1 , and the sealing layer SE1 are formed not only in the display area DA but also in the peripheral area SA and the blank portion MP.

[0140] Then, if Fig.16 As shown in FIG. 1 , a resist R1 patterned into a predetermined shape is formed on the sealing layer SE1 . The resist R1 overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0141] Then, if Fig.17 As shown, by etching using the resist R1 as a mask, the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 exposed from the resist R1 are sequentially removed, thereby exposing the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3.

[0142] Then, the resist R1 is removed, thereby forming the display element 201 in the sub-pixel SP1.

[0143] Then, if Fig.18 As shown, the display element 202 is formed. The steps of forming the display element 202 are the same as the steps of forming the display element 201. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, a cover layer CP2, and a sealing layer SE2 are sequentially formed on the lower electrode LE2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cover layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned in sequence by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element 202 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0144] Then, if Fig.19 As shown, the display element 203 is formed. The steps of forming the display element 203 are the same as the steps of forming the display element 201. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, a cap layer CP3, and a sealing layer SE3 are sequentially formed on the lower electrode LE3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned in sequence by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element 203 is formed in the sub-pixel SP3.

[0145] Then, form Figure 3 The resin layer 13, the sealing layer 14 and the resin layer 15 are shown. Thus, the display device DSP is completed.

[0146] It should be noted that in the above manufacturing process, it is assumed that the display element 201 is formed first, the display element 202 is formed next, and the display element 203 is formed last, but the formation order of the display elements 201, 202, and 203 is not limited to this example.

[0147] Fig. 20 It is used to illustrate Figure 8 The illustrated terminal TE is a cross-sectional view showing a state where a vapor-deposited film DF is formed.

[0148] In the process of forming the display elements 201, 202, and 203, the vapor-deposited film DF is also formed in the peripheral area SA. The vapor-deposited film DF herein includes, for example, Fig.15 The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are used to form the display element 201. The evaporated film DF is formed on the insulating layer 5, the insulating layer 12 and the terminal TE.

[0149] Since a part of the insulating layer 12 is covered by the insulating layer 5, the damage to the insulating layer 12 in the manufacturing process before the display element 201 is formed is reduced. In addition, compared with the case where the insulating layer 12 is not covered by the insulating layer 5, the contact area between the damaged region in the insulating layer 12 and the vapor-deposited film DF is smaller. The adhesion between the vapor-deposited film DF and the insulating layer 5 is stronger than the adhesion between the vapor-deposited film DF and the insulating layer 12, and the contact area between the vapor-deposited film DF and the insulating layer 5 is larger than the contact area between the vapor-deposited film DF and the insulating layer 12. Therefore, the detachment of the vapor-deposited film DF in the manufacturing process can be suppressed.

[0150] Next, comparative examples will be described.

[0151] Fig.21 It is a cross-sectional view for explaining a comparative example.

[0152] exist Fig.21 In the comparative example shown, the insulating layer 5 is not disposed on the insulating layer 12. In this case, the insulating layer 12 is damaged in the manufacturing process before forming the display element 201, and the surface of the insulating layer 12 is easily roughened. The evaporated film DF is formed on the insulating layer 12 and the terminal TE.

[0153] The insulation layer 12 and the vapor-deposited film DF have weak adhesion, and the vapor-deposited film DF is easily lifted from the insulation layer 12. As shown in the figure, a gap V is formed between the insulation layer 12 and the vapor-deposited film DF, and there is a risk that the vapor-deposited film DF will be separated from the insulation layer 12.

[0154] Here, the following describes the possible adverse conditions that may occur when the vapor-deposited film DF floats up from the insulating layer 12 and breaks. The vapor-deposited film DF separated from the insulating layer 12 becomes foreign matter and floats in the manufacturing device, which may become a source of contamination. In addition, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0155] In contrast, according to this embodiment, as shown in FIG. Fig. 20 As described above, in the region including the terminal TE, the detachment of the vapor deposited film DF can be suppressed. Figure 8 As described above, it is also possible to suppress the insulation layer 5 from being separated from the insulation layer 12. This can suppress contamination of the manufacturing device and generation of unwanted foreign matter, thereby suppressing a decrease in reliability.

[0156] It should be noted that even when the vapor-deposition film DF includes the organic layer OR2 , the upper electrode UE2 , and the cap layer CP2 for forming the display element 202 , the same effect can be obtained.

[0157] In addition, even when the vapor-deposition film DF includes the organic layer OR3 , the upper electrode UE3 , and the cap layer CP3 for forming the display element 203 , the same effect can be obtained.

[0158] Fig. 22 It is a cross-sectional view for explaining another comparative example.

[0159] exist Fig. 22 In the comparative example shown, the insulating layer 5 is formed so as to cover the insulating layer 12. The vapor-deposited film DF is formed on the insulating layer 5 and the terminal TE.

[0160] In this case, no path is formed that can release the moisture (or water vapor) contained in the insulating layer 12. Therefore, as shown in the figure, for example, due to the influence of the water vapor released from the insulating layer 12, a gap V is formed between the insulating layer 12 and the insulating layer 5, and there is a risk that the insulating layer 5 will be separated from the insulating layer 12.

[0161] In addition, stress is easily concentrated in the region CX where the insulating layer 12 as an organic insulating layer, the insulating layer 5 as an inorganic insulating layer, and the terminal TE as a metal layer contact each other. When the evaporated film DF is formed in such a region CX, the evaporated film DF is easily floated from the insulating layer 5 starting from the region CX where the stress is concentrated, and there is a risk that the evaporated film DF will be separated from the insulating layer 5.

[0162] On the other hand, according to the present embodiment, as described above, it is possible to suppress the insulation layer 5 from being separated from the insulation layer 12 and the vapor-deposited film DF from being separated from the insulation layer 5. Therefore, a decrease in reliability is suppressed.

[0163] In the above embodiment, for example, the insulating layer 116 corresponds to the first inorganic insulating layer, the insulating layer 5 corresponds to the second inorganic insulating layer, and the insulating layer 12 corresponds to the organic insulating layer. In addition, the opening OPA corresponds to the first opening, the opening OPB corresponds to the second opening, and the opening OP5 corresponds to the third opening.

[0164] As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same.

[0165] Based on the display device and the manufacturing method thereof described above as the embodiments of the present invention, any display device and the manufacturing method thereof that can be implemented by appropriately designing and modifying by a person skilled in the art also belongs to the scope of the present invention as long as it includes the gist of the present invention.

[0166] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations should also be understood to belong to the scope of the present invention. For example, those skilled in the art can add, delete or design changes to the above-mentioned embodiments, or add, omit or change the conditions of the process, as long as they have the gist of the present invention, they are also included in the scope of the present invention.

[0167] In addition, regarding other effects brought about by the schemes described in the above-mentioned embodiments, effects that can be clearly understood from the description of this specification or effects that can be appropriately thought of by those skilled in the art should of course be understood as effects brought about by the present invention.

Claims

1. A display device comprising: substrate; a first inorganic insulating layer disposed above the substrate over a display region where an image is displayed and a peripheral region outside the display region; an organic insulating layer, disposed on the first inorganic insulating layer; a lower electrode, which is arranged on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping with the peripheral edge of the lower electrode; an organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; and a plurality of terminals arranged on the first inorganic insulating layer in the peripheral region, The organic insulating layer has first openings respectively overlapping the plurality of terminals and at least one second opening located between adjacent terminals. The second inorganic insulating layer has third openings overlapping the plurality of terminals, respectively, and is in contact with the first inorganic insulating layer in the second openings.

2. The display device according to claim 1, wherein: One of the second openings extends in a direction intersecting with a direction in which the plurality of terminals are arranged.

3. The display device according to claim 1, wherein: The plurality of second openings are arranged in a direction intersecting a direction in which the plurality of terminals are arranged.

4. The display device according to claim 1, wherein: The organic insulating layer is exposed from the second inorganic insulating layer in the third opening.

5. The display device according to claim 1, wherein: In the organic insulating layer, a thickness just above the terminal is smaller than a thickness just below the lower electrode.

6. The display device according to claim 1, wherein: The terminal is a multilayer body including an aluminum layer, The organic insulating layer covers a peripheral portion of the terminal.

7. The display device according to claim 1, further comprising a partition wall in the display region, the partition wall having a lower portion arranged on the second inorganic insulating layer and formed of a conductive material, and an upper portion arranged on the lower portion and protruding from a side surface of the lower portion, The lower electrode, the organic layer, and the upper electrode are surrounded by the partition wall in a plan view. The upper electrode is in contact with the partition wall.

8. The display device according to claim 1, wherein: The first inorganic insulating layer and the second inorganic insulating layer are each formed of any one of silicon oxide, silicon nitride, and silicon oxynitride.

9. A method for manufacturing a display device, wherein: In the peripheral region, a plurality of terminals are formed on the first inorganic insulating layer. forming an organic insulating layer, the organic insulating layer having first openings respectively overlapping the plurality of terminals and at least one second opening located between adjacent terminals, In the display area, a lower electrode is formed on the organic insulating layer, forming a second inorganic insulating layer, the second inorganic insulating layer having third openings respectively overlapping the plurality of terminals, contacting the first inorganic insulating layer in the second openings, and overlapping the peripheral edge of the lower electrode, forming an organic layer including a light-emitting layer on the lower electrode, An upper electrode is formed on the organic layer.

10. The method for manufacturing a display device according to claim 9, wherein: The third opening of the second inorganic insulating layer is formed so as to expose the organic insulating layer.

11. The method for manufacturing a display device according to claim 9, wherein: The organic insulating layer is formed in such a manner that a thickness directly above the terminal becomes smaller than a thickness directly below the lower electrode.

12. The method for manufacturing a display device according to claim 9, wherein: The process of forming the terminal includes: forming a first conductive layer on the first inorganic insulating layer, forming a second conductive layer as an aluminum layer on the first conductive layer, forming a third conductive layer on the second conductive layer, A step of patterning the first conductive layer, the second conductive layer, and the third conductive layer.

13. The method for manufacturing a display device according to claim 12, wherein: The organic insulating layer is formed so as to cover the peripheral portion of the terminal.

14. The method for manufacturing a display device according to claim 9, wherein: Furthermore, before forming the organic layer, A partition wall is formed in the display region, the partition wall having a lower portion located on the second inorganic insulating layer and an upper portion located on the lower portion and protruding from a side surface of the lower portion.

15. The method for manufacturing a display device according to claim 14, wherein: The organic layer and the upper electrode are respectively formed by vapor deposition using the partition wall as a mask.

16. The method for manufacturing a display device according to claim 15, wherein: Further, after forming the upper electrode, forming a cap layer on the upper electrode by performing vapor deposition using the partition wall as a mask, A sealing layer is formed to cover the partition wall and the cap layer.

17. The method for manufacturing a display device according to claim 16, wherein: Further, after forming the sealing layer, forming a patterned resist on the sealing layer, Etching is performed using the resist as a mask to sequentially remove a portion of the sealing layer, a portion of the cap layer, a portion of the upper electrode, and a portion of the organic layer.

18. The method for manufacturing a display device according to claim 9, wherein: The first inorganic insulating layer and the second inorganic insulating layer are each formed of any one of silicon oxide, silicon nitride, and silicon oxynitride.

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