Techniques for stacked photonic integrated circuit dies

Abstract

Techniques for stacked photonic integrated circuit (PIC) dies are disclosed. In an illustrative embodiment, two or more PIC dies are stacked on each other with electronic integrated circuit (EIC) dies stacked on top. The PIC die may be optically coupled in any suitable manner, such as a mirror in an optical bridge, a write-through waveguide in an optical bridge, or a photonic wire bond. Stacked PIC dies can increase yield, reduce occupied space, reduce cost and allow different PIC technologies to be integrated into one device.

Description

Background Art

[0001] Photonic integrated circuits (PICs) can be used in several applications such as communications. As the size of PICs increases, the yield may decrease and the required package size may also increase, thereby increasing the cost and potentially limiting the performance of the PICs. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is an isometric view of one embodiment of a device having stacked PIC dies.

[0003] Figure 2 yes Figure 1 A cross-sectional view of an embodiment of a device.

[0004] Figure 3 yes Figure 1 A cross-sectional view of an embodiment of a device.

[0005] Figure 4 yes Figure 1 A cross-sectional view of an embodiment of a device.

[0006] Figure 5 yes Figure 1 A cross-sectional view of an embodiment of a device.

[0007] Figure 6 yes Figure 1 A cross-sectional view of an embodiment of a device.

[0008] Figure 7 is a simplified flow chart of at least one embodiment of a method for fabricating a device having stacked PIC dies.

[0009] Figure 8 is a top view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0010] Fig. 9 is a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly according to any embodiment disclosed herein.

[0011] FIG. 10A to FIG. 10D is a perspective view of exemplary planar, gate-all-around, and stacked gate-all-around transistors.

[0012] Fig.11 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any embodiment disclosed herein.

[0013] Fig.12 is a block diagram of an example electrical device that can include a microelectronic assembly according to any embodiment disclosed herein. DETAILED DESCRIPTION

[0014] In various embodiments disclosed herein, a device includes several photonic integrated circuit (PIC) dies and electronic integrated circuit (EIC) dies stacked on each other. The waveguides in the PIC dies are coupled to each other using optical bridges (such as mirrors or lenses in glass, direct write waveguides, or photonic wire bonding). Using stacked PIC dies can increase production and reduce the footprint of the device.

[0015] As used herein, the phrase "communicatively coupled" refers to the ability of a component to send or receive signals to or from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive signals to or from another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of communicatively coupled components include: an integrated circuit die located in the same package, the integrated circuit die communicating via an embedded bridge in the package substrate; and an integrated circuit component attached to a printed circuit board, which sends or receives signals to or from other integrated circuit components or electronic devices attached to the printed circuit board.

[0016] In the following description, specific details are set forth, but embodiments of the technology described herein may be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description. Phrases such as "an embodiment," "various embodiments," "some embodiments," etc. may include features, structures, or characteristics, but not every embodiment necessarily includes a particular feature, structure, or characteristic.

[0017] Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third", etc. describe common objects and indicate different instances of similar objects being referenced. Such adjectives do not imply that the objects described in this way must be in a given sequence, in a ranking, or in any other way in time or space. "Connected" may indicate that the elements are in direct physical or electrical contact, and "coupled" may indicate that the elements cooperate or interact, but they may or may not be in direct physical or electrical contact. In addition, the terms "including", "comprising", "having", etc. used in embodiments of the present disclosure are synonymous. The term "substantially" modified by the word includes an arrangement, orientation, spacing, or position that is slightly different from the meaning of the unmodified term. For example, the central axis of a magnetic plug substantially coaxially aligned with a through hole may be misaligned with the central axis of the through hole by a few degrees. In another example, a substrate assembly feature (such as a through width) described as having substantially listed dimensions may vary within a few percent of the listed dimensions.

[0018] It should be understood that in the examples further shown and described below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components. In addition, it will be understood that although certain figures show transistor designs with source / drain regions, electrodes, etc. having orthogonal (e.g., vertical) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 or 10 degrees of orthogonality) due to manufacturing methods used to produce such devices or for other reasons.

[0019] Reference is now made to the accompanying drawings, which are not necessarily drawn to scale, wherein similar or identical numbers may be used to designate the same or similar components in different drawings. The use of similar or identical numbers in different drawings does not mean that all drawings including similar or identical numbers constitute a single or identical embodiment. The same numbers with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0020] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding thereof. However, it is apparent that novel embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form to facilitate their description. It is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0021] As used herein, the phrase "located on" in the context of a first layer or component being located on a second layer or component means that the first layer or component is physically attached to the second layer or component directly (with no layers or components between the first layer or component and the second layer or component) or is physically attached to the second layer or component using one or more intermediate layers or components.

[0022] As used herein, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there are no layers or components between the adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is in physical contact with layer Y.

[0023] Reference now Figures 1 to 3 In one embodiment, the device 100 includes two photonic integrated circuit (PIC) dies 104, 106 and an electrical integrated circuit (EIC) die 102 stacked on top of each other. Figure 2 A cross-sectional side view of the device 100 is shown, and Figure 3 A top view of one of the PIC dies 106 is shown. An optical bridge 108 couples the waveguide in the upper PIC die 104 to the lower PIC die 106. The EIC die 102 and the PIC dies 104, 106 are supported on a circuit board 110.

[0024] Device 100 may be embodied as or otherwise include a system on a chip (SoC), a processor, a memory, a graphics processor, an accelerator, an application specific integrated circuit, a field programmable gate array, a network router, a network switch, a network interface controller, a server computer, a mobile computing device, etc.

[0025] In the illustrative embodiment, stacking two or more PIC dies 104, 106 provides several advantages. The yield of each of the several smaller PIC dies 104, 106 will generally be higher than the yield of the larger PIC die. Stacking the PIC dies 104, 106 may reduce the footprint required for the PIC dies 104, 106, or alternatively, may increase the actual estate of the PIC dies 104, 106 in the same footprint. Additionally, in some embodiments, the PIC dies 104, 106 may be manufactured using different technology nodes, may use different substrates, or may otherwise be incompatible with manufacturing on a single PIC die.

[0026] like Figure 2As shown, in one embodiment, the PIC die 104 has a substrate 202 and a photonic layer 204. Similarly, the PIC die 106 has a substrate 206 and a photonic layer 208. In the illustrative embodiment, some or all of the photonic components (i.e., waveguides, splitters, filters, lasers, etc.) are in the photonic layers 204, 208. Electrical vias 210, 212 can provide electrical connections between the PIC die 104, 106 and / or the EIC die 102. The vias 210, 212 can provide input / output connections, power delivery, etc. In some embodiments, the vias 210, 212 can provide electrical connections between the circuit board 110 and the PIC die 104, 106 and / or the EIC die 102.

[0027] In one embodiment, the waveguide 222 in the PIC die 104 is coupled to a vertical coupler 214, which vertically guides the light in the waveguide 222. The light forms a beam 218 outside the PIC die 104, which is reflected from the reflector 220 toward the PIC die 106. The vertical coupler 216 in the PIC die 106 couples the beam 218 into a waveguide 224 in the PIC die 106. The waveguides 222, 224 and other components of the PIC die 104, 106 can operate at any suitable wavelength, such as 400-1800 nanometers. In an illustrative embodiment, the operating wavelength has a center wavelength between 1260-1360 nanometers for an O-band signal or between 1530-1565 nanometers for a C-band signal. In other embodiments, the operating wavelength can be, for example, an S-band signal or an L-band signal.

[0028] To focus light from vertical coupler 214 to vertical coupler 216 (or vice versa), any suitable technique may be used, such as forming lenses or mirrors in photonic layers 204, 208 or substrates 202, 206, using curved mirrors 220 or lenses in optical bridge 108, and the like.

[0029] The EIC die 102 may be embodied as any suitable electrical integrated circuit. The EIC die 102 may be embodied as, form part of, or include a processor, a system on a chip (SoC), a memory, a graphics processor, an accelerator, an application specific integrated circuit, a field programmable gate array, etc. In the illustrative embodiment, the EIC die 102 is electrically coupled to the PIC die 104, 106 through vias 210, 212. Additionally or alternatively, the EIC die 102 may be electrically coupled to the PIC die 104, 106 or other components such as the circuit board 110 in any other suitable manner, such as wire bonding, bumps, embedded multi-die interconnect bridges (EMIBs), etc.

[0030] The PIC dies 104, 106 may be made of any suitable material. In the illustrative embodiment, the substrates 202, 206 of the PIC dies 104, 106 are made of silicon. In other embodiments, the substrates 202, 206 of the PIC dies 104, 106 may be made of any suitable material, such as glass, silicon oxide, polymers, etc. Similarly, the photonic layers 204, 208 may be made of or include any suitable material, such as silicon, silicon oxide, silicon nitride, polymers, glass, etc.

[0031] In the illustrative embodiment, the waveguides 222, 224 are silicon waveguides in the silicon oxide layers 204, 208. Each waveguide 222, 224 can have any suitable dimensions, such as a width and / or height of 0.1-10 microns. In the illustrative embodiment, each waveguide 222, 224 is square. In other embodiments, the waveguides 222, 224 can have different shapes, such as a rectangular shape. The PIC die 104 can include any suitable number of waveguides 222 coupled to the waveguide 224 of the PIC die 106, such as 1-128 waveguides 222 or more. Of course, the PIC die 104, 106 can include additional waveguides internally.

[0032] The PIC die 104, 106 may include one or more lasers or other light sources, detectors, amplitude and / or phase modulators, filters, splitters, amplifiers, interferometers, microring resonators, gratings, squeezing or other quantum light sources, etc. In some embodiments, light from an off-die source such as a laser may be provided to the PIC die 104, 106. The PIC die 104, 106 may perform any suitable function, such as converting optical signals to electrical signals or vice versa, matrix multiplication, quantum logic gates, optical computation gates, etc.

[0033] exist Figure 3 , a top view of one embodiment of a PIC die 106 is shown. In the illustrative embodiment, the PIC die 106 includes an array of Mach-Zehnder interferometers 304. The vertical coupler 216 couples light into and out of the waveguide 302. The vertical coupler 216 can be connected to another PIC die, such as the PIC die 104. The waveguide 302 of the PIC die 106 is provided as an input to the array of Mach-Zehnder interferometers 304. Each Mach-Zehnder interferometer includes two splitters 306, and a phase shifter 308. In the illustrative embodiment, the phase shifter 308 is controlled by an electrical signal from the EIC 102 through the vias 210, 212. It should be understood that Figure 3 The embodiment shown in FIG. 1 is only one possible embodiment of the PIC die 106, and other PIC die 106 may include Figure 3In some embodiments, the PIC dies 104, 106 may include vertical couplers 214, 216 along any edge of the PIC dies 104, 106 as desired.

[0034] In the illustrated embodiment, hybrid bonding is used to bond the EIC die 102 and the PIC die 104 together. In other embodiments, other techniques may be used, such as the use of microbumps. The PIC dies 104, 106 may be bonded together in a similar manner.

[0035] Any suitable technique may be used to place the PIC die 104, 106 and / or EIC die 102, such as by using a pick-and-place machine. The PIC die 104, 106 and / or EIC die 102 may include one or more fiducials that may be used by the pick-and-place machine to place another PIC die 104, 106 and / or EIC die 102. The fiducials may be embodied as, for example, points, lines, or other structures that indicate the location of a particular portion of the PIC die 104, 106 and / or EIC die 102. The pick-and-place machine may align the PIC die 104, 106 and / or EIC die 102 with high precision, such as misalignment of less than 3-0.3 microns at 3 sigma.

[0036] The optical bridge 108 may be made of any suitable material, such as glass, silicon, silicon oxide, polymers, etc. The reflector 220 may be made of any suitable material, such as aluminum, silver, interference films, etc. The device 100 may include any suitable number of optical bridges 108. For example, in one embodiment, one optical bridge 108 may provide all connections between the PIC dies 104, 106. In other embodiments, several optical bridges 108 may be used to provide connections between the PIC dies 104, 106. The optical bridge 108 may be located at any suitable location, such as along any edge of the PIC dies 104, 106. In some embodiments, a channel may be defined in the PIC dies 104, 106, and a portion of one or more optical bridges 108 may be placed in the channel, potentially aligned with one or more waveguides.

[0037] The illustrative circuit board 110 may be made of ceramic, glass, and / or organic-based materials (such as FR-4) with glass fiber and resin. The circuit board 110 may have any suitable length or width, such as 10-500 mm. The circuit board 110 may have any suitable thickness, such as 0.2-5 mm. The circuit board 110 may support additional components in addition to the PIC die 104, 106 and the EIC die 102, such as additional EIC die or PIC die, processor unit, memory device, accelerator device, etc.

[0038] It should be understood that Figure 1 The configuration shown of stacking one EIC die 102 on two PIC die 104, 106 is only one possible embodiment. In some embodiments, more or fewer EIC die and / or PIC die may be included. For example, in some embodiments, the PIC die 104 may have two EIC die 102 above it. In another example, the two PIC die may be below the EIC die 102. In some embodiments, one or more EIC die 102 may be between the two PIC die 104, 106. In general, any suitable arrangement of stacked EIC die and / or PIC die may be used. For example, the device 100 may include, for example, 2-10 PIC die and / or EIC die stacked on each other. In some embodiments, an optical bridge 108 may connect more than two PIC die. For example, an optical bridge 108 may optically couple a first PIC die to a second PIC die, optically couple a second PIC die to a third PIC die, and optically couple a first PIC die to a third PIC die. Additionally or alternatively, one optical bridge 108 may be used to optically couple the first PIC die to the second PIC die, and a second optical bridge 108 may be used to optically couple the second PIC die to a third PIC die.

[0039] Reference now Figure 4 In one embodiment, the device 100 includes PIC dies 104, 106, wherein the waveguides 222, 224 extend to the edges of the PIC dies 104, 106. In such an embodiment, the optical bridge 108 may include a reflector 220 that reflects edge-emitted light from the waveguide 222 to the waveguide 224 (or vice versa). Figure 1 and Figure 2 In the described embodiments, any suitable technique may be used to focus light from waveguide 222 to waveguide 224, such as forming lenses or mirrors in photonic layers 204, 208 or substrates 202, 206, using curved mirrors 220 or lenses in optical bridge 108, and the like.

[0040] Reference now Figure 5 In one embodiment, the device 100 includes an optical bridge 108 having a direct write waveguide 502 that connects light from the vertical coupler 214 to the vertical coupler 216. Any suitable direct write method may be used, such as using a femtosecond laser to write a waveguide in glass, crystal, or polymer.

[0041] Reference now Figure 6In one embodiment, the device 100 includes an optical bridge 108 having a photonic wire bond 602 connecting the waveguide 222 to the waveguide 224. In the illustrated embodiment, light from the waveguide 222 is evanescently coupled to the photonic wire bond 602, and then light in the photonic wire bond is evanescently coupled to the waveguide 224.

[0042] It should be understood that the possible methods described above for optically coupling the PIC dies 104, 106 together are only some of the possible methods, and other methods or combinations may be used. For example, in one embodiment, direct write waveguides may be used to create waveguides that are evanescently coupled to the waveguide 222 and / or the waveguide 224. In another example, photonic wire bonds 602 may be coupled to the edge emitting waveguides 222, 224 and / or the vertical couplers 214, 216. In general, any suitable coupling technique or combination of techniques may be used to optically couple the PIC dies 104, 106.

[0043] Reference now Figure 7 , in one embodiment, a flow chart of a method 700 for creating the device 100 is shown. The method 700 may be performed by a technician and / or by one or more automated machines. In some embodiments, one or more machines may be programmed to perform some or all of the steps of the method 700. Such a machine may include, for example, a memory, a processor, a data store, etc. The memory and / or the data store may store instructions that, when executed by the machine, cause the machine to perform some or all of the steps of the method 700. The method 700 may use any suitable set of techniques used in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, photolithography, ion implantation, dry etching, wet etching, thermal processing, flip chip, layer transfer, magnetron sputtering deposition, pulsed laser deposition, pick and place, etc. It should be understood that the method 700 is only one embodiment of a method for creating the device 100, and other methods may be used to create the device 100. In some embodiments, the steps of the method 700 may be performed in an order different from the order shown in the flow chart.

[0044] Method 700 begins at block 702, where PIC dies, such as PIC dies 104, 106, are fabricated. In block 704, the PIC dies may be fabricated on different substrates. In block 706, the PIC dies may be fabricated using different nodes. In block 708, the PIC dies may be fabricated using different lasers.

[0045] In block 710, the PIC die is tested. In block 712, the faulty PIC die is discarded. In some embodiments, the PIC die may be relatively small, so if a fault exists, only relatively small components may be discarded.

[0046] The PIC dies are stacked on top of each other in block 714. The PIC dies may be stacked using any suitable technique, such as copper bumping or hybrid bonding.

[0047] In block 716, the stacked PIC dies are optically coupled using optical bridge 108. In block 718, the stacked PIC dies may be optically coupled using vertically coupled waveguides and mirrors 220, such as Figure 2 In block 720, the stacked PIC dies may be optically coupled using edge emitting waveguides 222, 224 and reflector 220, as shown. Figure 4 In block 722, the stacked PIC dies may be optically coupled using the direct write waveguide 502 in the glass optical bridge 108, as shown. Figure 6 In block 724, the stacked PIC dies may be optically coupled using photonic wire bonding 602, such as Figure 6 shown.

[0048] One or more EIC dies 102 may be stacked on the PIC die in block 726. Additional packaging steps, such as wire bonding connections from the circuit board 110 to the EIC die 102, may then be performed.

[0049] Figure 8 802 (e.g., any suitable die as dies 102, 104, 106) that may be included in any device 100 disclosed herein. Wafer 800 may be composed of semiconductor material and may include one or more dies 802 having integrated circuit structures formed on a surface of wafer 800. Individual dies 802 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is completed, wafer 800 may undergo a singulation process in which dies 802 are separated from one another to provide discrete “chips” of an integrated circuit product. Die 802 may be any of dies 102, 104, 106 herein. Die 802 may include one or more transistors (e.g., the transistors discussed below). Fig. 9Some of the transistors 940 of the present invention), supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 800 or die 802 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 802. For example, a memory array formed of multiple memory devices may be formed in conjunction with a processor unit (e.g., Fig.12 The processor unit 1202 of the embodiment of the present invention is on the same die 802 or other logic configured to store information in the memory device or execute instructions stored in the memory array. Various devices in the device 100 disclosed herein can be manufactured using die-to-wafer assembly technology, in which some of the dies 102, 104, 106 are attached to a wafer 800 including other dies in the dies 102, 104, 106, and the wafer 800 is then singulated.

[0050] Fig. 9 1 is a cross-sectional side view of an integrated circuit device 900 that may be included in any of the devices 100 disclosed herein (e.g., in any of the dies 102, 104, 106). One or more of the integrated circuit devices 900 may be included in one or more of the dies 802 ( Figure 8 ). The integrated circuit device 900 may be formed on a die substrate 902 (eg, Figure 8 800) and may be included in a die (e.g., Figure 8 The die substrate 902 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 902 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 902 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as II-VI, III-V, or IV groups may also be used to form the die substrate 902. Although several examples of materials that may form the die substrate 902 are described herein, any material that may serve as the basis for the integrated circuit device 900 may be used. The die substrate 902 may be a single die (e.g., Figure 8 of a die 802) or a wafer (e.g., Figure 8A portion of the chip 800).

[0051] The integrated circuit device 900 may include one or more device layers 904 disposed on a die substrate 902. The device layer 904 may include features of one or more transistors 940 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 902. The transistor 940 may include, for example, one or more source and / or drain (S / D) regions 920, a gate 922 for controlling the flow of current between the S / D regions 920, and one or more S / D contacts 924 for routing electrical signals to / from the S / D regions 920. The transistor 940 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. The transistor 940 is not limited to Fig. 9 The types and configurations depicted in the drawings and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors (such as dual-gate transistors or tri-gate transistors), and wrap-around or full-all-around gate transistors (such as nanoribbon transistors, nanosheet transistors, or nanowire transistors).

[0052] FIG. 10A to FIG. 10D is a simplified perspective view of exemplary planar, FinFET, gate-all-around, and stacked gate-all-around transistors. FIG. 10A to FIG. 10D The transistor shown in FIG. 1 is formed on a substrate 1016 having a surface 1008 . An isolation region 1014 separates the source and drain regions of the transistor from other transistors and a body region 1018 of the substrate 1016 .

[0053] Fig. 10A is a perspective view of an exemplary planar transistor 1000 including a gate 1002 that controls current flow between a source region 1004 and a drain region 1006. Transistor 1000 is planar because source region 1004 and drain region 1006 are planar relative to substrate surface 1008.

[0054] Fig. 10B is a perspective view of an example FinFET transistor 1020 that includes a gate 1022 that controls current flow between a source region 1024 and a drain region 1026. Transistor 1020 is non-planar because source region 1024 and drain region 1026 include a "fin" that extends upward from substrate surface 1028. Because gate 1022 surrounds three sides of the semiconductor fin extending from source region 1024 to drain region 1026, transistor 1020 can be considered a tri-gate transistor. Fig. 10BOne S / D fin is shown extending through the gate 1022 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0055] Fig. 10C is a perspective view of a gate-all-around (GAA) transistor 1040 that includes a gate 1042 that controls current flow between a source region 1044 and a drain region 1046. Transistor 1040 is non-planar because source region 1044 and drain region 1046 are elevated from substrate surface 1028.

[0056] Fig. 10D 1060 is a perspective view of a GAA transistor 1060 including a gate 1062 that controls the flow of current between multiple elevated source regions 1064 and multiple elevated drain regions 1066. Transistor 1060 is a stacked GAA transistor because the gate controls the flow of current between multiple elevated S / D regions stacked on each other. Transistors 1040 and 1060 are considered to be full-all-around transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Depending on the width of the semiconductor portion extending through the gate (e.g., widths 1048 and 1068 of transistors 1040 and 1060, respectively), transistors 1040 and 1060 may alternatively be referred to as nanowire transistors, nanosheet transistors, or nanoribbon transistors.

[0057] return Fig. 9 , transistor 940 may include a gate 922 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one layer, or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0058] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0059] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 940 is a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0060] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0061] In some embodiments, when viewed as a cross section of the transistor 940 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 902 and two sidewall portions substantially perpendicular to the top surface of the die substrate 902. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 902 and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 902. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0062] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0063] The S / D region 920 may be formed within the die substrate 902 adjacent to the gate 922 of the individual transistor 940. For example, the S / D region 920 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 902 to form the S / D region 920. An annealing process to activate the dopants and diffuse them further into the die substrate 902 may follow the ion implantation process. In the latter process, the die substrate 902 may first be etched to form a recess at the location of the S / D region 920. An epitaxial deposition process may then be performed to fill the recess with the material used to fabricate the S / D region 920. In some embodiments, the S / D region 920 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form S / D region 920. In other embodiments, S / D region 920 may be formed using one or more layers of metals and / or metal alloys.

[0064] Electrical signals such as power and / or input / output (I / O) signals may be provided through one or more interconnect layers (in the Fig. 9 906-910) to and / or from devices (e.g., transistors 940) of device layer 904. For example, conductive features (e.g., gates 922 and S / D contacts 924) of device layer 904 can be electrically coupled to interconnect structures 928 of interconnect layers 906-910. One or more interconnect layers 906-910 can form a metallization stack (also referred to as an "ILD stack") 919 of integrated circuit device 900.

[0065] The interconnect structure 928 may be arranged within the interconnect layers 906-910 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to Fig. 9 The specific configuration of interconnect structure 928 is depicted in FIG. Fig. 9 A specific number of interconnect layers 906 - 910 are depicted in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0066] In some embodiments, the interconnect structure 928 may include a line 928a and / or a via 928b filled with a conductive material such as a metal. The line 928a may be arranged to route electrical signals in the direction of a plane substantially parallel to the surface of the die substrate 902 on which the device layer 904 is formed. For example, the line 928a may route electrical signals in the direction of entering and exiting the page and / or in the direction across the page. The via 928b may be arranged to route electrical signals in the direction of a plane substantially perpendicular to the surface of the die substrate 902 on which the device layer 904 is formed. In some embodiments, the via 928b may electrically couple the lines 928a of different interconnect layers 906-910 together.

[0067] like Fig. 9 As shown, the interconnect layers 906-910 may include a dielectric material 926 disposed between interconnect structures 928. In some embodiments, the dielectric material 926 disposed between the interconnect structures 928 in different ones of the interconnect layers 906-910 may have different compositions; in other embodiments, the composition of the dielectric material 926 between different interconnect layers 906-910 may be the same. The device layer 904 may also include a dielectric material 926 disposed between the transistor 940 and the bottom layer of the metallization stack. The dielectric material 926 included in the device layer 904 may have a different composition than the dielectric material 926 included in the interconnect layers 906-910; in other embodiments, the composition of the dielectric material 926 in the device layer 904 may be the same as the dielectric material 926 included in any one of the interconnect layers 906-910.

[0068] The first interconnect layer 906 (referred to as metal 1 or "M1") can be formed directly on the device layer 904. In some embodiments, as shown, the first interconnect layer 906 can include lines 928a and / or vias 928b. The lines 928a of the first interconnect layer 906 can be coupled to contacts (e.g., S / D contacts 924) of the device layer 904. The vias 928b of the first interconnect layer 906 can be coupled to the lines 928a of the second interconnect layer 908.

[0069] A second interconnect layer 908 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 906. In some embodiments, the second interconnect layer 908 may include vias 928b to couple wires 928a of the second interconnect layer 908 with wires 928a of the third interconnect layer 910. Although wires 928a and vias 928b are structurally depicted with lines within each interconnect layer for clarity, in some embodiments, wires 928a and vias 928b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0070] A third interconnect layer 910 (referred to as metal 3 or "M3") (and additional interconnect layers as needed) may be formed successively on the second interconnect layer 908 according to similar techniques and configurations as described in connection with the second interconnect layer 908 or the first interconnect layer 906. In some embodiments, interconnect layers that are "higher" (i.e., farther from the device layer 904) in the metallization stack 919 in the integrated circuit device 900 may be thicker than interconnect layers lower in the metallization stack 919, wherein the lines 928a and vias 928b in the higher interconnect layers are thicker than the lines 928a and vias 928b in the lower interconnect layers.

[0071] The integrated circuit device 900 may include a solder resist material 934 (eg, polyimide or a similar material) and one or more conductive contacts 936 formed on the interconnect layers 906-910. Fig. 9 , the conductive contacts 936 are shown as taking the form of bonding pads. The conductive contacts 936 can be electrically coupled to the interconnect structure 928 and configured to route electrical signals of the transistor(s) 940 to an external device. For example, solder bonds can be formed on one or more conductive contacts 936 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 900 to another component (e.g., a printed circuit board). The integrated circuit device 900 may include additional or alternative structures for routing electrical signals from the interconnect layers 906-910; for example, the conductive contacts 936 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0072] In some embodiments where the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include another metallization stack (not shown) on an opposite side of the device layer(s) 904. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 906-910 to provide a conductive path (e.g., including wires and vias) between the device layer(s) 904 and additional conductive contacts (not shown) on an opposite side of the integrated circuit device 900 from the conductive contacts 936.

[0073] In other embodiments where the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include one or more through silicon vias (TSVs) through the die substrate 902; these TSVs may contact the device layer(s) 904 and may provide a conductive path between the device layer(s) 904 and additional conductive contacts (not shown) on the side of the integrated circuit device 900 opposite the conductive contacts 936. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the side of the integrated circuit device 900 opposite the conductive contacts 936 to the transistor 940 and any other components integrated into the die 900, and the metallization stack 919 may be used to route I / O signals from the conductive contacts 936 to the transistor 940 and any other components integrated into the die 900.

[0074] Multiple integrated circuit devices 900 can be stacked with one or more TSVs in each stacked device, thereby providing a connection between one of the devices and any of the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between each HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0075] Fig.11 1 is a cross-sectional side view of an integrated circuit device assembly 1100 that may be included in any of the devices 100 disclosed herein. In some embodiments, the integrated circuit device assembly 1100 may be the device 100. The integrated circuit device assembly 1100 includes a plurality of components disposed on a circuit board 1102 (which may be a motherboard, a system board, a main board, etc.). The integrated circuit device assembly 1100 includes components disposed on a first side 1140 of the circuit board 1102 and an opposing second side 1142 of the circuit board 1102; generally, the components may be disposed on one or both of the sides 1140 and 1142. Any integrated circuit components discussed below with reference to the integrated circuit device assembly 1100 may take the form of any suitable embodiment in the embodiments of the device 100 disclosed herein.

[0076] In some embodiments, circuit board 1102 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1102 (optionally in combination with other metal layers). In other embodiments, circuit board 1102 may be a non-PCB substrate. In some embodiments, circuit board 1102 may be, for example, circuit board 110. Fig.11 The integrated circuit device assembly 1100 shown in FIG. 1 includes a package-on-interposer structure 1136 coupled to a first side 1140 of a circuit board 1102 via a coupling component 1116. The coupling component 1116 can electrically and mechanically couple the package-on-interposer structure 1136 to the circuit board 1102 and can include solder balls (e.g., Fig.11 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0077] The package-on-interposer structure 1136 may include an integrated circuit component 1120 coupled to the interposer 1104 via a coupling component 1118. The coupling component 1118 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 1116. Fig.11 A single integrated circuit assembly 1120 is shown in FIG. 1 , but multiple integrated circuit assemblies may be coupled to interposer 1104 ; indeed, additional interposers may be coupled to interposer 1104 . Interposer 1104 may provide an interposer substrate for bridging circuit board 1102 and integrated circuit assembly 1120 .

[0078] Integrated circuit assembly 1120 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Figure 8 The tube core 802, Fig. 9The integrated circuit assembly 1120 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit assembly 1120 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0079] In embodiments where the integrated circuit assembly 1120 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit assembly) or two or more different types (a heterogeneous multi-die integrated circuit assembly). A multi-die integrated circuit assembly may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0080] In addition to including one or more processor units, the integrated circuit assembly 1120 may also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit assembly includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges (such as silicon interposers) embedded in the packaging substrate, or a plurality of silicon interposers. Embedded Multi-Die Interconnect Bridge (EMIB)), or a combination thereof.

[0081] Typically, interposer 1104 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1104 can couple integrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of coupling component 1116 to couple to circuit board 1102. Fig.11In the illustrated embodiment, integrated circuit component 1120 and circuit board 1102 are attached to opposite sides of interposer 1104; in other embodiments, integrated circuit component 1120 and circuit board 1102 may be attached to the same side of interposer 1104. In some embodiments, three or more components may be interconnected through interposer 1104.

[0082] In some embodiments, the interposer 1104 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 1104 may be formed of alternative rigid or flexible materials, which may include the same materials used in semiconductor substrates described above, such as silicon, germanium, and other III-V and IV materials. The interposer 1104 may include metal interconnects 1108 and vias 1110, including but not limited to through-hole vias 1110-1 (which extend from the first side 1150 of the interposer 1104 to the second side 1154 of the interposer 1104), blind vias 1110-2 (which extend from the first side 1150 or the second side 1154 of the interposer 1104 to the internal metal layers), and buried vias 1110-3 (which connect the internal metal layers).

[0083] In some embodiments, the interposer 1104 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, the interposer 1104 including the silicon interposer may also include one or more routing layers to route connections on the first side of the interposer 1104 to an opposite second side of the interposer 1104.

[0084] The interposer 1104 may also include embedded devices 1114, including passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 1104. The package structure 1136 on the interposer may take the form of any package structure on the interposer known in the art. In an embodiment, the interposer is a non-printed circuit board.

[0085] The integrated circuit device assembly 1100 may include an integrated circuit component 1124 coupled to the first side 1140 of the circuit board 1102 via a coupling component 1122. The coupling component 1122 may take the form of any of the embodiments discussed above with reference to the coupling component 1116, and the integrated circuit component 1124 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1120.

[0086] Fig.11 The illustrated integrated circuit device assembly 1100 includes a package-on-package structure 1134 coupled to a second side 1142 of a circuit board 1102 via a coupling component 1128. The package-on-package structure 1134 may include an integrated circuit component 1126 and an integrated circuit component 1132 coupled together via a coupling component 1130, such that the integrated circuit component 1126 is disposed between the circuit board 1102 and the integrated circuit component 1132. The coupling components 1128 and 1130 may take the form of any of the embodiments of the coupling component 1116 discussed above, and the integrated circuit components 1126 and 1132 may take the form of any of the embodiments of the integrated circuit component 1120 discussed above. The package-on-package structure 1134 may be configured according to any package-on-package structure known in the art.

[0087] Fig.12 1 is a block diagram of an example electrical device 1200 that may include one or more of the devices 100 disclosed herein. For example, any suitable component in the components of the electrical device 1200 may include one or more of the integrated circuit device assembly 1100, the integrated circuit assembly 1120, the integrated circuit device 900, or the integrated circuit die 802 disclosed herein, and may be arranged in any of the devices 100 disclosed herein. Fig.12 1200, but any one or more of these components may be omitted or duplicated as applicable for the application. In some embodiments, some or all of the components included in the electrical device 1200 may be attached to one or more motherboards or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-chip (SoC) die.

[0088] Additionally, in various embodiments, the electrical device 1200 may not include Fig.121200, but the electrical device 1200 may include interface circuitry for coupling to one or more components. For example, the electrical device 1200 may not include the display device 1206, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1206 may be coupled. In another set of examples, the electrical device 1200 may not include the audio input device 1224 or the audio output device 1208, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 1224 or the audio output device 1208 may be coupled.

[0089] The electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1202 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, a processor unit may be referred to as an XPU (or xPU).

[0090] The electrical device 1200 may include a memory 1204, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1204 may include memory located on the same integrated circuit die as the processor unit 1202. The memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0091] In some embodiments, the electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric with another processor unit 1202 in the electrical device 1200. There may be a variety of differences between the processing units 1202 in the system based on a range of quality metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1202 in the electrical device 1200.

[0092] In some embodiments, the electrical device 1200 may include a communication component 1212 (e.g., one or more communication components). For example, the communication component 1212 may manage wireless communications for transmitting data to and from the electrical device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may transmit data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0093] The communication component 1212 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE802.16-2005 revision), Long Term Evolution (LTE) project, and any revisions, updates and / or modifications (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are often referred to as WiMAX networks (which is an acronym standing for Worldwide Interoperability for Microwave Access), which is a certification mark for products that pass conformance and interoperability testing of the IEEE 802.16 standards. The communication component 1212 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1212 can operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1212 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication component 1212 can operate according to other wireless protocols. The electrical device 1200 may include an antenna 1222 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0094] In some embodiments, the communication component 1212 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1212 can include multiple communication components. For example, the first communication component 1212 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication component 1212 can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 1212 can be dedicated to wireless communications, and the second communication component 1212 can be dedicated to wired communications.

[0095] The electrical device 1200 may include a battery / power circuit system 1214. The battery / power circuit system 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 1200 to an energy source separate from the electrical device 1200 (e.g., AC line power).

[0096] The electrical device 1200 may include a display device 1206 (or corresponding interface circuitry, as discussed above). The display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0097] The electrical device 1200 may include an audio output device 1208 (or corresponding interface circuitry, as discussed above). The audio output device 1208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0098] The electrical device 1200 may include an audio input device 1224 (or corresponding interface circuitry, as discussed above). The audio input device 1224 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1200 may include a global navigation satellite system (GNSS) device 1218 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. The GNSS device 1218 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0099] Electrical device 1200 may include other output devices 1210 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0100] The electrical device 1200 may include other input devices 1220 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1220 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereo camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0101] The electrical device 1200 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or equipment, a manufacturing equipment). In some embodiments, the electrical device 1200 may be any other electronic device that processes data. In some embodiments, the electrical device 1200 may include multiple discrete physical components. Given the range of devices that the electrical device 1200 may be in various embodiments, in some embodiments, the electrical device 1200 may be referred to as a computing device or a computing system.

[0102] Example

[0103] Illustrative examples of the technology disclosed herein are provided below. Embodiments of the technology may include any one or more of the examples described below and any combination.

[0104] Example 1 includes an apparatus comprising: a first photonic integrated circuit (PIC) die, wherein a first plurality of waveguides are defined in the first PIC die; and a second PIC die stacked on the first PIC die, wherein a second plurality of waveguides are defined in the second PIC die, wherein individual waveguides of the first plurality of waveguides are optically coupled to individual waveguides of the second plurality of waveguides.

[0105] Example 2 includes the subject matter of Example 1, and further includes an optical bridge, wherein the optical bridge optically couples the first plurality of waveguides to the second plurality of waveguides.

[0106] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the optical bridge comprises one or more mirrors, wherein the one or more mirrors direct light beams from the first plurality of waveguides to the second plurality of waveguides.

[0107] Example 4 includes the subject matter of any of Examples 1-3, and wherein the optical bridge comprises a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides direct light from the first plurality of waveguides to the second plurality of waveguides.

[0108] Example 5 includes the subject matter of any of Examples 1-4, and wherein the first PIC die comprises a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is used to couple light from each of the first plurality of waveguides from a surface of the first PIC die into each of the plurality of direct-write waveguides, and wherein the second PIC die comprises a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the second plurality of waveguides from a surface of the second PIC die into each of the plurality of direct-write waveguides.

[0109] Example 6 includes the subject matter of any of Examples 1-5, and wherein the optical bridge comprises a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds guide light from the first plurality of waveguides to the second plurality of waveguides.

[0110] Example 7 includes the subject matter of any of Examples 1-6, and wherein individual photonic wire bonds of the plurality of photonic wire bonds are evanescently coupled to individual waveguides of the first plurality of waveguides and are evanescently coupled to individual waveguides of the second plurality of waveguides.

[0111] Example 8 includes the subject matter of any of Examples 1-7, and wherein the apparatus comprises at least four PIC dies stacked on each other, wherein the at least four PIC dies include the first PIC die and the second PIC die.

[0112] Example 9 includes the subject matter of any of Examples 1-8, and further includes an electronic integrated circuit (EIC) die stacked on top of the second PIC die.

[0113] Example 10 includes the subject matter of any of Examples 1-9, and further includes one or more vias extending from the EIC die to the second PIC die, and one or more vias extending from the second PIC die to the first PIC die.

[0114] Example 11 includes the subject matter of any of Examples 1-10, and wherein the second PIC die is hybrid bonded to the first PIC die.

[0115] Example 12 includes the subject matter of any of Examples 1-11, and wherein the substrate of the first PIC die is a different type than the substrate of the second PIC die.

[0116] Example 13 includes a device comprising: a first photonic integrated circuit (PIC) die, wherein a first plurality of waveguides are defined in the first PIC die; a second PIC die stacked on the first PIC die, wherein a second plurality of waveguides are defined in the second PIC die; and a unit for optically coupling the first plurality of waveguides and the second plurality of waveguides.

[0117] Example 14 includes the subject matter of Example 13, and wherein the means for optically coupling the first plurality of waveguides and the second plurality of waveguides comprises an optical bridge.

[0118] Example 15 includes the subject matter of any of Examples 13 and 14, and wherein the optical bridge comprises one or more mirrors, wherein the one or more mirrors direct light beams from the first plurality of waveguides to the second plurality of waveguides.

[0119] Example 16 includes the subject matter of any of Examples 13-15, and wherein the optical bridge comprises a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides direct light from the first plurality of waveguides to the second plurality of waveguides.

[0120] Example 17 includes the subject matter of any of Examples 13-16, and wherein the first PIC die comprises a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is used to couple light from each of the first plurality of waveguides from a surface of the first PIC die into each of the plurality of direct-write waveguides, and wherein the second PIC die comprises a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the second plurality of waveguides from a surface of the second PIC die into each of the plurality of direct-write waveguides.

[0121] Example 18 includes the subject matter of any of Examples 13-17, and wherein the optical bridge comprises a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds guide light from the first plurality of waveguides to the second plurality of waveguides.

[0122] Example 19 includes the subject matter of any of Examples 13-18, and wherein individual photonic wire bonds of the plurality of photonic wire bonds are evanescently coupled to individual waveguides of the first plurality of waveguides and are evanescently coupled to individual waveguides of the second plurality of waveguides.

[0123] Example 20 includes the subject matter of any of Examples 13-19, and wherein the apparatus comprises at least four PIC dies stacked on each other, wherein the at least four PIC dies include the first PIC die and the second PIC die.

[0124] Example 21 includes the subject matter of any of Examples 13-20, and further includes an electronic integrated circuit (EIC) die stacked on top of the second PIC die.

[0125] Example 22 includes the subject matter of any of Examples 13-21, and further includes one or more vias extending from the EIC die to the second PIC die, and one or more vias extending from the second PIC die to the first PIC die.

[0126] Example 23 includes the subject matter of any of Examples 13-22, and wherein the second PIC die is hybrid bonded to the first PIC die.

[0127] Example 24 includes the subject matter of any of Examples 13-23, and wherein the substrate of the first PIC die is a different type than the substrate of the second PIC die.

[0128] Example 25 includes a method comprising: preparing a plurality of photonic integrated circuit (PIC) dies, wherein each of the plurality of PIC dies includes a plurality of waveguides; testing each of the plurality of PIC dies to determine a plurality of non-faulty PIC dies; stacking two or more of the plurality of non-faulty PIC dies; and optically coupling the plurality of waveguides of the two or more of the plurality of non-faulty PIC dies to each other.

[0129] Example 26 includes the subject matter of Example 25, and wherein the two or more of the plurality of non-faulty PIC dies include a first PIC die and a second PIC die, and wherein optically coupling the plurality of waveguides of the two or more of the plurality of non-faulty PIC dies to each other comprises: optically coupling the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die using an optical bridge.

[0130] Example 27 includes the subject matter of any of Examples 25 and 26, and wherein the optical bridge comprises one or more reflectors, wherein the one or more reflectors direct light beams from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

[0131] Example 28 includes the subject matter of any of Examples 25-27, and wherein the optical bridge comprises a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides direct light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

[0132] Example 29 includes the subject matter of any of Examples 25-28, and wherein the first PIC die comprises a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is used to couple light from each of the plurality of waveguides of the first PIC die from a surface of the first PIC die into each of the plurality of direct-write waveguides, and wherein the second PIC die comprises a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the plurality of waveguides of the second PIC die from a surface of the second PIC die into each of the plurality of direct-write waveguides.

[0133] Example 30 includes the subject matter of any of Examples 25-29, and wherein the optical bridge comprises a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds direct light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

[0134] Example 31 includes the subject matter of any of Examples 25-30, and wherein individual ones of the plurality of photonic wire bonds are evanescently coupled to individual ones of the plurality of waveguides of the first PIC die and are evanescently coupled to individual ones of the plurality of waveguides of the second PIC die.

[0135] Example 32 includes the subject matter of any of Examples 25-31, and wherein two or more of the plurality of non-faulty PIC dies include at least four PIC dies.

[0136] Example 33 includes the subject matter of any of Examples 25-32, and further includes an electronic integrated circuit (EIC) die stacked on top of the plurality of non-faulty PIC dies.

[0137] Example 34 includes the subject matter of any of Examples 25-33, and further includes one or more vias extending from the EIC die to the plurality of non-faulty PIC dies.

[0138] Example 35 includes the subject matter of any of Examples 25-34, and wherein the plurality of non-faulty PIC dies are hybrid-bonded together.

[0139] Example 36 includes the subject matter of any of Examples 25-35, and wherein the plurality of non-faulty PIC dies comprises two or more different types of substrates.

Claims

1. A device comprising: a first photonic integrated circuit (PIC) die, wherein a first plurality of waveguides are defined in the first PIC die; and A second PIC die is stacked on the first PIC die, wherein a second plurality of waveguides are defined in the second PIC die, wherein individual waveguides of the first plurality of waveguides are optically coupled to individual waveguides of the second plurality of waveguides.

2. The device according to claim 1, further comprising an optical bridge, wherein The optical bridge optically couples the first plurality of waveguides to the second plurality of waveguides.

3. The device according to claim 2, wherein: The optical bridge includes one or more mirrors, wherein the one or more mirrors direct light beams from the first plurality of waveguides to the second plurality of waveguides.

4. The device according to claim 2, wherein: The optical bridge includes a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides direct light from the first plurality of waveguides to the second plurality of waveguides.

5. The device according to claim 4, wherein: The first PIC die includes a first plurality of vertical couplers, wherein each vertical coupler of the first plurality of vertical couplers is used to couple light from each waveguide of the first plurality of waveguides from a surface of the first PIC die into each direct-write waveguide of the plurality of direct-write waveguides, The second PIC die includes a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the second plurality of waveguides from a surface of the second PIC die into each of the plurality of direct-write waveguides.

6. The device according to claim 2, wherein: The optical bridge includes a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds direct light from the first plurality of waveguides to the second plurality of waveguides.

7. The device according to claim 6, wherein: Respective photonic wire bonds of the plurality of photonic wire bonds are evanescently coupled to respective waveguides of the first plurality of waveguides and are evanescently coupled to respective waveguides of the second plurality of waveguides.

8. The device according to claim 1, wherein: The apparatus comprises at least four PIC dies stacked on each other, wherein the at least four PIC dies comprise the first PIC die and the second PIC die.

9. The apparatus of claim 1 further comprising an electronic integrated circuit (EIC) die stacked on top of the second PIC die.

10. The apparatus of claim 9, further comprising one or more vias extending from the EIC die to the second PIC die, and one or more vias extending from the second PIC die to the first PIC die.

11. The device according to claim 1, wherein: The second PIC die is hybrid bonded to the first PIC die.

12. The device according to claim 1, wherein: The substrate of the first PIC die is of a different type than the substrate of the second PIC die.

13. An apparatus comprising: a first photonic integrated circuit (PIC) die, wherein a first plurality of waveguides are defined in the first PIC die; a second PIC die stacked on the first PIC die, wherein a second plurality of waveguides are defined in the second PIC die; and Means for optically coupling the first plurality of waveguides and the second plurality of waveguides.

14. The device according to claim 13, wherein: The means for optically coupling the first plurality of waveguides and the second plurality of waveguides comprises an optical bridge.

15. The device according to claim 14, wherein: The optical bridge includes one or more mirrors, wherein the one or more mirrors direct light beams from the first plurality of waveguides to the second plurality of waveguides.

16. The device according to claim 14, wherein: The optical bridge includes a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides direct light from the first plurality of waveguides to the second plurality of waveguides.

17. The device according to claim 14, wherein: The optical bridge includes a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds direct light from the first plurality of waveguides to the second plurality of waveguides.

18. The apparatus of claim 13, further comprising an electronic integrated circuit (EIC) die stacked on top of the second PIC die.

19. A method comprising: preparing a plurality of photonic integrated circuit (PIC) dies, wherein each of the plurality of PIC dies comprises a plurality of waveguides; testing individual PIC dies of the plurality of PIC dies to determine a plurality of non-faulty PIC dies; stacking two or more non-faulty PIC dies of the plurality of non-faulty PIC dies; and The plurality of waveguides of the two or more non-faulty PIC dies of the plurality of non-faulty PIC dies are optically coupled to each other.

20. The method according to claim 19, wherein: The two or more non-faulty PIC dies of the plurality of non-faulty PIC dies include a first PIC die and a second PIC die, wherein optically coupling the plurality of waveguides of the two or more non-faulty PIC dies of the plurality of non-faulty PIC dies to each other includes optically coupling the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die using an optical bridge.

21. The method according to claim 20, wherein: The optical bridge includes one or more reflectors, wherein the one or more reflectors direct light beams from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

22. The method according to claim 20, wherein: The optical bridge includes a plurality of direct-write waveguides, wherein the plurality of direct-write waveguides direct light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

23. The method according to claim 22, wherein: The first PIC die comprises a first plurality of vertical couplers, wherein each of the first plurality of vertical couplers is used to couple light from each of the plurality of waveguides of the first PIC die from a surface of the first PIC die into each of the plurality of direct-write waveguides, The second PIC die includes a second plurality of vertical couplers, wherein each of the second plurality of vertical couplers is used to couple light from each of the plurality of waveguides of the second PIC die from a surface of the second PIC die into each of the plurality of direct-write waveguides.

24. The method according to claim 20, wherein: The optical bridge includes a plurality of photonic wire bonds, wherein the plurality of photonic wire bonds direct light from the plurality of waveguides of the first PIC die to the plurality of waveguides of the second PIC die.

25. The method of claim 19, further comprising stacking an electronic integrated circuit (EIC) die on top of the plurality of non-faulty PIC dies.

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